1052aa3ccSAndi Kleen[ 2052aa3ccSAndi Kleen { 3*c42bee96SIan Rogers "BriefDescription": "BACLEARS asserted.", 4*c42bee96SIan Rogers "EventCode": "0xE6", 5*c42bee96SIan Rogers "EventName": "BACLEARS.ANY", 6*c42bee96SIan Rogers "SampleAfterValue": "2000000", 7*c42bee96SIan Rogers "UMask": "0x1" 8052aa3ccSAndi Kleen }, 9052aa3ccSAndi Kleen { 10*c42bee96SIan Rogers "BriefDescription": "Cycles during which instruction fetches are stalled.", 11052aa3ccSAndi Kleen "EventCode": "0x86", 12052aa3ccSAndi Kleen "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", 13052aa3ccSAndi Kleen "SampleAfterValue": "2000000", 14*c42bee96SIan Rogers "UMask": "0x1" 15052aa3ccSAndi Kleen }, 16052aa3ccSAndi Kleen { 17*c42bee96SIan Rogers "BriefDescription": "Decode stall due to IQ full", 18052aa3ccSAndi Kleen "EventCode": "0x87", 19052aa3ccSAndi Kleen "EventName": "DECODE_STALL.IQ_FULL", 20052aa3ccSAndi Kleen "SampleAfterValue": "2000000", 21*c42bee96SIan Rogers "UMask": "0x2" 22052aa3ccSAndi Kleen }, 23052aa3ccSAndi Kleen { 24*c42bee96SIan Rogers "BriefDescription": "Decode stall due to PFB empty", 25*c42bee96SIan Rogers "EventCode": "0x87", 26*c42bee96SIan Rogers "EventName": "DECODE_STALL.PFB_EMPTY", 27052aa3ccSAndi Kleen "SampleAfterValue": "2000000", 28*c42bee96SIan Rogers "UMask": "0x1" 29052aa3ccSAndi Kleen }, 30052aa3ccSAndi Kleen { 31*c42bee96SIan Rogers "BriefDescription": "Instruction fetches.", 32*c42bee96SIan Rogers "EventCode": "0x80", 33*c42bee96SIan Rogers "EventName": "ICACHE.ACCESSES", 34*c42bee96SIan Rogers "SampleAfterValue": "200000", 35*c42bee96SIan Rogers "UMask": "0x3" 36052aa3ccSAndi Kleen }, 37052aa3ccSAndi Kleen { 38*c42bee96SIan Rogers "BriefDescription": "Icache hit", 39*c42bee96SIan Rogers "EventCode": "0x80", 40*c42bee96SIan Rogers "EventName": "ICACHE.HIT", 41*c42bee96SIan Rogers "SampleAfterValue": "200000", 42*c42bee96SIan Rogers "UMask": "0x1" 43*c42bee96SIan Rogers }, 44*c42bee96SIan Rogers { 45*c42bee96SIan Rogers "BriefDescription": "Icache miss", 46*c42bee96SIan Rogers "EventCode": "0x80", 47*c42bee96SIan Rogers "EventName": "ICACHE.MISSES", 48*c42bee96SIan Rogers "SampleAfterValue": "200000", 49*c42bee96SIan Rogers "UMask": "0x2" 50*c42bee96SIan Rogers }, 51*c42bee96SIan Rogers { 52*c42bee96SIan Rogers "BriefDescription": "All Instructions decoded", 53*c42bee96SIan Rogers "EventCode": "0xAA", 54052aa3ccSAndi Kleen "EventName": "MACRO_INSTS.ALL_DECODED", 55052aa3ccSAndi Kleen "SampleAfterValue": "2000000", 56*c42bee96SIan Rogers "UMask": "0x3" 57052aa3ccSAndi Kleen }, 58052aa3ccSAndi Kleen { 59*c42bee96SIan Rogers "BriefDescription": "CISC macro instructions decoded", 60*c42bee96SIan Rogers "EventCode": "0xAA", 61*c42bee96SIan Rogers "EventName": "MACRO_INSTS.CISC_DECODED", 62*c42bee96SIan Rogers "SampleAfterValue": "2000000", 63*c42bee96SIan Rogers "UMask": "0x2" 64*c42bee96SIan Rogers }, 65*c42bee96SIan Rogers { 66*c42bee96SIan Rogers "BriefDescription": "Non-CISC nacro instructions decoded", 67*c42bee96SIan Rogers "EventCode": "0xAA", 68*c42bee96SIan Rogers "EventName": "MACRO_INSTS.NON_CISC_DECODED", 69*c42bee96SIan Rogers "SampleAfterValue": "2000000", 70*c42bee96SIan Rogers "UMask": "0x1" 71*c42bee96SIan Rogers }, 72*c42bee96SIan Rogers { 73*c42bee96SIan Rogers "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.", 74*c42bee96SIan Rogers "CounterMask": "1", 75*c42bee96SIan Rogers "EventCode": "0xA9", 76052aa3ccSAndi Kleen "EventName": "UOPS.MS_CYCLES", 77052aa3ccSAndi Kleen "SampleAfterValue": "2000000", 78*c42bee96SIan Rogers "UMask": "0x1" 79052aa3ccSAndi Kleen } 80052aa3ccSAndi Kleen] 81