xref: /openbmc/linux/tools/perf/pmu-events/arch/x86/bonnell/cache.json (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18) 
1052aa3ccSAndi Kleen[
2052aa3ccSAndi Kleen    {
3*c42bee96SIan Rogers        "BriefDescription": "L1 Data Cacheable reads and writes",
4052aa3ccSAndi Kleen        "EventCode": "0x40",
5052aa3ccSAndi Kleen        "EventName": "L1D_CACHE.ALL_CACHE_REF",
6052aa3ccSAndi Kleen        "SampleAfterValue": "2000000",
7*c42bee96SIan Rogers        "UMask": "0xa3"
8052aa3ccSAndi Kleen    },
9052aa3ccSAndi Kleen    {
10*c42bee96SIan Rogers        "BriefDescription": "L1 Data reads and writes",
11*c42bee96SIan Rogers        "EventCode": "0x40",
12*c42bee96SIan Rogers        "EventName": "L1D_CACHE.ALL_REF",
13*c42bee96SIan Rogers        "SampleAfterValue": "2000000",
14*c42bee96SIan Rogers        "UMask": "0x83"
15052aa3ccSAndi Kleen    },
16052aa3ccSAndi Kleen    {
17*c42bee96SIan Rogers        "BriefDescription": "Modified cache lines evicted from the L1 data cache",
18052aa3ccSAndi Kleen        "EventCode": "0x40",
19052aa3ccSAndi Kleen        "EventName": "L1D_CACHE.EVICT",
20052aa3ccSAndi Kleen        "SampleAfterValue": "200000",
21*c42bee96SIan Rogers        "UMask": "0x10"
22052aa3ccSAndi Kleen    },
23052aa3ccSAndi Kleen    {
24*c42bee96SIan Rogers        "BriefDescription": "L1 Cacheable Data Reads",
25*c42bee96SIan Rogers        "EventCode": "0x40",
26*c42bee96SIan Rogers        "EventName": "L1D_CACHE.LD",
27*c42bee96SIan Rogers        "SampleAfterValue": "2000000",
28*c42bee96SIan Rogers        "UMask": "0xa1"
29*c42bee96SIan Rogers    },
30*c42bee96SIan Rogers    {
31*c42bee96SIan Rogers        "BriefDescription": "L1 Data line replacements",
32*c42bee96SIan Rogers        "EventCode": "0x40",
33*c42bee96SIan Rogers        "EventName": "L1D_CACHE.REPL",
34*c42bee96SIan Rogers        "SampleAfterValue": "200000",
35*c42bee96SIan Rogers        "UMask": "0x8"
36*c42bee96SIan Rogers    },
37*c42bee96SIan Rogers    {
38*c42bee96SIan Rogers        "BriefDescription": "Modified cache lines allocated in the L1 data cache",
39*c42bee96SIan Rogers        "EventCode": "0x40",
40*c42bee96SIan Rogers        "EventName": "L1D_CACHE.REPLM",
41*c42bee96SIan Rogers        "SampleAfterValue": "200000",
42*c42bee96SIan Rogers        "UMask": "0x48"
43*c42bee96SIan Rogers    },
44*c42bee96SIan Rogers    {
45*c42bee96SIan Rogers        "BriefDescription": "L1 Cacheable Data Writes",
46*c42bee96SIan Rogers        "EventCode": "0x40",
47*c42bee96SIan Rogers        "EventName": "L1D_CACHE.ST",
48*c42bee96SIan Rogers        "SampleAfterValue": "2000000",
49*c42bee96SIan Rogers        "UMask": "0xa2"
50*c42bee96SIan Rogers    },
51*c42bee96SIan Rogers    {
52*c42bee96SIan Rogers        "BriefDescription": "Cycles L2 address bus is in use.",
53*c42bee96SIan Rogers        "EventCode": "0x21",
54*c42bee96SIan Rogers        "EventName": "L2_ADS.SELF",
55*c42bee96SIan Rogers        "SampleAfterValue": "200000",
56*c42bee96SIan Rogers        "UMask": "0x40"
57*c42bee96SIan Rogers    },
58*c42bee96SIan Rogers    {
59*c42bee96SIan Rogers        "BriefDescription": "All data requests from the L1 data cache",
60*c42bee96SIan Rogers        "EventCode": "0x2C",
61*c42bee96SIan Rogers        "EventName": "L2_DATA_RQSTS.SELF.E_STATE",
62*c42bee96SIan Rogers        "SampleAfterValue": "200000",
63*c42bee96SIan Rogers        "UMask": "0x44"
64*c42bee96SIan Rogers    },
65*c42bee96SIan Rogers    {
66*c42bee96SIan Rogers        "BriefDescription": "All data requests from the L1 data cache",
67*c42bee96SIan Rogers        "EventCode": "0x2C",
68*c42bee96SIan Rogers        "EventName": "L2_DATA_RQSTS.SELF.I_STATE",
69*c42bee96SIan Rogers        "SampleAfterValue": "200000",
70*c42bee96SIan Rogers        "UMask": "0x41"
71*c42bee96SIan Rogers    },
72*c42bee96SIan Rogers    {
73*c42bee96SIan Rogers        "BriefDescription": "All data requests from the L1 data cache",
74*c42bee96SIan Rogers        "EventCode": "0x2C",
75*c42bee96SIan Rogers        "EventName": "L2_DATA_RQSTS.SELF.MESI",
76*c42bee96SIan Rogers        "SampleAfterValue": "200000",
77*c42bee96SIan Rogers        "UMask": "0x4f"
78*c42bee96SIan Rogers    },
79*c42bee96SIan Rogers    {
80*c42bee96SIan Rogers        "BriefDescription": "All data requests from the L1 data cache",
81*c42bee96SIan Rogers        "EventCode": "0x2C",
82*c42bee96SIan Rogers        "EventName": "L2_DATA_RQSTS.SELF.M_STATE",
83*c42bee96SIan Rogers        "SampleAfterValue": "200000",
84*c42bee96SIan Rogers        "UMask": "0x48"
85*c42bee96SIan Rogers    },
86*c42bee96SIan Rogers    {
87*c42bee96SIan Rogers        "BriefDescription": "All data requests from the L1 data cache",
88*c42bee96SIan Rogers        "EventCode": "0x2C",
89*c42bee96SIan Rogers        "EventName": "L2_DATA_RQSTS.SELF.S_STATE",
90*c42bee96SIan Rogers        "SampleAfterValue": "200000",
91*c42bee96SIan Rogers        "UMask": "0x42"
92*c42bee96SIan Rogers    },
93*c42bee96SIan Rogers    {
94*c42bee96SIan Rogers        "BriefDescription": "Cycles the L2 cache data bus is busy.",
95*c42bee96SIan Rogers        "EventCode": "0x22",
96*c42bee96SIan Rogers        "EventName": "L2_DBUS_BUSY.SELF",
97*c42bee96SIan Rogers        "SampleAfterValue": "200000",
98*c42bee96SIan Rogers        "UMask": "0x40"
99*c42bee96SIan Rogers    },
100*c42bee96SIan Rogers    {
101*c42bee96SIan Rogers        "BriefDescription": "Cycles the L2 transfers data to the core.",
102*c42bee96SIan Rogers        "EventCode": "0x23",
103*c42bee96SIan Rogers        "EventName": "L2_DBUS_BUSY_RD.SELF",
104*c42bee96SIan Rogers        "SampleAfterValue": "200000",
105*c42bee96SIan Rogers        "UMask": "0x40"
106*c42bee96SIan Rogers    },
107*c42bee96SIan Rogers    {
108*c42bee96SIan Rogers        "BriefDescription": "L2 cacheable instruction fetch requests",
109*c42bee96SIan Rogers        "EventCode": "0x28",
110*c42bee96SIan Rogers        "EventName": "L2_IFETCH.SELF.E_STATE",
111*c42bee96SIan Rogers        "SampleAfterValue": "200000",
112*c42bee96SIan Rogers        "UMask": "0x44"
113*c42bee96SIan Rogers    },
114*c42bee96SIan Rogers    {
115*c42bee96SIan Rogers        "BriefDescription": "L2 cacheable instruction fetch requests",
116*c42bee96SIan Rogers        "EventCode": "0x28",
117*c42bee96SIan Rogers        "EventName": "L2_IFETCH.SELF.I_STATE",
118*c42bee96SIan Rogers        "SampleAfterValue": "200000",
119*c42bee96SIan Rogers        "UMask": "0x41"
120*c42bee96SIan Rogers    },
121*c42bee96SIan Rogers    {
122*c42bee96SIan Rogers        "BriefDescription": "L2 cacheable instruction fetch requests",
123*c42bee96SIan Rogers        "EventCode": "0x28",
124*c42bee96SIan Rogers        "EventName": "L2_IFETCH.SELF.MESI",
125*c42bee96SIan Rogers        "SampleAfterValue": "200000",
126*c42bee96SIan Rogers        "UMask": "0x4f"
127*c42bee96SIan Rogers    },
128*c42bee96SIan Rogers    {
129*c42bee96SIan Rogers        "BriefDescription": "L2 cacheable instruction fetch requests",
130*c42bee96SIan Rogers        "EventCode": "0x28",
131*c42bee96SIan Rogers        "EventName": "L2_IFETCH.SELF.M_STATE",
132*c42bee96SIan Rogers        "SampleAfterValue": "200000",
133*c42bee96SIan Rogers        "UMask": "0x48"
134*c42bee96SIan Rogers    },
135*c42bee96SIan Rogers    {
136*c42bee96SIan Rogers        "BriefDescription": "L2 cacheable instruction fetch requests",
137*c42bee96SIan Rogers        "EventCode": "0x28",
138*c42bee96SIan Rogers        "EventName": "L2_IFETCH.SELF.S_STATE",
139*c42bee96SIan Rogers        "SampleAfterValue": "200000",
140*c42bee96SIan Rogers        "UMask": "0x42"
141*c42bee96SIan Rogers    },
142*c42bee96SIan Rogers    {
143*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
144*c42bee96SIan Rogers        "EventCode": "0x29",
145*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.ANY.E_STATE",
146*c42bee96SIan Rogers        "SampleAfterValue": "200000",
147*c42bee96SIan Rogers        "UMask": "0x74"
148*c42bee96SIan Rogers    },
149*c42bee96SIan Rogers    {
150*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
151*c42bee96SIan Rogers        "EventCode": "0x29",
152*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.ANY.I_STATE",
153*c42bee96SIan Rogers        "SampleAfterValue": "200000",
154*c42bee96SIan Rogers        "UMask": "0x71"
155*c42bee96SIan Rogers    },
156*c42bee96SIan Rogers    {
157*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
158*c42bee96SIan Rogers        "EventCode": "0x29",
159*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.ANY.MESI",
160*c42bee96SIan Rogers        "SampleAfterValue": "200000",
161*c42bee96SIan Rogers        "UMask": "0x7f"
162*c42bee96SIan Rogers    },
163*c42bee96SIan Rogers    {
164*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
165*c42bee96SIan Rogers        "EventCode": "0x29",
166*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.ANY.M_STATE",
167*c42bee96SIan Rogers        "SampleAfterValue": "200000",
168*c42bee96SIan Rogers        "UMask": "0x78"
169*c42bee96SIan Rogers    },
170*c42bee96SIan Rogers    {
171*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
172*c42bee96SIan Rogers        "EventCode": "0x29",
173*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.ANY.S_STATE",
174*c42bee96SIan Rogers        "SampleAfterValue": "200000",
175*c42bee96SIan Rogers        "UMask": "0x72"
176*c42bee96SIan Rogers    },
177*c42bee96SIan Rogers    {
178*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
179*c42bee96SIan Rogers        "EventCode": "0x29",
180*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.DEMAND.E_STATE",
181*c42bee96SIan Rogers        "SampleAfterValue": "200000",
182*c42bee96SIan Rogers        "UMask": "0x44"
183*c42bee96SIan Rogers    },
184*c42bee96SIan Rogers    {
185*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
186*c42bee96SIan Rogers        "EventCode": "0x29",
187*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.DEMAND.I_STATE",
188*c42bee96SIan Rogers        "SampleAfterValue": "200000",
189*c42bee96SIan Rogers        "UMask": "0x41"
190*c42bee96SIan Rogers    },
191*c42bee96SIan Rogers    {
192*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
193*c42bee96SIan Rogers        "EventCode": "0x29",
194*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.DEMAND.MESI",
195*c42bee96SIan Rogers        "SampleAfterValue": "200000",
196*c42bee96SIan Rogers        "UMask": "0x4f"
197*c42bee96SIan Rogers    },
198*c42bee96SIan Rogers    {
199*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
200*c42bee96SIan Rogers        "EventCode": "0x29",
201*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.DEMAND.M_STATE",
202*c42bee96SIan Rogers        "SampleAfterValue": "200000",
203*c42bee96SIan Rogers        "UMask": "0x48"
204*c42bee96SIan Rogers    },
205*c42bee96SIan Rogers    {
206*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
207*c42bee96SIan Rogers        "EventCode": "0x29",
208*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.DEMAND.S_STATE",
209*c42bee96SIan Rogers        "SampleAfterValue": "200000",
210*c42bee96SIan Rogers        "UMask": "0x42"
211*c42bee96SIan Rogers    },
212*c42bee96SIan Rogers    {
213*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
214*c42bee96SIan Rogers        "EventCode": "0x29",
215*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.PREFETCH.E_STATE",
216*c42bee96SIan Rogers        "SampleAfterValue": "200000",
217*c42bee96SIan Rogers        "UMask": "0x54"
218*c42bee96SIan Rogers    },
219*c42bee96SIan Rogers    {
220*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
221*c42bee96SIan Rogers        "EventCode": "0x29",
222*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.PREFETCH.I_STATE",
223*c42bee96SIan Rogers        "SampleAfterValue": "200000",
224*c42bee96SIan Rogers        "UMask": "0x51"
225*c42bee96SIan Rogers    },
226*c42bee96SIan Rogers    {
227*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
228*c42bee96SIan Rogers        "EventCode": "0x29",
229*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.PREFETCH.MESI",
230*c42bee96SIan Rogers        "SampleAfterValue": "200000",
231*c42bee96SIan Rogers        "UMask": "0x5f"
232*c42bee96SIan Rogers    },
233*c42bee96SIan Rogers    {
234*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
235*c42bee96SIan Rogers        "EventCode": "0x29",
236*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.PREFETCH.M_STATE",
237*c42bee96SIan Rogers        "SampleAfterValue": "200000",
238*c42bee96SIan Rogers        "UMask": "0x58"
239*c42bee96SIan Rogers    },
240*c42bee96SIan Rogers    {
241*c42bee96SIan Rogers        "BriefDescription": "L2 cache reads",
242*c42bee96SIan Rogers        "EventCode": "0x29",
243*c42bee96SIan Rogers        "EventName": "L2_LD.SELF.PREFETCH.S_STATE",
244*c42bee96SIan Rogers        "SampleAfterValue": "200000",
245*c42bee96SIan Rogers        "UMask": "0x52"
246*c42bee96SIan Rogers    },
247*c42bee96SIan Rogers    {
248*c42bee96SIan Rogers        "BriefDescription": "All read requests from L1 instruction and data caches",
249*c42bee96SIan Rogers        "EventCode": "0x2D",
250*c42bee96SIan Rogers        "EventName": "L2_LD_IFETCH.SELF.E_STATE",
251*c42bee96SIan Rogers        "SampleAfterValue": "200000",
252*c42bee96SIan Rogers        "UMask": "0x44"
253*c42bee96SIan Rogers    },
254*c42bee96SIan Rogers    {
255*c42bee96SIan Rogers        "BriefDescription": "All read requests from L1 instruction and data caches",
256*c42bee96SIan Rogers        "EventCode": "0x2D",
257*c42bee96SIan Rogers        "EventName": "L2_LD_IFETCH.SELF.I_STATE",
258*c42bee96SIan Rogers        "SampleAfterValue": "200000",
259*c42bee96SIan Rogers        "UMask": "0x41"
260*c42bee96SIan Rogers    },
261*c42bee96SIan Rogers    {
262*c42bee96SIan Rogers        "BriefDescription": "All read requests from L1 instruction and data caches",
263*c42bee96SIan Rogers        "EventCode": "0x2D",
264*c42bee96SIan Rogers        "EventName": "L2_LD_IFETCH.SELF.MESI",
265*c42bee96SIan Rogers        "SampleAfterValue": "200000",
266*c42bee96SIan Rogers        "UMask": "0x4f"
267*c42bee96SIan Rogers    },
268*c42bee96SIan Rogers    {
269*c42bee96SIan Rogers        "BriefDescription": "All read requests from L1 instruction and data caches",
270*c42bee96SIan Rogers        "EventCode": "0x2D",
271*c42bee96SIan Rogers        "EventName": "L2_LD_IFETCH.SELF.M_STATE",
272*c42bee96SIan Rogers        "SampleAfterValue": "200000",
273*c42bee96SIan Rogers        "UMask": "0x48"
274*c42bee96SIan Rogers    },
275*c42bee96SIan Rogers    {
276*c42bee96SIan Rogers        "BriefDescription": "All read requests from L1 instruction and data caches",
277*c42bee96SIan Rogers        "EventCode": "0x2D",
278*c42bee96SIan Rogers        "EventName": "L2_LD_IFETCH.SELF.S_STATE",
279*c42bee96SIan Rogers        "SampleAfterValue": "200000",
280*c42bee96SIan Rogers        "UMask": "0x42"
281*c42bee96SIan Rogers    },
282*c42bee96SIan Rogers    {
283*c42bee96SIan Rogers        "BriefDescription": "L2 cache misses.",
284*c42bee96SIan Rogers        "EventCode": "0x24",
285*c42bee96SIan Rogers        "EventName": "L2_LINES_IN.SELF.ANY",
286*c42bee96SIan Rogers        "SampleAfterValue": "200000",
287*c42bee96SIan Rogers        "UMask": "0x70"
288*c42bee96SIan Rogers    },
289*c42bee96SIan Rogers    {
290*c42bee96SIan Rogers        "BriefDescription": "L2 cache misses.",
291*c42bee96SIan Rogers        "EventCode": "0x24",
292*c42bee96SIan Rogers        "EventName": "L2_LINES_IN.SELF.DEMAND",
293*c42bee96SIan Rogers        "SampleAfterValue": "200000",
294*c42bee96SIan Rogers        "UMask": "0x40"
295*c42bee96SIan Rogers    },
296*c42bee96SIan Rogers    {
297*c42bee96SIan Rogers        "BriefDescription": "L2 cache misses.",
298*c42bee96SIan Rogers        "EventCode": "0x24",
299*c42bee96SIan Rogers        "EventName": "L2_LINES_IN.SELF.PREFETCH",
300*c42bee96SIan Rogers        "SampleAfterValue": "200000",
301*c42bee96SIan Rogers        "UMask": "0x50"
302*c42bee96SIan Rogers    },
303*c42bee96SIan Rogers    {
304*c42bee96SIan Rogers        "BriefDescription": "L2 cache lines evicted.",
305*c42bee96SIan Rogers        "EventCode": "0x26",
306*c42bee96SIan Rogers        "EventName": "L2_LINES_OUT.SELF.ANY",
307*c42bee96SIan Rogers        "SampleAfterValue": "200000",
308*c42bee96SIan Rogers        "UMask": "0x70"
309*c42bee96SIan Rogers    },
310*c42bee96SIan Rogers    {
311*c42bee96SIan Rogers        "BriefDescription": "L2 cache lines evicted.",
312*c42bee96SIan Rogers        "EventCode": "0x26",
313*c42bee96SIan Rogers        "EventName": "L2_LINES_OUT.SELF.DEMAND",
314*c42bee96SIan Rogers        "SampleAfterValue": "200000",
315*c42bee96SIan Rogers        "UMask": "0x40"
316*c42bee96SIan Rogers    },
317*c42bee96SIan Rogers    {
318*c42bee96SIan Rogers        "BriefDescription": "L2 cache lines evicted.",
319*c42bee96SIan Rogers        "EventCode": "0x26",
320*c42bee96SIan Rogers        "EventName": "L2_LINES_OUT.SELF.PREFETCH",
321*c42bee96SIan Rogers        "SampleAfterValue": "200000",
322*c42bee96SIan Rogers        "UMask": "0x50"
323*c42bee96SIan Rogers    },
324*c42bee96SIan Rogers    {
325*c42bee96SIan Rogers        "BriefDescription": "L2 locked accesses",
326*c42bee96SIan Rogers        "EventCode": "0x2B",
327*c42bee96SIan Rogers        "EventName": "L2_LOCK.SELF.E_STATE",
328*c42bee96SIan Rogers        "SampleAfterValue": "200000",
329*c42bee96SIan Rogers        "UMask": "0x44"
330*c42bee96SIan Rogers    },
331*c42bee96SIan Rogers    {
332*c42bee96SIan Rogers        "BriefDescription": "L2 locked accesses",
333*c42bee96SIan Rogers        "EventCode": "0x2B",
334*c42bee96SIan Rogers        "EventName": "L2_LOCK.SELF.I_STATE",
335*c42bee96SIan Rogers        "SampleAfterValue": "200000",
336*c42bee96SIan Rogers        "UMask": "0x41"
337*c42bee96SIan Rogers    },
338*c42bee96SIan Rogers    {
339*c42bee96SIan Rogers        "BriefDescription": "L2 locked accesses",
340*c42bee96SIan Rogers        "EventCode": "0x2B",
341*c42bee96SIan Rogers        "EventName": "L2_LOCK.SELF.MESI",
342*c42bee96SIan Rogers        "SampleAfterValue": "200000",
343*c42bee96SIan Rogers        "UMask": "0x4f"
344*c42bee96SIan Rogers    },
345*c42bee96SIan Rogers    {
346*c42bee96SIan Rogers        "BriefDescription": "L2 locked accesses",
347*c42bee96SIan Rogers        "EventCode": "0x2B",
348*c42bee96SIan Rogers        "EventName": "L2_LOCK.SELF.M_STATE",
349*c42bee96SIan Rogers        "SampleAfterValue": "200000",
350*c42bee96SIan Rogers        "UMask": "0x48"
351*c42bee96SIan Rogers    },
352*c42bee96SIan Rogers    {
353*c42bee96SIan Rogers        "BriefDescription": "L2 locked accesses",
354*c42bee96SIan Rogers        "EventCode": "0x2B",
355*c42bee96SIan Rogers        "EventName": "L2_LOCK.SELF.S_STATE",
356*c42bee96SIan Rogers        "SampleAfterValue": "200000",
357*c42bee96SIan Rogers        "UMask": "0x42"
358*c42bee96SIan Rogers    },
359*c42bee96SIan Rogers    {
360*c42bee96SIan Rogers        "BriefDescription": "L2 cache line modifications.",
361*c42bee96SIan Rogers        "EventCode": "0x25",
362*c42bee96SIan Rogers        "EventName": "L2_M_LINES_IN.SELF",
363*c42bee96SIan Rogers        "SampleAfterValue": "200000",
364*c42bee96SIan Rogers        "UMask": "0x40"
365*c42bee96SIan Rogers    },
366*c42bee96SIan Rogers    {
367*c42bee96SIan Rogers        "BriefDescription": "Modified lines evicted from the L2 cache",
368*c42bee96SIan Rogers        "EventCode": "0x27",
369*c42bee96SIan Rogers        "EventName": "L2_M_LINES_OUT.SELF.ANY",
370*c42bee96SIan Rogers        "SampleAfterValue": "200000",
371*c42bee96SIan Rogers        "UMask": "0x70"
372*c42bee96SIan Rogers    },
373*c42bee96SIan Rogers    {
374*c42bee96SIan Rogers        "BriefDescription": "Modified lines evicted from the L2 cache",
375*c42bee96SIan Rogers        "EventCode": "0x27",
376*c42bee96SIan Rogers        "EventName": "L2_M_LINES_OUT.SELF.DEMAND",
377*c42bee96SIan Rogers        "SampleAfterValue": "200000",
378*c42bee96SIan Rogers        "UMask": "0x40"
379*c42bee96SIan Rogers    },
380*c42bee96SIan Rogers    {
381*c42bee96SIan Rogers        "BriefDescription": "Modified lines evicted from the L2 cache",
382*c42bee96SIan Rogers        "EventCode": "0x27",
383*c42bee96SIan Rogers        "EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
384*c42bee96SIan Rogers        "SampleAfterValue": "200000",
385*c42bee96SIan Rogers        "UMask": "0x50"
386*c42bee96SIan Rogers    },
387*c42bee96SIan Rogers    {
388*c42bee96SIan Rogers        "BriefDescription": "Cycles no L2 cache requests are pending",
389*c42bee96SIan Rogers        "EventCode": "0x32",
390*c42bee96SIan Rogers        "EventName": "L2_NO_REQ.SELF",
391*c42bee96SIan Rogers        "SampleAfterValue": "200000",
392*c42bee96SIan Rogers        "UMask": "0x40"
393*c42bee96SIan Rogers    },
394*c42bee96SIan Rogers    {
395*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
396*c42bee96SIan Rogers        "EventCode": "0x30",
397*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
398*c42bee96SIan Rogers        "SampleAfterValue": "200000",
399*c42bee96SIan Rogers        "UMask": "0x74"
400*c42bee96SIan Rogers    },
401*c42bee96SIan Rogers    {
402*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
403*c42bee96SIan Rogers        "EventCode": "0x30",
404*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
405*c42bee96SIan Rogers        "SampleAfterValue": "200000",
406*c42bee96SIan Rogers        "UMask": "0x71"
407*c42bee96SIan Rogers    },
408*c42bee96SIan Rogers    {
409*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
410*c42bee96SIan Rogers        "EventCode": "0x30",
411*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
412*c42bee96SIan Rogers        "SampleAfterValue": "200000",
413*c42bee96SIan Rogers        "UMask": "0x7f"
414*c42bee96SIan Rogers    },
415*c42bee96SIan Rogers    {
416*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
417*c42bee96SIan Rogers        "EventCode": "0x30",
418*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
419*c42bee96SIan Rogers        "SampleAfterValue": "200000",
420*c42bee96SIan Rogers        "UMask": "0x78"
421*c42bee96SIan Rogers    },
422*c42bee96SIan Rogers    {
423*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
424*c42bee96SIan Rogers        "EventCode": "0x30",
425*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
426*c42bee96SIan Rogers        "SampleAfterValue": "200000",
427*c42bee96SIan Rogers        "UMask": "0x72"
428*c42bee96SIan Rogers    },
429*c42bee96SIan Rogers    {
430*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
431*c42bee96SIan Rogers        "EventCode": "0x30",
432*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
433*c42bee96SIan Rogers        "SampleAfterValue": "200000",
434*c42bee96SIan Rogers        "UMask": "0x44"
435*c42bee96SIan Rogers    },
436*c42bee96SIan Rogers    {
437*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
438*c42bee96SIan Rogers        "EventCode": "0x30",
439*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
440*c42bee96SIan Rogers        "SampleAfterValue": "200000",
441*c42bee96SIan Rogers        "UMask": "0x41"
442*c42bee96SIan Rogers    },
443*c42bee96SIan Rogers    {
444*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
445*c42bee96SIan Rogers        "EventCode": "0x30",
446*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
447*c42bee96SIan Rogers        "SampleAfterValue": "200000",
448*c42bee96SIan Rogers        "UMask": "0x4f"
449*c42bee96SIan Rogers    },
450*c42bee96SIan Rogers    {
451*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
452*c42bee96SIan Rogers        "EventCode": "0x30",
453*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
454*c42bee96SIan Rogers        "SampleAfterValue": "200000",
455*c42bee96SIan Rogers        "UMask": "0x48"
456*c42bee96SIan Rogers    },
457*c42bee96SIan Rogers    {
458*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
459*c42bee96SIan Rogers        "EventCode": "0x30",
460*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
461*c42bee96SIan Rogers        "SampleAfterValue": "200000",
462*c42bee96SIan Rogers        "UMask": "0x42"
463*c42bee96SIan Rogers    },
464*c42bee96SIan Rogers    {
465*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
466*c42bee96SIan Rogers        "EventCode": "0x30",
467*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
468*c42bee96SIan Rogers        "SampleAfterValue": "200000",
469*c42bee96SIan Rogers        "UMask": "0x54"
470*c42bee96SIan Rogers    },
471*c42bee96SIan Rogers    {
472*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
473*c42bee96SIan Rogers        "EventCode": "0x30",
474*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
475*c42bee96SIan Rogers        "SampleAfterValue": "200000",
476*c42bee96SIan Rogers        "UMask": "0x51"
477*c42bee96SIan Rogers    },
478*c42bee96SIan Rogers    {
479*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
480*c42bee96SIan Rogers        "EventCode": "0x30",
481*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
482*c42bee96SIan Rogers        "SampleAfterValue": "200000",
483*c42bee96SIan Rogers        "UMask": "0x5f"
484*c42bee96SIan Rogers    },
485*c42bee96SIan Rogers    {
486*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
487*c42bee96SIan Rogers        "EventCode": "0x30",
488*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
489*c42bee96SIan Rogers        "SampleAfterValue": "200000",
490*c42bee96SIan Rogers        "UMask": "0x58"
491*c42bee96SIan Rogers    },
492*c42bee96SIan Rogers    {
493*c42bee96SIan Rogers        "BriefDescription": "Rejected L2 cache requests",
494*c42bee96SIan Rogers        "EventCode": "0x30",
495*c42bee96SIan Rogers        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
496*c42bee96SIan Rogers        "SampleAfterValue": "200000",
497*c42bee96SIan Rogers        "UMask": "0x52"
498*c42bee96SIan Rogers    },
499*c42bee96SIan Rogers    {
500*c42bee96SIan Rogers        "BriefDescription": "L2 cache requests",
501*c42bee96SIan Rogers        "EventCode": "0x2E",
502*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.ANY.E_STATE",
503*c42bee96SIan Rogers        "SampleAfterValue": "200000",
504*c42bee96SIan Rogers        "UMask": "0x74"
505*c42bee96SIan Rogers    },
506*c42bee96SIan Rogers    {
507*c42bee96SIan Rogers        "BriefDescription": "L2 cache requests",
508*c42bee96SIan Rogers        "EventCode": "0x2E",
509*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.ANY.I_STATE",
510*c42bee96SIan Rogers        "SampleAfterValue": "200000",
511*c42bee96SIan Rogers        "UMask": "0x71"
512*c42bee96SIan Rogers    },
513*c42bee96SIan Rogers    {
514*c42bee96SIan Rogers        "BriefDescription": "L2 cache requests",
515*c42bee96SIan Rogers        "EventCode": "0x2E",
516*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.ANY.MESI",
517*c42bee96SIan Rogers        "SampleAfterValue": "200000",
518*c42bee96SIan Rogers        "UMask": "0x7f"
519*c42bee96SIan Rogers    },
520*c42bee96SIan Rogers    {
521*c42bee96SIan Rogers        "BriefDescription": "L2 cache requests",
522*c42bee96SIan Rogers        "EventCode": "0x2E",
523*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.ANY.M_STATE",
524*c42bee96SIan Rogers        "SampleAfterValue": "200000",
525*c42bee96SIan Rogers        "UMask": "0x78"
526*c42bee96SIan Rogers    },
527*c42bee96SIan Rogers    {
528*c42bee96SIan Rogers        "BriefDescription": "L2 cache requests",
529*c42bee96SIan Rogers        "EventCode": "0x2E",
530*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.ANY.S_STATE",
531*c42bee96SIan Rogers        "SampleAfterValue": "200000",
532*c42bee96SIan Rogers        "UMask": "0x72"
533*c42bee96SIan Rogers    },
534*c42bee96SIan Rogers    {
535*c42bee96SIan Rogers        "BriefDescription": "L2 cache requests",
536*c42bee96SIan Rogers        "EventCode": "0x2E",
537*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
538*c42bee96SIan Rogers        "SampleAfterValue": "200000",
539*c42bee96SIan Rogers        "UMask": "0x44"
540*c42bee96SIan Rogers    },
541*c42bee96SIan Rogers    {
542*c42bee96SIan Rogers        "BriefDescription": "L2 cache demand requests from this core that missed the L2",
543*c42bee96SIan Rogers        "EventCode": "0x2E",
544*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
545*c42bee96SIan Rogers        "SampleAfterValue": "200000",
546*c42bee96SIan Rogers        "UMask": "0x41"
547*c42bee96SIan Rogers    },
548*c42bee96SIan Rogers    {
549*c42bee96SIan Rogers        "BriefDescription": "L2 cache demand requests from this core",
550*c42bee96SIan Rogers        "EventCode": "0x2E",
551*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.DEMAND.MESI",
552*c42bee96SIan Rogers        "SampleAfterValue": "200000",
553*c42bee96SIan Rogers        "UMask": "0x4f"
554*c42bee96SIan Rogers    },
555*c42bee96SIan Rogers    {
556*c42bee96SIan Rogers        "BriefDescription": "L2 cache requests",
557*c42bee96SIan Rogers        "EventCode": "0x2E",
558*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
559*c42bee96SIan Rogers        "SampleAfterValue": "200000",
560*c42bee96SIan Rogers        "UMask": "0x48"
561*c42bee96SIan Rogers    },
562*c42bee96SIan Rogers    {
563*c42bee96SIan Rogers        "BriefDescription": "L2 cache requests",
564*c42bee96SIan Rogers        "EventCode": "0x2E",
565*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
566*c42bee96SIan Rogers        "SampleAfterValue": "200000",
567*c42bee96SIan Rogers        "UMask": "0x42"
568*c42bee96SIan Rogers    },
569*c42bee96SIan Rogers    {
570*c42bee96SIan Rogers        "BriefDescription": "L2 cache requests",
571*c42bee96SIan Rogers        "EventCode": "0x2E",
572*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
573*c42bee96SIan Rogers        "SampleAfterValue": "200000",
574*c42bee96SIan Rogers        "UMask": "0x54"
575*c42bee96SIan Rogers    },
576*c42bee96SIan Rogers    {
577*c42bee96SIan Rogers        "BriefDescription": "L2 cache requests",
578*c42bee96SIan Rogers        "EventCode": "0x2E",
579*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
580*c42bee96SIan Rogers        "SampleAfterValue": "200000",
581*c42bee96SIan Rogers        "UMask": "0x51"
582*c42bee96SIan Rogers    },
583*c42bee96SIan Rogers    {
584*c42bee96SIan Rogers        "BriefDescription": "L2 cache requests",
585*c42bee96SIan Rogers        "EventCode": "0x2E",
586*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
587*c42bee96SIan Rogers        "SampleAfterValue": "200000",
588*c42bee96SIan Rogers        "UMask": "0x5f"
589*c42bee96SIan Rogers    },
590*c42bee96SIan Rogers    {
591*c42bee96SIan Rogers        "BriefDescription": "L2 cache requests",
592*c42bee96SIan Rogers        "EventCode": "0x2E",
593*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
594*c42bee96SIan Rogers        "SampleAfterValue": "200000",
595*c42bee96SIan Rogers        "UMask": "0x58"
596*c42bee96SIan Rogers    },
597*c42bee96SIan Rogers    {
598*c42bee96SIan Rogers        "BriefDescription": "L2 cache requests",
599*c42bee96SIan Rogers        "EventCode": "0x2E",
600*c42bee96SIan Rogers        "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
601*c42bee96SIan Rogers        "SampleAfterValue": "200000",
602*c42bee96SIan Rogers        "UMask": "0x52"
603*c42bee96SIan Rogers    },
604*c42bee96SIan Rogers    {
605*c42bee96SIan Rogers        "BriefDescription": "L2 store requests",
606*c42bee96SIan Rogers        "EventCode": "0x2A",
607*c42bee96SIan Rogers        "EventName": "L2_ST.SELF.E_STATE",
608*c42bee96SIan Rogers        "SampleAfterValue": "200000",
609*c42bee96SIan Rogers        "UMask": "0x44"
610*c42bee96SIan Rogers    },
611*c42bee96SIan Rogers    {
612*c42bee96SIan Rogers        "BriefDescription": "L2 store requests",
613*c42bee96SIan Rogers        "EventCode": "0x2A",
614*c42bee96SIan Rogers        "EventName": "L2_ST.SELF.I_STATE",
615*c42bee96SIan Rogers        "SampleAfterValue": "200000",
616*c42bee96SIan Rogers        "UMask": "0x41"
617*c42bee96SIan Rogers    },
618*c42bee96SIan Rogers    {
619*c42bee96SIan Rogers        "BriefDescription": "L2 store requests",
620*c42bee96SIan Rogers        "EventCode": "0x2A",
621*c42bee96SIan Rogers        "EventName": "L2_ST.SELF.MESI",
622*c42bee96SIan Rogers        "SampleAfterValue": "200000",
623*c42bee96SIan Rogers        "UMask": "0x4f"
624*c42bee96SIan Rogers    },
625*c42bee96SIan Rogers    {
626*c42bee96SIan Rogers        "BriefDescription": "L2 store requests",
627*c42bee96SIan Rogers        "EventCode": "0x2A",
628*c42bee96SIan Rogers        "EventName": "L2_ST.SELF.M_STATE",
629*c42bee96SIan Rogers        "SampleAfterValue": "200000",
630*c42bee96SIan Rogers        "UMask": "0x48"
631*c42bee96SIan Rogers    },
632*c42bee96SIan Rogers    {
633*c42bee96SIan Rogers        "BriefDescription": "L2 store requests",
634*c42bee96SIan Rogers        "EventCode": "0x2A",
635*c42bee96SIan Rogers        "EventName": "L2_ST.SELF.S_STATE",
636*c42bee96SIan Rogers        "SampleAfterValue": "200000",
637*c42bee96SIan Rogers        "UMask": "0x42"
638*c42bee96SIan Rogers    },
639*c42bee96SIan Rogers    {
640*c42bee96SIan Rogers        "BriefDescription": "Retired loads that hit the L2 cache (precise event).",
641*c42bee96SIan Rogers        "EventCode": "0xCB",
642052aa3ccSAndi Kleen        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
643052aa3ccSAndi Kleen        "SampleAfterValue": "200000",
644*c42bee96SIan Rogers        "UMask": "0x1"
645052aa3ccSAndi Kleen    },
646052aa3ccSAndi Kleen    {
647*c42bee96SIan Rogers        "BriefDescription": "Retired loads that miss the L2 cache",
648*c42bee96SIan Rogers        "EventCode": "0xCB",
649052aa3ccSAndi Kleen        "EventName": "MEM_LOAD_RETIRED.L2_MISS",
650052aa3ccSAndi Kleen        "SampleAfterValue": "10000",
651*c42bee96SIan Rogers        "UMask": "0x2"
652052aa3ccSAndi Kleen    }
653052aa3ccSAndi Kleen]
654