1*eafcbb68SZhengjun Xing[ 2*eafcbb68SZhengjun Xing { 3*eafcbb68SZhengjun Xing "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.", 4*eafcbb68SZhengjun Xing "EventCode": "0x08", 5*eafcbb68SZhengjun Xing "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 6*eafcbb68SZhengjun Xing "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", 7*eafcbb68SZhengjun Xing "SampleAfterValue": "200003", 8*eafcbb68SZhengjun Xing "UMask": "0xe" 9*eafcbb68SZhengjun Xing }, 10*eafcbb68SZhengjun Xing { 11*eafcbb68SZhengjun Xing "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.", 12*eafcbb68SZhengjun Xing "EventCode": "0x49", 13*eafcbb68SZhengjun Xing "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 14*eafcbb68SZhengjun Xing "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", 15*eafcbb68SZhengjun Xing "SampleAfterValue": "2000003", 16*eafcbb68SZhengjun Xing "UMask": "0xe" 17*eafcbb68SZhengjun Xing }, 18*eafcbb68SZhengjun Xing { 19*eafcbb68SZhengjun Xing "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", 20*eafcbb68SZhengjun Xing "EventCode": "0x85", 21*eafcbb68SZhengjun Xing "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", 22*eafcbb68SZhengjun Xing "SampleAfterValue": "1000003", 23*eafcbb68SZhengjun Xing "UMask": "0x1" 24*eafcbb68SZhengjun Xing }, 25*eafcbb68SZhengjun Xing { 26*eafcbb68SZhengjun Xing "BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.", 27*eafcbb68SZhengjun Xing "EventCode": "0x85", 28*eafcbb68SZhengjun Xing "EventName": "ITLB_MISSES.PDE_CACHE_MISS", 29*eafcbb68SZhengjun Xing "SampleAfterValue": "2000003", 30*eafcbb68SZhengjun Xing "UMask": "0x80" 31*eafcbb68SZhengjun Xing }, 32*eafcbb68SZhengjun Xing { 33*eafcbb68SZhengjun Xing "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", 34*eafcbb68SZhengjun Xing "EventCode": "0x85", 35*eafcbb68SZhengjun Xing "EventName": "ITLB_MISSES.WALK_COMPLETED", 36*eafcbb68SZhengjun Xing "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", 37*eafcbb68SZhengjun Xing "SampleAfterValue": "200003", 38*eafcbb68SZhengjun Xing "UMask": "0xe" 39*eafcbb68SZhengjun Xing }, 40*eafcbb68SZhengjun Xing { 41*eafcbb68SZhengjun Xing "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.", 42*eafcbb68SZhengjun Xing "EventCode": "0x05", 43*eafcbb68SZhengjun Xing "EventName": "LD_HEAD.DTLB_MISS_AT_RET", 44*eafcbb68SZhengjun Xing "SampleAfterValue": "1000003", 45*eafcbb68SZhengjun Xing "UMask": "0x90" 46*eafcbb68SZhengjun Xing } 47*eafcbb68SZhengjun Xing] 48