1ea8d0ed6SKan Liang // SPDX-License-Identifier: GPL-2.0 2ea8d0ed6SKan Liang #include <stdio.h> 3eb39bf32SRavi Bangoria #include <stdlib.h> 4ea8d0ed6SKan Liang #include "util/evsel.h" 5eb39bf32SRavi Bangoria #include "util/env.h" 6*d98079c0SIan Rogers #include "util/pmu.h" 7eb39bf32SRavi Bangoria #include "linux/string.h" 8ea8d0ed6SKan Liang 9ea8d0ed6SKan Liang void arch_evsel__set_sample_weight(struct evsel *evsel) 10ea8d0ed6SKan Liang { 11ea8d0ed6SKan Liang evsel__set_sample_bit(evsel, WEIGHT_STRUCT); 12ea8d0ed6SKan Liang } 13eb39bf32SRavi Bangoria 14eb39bf32SRavi Bangoria void arch_evsel__fixup_new_cycles(struct perf_event_attr *attr) 15eb39bf32SRavi Bangoria { 16eb39bf32SRavi Bangoria struct perf_env env = { .total_mem = 0, } ; 17eb39bf32SRavi Bangoria 18eb39bf32SRavi Bangoria if (!perf_env__cpuid(&env)) 19eb39bf32SRavi Bangoria return; 20eb39bf32SRavi Bangoria 21eb39bf32SRavi Bangoria /* 22eb39bf32SRavi Bangoria * On AMD, precise cycles event sampling internally uses IBS pmu. 23eb39bf32SRavi Bangoria * But IBS does not have filtering capabilities and perf by default 24eb39bf32SRavi Bangoria * sets exclude_guest = 1. This makes IBS pmu event init fail and 25eb39bf32SRavi Bangoria * thus perf ends up doing non-precise sampling. Avoid it by clearing 26eb39bf32SRavi Bangoria * exclude_guest. 27eb39bf32SRavi Bangoria */ 28eb39bf32SRavi Bangoria if (env.cpuid && strstarts(env.cpuid, "AuthenticAMD")) 29eb39bf32SRavi Bangoria attr->exclude_guest = 0; 30eb39bf32SRavi Bangoria 31eb39bf32SRavi Bangoria free(env.cpuid); 32eb39bf32SRavi Bangoria } 33*d98079c0SIan Rogers 34*d98079c0SIan Rogers bool arch_evsel__must_be_in_group(const struct evsel *evsel) 35*d98079c0SIan Rogers { 36*d98079c0SIan Rogers if ((evsel->pmu_name && strcmp(evsel->pmu_name, "cpu")) || 37*d98079c0SIan Rogers !pmu_have_event("cpu", "slots")) 38*d98079c0SIan Rogers return false; 39*d98079c0SIan Rogers 40*d98079c0SIan Rogers return evsel->name && 41*d98079c0SIan Rogers (!strcasecmp(evsel->name, "slots") || 42*d98079c0SIan Rogers strcasestr(evsel->name, "topdown")); 43*d98079c0SIan Rogers } 44