1271661c1SWilly Tarreau /* SPDX-License-Identifier: LGPL-2.1 OR MIT */
2271661c1SWilly Tarreau /*
3271661c1SWilly Tarreau * ARM specific definitions for NOLIBC
4271661c1SWilly Tarreau * Copyright (C) 2017-2022 Willy Tarreau <w@1wt.eu>
5271661c1SWilly Tarreau */
6271661c1SWilly Tarreau
7271661c1SWilly Tarreau #ifndef _NOLIBC_ARCH_ARM_H
8271661c1SWilly Tarreau #define _NOLIBC_ARCH_ARM_H
9271661c1SWilly Tarreau
10818924d1SThomas Weißschuh #include "compiler.h"
11*61f98807SZhangjin Wu #include "crt.h"
12818924d1SThomas Weißschuh
13271661c1SWilly Tarreau /* Syscalls for ARM in ARM or Thumb modes :
14271661c1SWilly Tarreau * - registers are 32-bit
15271661c1SWilly Tarreau * - stack is 8-byte aligned
16271661c1SWilly Tarreau * ( http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka4127.html)
17271661c1SWilly Tarreau * - syscall number is passed in r7
18271661c1SWilly Tarreau * - arguments are in r0, r1, r2, r3, r4, r5
19271661c1SWilly Tarreau * - the system call is performed by calling svc #0
20271661c1SWilly Tarreau * - syscall return comes in r0.
21271661c1SWilly Tarreau * - only lr is clobbered.
22271661c1SWilly Tarreau * - the arguments are cast to long and assigned into the target registers
23271661c1SWilly Tarreau * which are then simply passed as registers to the asm code, so that we
24271661c1SWilly Tarreau * don't have to experience issues with register constraints.
25271661c1SWilly Tarreau * - the syscall number is always specified last in order to allow to force
26271661c1SWilly Tarreau * some registers before (gcc refuses a %-register at the last position).
275a51b6deSWilly Tarreau * - in thumb mode without -fomit-frame-pointer, r7 is also used to store the
285a51b6deSWilly Tarreau * frame pointer, and we cannot directly assign it as a register variable,
295a51b6deSWilly Tarreau * nor can we clobber it. Instead we assign the r6 register and swap it
305a51b6deSWilly Tarreau * with r7 before calling svc, and r6 is marked as clobbered.
315a51b6deSWilly Tarreau * We're just using any regular register which we assign to r7 after saving
325a51b6deSWilly Tarreau * it.
33271661c1SWilly Tarreau *
34271661c1SWilly Tarreau * Also, ARM supports the old_select syscall if newselect is not available
35271661c1SWilly Tarreau */
36271661c1SWilly Tarreau #define __ARCH_WANT_SYS_OLD_SELECT
37271661c1SWilly Tarreau
385a51b6deSWilly Tarreau #if (defined(__THUMBEB__) || defined(__THUMBEL__)) && \
395a51b6deSWilly Tarreau !defined(NOLIBC_OMIT_FRAME_POINTER)
405a51b6deSWilly Tarreau /* swap r6,r7 needed in Thumb mode since we can't use nor clobber r7 */
415a51b6deSWilly Tarreau #define _NOLIBC_SYSCALL_REG "r6"
425a51b6deSWilly Tarreau #define _NOLIBC_THUMB_SET_R7 "eor r7, r6\neor r6, r7\neor r7, r6\n"
435a51b6deSWilly Tarreau #define _NOLIBC_THUMB_RESTORE_R7 "mov r7, r6\n"
445a51b6deSWilly Tarreau
455a51b6deSWilly Tarreau #else /* we're in ARM mode */
465a51b6deSWilly Tarreau /* in Arm mode we can directly use r7 */
475a51b6deSWilly Tarreau #define _NOLIBC_SYSCALL_REG "r7"
485a51b6deSWilly Tarreau #define _NOLIBC_THUMB_SET_R7 ""
495a51b6deSWilly Tarreau #define _NOLIBC_THUMB_RESTORE_R7 ""
505a51b6deSWilly Tarreau
515a51b6deSWilly Tarreau #endif /* end THUMB */
525a51b6deSWilly Tarreau
53271661c1SWilly Tarreau #define my_syscall0(num) \
54271661c1SWilly Tarreau ({ \
555a51b6deSWilly Tarreau register long _num __asm__(_NOLIBC_SYSCALL_REG) = (num); \
5637d62758SAmmar Faizi register long _arg1 __asm__ ("r0"); \
57271661c1SWilly Tarreau \
5837d62758SAmmar Faizi __asm__ volatile ( \
595a51b6deSWilly Tarreau _NOLIBC_THUMB_SET_R7 \
60271661c1SWilly Tarreau "svc #0\n" \
615a51b6deSWilly Tarreau _NOLIBC_THUMB_RESTORE_R7 \
625a51b6deSWilly Tarreau : "=r"(_arg1), "=r"(_num) \
635a51b6deSWilly Tarreau : "r"(_arg1), \
645a51b6deSWilly Tarreau "r"(_num) \
65271661c1SWilly Tarreau : "memory", "cc", "lr" \
66271661c1SWilly Tarreau ); \
67271661c1SWilly Tarreau _arg1; \
68271661c1SWilly Tarreau })
69271661c1SWilly Tarreau
70271661c1SWilly Tarreau #define my_syscall1(num, arg1) \
71271661c1SWilly Tarreau ({ \
725a51b6deSWilly Tarreau register long _num __asm__(_NOLIBC_SYSCALL_REG) = (num); \
7337d62758SAmmar Faizi register long _arg1 __asm__ ("r0") = (long)(arg1); \
74271661c1SWilly Tarreau \
7537d62758SAmmar Faizi __asm__ volatile ( \
765a51b6deSWilly Tarreau _NOLIBC_THUMB_SET_R7 \
77271661c1SWilly Tarreau "svc #0\n" \
785a51b6deSWilly Tarreau _NOLIBC_THUMB_RESTORE_R7 \
795a51b6deSWilly Tarreau : "=r"(_arg1), "=r" (_num) \
80271661c1SWilly Tarreau : "r"(_arg1), \
81271661c1SWilly Tarreau "r"(_num) \
82271661c1SWilly Tarreau : "memory", "cc", "lr" \
83271661c1SWilly Tarreau ); \
84271661c1SWilly Tarreau _arg1; \
85271661c1SWilly Tarreau })
86271661c1SWilly Tarreau
87271661c1SWilly Tarreau #define my_syscall2(num, arg1, arg2) \
88271661c1SWilly Tarreau ({ \
895a51b6deSWilly Tarreau register long _num __asm__(_NOLIBC_SYSCALL_REG) = (num); \
9037d62758SAmmar Faizi register long _arg1 __asm__ ("r0") = (long)(arg1); \
9137d62758SAmmar Faizi register long _arg2 __asm__ ("r1") = (long)(arg2); \
92271661c1SWilly Tarreau \
9337d62758SAmmar Faizi __asm__ volatile ( \
945a51b6deSWilly Tarreau _NOLIBC_THUMB_SET_R7 \
95271661c1SWilly Tarreau "svc #0\n" \
965a51b6deSWilly Tarreau _NOLIBC_THUMB_RESTORE_R7 \
975a51b6deSWilly Tarreau : "=r"(_arg1), "=r" (_num) \
98271661c1SWilly Tarreau : "r"(_arg1), "r"(_arg2), \
99271661c1SWilly Tarreau "r"(_num) \
100271661c1SWilly Tarreau : "memory", "cc", "lr" \
101271661c1SWilly Tarreau ); \
102271661c1SWilly Tarreau _arg1; \
103271661c1SWilly Tarreau })
104271661c1SWilly Tarreau
105271661c1SWilly Tarreau #define my_syscall3(num, arg1, arg2, arg3) \
106271661c1SWilly Tarreau ({ \
1075a51b6deSWilly Tarreau register long _num __asm__(_NOLIBC_SYSCALL_REG) = (num); \
10837d62758SAmmar Faizi register long _arg1 __asm__ ("r0") = (long)(arg1); \
10937d62758SAmmar Faizi register long _arg2 __asm__ ("r1") = (long)(arg2); \
11037d62758SAmmar Faizi register long _arg3 __asm__ ("r2") = (long)(arg3); \
111271661c1SWilly Tarreau \
11237d62758SAmmar Faizi __asm__ volatile ( \
1135a51b6deSWilly Tarreau _NOLIBC_THUMB_SET_R7 \
114271661c1SWilly Tarreau "svc #0\n" \
1155a51b6deSWilly Tarreau _NOLIBC_THUMB_RESTORE_R7 \
1165a51b6deSWilly Tarreau : "=r"(_arg1), "=r" (_num) \
117271661c1SWilly Tarreau : "r"(_arg1), "r"(_arg2), "r"(_arg3), \
118271661c1SWilly Tarreau "r"(_num) \
119271661c1SWilly Tarreau : "memory", "cc", "lr" \
120271661c1SWilly Tarreau ); \
121271661c1SWilly Tarreau _arg1; \
122271661c1SWilly Tarreau })
123271661c1SWilly Tarreau
124271661c1SWilly Tarreau #define my_syscall4(num, arg1, arg2, arg3, arg4) \
125271661c1SWilly Tarreau ({ \
1265a51b6deSWilly Tarreau register long _num __asm__(_NOLIBC_SYSCALL_REG) = (num); \
12737d62758SAmmar Faizi register long _arg1 __asm__ ("r0") = (long)(arg1); \
12837d62758SAmmar Faizi register long _arg2 __asm__ ("r1") = (long)(arg2); \
12937d62758SAmmar Faizi register long _arg3 __asm__ ("r2") = (long)(arg3); \
13037d62758SAmmar Faizi register long _arg4 __asm__ ("r3") = (long)(arg4); \
131271661c1SWilly Tarreau \
13237d62758SAmmar Faizi __asm__ volatile ( \
1335a51b6deSWilly Tarreau _NOLIBC_THUMB_SET_R7 \
134271661c1SWilly Tarreau "svc #0\n" \
1355a51b6deSWilly Tarreau _NOLIBC_THUMB_RESTORE_R7 \
1365a51b6deSWilly Tarreau : "=r"(_arg1), "=r" (_num) \
137271661c1SWilly Tarreau : "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), \
138271661c1SWilly Tarreau "r"(_num) \
139271661c1SWilly Tarreau : "memory", "cc", "lr" \
140271661c1SWilly Tarreau ); \
141271661c1SWilly Tarreau _arg1; \
142271661c1SWilly Tarreau })
143271661c1SWilly Tarreau
144271661c1SWilly Tarreau #define my_syscall5(num, arg1, arg2, arg3, arg4, arg5) \
145271661c1SWilly Tarreau ({ \
1465a51b6deSWilly Tarreau register long _num __asm__(_NOLIBC_SYSCALL_REG) = (num); \
14737d62758SAmmar Faizi register long _arg1 __asm__ ("r0") = (long)(arg1); \
14837d62758SAmmar Faizi register long _arg2 __asm__ ("r1") = (long)(arg2); \
14937d62758SAmmar Faizi register long _arg3 __asm__ ("r2") = (long)(arg3); \
15037d62758SAmmar Faizi register long _arg4 __asm__ ("r3") = (long)(arg4); \
15137d62758SAmmar Faizi register long _arg5 __asm__ ("r4") = (long)(arg5); \
152271661c1SWilly Tarreau \
15337d62758SAmmar Faizi __asm__ volatile ( \
1545a51b6deSWilly Tarreau _NOLIBC_THUMB_SET_R7 \
155271661c1SWilly Tarreau "svc #0\n" \
1565a51b6deSWilly Tarreau _NOLIBC_THUMB_RESTORE_R7 \
1575a51b6deSWilly Tarreau : "=r"(_arg1), "=r" (_num) \
158271661c1SWilly Tarreau : "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5), \
159271661c1SWilly Tarreau "r"(_num) \
160271661c1SWilly Tarreau : "memory", "cc", "lr" \
161271661c1SWilly Tarreau ); \
162271661c1SWilly Tarreau _arg1; \
163271661c1SWilly Tarreau })
164271661c1SWilly Tarreau
165646ff7c7SZhangjin Wu #define my_syscall6(num, arg1, arg2, arg3, arg4, arg5, arg6) \
166646ff7c7SZhangjin Wu ({ \
167646ff7c7SZhangjin Wu register long _num __asm__(_NOLIBC_SYSCALL_REG) = (num); \
168646ff7c7SZhangjin Wu register long _arg1 __asm__ ("r0") = (long)(arg1); \
169646ff7c7SZhangjin Wu register long _arg2 __asm__ ("r1") = (long)(arg2); \
170646ff7c7SZhangjin Wu register long _arg3 __asm__ ("r2") = (long)(arg3); \
171646ff7c7SZhangjin Wu register long _arg4 __asm__ ("r3") = (long)(arg4); \
172646ff7c7SZhangjin Wu register long _arg5 __asm__ ("r4") = (long)(arg5); \
173646ff7c7SZhangjin Wu register long _arg6 __asm__ ("r5") = (long)(arg6); \
174646ff7c7SZhangjin Wu \
175646ff7c7SZhangjin Wu __asm__ volatile ( \
176646ff7c7SZhangjin Wu _NOLIBC_THUMB_SET_R7 \
177646ff7c7SZhangjin Wu "svc #0\n" \
178646ff7c7SZhangjin Wu _NOLIBC_THUMB_RESTORE_R7 \
179646ff7c7SZhangjin Wu : "=r"(_arg1), "=r" (_num) \
180646ff7c7SZhangjin Wu : "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5), \
181646ff7c7SZhangjin Wu "r"(_arg6), "r"(_num) \
182646ff7c7SZhangjin Wu : "memory", "cc", "lr" \
183646ff7c7SZhangjin Wu ); \
184646ff7c7SZhangjin Wu _arg1; \
185646ff7c7SZhangjin Wu })
186646ff7c7SZhangjin Wu
187271661c1SWilly Tarreau /* startup code */
_start(void)188bff60150SZhangjin Wu void __attribute__((weak, noreturn, optimize("Os", "omit-frame-pointer"))) __no_stack_protector _start(void)
1897f854858SWilly Tarreau {
1907f854858SWilly Tarreau __asm__ volatile (
191*61f98807SZhangjin Wu "mov %r0, sp\n" /* save stack pointer to %r0, as arg1 of _start_c */
192*61f98807SZhangjin Wu "and ip, %r0, #-8\n" /* sp must be 8-byte aligned in the callee */
193*61f98807SZhangjin Wu "mov sp, ip\n"
194*61f98807SZhangjin Wu "bl _start_c\n" /* transfer to c runtime */
1957f854858SWilly Tarreau );
1967f854858SWilly Tarreau __builtin_unreachable();
1977f854858SWilly Tarreau }
198271661c1SWilly Tarreau
199fddc8f81SThomas Weißschuh #endif /* _NOLIBC_ARCH_ARM_H */
200