xref: /openbmc/linux/sound/soc/ux500/ux500_msp_dai.c (revision f61ab093828df646b5df35f244577859efe4329c)
13592b7f6SOla Lilja /*
23592b7f6SOla Lilja  * Copyright (C) ST-Ericsson SA 2012
33592b7f6SOla Lilja  *
43592b7f6SOla Lilja  * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
53592b7f6SOla Lilja  *         Roger Nilsson <roger.xr.nilsson@stericsson.com>
63592b7f6SOla Lilja  *         for ST-Ericsson.
73592b7f6SOla Lilja  *
83592b7f6SOla Lilja  * License terms:
93592b7f6SOla Lilja  *
103592b7f6SOla Lilja  * This program is free software; you can redistribute it and/or modify
113592b7f6SOla Lilja  * it under the terms of the GNU General Public License version 2 as published
123592b7f6SOla Lilja  * by the Free Software Foundation.
133592b7f6SOla Lilja  */
143592b7f6SOla Lilja 
153592b7f6SOla Lilja #include <linux/module.h>
163592b7f6SOla Lilja #include <linux/slab.h>
173592b7f6SOla Lilja #include <linux/bitops.h>
183592b7f6SOla Lilja #include <linux/platform_device.h>
193592b7f6SOla Lilja #include <linux/clk.h>
203592b7f6SOla Lilja #include <linux/regulator/consumer.h>
213592b7f6SOla Lilja #include <linux/mfd/dbx500-prcmu.h>
223592b7f6SOla Lilja 
233592b7f6SOla Lilja #include <mach/hardware.h>
24aa50fe55SLee Jones #include <mach/msp.h>
253592b7f6SOla Lilja 
263592b7f6SOla Lilja #include <sound/soc.h>
273592b7f6SOla Lilja #include <sound/soc-dai.h>
283592b7f6SOla Lilja 
293592b7f6SOla Lilja #include "ux500_msp_i2s.h"
303592b7f6SOla Lilja #include "ux500_msp_dai.h"
313592b7f6SOla Lilja 
323592b7f6SOla Lilja static int setup_pcm_multichan(struct snd_soc_dai *dai,
333592b7f6SOla Lilja 			struct ux500_msp_config *msp_config)
343592b7f6SOla Lilja {
353592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
363592b7f6SOla Lilja 	struct msp_multichannel_config *multi =
373592b7f6SOla Lilja 					&msp_config->multichannel_config;
383592b7f6SOla Lilja 
393592b7f6SOla Lilja 	if (drvdata->slots > 1) {
403592b7f6SOla Lilja 		msp_config->multichannel_configured = 1;
413592b7f6SOla Lilja 
423592b7f6SOla Lilja 		multi->tx_multichannel_enable = true;
433592b7f6SOla Lilja 		multi->rx_multichannel_enable = true;
443592b7f6SOla Lilja 		multi->rx_comparison_enable_mode = MSP_COMPARISON_DISABLED;
453592b7f6SOla Lilja 
463592b7f6SOla Lilja 		multi->tx_channel_0_enable = drvdata->tx_mask;
473592b7f6SOla Lilja 		multi->tx_channel_1_enable = 0;
483592b7f6SOla Lilja 		multi->tx_channel_2_enable = 0;
493592b7f6SOla Lilja 		multi->tx_channel_3_enable = 0;
503592b7f6SOla Lilja 
513592b7f6SOla Lilja 		multi->rx_channel_0_enable = drvdata->rx_mask;
523592b7f6SOla Lilja 		multi->rx_channel_1_enable = 0;
533592b7f6SOla Lilja 		multi->rx_channel_2_enable = 0;
543592b7f6SOla Lilja 		multi->rx_channel_3_enable = 0;
553592b7f6SOla Lilja 
563592b7f6SOla Lilja 		dev_dbg(dai->dev,
573592b7f6SOla Lilja 			"%s: Multichannel enabled. Slots: %d, TX: %u, RX: %u\n",
583592b7f6SOla Lilja 			__func__, drvdata->slots, multi->tx_channel_0_enable,
593592b7f6SOla Lilja 			multi->rx_channel_0_enable);
603592b7f6SOla Lilja 	}
613592b7f6SOla Lilja 
623592b7f6SOla Lilja 	return 0;
633592b7f6SOla Lilja }
643592b7f6SOla Lilja 
653592b7f6SOla Lilja static int setup_frameper(struct snd_soc_dai *dai, unsigned int rate,
663592b7f6SOla Lilja 			struct msp_protdesc *prot_desc)
673592b7f6SOla Lilja {
683592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
693592b7f6SOla Lilja 
703592b7f6SOla Lilja 	switch (drvdata->slots) {
713592b7f6SOla Lilja 	case 1:
723592b7f6SOla Lilja 		switch (rate) {
733592b7f6SOla Lilja 		case 8000:
743592b7f6SOla Lilja 			prot_desc->frame_period =
753592b7f6SOla Lilja 				FRAME_PER_SINGLE_SLOT_8_KHZ;
763592b7f6SOla Lilja 			break;
773592b7f6SOla Lilja 
783592b7f6SOla Lilja 		case 16000:
793592b7f6SOla Lilja 			prot_desc->frame_period =
803592b7f6SOla Lilja 				FRAME_PER_SINGLE_SLOT_16_KHZ;
813592b7f6SOla Lilja 			break;
823592b7f6SOla Lilja 
833592b7f6SOla Lilja 		case 44100:
843592b7f6SOla Lilja 			prot_desc->frame_period =
853592b7f6SOla Lilja 				FRAME_PER_SINGLE_SLOT_44_1_KHZ;
863592b7f6SOla Lilja 			break;
873592b7f6SOla Lilja 
883592b7f6SOla Lilja 		case 48000:
893592b7f6SOla Lilja 			prot_desc->frame_period =
903592b7f6SOla Lilja 				FRAME_PER_SINGLE_SLOT_48_KHZ;
913592b7f6SOla Lilja 			break;
923592b7f6SOla Lilja 
933592b7f6SOla Lilja 		default:
943592b7f6SOla Lilja 			dev_err(dai->dev,
953592b7f6SOla Lilja 				"%s: Error: Unsupported sample-rate (freq = %d)!\n",
963592b7f6SOla Lilja 				__func__, rate);
973592b7f6SOla Lilja 			return -EINVAL;
983592b7f6SOla Lilja 		}
993592b7f6SOla Lilja 		break;
1003592b7f6SOla Lilja 
1013592b7f6SOla Lilja 	case 2:
1023592b7f6SOla Lilja 		prot_desc->frame_period = FRAME_PER_2_SLOTS;
1033592b7f6SOla Lilja 		break;
1043592b7f6SOla Lilja 
1053592b7f6SOla Lilja 	case 8:
1063592b7f6SOla Lilja 		prot_desc->frame_period = FRAME_PER_8_SLOTS;
1073592b7f6SOla Lilja 		break;
1083592b7f6SOla Lilja 
1093592b7f6SOla Lilja 	case 16:
1103592b7f6SOla Lilja 		prot_desc->frame_period = FRAME_PER_16_SLOTS;
1113592b7f6SOla Lilja 		break;
1123592b7f6SOla Lilja 	default:
1133592b7f6SOla Lilja 		dev_err(dai->dev,
1143592b7f6SOla Lilja 			"%s: Error: Unsupported slot-count (slots = %d)!\n",
1153592b7f6SOla Lilja 			__func__, drvdata->slots);
1163592b7f6SOla Lilja 		return -EINVAL;
1173592b7f6SOla Lilja 	}
1183592b7f6SOla Lilja 
1193592b7f6SOla Lilja 	prot_desc->clocks_per_frame =
1203592b7f6SOla Lilja 			prot_desc->frame_period+1;
1213592b7f6SOla Lilja 
1223592b7f6SOla Lilja 	dev_dbg(dai->dev, "%s: Clocks per frame: %u\n",
1233592b7f6SOla Lilja 		__func__,
1243592b7f6SOla Lilja 		prot_desc->clocks_per_frame);
1253592b7f6SOla Lilja 
1263592b7f6SOla Lilja 	return 0;
1273592b7f6SOla Lilja }
1283592b7f6SOla Lilja 
1293592b7f6SOla Lilja static int setup_pcm_framing(struct snd_soc_dai *dai, unsigned int rate,
1303592b7f6SOla Lilja 			struct msp_protdesc *prot_desc)
1313592b7f6SOla Lilja {
1323592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
1333592b7f6SOla Lilja 
1343592b7f6SOla Lilja 	u32 frame_length = MSP_FRAME_LEN_1;
1353592b7f6SOla Lilja 	prot_desc->frame_width = 0;
1363592b7f6SOla Lilja 
1373592b7f6SOla Lilja 	switch (drvdata->slots) {
1383592b7f6SOla Lilja 	case 1:
1393592b7f6SOla Lilja 		frame_length = MSP_FRAME_LEN_1;
1403592b7f6SOla Lilja 		break;
1413592b7f6SOla Lilja 
1423592b7f6SOla Lilja 	case 2:
1433592b7f6SOla Lilja 		frame_length = MSP_FRAME_LEN_2;
1443592b7f6SOla Lilja 		break;
1453592b7f6SOla Lilja 
1463592b7f6SOla Lilja 	case 8:
1473592b7f6SOla Lilja 		frame_length = MSP_FRAME_LEN_8;
1483592b7f6SOla Lilja 		break;
1493592b7f6SOla Lilja 
1503592b7f6SOla Lilja 	case 16:
1513592b7f6SOla Lilja 		frame_length = MSP_FRAME_LEN_16;
1523592b7f6SOla Lilja 		break;
1533592b7f6SOla Lilja 	default:
1543592b7f6SOla Lilja 		dev_err(dai->dev,
1553592b7f6SOla Lilja 			"%s: Error: Unsupported slot-count (slots = %d)!\n",
1563592b7f6SOla Lilja 			__func__, drvdata->slots);
1573592b7f6SOla Lilja 		return -EINVAL;
1583592b7f6SOla Lilja 	}
1593592b7f6SOla Lilja 
1603592b7f6SOla Lilja 	prot_desc->tx_frame_len_1 = frame_length;
1613592b7f6SOla Lilja 	prot_desc->rx_frame_len_1 = frame_length;
1623592b7f6SOla Lilja 	prot_desc->tx_frame_len_2 = frame_length;
1633592b7f6SOla Lilja 	prot_desc->rx_frame_len_2 = frame_length;
1643592b7f6SOla Lilja 
1653592b7f6SOla Lilja 	prot_desc->tx_elem_len_1 = MSP_ELEM_LEN_16;
1663592b7f6SOla Lilja 	prot_desc->rx_elem_len_1 = MSP_ELEM_LEN_16;
1673592b7f6SOla Lilja 	prot_desc->tx_elem_len_2 = MSP_ELEM_LEN_16;
1683592b7f6SOla Lilja 	prot_desc->rx_elem_len_2 = MSP_ELEM_LEN_16;
1693592b7f6SOla Lilja 
1703592b7f6SOla Lilja 	return setup_frameper(dai, rate, prot_desc);
1713592b7f6SOla Lilja }
1723592b7f6SOla Lilja 
1733592b7f6SOla Lilja static int setup_clocking(struct snd_soc_dai *dai,
1743592b7f6SOla Lilja 			unsigned int fmt,
1753592b7f6SOla Lilja 			struct ux500_msp_config *msp_config)
1763592b7f6SOla Lilja {
1773592b7f6SOla Lilja 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1783592b7f6SOla Lilja 	case SND_SOC_DAIFMT_NB_NF:
1793592b7f6SOla Lilja 		break;
1803592b7f6SOla Lilja 
1813592b7f6SOla Lilja 	case SND_SOC_DAIFMT_NB_IF:
1823592b7f6SOla Lilja 		msp_config->tx_fsync_pol ^= 1 << TFSPOL_SHIFT;
1833592b7f6SOla Lilja 		msp_config->rx_fsync_pol ^= 1 << RFSPOL_SHIFT;
1843592b7f6SOla Lilja 
1853592b7f6SOla Lilja 		break;
1863592b7f6SOla Lilja 
1873592b7f6SOla Lilja 	default:
1883592b7f6SOla Lilja 		dev_err(dai->dev,
1893592b7f6SOla Lilja 			"%s: Error: Unsopported inversion (fmt = 0x%x)!\n",
1903592b7f6SOla Lilja 			__func__, fmt);
1913592b7f6SOla Lilja 
1923592b7f6SOla Lilja 		return -EINVAL;
1933592b7f6SOla Lilja 	}
1943592b7f6SOla Lilja 
1953592b7f6SOla Lilja 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1963592b7f6SOla Lilja 	case SND_SOC_DAIFMT_CBM_CFM:
1973592b7f6SOla Lilja 		dev_dbg(dai->dev, "%s: Codec is master.\n", __func__);
1983592b7f6SOla Lilja 
1993592b7f6SOla Lilja 		msp_config->iodelay = 0x20;
2003592b7f6SOla Lilja 		msp_config->rx_fsync_sel = 0;
2013592b7f6SOla Lilja 		msp_config->tx_fsync_sel = 1 << TFSSEL_SHIFT;
2023592b7f6SOla Lilja 		msp_config->tx_clk_sel = 0;
2033592b7f6SOla Lilja 		msp_config->rx_clk_sel = 0;
2043592b7f6SOla Lilja 		msp_config->srg_clk_sel = 0x2 << SCKSEL_SHIFT;
2053592b7f6SOla Lilja 
2063592b7f6SOla Lilja 		break;
2073592b7f6SOla Lilja 
2083592b7f6SOla Lilja 	case SND_SOC_DAIFMT_CBS_CFS:
2093592b7f6SOla Lilja 		dev_dbg(dai->dev, "%s: Codec is slave.\n", __func__);
2103592b7f6SOla Lilja 
2113592b7f6SOla Lilja 		msp_config->tx_clk_sel = TX_CLK_SEL_SRG;
2123592b7f6SOla Lilja 		msp_config->tx_fsync_sel = TX_SYNC_SRG_PROG;
2133592b7f6SOla Lilja 		msp_config->rx_clk_sel = RX_CLK_SEL_SRG;
2143592b7f6SOla Lilja 		msp_config->rx_fsync_sel = RX_SYNC_SRG;
2153592b7f6SOla Lilja 		msp_config->srg_clk_sel = 1 << SCKSEL_SHIFT;
2163592b7f6SOla Lilja 
2173592b7f6SOla Lilja 		break;
2183592b7f6SOla Lilja 
2193592b7f6SOla Lilja 	default:
2203592b7f6SOla Lilja 		dev_err(dai->dev, "%s: Error: Unsopported master (fmt = 0x%x)!\n",
2213592b7f6SOla Lilja 			__func__, fmt);
2223592b7f6SOla Lilja 
2233592b7f6SOla Lilja 		return -EINVAL;
2243592b7f6SOla Lilja 	}
2253592b7f6SOla Lilja 
2263592b7f6SOla Lilja 	return 0;
2273592b7f6SOla Lilja }
2283592b7f6SOla Lilja 
2293592b7f6SOla Lilja static int setup_pcm_protdesc(struct snd_soc_dai *dai,
2303592b7f6SOla Lilja 				unsigned int fmt,
2313592b7f6SOla Lilja 				struct msp_protdesc *prot_desc)
2323592b7f6SOla Lilja {
2333592b7f6SOla Lilja 	prot_desc->rx_phase_mode = MSP_SINGLE_PHASE;
2343592b7f6SOla Lilja 	prot_desc->tx_phase_mode = MSP_SINGLE_PHASE;
2353592b7f6SOla Lilja 	prot_desc->rx_phase2_start_mode = MSP_PHASE2_START_MODE_IMEDIATE;
2363592b7f6SOla Lilja 	prot_desc->tx_phase2_start_mode = MSP_PHASE2_START_MODE_IMEDIATE;
2373592b7f6SOla Lilja 	prot_desc->rx_byte_order = MSP_BTF_MS_BIT_FIRST;
2383592b7f6SOla Lilja 	prot_desc->tx_byte_order = MSP_BTF_MS_BIT_FIRST;
2393592b7f6SOla Lilja 	prot_desc->tx_fsync_pol = MSP_FSYNC_POL(MSP_FSYNC_POL_ACT_HI);
2403592b7f6SOla Lilja 	prot_desc->rx_fsync_pol = MSP_FSYNC_POL_ACT_HI << RFSPOL_SHIFT;
2413592b7f6SOla Lilja 
2423592b7f6SOla Lilja 	if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_A) {
2433592b7f6SOla Lilja 		dev_dbg(dai->dev, "%s: DSP_A.\n", __func__);
2443592b7f6SOla Lilja 		prot_desc->rx_clk_pol = MSP_RISING_EDGE;
2453592b7f6SOla Lilja 		prot_desc->tx_clk_pol = MSP_FALLING_EDGE;
2463592b7f6SOla Lilja 
2473592b7f6SOla Lilja 		prot_desc->rx_data_delay = MSP_DELAY_1;
2483592b7f6SOla Lilja 		prot_desc->tx_data_delay = MSP_DELAY_1;
2493592b7f6SOla Lilja 	} else {
2503592b7f6SOla Lilja 		dev_dbg(dai->dev, "%s: DSP_B.\n", __func__);
2513592b7f6SOla Lilja 		prot_desc->rx_clk_pol = MSP_FALLING_EDGE;
2523592b7f6SOla Lilja 		prot_desc->tx_clk_pol = MSP_RISING_EDGE;
2533592b7f6SOla Lilja 
2543592b7f6SOla Lilja 		prot_desc->rx_data_delay = MSP_DELAY_0;
2553592b7f6SOla Lilja 		prot_desc->tx_data_delay = MSP_DELAY_0;
2563592b7f6SOla Lilja 	}
2573592b7f6SOla Lilja 
2583592b7f6SOla Lilja 	prot_desc->rx_half_word_swap = MSP_SWAP_NONE;
2593592b7f6SOla Lilja 	prot_desc->tx_half_word_swap = MSP_SWAP_NONE;
2603592b7f6SOla Lilja 	prot_desc->compression_mode = MSP_COMPRESS_MODE_LINEAR;
2613592b7f6SOla Lilja 	prot_desc->expansion_mode = MSP_EXPAND_MODE_LINEAR;
2623592b7f6SOla Lilja 	prot_desc->frame_sync_ignore = MSP_FSYNC_IGNORE;
2633592b7f6SOla Lilja 
2643592b7f6SOla Lilja 	return 0;
2653592b7f6SOla Lilja }
2663592b7f6SOla Lilja 
2673592b7f6SOla Lilja static int setup_i2s_protdesc(struct msp_protdesc *prot_desc)
2683592b7f6SOla Lilja {
2693592b7f6SOla Lilja 	prot_desc->rx_phase_mode = MSP_DUAL_PHASE;
2703592b7f6SOla Lilja 	prot_desc->tx_phase_mode = MSP_DUAL_PHASE;
2713592b7f6SOla Lilja 	prot_desc->rx_phase2_start_mode = MSP_PHASE2_START_MODE_FSYNC;
2723592b7f6SOla Lilja 	prot_desc->tx_phase2_start_mode = MSP_PHASE2_START_MODE_FSYNC;
2733592b7f6SOla Lilja 	prot_desc->rx_byte_order = MSP_BTF_MS_BIT_FIRST;
2743592b7f6SOla Lilja 	prot_desc->tx_byte_order = MSP_BTF_MS_BIT_FIRST;
2753592b7f6SOla Lilja 	prot_desc->tx_fsync_pol = MSP_FSYNC_POL(MSP_FSYNC_POL_ACT_LO);
2763592b7f6SOla Lilja 	prot_desc->rx_fsync_pol = MSP_FSYNC_POL_ACT_LO << RFSPOL_SHIFT;
2773592b7f6SOla Lilja 
2783592b7f6SOla Lilja 	prot_desc->rx_frame_len_1 = MSP_FRAME_LEN_1;
2793592b7f6SOla Lilja 	prot_desc->rx_frame_len_2 = MSP_FRAME_LEN_1;
2803592b7f6SOla Lilja 	prot_desc->tx_frame_len_1 = MSP_FRAME_LEN_1;
2813592b7f6SOla Lilja 	prot_desc->tx_frame_len_2 = MSP_FRAME_LEN_1;
2823592b7f6SOla Lilja 	prot_desc->rx_elem_len_1 = MSP_ELEM_LEN_16;
2833592b7f6SOla Lilja 	prot_desc->rx_elem_len_2 = MSP_ELEM_LEN_16;
2843592b7f6SOla Lilja 	prot_desc->tx_elem_len_1 = MSP_ELEM_LEN_16;
2853592b7f6SOla Lilja 	prot_desc->tx_elem_len_2 = MSP_ELEM_LEN_16;
2863592b7f6SOla Lilja 
2873592b7f6SOla Lilja 	prot_desc->rx_clk_pol = MSP_RISING_EDGE;
2883592b7f6SOla Lilja 	prot_desc->tx_clk_pol = MSP_FALLING_EDGE;
2893592b7f6SOla Lilja 
2903592b7f6SOla Lilja 	prot_desc->rx_data_delay = MSP_DELAY_0;
2913592b7f6SOla Lilja 	prot_desc->tx_data_delay = MSP_DELAY_0;
2923592b7f6SOla Lilja 
2933592b7f6SOla Lilja 	prot_desc->tx_half_word_swap = MSP_SWAP_NONE;
2943592b7f6SOla Lilja 	prot_desc->rx_half_word_swap = MSP_SWAP_NONE;
2953592b7f6SOla Lilja 	prot_desc->compression_mode = MSP_COMPRESS_MODE_LINEAR;
2963592b7f6SOla Lilja 	prot_desc->expansion_mode = MSP_EXPAND_MODE_LINEAR;
2973592b7f6SOla Lilja 	prot_desc->frame_sync_ignore = MSP_FSYNC_IGNORE;
2983592b7f6SOla Lilja 
2993592b7f6SOla Lilja 	return 0;
3003592b7f6SOla Lilja }
3013592b7f6SOla Lilja 
3023592b7f6SOla Lilja static int setup_msp_config(struct snd_pcm_substream *substream,
3033592b7f6SOla Lilja 			struct snd_soc_dai *dai,
3043592b7f6SOla Lilja 			struct ux500_msp_config *msp_config)
3053592b7f6SOla Lilja {
3063592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
3073592b7f6SOla Lilja 	struct msp_protdesc *prot_desc = &msp_config->protdesc;
3083592b7f6SOla Lilja 	struct snd_pcm_runtime *runtime = substream->runtime;
3093592b7f6SOla Lilja 	unsigned int fmt = drvdata->fmt;
3103592b7f6SOla Lilja 	int ret;
3113592b7f6SOla Lilja 
3123592b7f6SOla Lilja 	memset(msp_config, 0, sizeof(*msp_config));
3133592b7f6SOla Lilja 
3143592b7f6SOla Lilja 	msp_config->f_inputclk = drvdata->master_clk;
3153592b7f6SOla Lilja 
3163592b7f6SOla Lilja 	msp_config->tx_fifo_config = TX_FIFO_ENABLE;
3173592b7f6SOla Lilja 	msp_config->rx_fifo_config = RX_FIFO_ENABLE;
3183592b7f6SOla Lilja 	msp_config->def_elem_len = 1;
3193592b7f6SOla Lilja 	msp_config->direction = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
3203592b7f6SOla Lilja 				MSP_DIR_TX : MSP_DIR_RX;
3213592b7f6SOla Lilja 	msp_config->data_size = MSP_DATA_BITS_32;
3223592b7f6SOla Lilja 	msp_config->frame_freq = runtime->rate;
3233592b7f6SOla Lilja 
3243592b7f6SOla Lilja 	dev_dbg(dai->dev, "%s: f_inputclk = %u, frame_freq = %u.\n",
3253592b7f6SOla Lilja 	       __func__, msp_config->f_inputclk, msp_config->frame_freq);
3263592b7f6SOla Lilja 	/* To avoid division by zero */
3273592b7f6SOla Lilja 	prot_desc->clocks_per_frame = 1;
3283592b7f6SOla Lilja 
3293592b7f6SOla Lilja 	dev_dbg(dai->dev, "%s: rate: %u, channels: %d.\n", __func__,
3303592b7f6SOla Lilja 		runtime->rate, runtime->channels);
3313592b7f6SOla Lilja 	switch (fmt &
3323592b7f6SOla Lilja 		(SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
3333592b7f6SOla Lilja 	case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
3343592b7f6SOla Lilja 		dev_dbg(dai->dev, "%s: SND_SOC_DAIFMT_I2S.\n", __func__);
3353592b7f6SOla Lilja 
3363592b7f6SOla Lilja 		msp_config->default_protdesc = 1;
3373592b7f6SOla Lilja 		msp_config->protocol = MSP_I2S_PROTOCOL;
3383592b7f6SOla Lilja 		break;
3393592b7f6SOla Lilja 
3403592b7f6SOla Lilja 	case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
3413592b7f6SOla Lilja 		dev_dbg(dai->dev, "%s: SND_SOC_DAIFMT_I2S.\n", __func__);
3423592b7f6SOla Lilja 
3433592b7f6SOla Lilja 		msp_config->data_size = MSP_DATA_BITS_16;
3443592b7f6SOla Lilja 		msp_config->protocol = MSP_I2S_PROTOCOL;
3453592b7f6SOla Lilja 
3463592b7f6SOla Lilja 		ret = setup_i2s_protdesc(prot_desc);
3473592b7f6SOla Lilja 		if (ret < 0)
3483592b7f6SOla Lilja 			return ret;
3493592b7f6SOla Lilja 
3503592b7f6SOla Lilja 		break;
3513592b7f6SOla Lilja 
3523592b7f6SOla Lilja 	case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
3533592b7f6SOla Lilja 	case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
3543592b7f6SOla Lilja 	case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBS_CFS:
3553592b7f6SOla Lilja 	case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBM_CFM:
3563592b7f6SOla Lilja 		dev_dbg(dai->dev, "%s: PCM format.\n", __func__);
3573592b7f6SOla Lilja 
3583592b7f6SOla Lilja 		msp_config->data_size = MSP_DATA_BITS_16;
3593592b7f6SOla Lilja 		msp_config->protocol = MSP_PCM_PROTOCOL;
3603592b7f6SOla Lilja 
3613592b7f6SOla Lilja 		ret = setup_pcm_protdesc(dai, fmt, prot_desc);
3623592b7f6SOla Lilja 		if (ret < 0)
3633592b7f6SOla Lilja 			return ret;
3643592b7f6SOla Lilja 
3653592b7f6SOla Lilja 		ret = setup_pcm_multichan(dai, msp_config);
3663592b7f6SOla Lilja 		if (ret < 0)
3673592b7f6SOla Lilja 			return ret;
3683592b7f6SOla Lilja 
3693592b7f6SOla Lilja 		ret = setup_pcm_framing(dai, runtime->rate, prot_desc);
3703592b7f6SOla Lilja 		if (ret < 0)
3713592b7f6SOla Lilja 			return ret;
3723592b7f6SOla Lilja 
3733592b7f6SOla Lilja 		break;
3743592b7f6SOla Lilja 
3753592b7f6SOla Lilja 	default:
3763592b7f6SOla Lilja 		dev_err(dai->dev, "%s: Error: Unsopported format (%d)!\n",
3773592b7f6SOla Lilja 			__func__, fmt);
3783592b7f6SOla Lilja 		return -EINVAL;
3793592b7f6SOla Lilja 	}
3803592b7f6SOla Lilja 
3813592b7f6SOla Lilja 	return setup_clocking(dai, fmt, msp_config);
3823592b7f6SOla Lilja }
3833592b7f6SOla Lilja 
3843592b7f6SOla Lilja static int ux500_msp_dai_startup(struct snd_pcm_substream *substream,
3853592b7f6SOla Lilja 				struct snd_soc_dai *dai)
3863592b7f6SOla Lilja {
3873592b7f6SOla Lilja 	int ret = 0;
3883592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
3893592b7f6SOla Lilja 
3903592b7f6SOla Lilja 	dev_dbg(dai->dev, "%s: MSP %d (%s): Enter.\n", __func__, dai->id,
3913592b7f6SOla Lilja 		snd_pcm_stream_str(substream));
3923592b7f6SOla Lilja 
3933592b7f6SOla Lilja 	/* Enable regulator */
3943592b7f6SOla Lilja 	ret = regulator_enable(drvdata->reg_vape);
3953592b7f6SOla Lilja 	if (ret != 0) {
3963592b7f6SOla Lilja 		dev_err(drvdata->msp->dev,
3973592b7f6SOla Lilja 			"%s: Failed to enable regulator!\n", __func__);
3983592b7f6SOla Lilja 		return ret;
3993592b7f6SOla Lilja 	}
4003592b7f6SOla Lilja 
401*f61ab093SUlf Hansson 	/* Prepare and enable clocks */
402*f61ab093SUlf Hansson 	dev_dbg(dai->dev, "%s: Enabling MSP-clocks.\n", __func__);
403*f61ab093SUlf Hansson 	ret = clk_prepare_enable(drvdata->pclk);
404*f61ab093SUlf Hansson 	if (ret) {
405*f61ab093SUlf Hansson 		dev_err(drvdata->msp->dev,
406*f61ab093SUlf Hansson 			"%s: Failed to prepare/enable pclk!\n", __func__);
407*f61ab093SUlf Hansson 		goto err_pclk;
408*f61ab093SUlf Hansson 	}
4093592b7f6SOla Lilja 
410*f61ab093SUlf Hansson 	ret = clk_prepare_enable(drvdata->clk);
411*f61ab093SUlf Hansson 	if (ret) {
412*f61ab093SUlf Hansson 		dev_err(drvdata->msp->dev,
413*f61ab093SUlf Hansson 			"%s: Failed to prepare/enable clk!\n", __func__);
414*f61ab093SUlf Hansson 		goto err_clk;
415*f61ab093SUlf Hansson 	}
416*f61ab093SUlf Hansson 
417*f61ab093SUlf Hansson 	return ret;
418*f61ab093SUlf Hansson err_clk:
419*f61ab093SUlf Hansson 	clk_disable_unprepare(drvdata->pclk);
420*f61ab093SUlf Hansson err_pclk:
421*f61ab093SUlf Hansson 	regulator_disable(drvdata->reg_vape);
422fe36a0b2SUlf Hansson 	return ret;
4233592b7f6SOla Lilja }
4243592b7f6SOla Lilja 
4253592b7f6SOla Lilja static void ux500_msp_dai_shutdown(struct snd_pcm_substream *substream,
4263592b7f6SOla Lilja 				struct snd_soc_dai *dai)
4273592b7f6SOla Lilja {
4283592b7f6SOla Lilja 	int ret;
4293592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
4303592b7f6SOla Lilja 	bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
4313592b7f6SOla Lilja 
4323592b7f6SOla Lilja 	dev_dbg(dai->dev, "%s: MSP %d (%s): Enter.\n", __func__, dai->id,
4333592b7f6SOla Lilja 		snd_pcm_stream_str(substream));
4343592b7f6SOla Lilja 
4353592b7f6SOla Lilja 	if (drvdata->vape_opp_constraint == 1) {
4363592b7f6SOla Lilja 		prcmu_qos_update_requirement(PRCMU_QOS_APE_OPP,
4373592b7f6SOla Lilja 					"ux500_msp_i2s", 50);
4383592b7f6SOla Lilja 		drvdata->vape_opp_constraint = 0;
4393592b7f6SOla Lilja 	}
4403592b7f6SOla Lilja 
4413592b7f6SOla Lilja 	if (ux500_msp_i2s_close(drvdata->msp,
4423592b7f6SOla Lilja 				is_playback ? MSP_DIR_TX : MSP_DIR_RX)) {
4433592b7f6SOla Lilja 		dev_err(dai->dev,
4443592b7f6SOla Lilja 			"%s: Error: MSP %d (%s): Unable to close i2s.\n",
4453592b7f6SOla Lilja 			__func__, dai->id, snd_pcm_stream_str(substream));
4463592b7f6SOla Lilja 	}
4473592b7f6SOla Lilja 
448*f61ab093SUlf Hansson 	/* Disable and unprepare clocks */
449fe36a0b2SUlf Hansson 	clk_disable_unprepare(drvdata->clk);
450*f61ab093SUlf Hansson 	clk_disable_unprepare(drvdata->pclk);
4513592b7f6SOla Lilja 
4523592b7f6SOla Lilja 	/* Disable regulator */
4533592b7f6SOla Lilja 	ret = regulator_disable(drvdata->reg_vape);
4543592b7f6SOla Lilja 	if (ret < 0)
4553592b7f6SOla Lilja 		dev_err(dai->dev,
4563592b7f6SOla Lilja 			"%s: ERROR: Failed to disable regulator (%d)!\n",
4573592b7f6SOla Lilja 			__func__, ret);
4583592b7f6SOla Lilja }
4593592b7f6SOla Lilja 
4603592b7f6SOla Lilja static int ux500_msp_dai_prepare(struct snd_pcm_substream *substream,
4613592b7f6SOla Lilja 				struct snd_soc_dai *dai)
4623592b7f6SOla Lilja {
4633592b7f6SOla Lilja 	int ret = 0;
4643592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
4653592b7f6SOla Lilja 	struct snd_pcm_runtime *runtime = substream->runtime;
4663592b7f6SOla Lilja 	struct ux500_msp_config msp_config;
4673592b7f6SOla Lilja 
4683592b7f6SOla Lilja 	dev_dbg(dai->dev, "%s: MSP %d (%s): Enter (rate = %d).\n", __func__,
4693592b7f6SOla Lilja 		dai->id, snd_pcm_stream_str(substream), runtime->rate);
4703592b7f6SOla Lilja 
4713592b7f6SOla Lilja 	setup_msp_config(substream, dai, &msp_config);
4723592b7f6SOla Lilja 
4733592b7f6SOla Lilja 	ret = ux500_msp_i2s_open(drvdata->msp, &msp_config);
4743592b7f6SOla Lilja 	if (ret < 0) {
4753592b7f6SOla Lilja 		dev_err(dai->dev, "%s: Error: msp_setup failed (ret = %d)!\n",
4763592b7f6SOla Lilja 			__func__, ret);
4773592b7f6SOla Lilja 		return ret;
4783592b7f6SOla Lilja 	}
4793592b7f6SOla Lilja 
4803592b7f6SOla Lilja 	/* Set OPP-level */
4813592b7f6SOla Lilja 	if ((drvdata->fmt & SND_SOC_DAIFMT_MASTER_MASK) &&
4823592b7f6SOla Lilja 		(drvdata->msp->f_bitclk > 19200000)) {
4833592b7f6SOla Lilja 		/* If the bit-clock is higher than 19.2MHz, Vape should be
4843592b7f6SOla Lilja 		 * run in 100% OPP. Only when bit-clock is used (MSP master) */
4853592b7f6SOla Lilja 		prcmu_qos_update_requirement(PRCMU_QOS_APE_OPP,
4863592b7f6SOla Lilja 					"ux500-msp-i2s", 100);
4873592b7f6SOla Lilja 		drvdata->vape_opp_constraint = 1;
4883592b7f6SOla Lilja 	} else {
4893592b7f6SOla Lilja 		prcmu_qos_update_requirement(PRCMU_QOS_APE_OPP,
4903592b7f6SOla Lilja 					"ux500-msp-i2s", 50);
4913592b7f6SOla Lilja 		drvdata->vape_opp_constraint = 0;
4923592b7f6SOla Lilja 	}
4933592b7f6SOla Lilja 
4943592b7f6SOla Lilja 	return ret;
4953592b7f6SOla Lilja }
4963592b7f6SOla Lilja 
4973592b7f6SOla Lilja static int ux500_msp_dai_hw_params(struct snd_pcm_substream *substream,
4983592b7f6SOla Lilja 				struct snd_pcm_hw_params *params,
4993592b7f6SOla Lilja 				struct snd_soc_dai *dai)
5003592b7f6SOla Lilja {
5013592b7f6SOla Lilja 	unsigned int mask, slots_active;
5023592b7f6SOla Lilja 	struct snd_pcm_runtime *runtime = substream->runtime;
5033592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
5043592b7f6SOla Lilja 
5053592b7f6SOla Lilja 	dev_dbg(dai->dev, "%s: MSP %d (%s): Enter.\n",
5063592b7f6SOla Lilja 			__func__, dai->id, snd_pcm_stream_str(substream));
5073592b7f6SOla Lilja 
5083592b7f6SOla Lilja 	switch (drvdata->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
5093592b7f6SOla Lilja 	case SND_SOC_DAIFMT_I2S:
5103592b7f6SOla Lilja 		snd_pcm_hw_constraint_minmax(runtime,
5113592b7f6SOla Lilja 				SNDRV_PCM_HW_PARAM_CHANNELS,
5123592b7f6SOla Lilja 				1, 2);
5133592b7f6SOla Lilja 		break;
5143592b7f6SOla Lilja 
5153592b7f6SOla Lilja 	case SND_SOC_DAIFMT_DSP_B:
5163592b7f6SOla Lilja 	case SND_SOC_DAIFMT_DSP_A:
5173592b7f6SOla Lilja 		mask = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5183592b7f6SOla Lilja 			drvdata->tx_mask :
5193592b7f6SOla Lilja 			drvdata->rx_mask;
5203592b7f6SOla Lilja 
5213592b7f6SOla Lilja 		slots_active = hweight32(mask);
5223592b7f6SOla Lilja 		dev_dbg(dai->dev, "TDM-slots active: %d", slots_active);
5233592b7f6SOla Lilja 
5243592b7f6SOla Lilja 		snd_pcm_hw_constraint_minmax(runtime,
5253592b7f6SOla Lilja 				SNDRV_PCM_HW_PARAM_CHANNELS,
5263592b7f6SOla Lilja 				slots_active, slots_active);
5273592b7f6SOla Lilja 		break;
5283592b7f6SOla Lilja 
5293592b7f6SOla Lilja 	default:
5303592b7f6SOla Lilja 		dev_err(dai->dev,
5313592b7f6SOla Lilja 			"%s: Error: Unsupported protocol (fmt = 0x%x)!\n",
5323592b7f6SOla Lilja 			__func__, drvdata->fmt);
5333592b7f6SOla Lilja 		return -EINVAL;
5343592b7f6SOla Lilja 	}
5353592b7f6SOla Lilja 
5363592b7f6SOla Lilja 	return 0;
5373592b7f6SOla Lilja }
5383592b7f6SOla Lilja 
5393592b7f6SOla Lilja static int ux500_msp_dai_set_dai_fmt(struct snd_soc_dai *dai,
5403592b7f6SOla Lilja 				unsigned int fmt)
5413592b7f6SOla Lilja {
5423592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
5433592b7f6SOla Lilja 
5443592b7f6SOla Lilja 	dev_dbg(dai->dev, "%s: MSP %d: Enter.\n", __func__, dai->id);
5453592b7f6SOla Lilja 
5463592b7f6SOla Lilja 	switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
5473592b7f6SOla Lilja 		SND_SOC_DAIFMT_MASTER_MASK)) {
5483592b7f6SOla Lilja 	case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
5493592b7f6SOla Lilja 	case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
5503592b7f6SOla Lilja 	case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBS_CFS:
5513592b7f6SOla Lilja 	case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBM_CFM:
5523592b7f6SOla Lilja 	case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
5533592b7f6SOla Lilja 	case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
5543592b7f6SOla Lilja 		break;
5553592b7f6SOla Lilja 
5563592b7f6SOla Lilja 	default:
5573592b7f6SOla Lilja 		dev_err(dai->dev,
5583592b7f6SOla Lilja 			"%s: Error: Unsupported protocol/master (fmt = 0x%x)!\n",
5593592b7f6SOla Lilja 			__func__, drvdata->fmt);
5603592b7f6SOla Lilja 		return -EINVAL;
5613592b7f6SOla Lilja 	}
5623592b7f6SOla Lilja 
5633592b7f6SOla Lilja 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
5643592b7f6SOla Lilja 	case SND_SOC_DAIFMT_NB_NF:
5653592b7f6SOla Lilja 	case SND_SOC_DAIFMT_NB_IF:
5663592b7f6SOla Lilja 	case SND_SOC_DAIFMT_IB_IF:
5673592b7f6SOla Lilja 		break;
5683592b7f6SOla Lilja 
5693592b7f6SOla Lilja 	default:
5703592b7f6SOla Lilja 		dev_err(dai->dev,
5713592b7f6SOla Lilja 			"%s: Error: Unsupported inversion (fmt = 0x%x)!\n",
5723592b7f6SOla Lilja 			__func__, drvdata->fmt);
5733592b7f6SOla Lilja 		return -EINVAL;
5743592b7f6SOla Lilja 	}
5753592b7f6SOla Lilja 
5763592b7f6SOla Lilja 	drvdata->fmt = fmt;
5773592b7f6SOla Lilja 	return 0;
5783592b7f6SOla Lilja }
5793592b7f6SOla Lilja 
5803592b7f6SOla Lilja static int ux500_msp_dai_set_tdm_slot(struct snd_soc_dai *dai,
5813592b7f6SOla Lilja 				unsigned int tx_mask,
5823592b7f6SOla Lilja 				unsigned int rx_mask,
5833592b7f6SOla Lilja 				int slots, int slot_width)
5843592b7f6SOla Lilja {
5853592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
5863592b7f6SOla Lilja 	unsigned int cap;
5873592b7f6SOla Lilja 
5883592b7f6SOla Lilja 	switch (slots) {
5893592b7f6SOla Lilja 	case 1:
5903592b7f6SOla Lilja 		cap = 0x01;
5913592b7f6SOla Lilja 		break;
5923592b7f6SOla Lilja 	case 2:
5933592b7f6SOla Lilja 		cap = 0x03;
5943592b7f6SOla Lilja 		break;
5953592b7f6SOla Lilja 	case 8:
5963592b7f6SOla Lilja 		cap = 0xFF;
5973592b7f6SOla Lilja 		break;
5983592b7f6SOla Lilja 	case 16:
5993592b7f6SOla Lilja 		cap = 0xFFFF;
6003592b7f6SOla Lilja 		break;
6013592b7f6SOla Lilja 	default:
6023592b7f6SOla Lilja 		dev_err(dai->dev, "%s: Error: Unsupported slot-count (%d)!\n",
6033592b7f6SOla Lilja 			__func__, slots);
6043592b7f6SOla Lilja 		return -EINVAL;
6053592b7f6SOla Lilja 	}
6063592b7f6SOla Lilja 	drvdata->slots = slots;
6073592b7f6SOla Lilja 
6083592b7f6SOla Lilja 	if (!(slot_width == 16)) {
6093592b7f6SOla Lilja 		dev_err(dai->dev, "%s: Error: Unsupported slot-width (%d)!\n",
6103592b7f6SOla Lilja 			__func__, slot_width);
6113592b7f6SOla Lilja 		return -EINVAL;
6123592b7f6SOla Lilja 	}
6133592b7f6SOla Lilja 	drvdata->slot_width = slot_width;
6143592b7f6SOla Lilja 
6153592b7f6SOla Lilja 	drvdata->tx_mask = tx_mask & cap;
6163592b7f6SOla Lilja 	drvdata->rx_mask = rx_mask & cap;
6173592b7f6SOla Lilja 
6183592b7f6SOla Lilja 	return 0;
6193592b7f6SOla Lilja }
6203592b7f6SOla Lilja 
6213592b7f6SOla Lilja static int ux500_msp_dai_set_dai_sysclk(struct snd_soc_dai *dai,
6223592b7f6SOla Lilja 					int clk_id, unsigned int freq, int dir)
6233592b7f6SOla Lilja {
6243592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
6253592b7f6SOla Lilja 
6263592b7f6SOla Lilja 	dev_dbg(dai->dev, "%s: MSP %d: Enter. clk-id: %d, freq: %u.\n",
6273592b7f6SOla Lilja 		__func__, dai->id, clk_id, freq);
6283592b7f6SOla Lilja 
6293592b7f6SOla Lilja 	switch (clk_id) {
6303592b7f6SOla Lilja 	case UX500_MSP_MASTER_CLOCK:
6313592b7f6SOla Lilja 		drvdata->master_clk = freq;
6323592b7f6SOla Lilja 		break;
6333592b7f6SOla Lilja 
6343592b7f6SOla Lilja 	default:
6353592b7f6SOla Lilja 		dev_err(dai->dev, "%s: MSP %d: Invalid clk-id (%d)!\n",
6363592b7f6SOla Lilja 			__func__, dai->id, clk_id);
6373592b7f6SOla Lilja 		return -EINVAL;
6383592b7f6SOla Lilja 	}
6393592b7f6SOla Lilja 
6403592b7f6SOla Lilja 	return 0;
6413592b7f6SOla Lilja }
6423592b7f6SOla Lilja 
6433592b7f6SOla Lilja static int ux500_msp_dai_trigger(struct snd_pcm_substream *substream,
6443592b7f6SOla Lilja 				int cmd, struct snd_soc_dai *dai)
6453592b7f6SOla Lilja {
6463592b7f6SOla Lilja 	int ret = 0;
6473592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
6483592b7f6SOla Lilja 
6493592b7f6SOla Lilja 	dev_dbg(dai->dev, "%s: MSP %d (%s): Enter (msp->id = %d, cmd = %d).\n",
6503592b7f6SOla Lilja 		__func__, dai->id, snd_pcm_stream_str(substream),
6513592b7f6SOla Lilja 		(int)drvdata->msp->id, cmd);
6523592b7f6SOla Lilja 
6533592b7f6SOla Lilja 	ret = ux500_msp_i2s_trigger(drvdata->msp, cmd, substream->stream);
6543592b7f6SOla Lilja 
6553592b7f6SOla Lilja 	return ret;
6563592b7f6SOla Lilja }
6573592b7f6SOla Lilja 
6583592b7f6SOla Lilja static int ux500_msp_dai_probe(struct snd_soc_dai *dai)
6593592b7f6SOla Lilja {
6603592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(dai->dev);
6613592b7f6SOla Lilja 
6623592b7f6SOla Lilja 	drvdata->playback_dma_data.dma_cfg = drvdata->msp->dma_cfg_tx;
6633592b7f6SOla Lilja 	drvdata->capture_dma_data.dma_cfg = drvdata->msp->dma_cfg_rx;
6643592b7f6SOla Lilja 
6653592b7f6SOla Lilja 	dai->playback_dma_data = &drvdata->playback_dma_data;
6663592b7f6SOla Lilja 	dai->capture_dma_data = &drvdata->capture_dma_data;
6673592b7f6SOla Lilja 
6683592b7f6SOla Lilja 	drvdata->playback_dma_data.data_size = drvdata->slot_width;
6693592b7f6SOla Lilja 	drvdata->capture_dma_data.data_size = drvdata->slot_width;
6703592b7f6SOla Lilja 
6713592b7f6SOla Lilja 	return 0;
6723592b7f6SOla Lilja }
6733592b7f6SOla Lilja 
6743592b7f6SOla Lilja static struct snd_soc_dai_ops ux500_msp_dai_ops[] = {
6753592b7f6SOla Lilja 	{
6763592b7f6SOla Lilja 		.set_sysclk = ux500_msp_dai_set_dai_sysclk,
6773592b7f6SOla Lilja 		.set_fmt = ux500_msp_dai_set_dai_fmt,
6783592b7f6SOla Lilja 		.set_tdm_slot = ux500_msp_dai_set_tdm_slot,
6793592b7f6SOla Lilja 		.startup = ux500_msp_dai_startup,
6803592b7f6SOla Lilja 		.shutdown = ux500_msp_dai_shutdown,
6813592b7f6SOla Lilja 		.prepare = ux500_msp_dai_prepare,
6823592b7f6SOla Lilja 		.trigger = ux500_msp_dai_trigger,
6833592b7f6SOla Lilja 		.hw_params = ux500_msp_dai_hw_params,
6843592b7f6SOla Lilja 	}
6853592b7f6SOla Lilja };
6863592b7f6SOla Lilja 
6873592b7f6SOla Lilja static struct snd_soc_dai_driver ux500_msp_dai_drv[UX500_NBR_OF_DAI] = {
6883592b7f6SOla Lilja 	{
6893592b7f6SOla Lilja 		.name = "ux500-msp-i2s.0",
6903592b7f6SOla Lilja 		.probe = ux500_msp_dai_probe,
6913592b7f6SOla Lilja 		.id = 0,
6923592b7f6SOla Lilja 		.suspend = NULL,
6933592b7f6SOla Lilja 		.resume = NULL,
6943592b7f6SOla Lilja 		.playback = {
6953592b7f6SOla Lilja 			.channels_min = UX500_MSP_MIN_CHANNELS,
6963592b7f6SOla Lilja 			.channels_max = UX500_MSP_MAX_CHANNELS,
6973592b7f6SOla Lilja 			.rates = UX500_I2S_RATES,
6983592b7f6SOla Lilja 			.formats = UX500_I2S_FORMATS,
6993592b7f6SOla Lilja 		},
7003592b7f6SOla Lilja 		.capture = {
7013592b7f6SOla Lilja 			.channels_min = UX500_MSP_MIN_CHANNELS,
7023592b7f6SOla Lilja 			.channels_max = UX500_MSP_MAX_CHANNELS,
7033592b7f6SOla Lilja 			.rates = UX500_I2S_RATES,
7043592b7f6SOla Lilja 			.formats = UX500_I2S_FORMATS,
7053592b7f6SOla Lilja 		},
7063592b7f6SOla Lilja 		.ops = ux500_msp_dai_ops,
7073592b7f6SOla Lilja 	},
7083592b7f6SOla Lilja 	{
7093592b7f6SOla Lilja 		.name = "ux500-msp-i2s.1",
7103592b7f6SOla Lilja 		.probe = ux500_msp_dai_probe,
7113592b7f6SOla Lilja 		.id = 1,
7123592b7f6SOla Lilja 		.suspend = NULL,
7133592b7f6SOla Lilja 		.resume = NULL,
7143592b7f6SOla Lilja 		.playback = {
7153592b7f6SOla Lilja 			.channels_min = UX500_MSP_MIN_CHANNELS,
7163592b7f6SOla Lilja 			.channels_max = UX500_MSP_MAX_CHANNELS,
7173592b7f6SOla Lilja 			.rates = UX500_I2S_RATES,
7183592b7f6SOla Lilja 			.formats = UX500_I2S_FORMATS,
7193592b7f6SOla Lilja 		},
7203592b7f6SOla Lilja 		.capture = {
7213592b7f6SOla Lilja 			.channels_min = UX500_MSP_MIN_CHANNELS,
7223592b7f6SOla Lilja 			.channels_max = UX500_MSP_MAX_CHANNELS,
7233592b7f6SOla Lilja 			.rates = UX500_I2S_RATES,
7243592b7f6SOla Lilja 			.formats = UX500_I2S_FORMATS,
7253592b7f6SOla Lilja 		},
7263592b7f6SOla Lilja 		.ops = ux500_msp_dai_ops,
7273592b7f6SOla Lilja 	},
7283592b7f6SOla Lilja 	{
7293592b7f6SOla Lilja 		.name = "ux500-msp-i2s.2",
7303592b7f6SOla Lilja 		.id = 2,
7313592b7f6SOla Lilja 		.probe = ux500_msp_dai_probe,
7323592b7f6SOla Lilja 		.suspend = NULL,
7333592b7f6SOla Lilja 		.resume = NULL,
7343592b7f6SOla Lilja 		.playback = {
7353592b7f6SOla Lilja 			.channels_min = UX500_MSP_MIN_CHANNELS,
7363592b7f6SOla Lilja 			.channels_max = UX500_MSP_MAX_CHANNELS,
7373592b7f6SOla Lilja 			.rates = UX500_I2S_RATES,
7383592b7f6SOla Lilja 			.formats = UX500_I2S_FORMATS,
7393592b7f6SOla Lilja 		},
7403592b7f6SOla Lilja 		.capture = {
7413592b7f6SOla Lilja 			.channels_min = UX500_MSP_MIN_CHANNELS,
7423592b7f6SOla Lilja 			.channels_max = UX500_MSP_MAX_CHANNELS,
7433592b7f6SOla Lilja 			.rates = UX500_I2S_RATES,
7443592b7f6SOla Lilja 			.formats = UX500_I2S_FORMATS,
7453592b7f6SOla Lilja 		},
7463592b7f6SOla Lilja 		.ops = ux500_msp_dai_ops,
7473592b7f6SOla Lilja 	},
7483592b7f6SOla Lilja 	{
7493592b7f6SOla Lilja 		.name = "ux500-msp-i2s.3",
7503592b7f6SOla Lilja 		.probe = ux500_msp_dai_probe,
7513592b7f6SOla Lilja 		.id = 3,
7523592b7f6SOla Lilja 		.suspend = NULL,
7533592b7f6SOla Lilja 		.resume = NULL,
7543592b7f6SOla Lilja 		.playback = {
7553592b7f6SOla Lilja 			.channels_min = UX500_MSP_MIN_CHANNELS,
7563592b7f6SOla Lilja 			.channels_max = UX500_MSP_MAX_CHANNELS,
7573592b7f6SOla Lilja 			.rates = UX500_I2S_RATES,
7583592b7f6SOla Lilja 			.formats = UX500_I2S_FORMATS,
7593592b7f6SOla Lilja 		},
7603592b7f6SOla Lilja 		.capture = {
7613592b7f6SOla Lilja 			.channels_min = UX500_MSP_MIN_CHANNELS,
7623592b7f6SOla Lilja 			.channels_max = UX500_MSP_MAX_CHANNELS,
7633592b7f6SOla Lilja 			.rates = UX500_I2S_RATES,
7643592b7f6SOla Lilja 			.formats = UX500_I2S_FORMATS,
7653592b7f6SOla Lilja 		},
7663592b7f6SOla Lilja 		.ops = ux500_msp_dai_ops,
7673592b7f6SOla Lilja 	},
7683592b7f6SOla Lilja };
7693592b7f6SOla Lilja 
7703592b7f6SOla Lilja static int __devinit ux500_msp_drv_probe(struct platform_device *pdev)
7713592b7f6SOla Lilja {
7723592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata;
7733592b7f6SOla Lilja 	int ret = 0;
7743592b7f6SOla Lilja 
7753592b7f6SOla Lilja 	dev_dbg(&pdev->dev, "%s: Enter (pdev->name = %s).\n", __func__,
7763592b7f6SOla Lilja 		pdev->name);
7773592b7f6SOla Lilja 
7783592b7f6SOla Lilja 	drvdata = devm_kzalloc(&pdev->dev,
7793592b7f6SOla Lilja 				sizeof(struct ux500_msp_i2s_drvdata),
7803592b7f6SOla Lilja 				GFP_KERNEL);
7810dcd4742SLee Jones 	if (!drvdata)
7820dcd4742SLee Jones 		return -ENOMEM;
7830dcd4742SLee Jones 
7843592b7f6SOla Lilja 	drvdata->fmt = 0;
7853592b7f6SOla Lilja 	drvdata->slots = 1;
7863592b7f6SOla Lilja 	drvdata->tx_mask = 0x01;
7873592b7f6SOla Lilja 	drvdata->rx_mask = 0x01;
7883592b7f6SOla Lilja 	drvdata->slot_width = 16;
7893592b7f6SOla Lilja 	drvdata->master_clk = MSP_INPUT_FREQ_APB;
7903592b7f6SOla Lilja 
7913592b7f6SOla Lilja 	drvdata->reg_vape = devm_regulator_get(&pdev->dev, "v-ape");
7923592b7f6SOla Lilja 	if (IS_ERR(drvdata->reg_vape)) {
7933592b7f6SOla Lilja 		ret = (int)PTR_ERR(drvdata->reg_vape);
7943592b7f6SOla Lilja 		dev_err(&pdev->dev,
7953592b7f6SOla Lilja 			"%s: ERROR: Failed to get Vape supply (%d)!\n",
7963592b7f6SOla Lilja 			__func__, ret);
7973592b7f6SOla Lilja 		return ret;
7983592b7f6SOla Lilja 	}
7993592b7f6SOla Lilja 	prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP, (char *)pdev->name, 50);
8003592b7f6SOla Lilja 
801*f61ab093SUlf Hansson 	drvdata->pclk = clk_get(&pdev->dev, "apb_pclk");
802*f61ab093SUlf Hansson 	if (IS_ERR(drvdata->pclk)) {
803*f61ab093SUlf Hansson 		ret = (int)PTR_ERR(drvdata->pclk);
804*f61ab093SUlf Hansson 		dev_err(&pdev->dev, "%s: ERROR: clk_get of pclk failed (%d)!\n",
805*f61ab093SUlf Hansson 			__func__, ret);
806*f61ab093SUlf Hansson 		goto err_pclk;
807*f61ab093SUlf Hansson 	}
808*f61ab093SUlf Hansson 
8093592b7f6SOla Lilja 	drvdata->clk = clk_get(&pdev->dev, NULL);
8103592b7f6SOla Lilja 	if (IS_ERR(drvdata->clk)) {
8113592b7f6SOla Lilja 		ret = (int)PTR_ERR(drvdata->clk);
8123592b7f6SOla Lilja 		dev_err(&pdev->dev, "%s: ERROR: clk_get failed (%d)!\n",
8133592b7f6SOla Lilja 			__func__, ret);
8143592b7f6SOla Lilja 		goto err_clk;
8153592b7f6SOla Lilja 	}
8163592b7f6SOla Lilja 
8173592b7f6SOla Lilja 	ret = ux500_msp_i2s_init_msp(pdev, &drvdata->msp,
8183592b7f6SOla Lilja 				pdev->dev.platform_data);
8193592b7f6SOla Lilja 	if (!drvdata->msp) {
8203592b7f6SOla Lilja 		dev_err(&pdev->dev,
8213592b7f6SOla Lilja 			"%s: ERROR: Failed to init MSP-struct (%d)!",
8223592b7f6SOla Lilja 			__func__, ret);
8233592b7f6SOla Lilja 		goto err_init_msp;
8243592b7f6SOla Lilja 	}
8253592b7f6SOla Lilja 	dev_set_drvdata(&pdev->dev, drvdata);
8263592b7f6SOla Lilja 
8273592b7f6SOla Lilja 	ret = snd_soc_register_dai(&pdev->dev,
8283592b7f6SOla Lilja 				&ux500_msp_dai_drv[drvdata->msp->id]);
8293592b7f6SOla Lilja 	if (ret < 0) {
8303592b7f6SOla Lilja 		dev_err(&pdev->dev, "Error: %s: Failed to register MSP%d!\n",
8313592b7f6SOla Lilja 			__func__, drvdata->msp->id);
8323592b7f6SOla Lilja 		goto err_init_msp;
8333592b7f6SOla Lilja 	}
8343592b7f6SOla Lilja 
8353592b7f6SOla Lilja 	return 0;
8363592b7f6SOla Lilja 
8373592b7f6SOla Lilja err_init_msp:
8383592b7f6SOla Lilja 	clk_put(drvdata->clk);
8393592b7f6SOla Lilja err_clk:
840*f61ab093SUlf Hansson 	clk_put(drvdata->pclk);
841*f61ab093SUlf Hansson err_pclk:
8423592b7f6SOla Lilja 	devm_regulator_put(drvdata->reg_vape);
8433592b7f6SOla Lilja 
8443592b7f6SOla Lilja 	return ret;
8453592b7f6SOla Lilja }
8463592b7f6SOla Lilja 
8473592b7f6SOla Lilja static int __devexit ux500_msp_drv_remove(struct platform_device *pdev)
8483592b7f6SOla Lilja {
8493592b7f6SOla Lilja 	struct ux500_msp_i2s_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
8503592b7f6SOla Lilja 
8513592b7f6SOla Lilja 	snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(ux500_msp_dai_drv));
8523592b7f6SOla Lilja 
8533592b7f6SOla Lilja 	devm_regulator_put(drvdata->reg_vape);
8543592b7f6SOla Lilja 	prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP, "ux500_msp_i2s");
8553592b7f6SOla Lilja 
8563592b7f6SOla Lilja 	clk_put(drvdata->clk);
857*f61ab093SUlf Hansson 	clk_put(drvdata->pclk);
8583592b7f6SOla Lilja 
8593592b7f6SOla Lilja 	ux500_msp_i2s_cleanup_msp(pdev, drvdata->msp);
8603592b7f6SOla Lilja 
8613592b7f6SOla Lilja 	return 0;
8623592b7f6SOla Lilja }
8633592b7f6SOla Lilja 
86449731c23SLee Jones static const struct of_device_id ux500_msp_i2s_match[] = {
86549731c23SLee Jones 	{ .compatible = "stericsson,ux500-msp-i2s", },
86649731c23SLee Jones 	{},
86749731c23SLee Jones };
86849731c23SLee Jones 
8693592b7f6SOla Lilja static struct platform_driver msp_i2s_driver = {
8703592b7f6SOla Lilja 	.driver = {
8713592b7f6SOla Lilja 		.name = "ux500-msp-i2s",
8723592b7f6SOla Lilja 		.owner = THIS_MODULE,
87349731c23SLee Jones 		.of_match_table = ux500_msp_i2s_match,
8743592b7f6SOla Lilja 	},
8753592b7f6SOla Lilja 	.probe = ux500_msp_drv_probe,
8763592b7f6SOla Lilja 	.remove = ux500_msp_drv_remove,
8773592b7f6SOla Lilja };
8783592b7f6SOla Lilja module_platform_driver(msp_i2s_driver);
8793592b7f6SOla Lilja 
8803592b7f6SOla Lilja MODULE_LICENSE("GPL v2");
881