1*327ef647SSameer Pujar /* SPDX-License-Identifier: GPL-2.0-only */ 2*327ef647SSameer Pujar /* 3*327ef647SSameer Pujar * tegra186_dspk.h - Definitions for Tegra186 DSPK driver 4*327ef647SSameer Pujar * 5*327ef647SSameer Pujar * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. 6*327ef647SSameer Pujar * 7*327ef647SSameer Pujar */ 8*327ef647SSameer Pujar 9*327ef647SSameer Pujar #ifndef __TEGRA186_DSPK_H__ 10*327ef647SSameer Pujar #define __TEGRA186_DSPK_H__ 11*327ef647SSameer Pujar 12*327ef647SSameer Pujar /* Register offsets from DSPK BASE */ 13*327ef647SSameer Pujar #define TEGRA186_DSPK_RX_STATUS 0x0c 14*327ef647SSameer Pujar #define TEGRA186_DSPK_RX_INT_STATUS 0x10 15*327ef647SSameer Pujar #define TEGRA186_DSPK_RX_INT_MASK 0x14 16*327ef647SSameer Pujar #define TEGRA186_DSPK_RX_INT_SET 0x18 17*327ef647SSameer Pujar #define TEGRA186_DSPK_RX_INT_CLEAR 0x1c 18*327ef647SSameer Pujar #define TEGRA186_DSPK_RX_CIF_CTRL 0x20 19*327ef647SSameer Pujar #define TEGRA186_DSPK_ENABLE 0x40 20*327ef647SSameer Pujar #define TEGRA186_DSPK_SOFT_RESET 0x44 21*327ef647SSameer Pujar #define TEGRA186_DSPK_CG 0x48 22*327ef647SSameer Pujar #define TEGRA186_DSPK_STATUS 0x4c 23*327ef647SSameer Pujar #define TEGRA186_DSPK_INT_STATUS 0x50 24*327ef647SSameer Pujar #define TEGRA186_DSPK_CORE_CTRL 0x60 25*327ef647SSameer Pujar #define TEGRA186_DSPK_CODEC_CTRL 0x64 26*327ef647SSameer Pujar 27*327ef647SSameer Pujar /* DSPK CORE CONTROL fields */ 28*327ef647SSameer Pujar #define CH_SEL_SHIFT 8 29*327ef647SSameer Pujar #define TEGRA186_DSPK_CHANNEL_SELECT_MASK (0x3 << CH_SEL_SHIFT) 30*327ef647SSameer Pujar #define DSPK_OSR_SHIFT 4 31*327ef647SSameer Pujar #define TEGRA186_DSPK_OSR_MASK (0x3 << DSPK_OSR_SHIFT) 32*327ef647SSameer Pujar #define LRSEL_POL_SHIFT 0 33*327ef647SSameer Pujar #define TEGRA186_DSPK_CTRL_LRSEL_POLARITY_MASK (0x1 << LRSEL_POL_SHIFT) 34*327ef647SSameer Pujar #define TEGRA186_DSPK_RX_FIFO_DEPTH 64 35*327ef647SSameer Pujar 36*327ef647SSameer Pujar #define DSPK_OSR_FACTOR 32 37*327ef647SSameer Pujar 38*327ef647SSameer Pujar /* DSPK interface clock ratio */ 39*327ef647SSameer Pujar #define DSPK_CLK_RATIO 4 40*327ef647SSameer Pujar 41*327ef647SSameer Pujar enum tegra_dspk_osr { 42*327ef647SSameer Pujar DSPK_OSR_32, 43*327ef647SSameer Pujar DSPK_OSR_64, 44*327ef647SSameer Pujar DSPK_OSR_128, 45*327ef647SSameer Pujar DSPK_OSR_256, 46*327ef647SSameer Pujar }; 47*327ef647SSameer Pujar 48*327ef647SSameer Pujar enum tegra_dspk_ch_sel { 49*327ef647SSameer Pujar DSPK_CH_SELECT_LEFT, 50*327ef647SSameer Pujar DSPK_CH_SELECT_RIGHT, 51*327ef647SSameer Pujar DSPK_CH_SELECT_STEREO, 52*327ef647SSameer Pujar }; 53*327ef647SSameer Pujar 54*327ef647SSameer Pujar enum tegra_dspk_lrsel { 55*327ef647SSameer Pujar DSPK_LRSEL_LEFT, 56*327ef647SSameer Pujar DSPK_LRSEL_RIGHT, 57*327ef647SSameer Pujar }; 58*327ef647SSameer Pujar 59*327ef647SSameer Pujar struct tegra186_dspk { 60*327ef647SSameer Pujar unsigned int rx_fifo_th; 61*327ef647SSameer Pujar unsigned int osr_val; 62*327ef647SSameer Pujar unsigned int lrsel; 63*327ef647SSameer Pujar unsigned int ch_sel; 64*327ef647SSameer Pujar unsigned int mono_to_stereo; 65*327ef647SSameer Pujar unsigned int stereo_to_mono; 66*327ef647SSameer Pujar struct clk *clk_dspk; 67*327ef647SSameer Pujar struct regmap *regmap; 68*327ef647SSameer Pujar }; 69*327ef647SSameer Pujar 70*327ef647SSameer Pujar #endif 71