1210b3ab9STinghan Shen /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2210b3ab9STinghan Shen 3210b3ab9STinghan Shen /* 4210b3ab9STinghan Shen * Copyright (c) 2022 MediaTek Corporation. All rights reserved. 5210b3ab9STinghan Shen * 6210b3ab9STinghan Shen * Header file for the mt8186 DSP clock definition 7210b3ab9STinghan Shen */ 8210b3ab9STinghan Shen 9210b3ab9STinghan Shen #ifndef __MT8186_CLK_H 10210b3ab9STinghan Shen #define __MT8186_CLK_H 11210b3ab9STinghan Shen 12210b3ab9STinghan Shen struct snd_sof_dev; 13210b3ab9STinghan Shen 14210b3ab9STinghan Shen /* DSP clock */ 15210b3ab9STinghan Shen enum adsp_clk_id { 16210b3ab9STinghan Shen CLK_TOP_AUDIODSP, 17210b3ab9STinghan Shen CLK_TOP_ADSP_BUS, 18210b3ab9STinghan Shen ADSP_CLK_MAX 19210b3ab9STinghan Shen }; 20210b3ab9STinghan Shen 21210b3ab9STinghan Shen int mt8186_adsp_init_clock(struct snd_sof_dev *sdev); 22*9ce170dcSTinghan Shen int mt8186_adsp_clock_on(struct snd_sof_dev *sdev); 23*9ce170dcSTinghan Shen void mt8186_adsp_clock_off(struct snd_sof_dev *sdev); 24210b3ab9STinghan Shen #endif 25