1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2017 Intel Corporation. All rights reserved. 7 * 8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 */ 10 11 #ifndef __SOF_INTEL_HDA_H 12 #define __SOF_INTEL_HDA_H 13 14 #include <linux/soundwire/sdw.h> 15 #include <linux/soundwire/sdw_intel.h> 16 #include <sound/compress_driver.h> 17 #include <sound/hda_codec.h> 18 #include <sound/hdaudio_ext.h> 19 #include "../sof-client-probes.h" 20 #include "../sof-audio.h" 21 #include "shim.h" 22 23 /* PCI registers */ 24 #define PCI_TCSEL 0x44 25 #define PCI_PGCTL PCI_TCSEL 26 #define PCI_CGCTL 0x48 27 28 /* PCI_PGCTL bits */ 29 #define PCI_PGCTL_ADSPPGD BIT(2) 30 #define PCI_PGCTL_LSRMD_MASK BIT(4) 31 32 /* PCI_CGCTL bits */ 33 #define PCI_CGCTL_MISCBDCGE_MASK BIT(6) 34 #define PCI_CGCTL_ADSPDCGE BIT(1) 35 36 /* Legacy HDA registers and bits used - widths are variable */ 37 #define SOF_HDA_GCAP 0x0 38 #define SOF_HDA_GCTL 0x8 39 /* accept unsol. response enable */ 40 #define SOF_HDA_GCTL_UNSOL BIT(8) 41 #define SOF_HDA_LLCH 0x14 42 #define SOF_HDA_INTCTL 0x20 43 #define SOF_HDA_INTSTS 0x24 44 #define SOF_HDA_WAKESTS 0x0E 45 #define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1) 46 #define SOF_HDA_RIRBSTS 0x5d 47 48 /* SOF_HDA_GCTL register bist */ 49 #define SOF_HDA_GCTL_RESET BIT(0) 50 51 /* SOF_HDA_INCTL regs */ 52 #define SOF_HDA_INT_GLOBAL_EN BIT(31) 53 #define SOF_HDA_INT_CTRL_EN BIT(30) 54 #define SOF_HDA_INT_ALL_STREAM 0xff 55 56 /* SOF_HDA_INTSTS regs */ 57 #define SOF_HDA_INTSTS_GIS BIT(31) 58 59 #define SOF_HDA_MAX_CAPS 10 60 #define SOF_HDA_CAP_ID_OFF 16 61 #define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\ 62 SOF_HDA_CAP_ID_OFF) 63 #define SOF_HDA_CAP_NEXT_MASK 0xFFFF 64 65 #define SOF_HDA_GTS_CAP_ID 0x1 66 #define SOF_HDA_ML_CAP_ID 0x2 67 68 #define SOF_HDA_PP_CAP_ID 0x3 69 #define SOF_HDA_REG_PP_PPCH 0x10 70 #define SOF_HDA_REG_PP_PPCTL 0x04 71 #define SOF_HDA_REG_PP_PPSTS 0x08 72 #define SOF_HDA_PPCTL_PIE BIT(31) 73 #define SOF_HDA_PPCTL_GPROCEN BIT(30) 74 75 /*Vendor Specific Registers*/ 76 #define SOF_HDA_VS_D0I3C 0x104A 77 78 /* D0I3C Register fields */ 79 #define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */ 80 #define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */ 81 82 /* DPIB entry size: 8 Bytes = 2 DWords */ 83 #define SOF_HDA_DPIB_ENTRY_SIZE 0x8 84 85 #define SOF_HDA_SPIB_CAP_ID 0x4 86 #define SOF_HDA_DRSM_CAP_ID 0x5 87 88 #define SOF_HDA_SPIB_BASE 0x08 89 #define SOF_HDA_SPIB_INTERVAL 0x08 90 #define SOF_HDA_SPIB_SPIB 0x00 91 #define SOF_HDA_SPIB_MAXFIFO 0x04 92 93 #define SOF_HDA_PPHC_BASE 0x10 94 #define SOF_HDA_PPHC_INTERVAL 0x10 95 96 #define SOF_HDA_PPLC_BASE 0x10 97 #define SOF_HDA_PPLC_MULTI 0x10 98 #define SOF_HDA_PPLC_INTERVAL 0x10 99 100 #define SOF_HDA_DRSM_BASE 0x08 101 #define SOF_HDA_DRSM_INTERVAL 0x08 102 103 /* Descriptor error interrupt */ 104 #define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10 105 106 /* FIFO error interrupt */ 107 #define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08 108 109 /* Buffer completion interrupt */ 110 #define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04 111 112 #define SOF_HDA_CL_DMA_SD_INT_MASK \ 113 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \ 114 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \ 115 SOF_HDA_CL_DMA_SD_INT_COMPLETE) 116 #define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */ 117 118 /* Intel HD Audio Code Loader DMA Registers */ 119 #define SOF_HDA_ADSP_LOADER_BASE 0x80 120 #define SOF_HDA_ADSP_DPLBASE 0x70 121 #define SOF_HDA_ADSP_DPUBASE 0x74 122 #define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01 123 124 /* Stream Registers */ 125 #define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00 126 #define SOF_HDA_ADSP_REG_CL_SD_STS 0x03 127 #define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04 128 #define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08 129 #define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C 130 #define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E 131 #define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10 132 #define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12 133 #define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14 134 #define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18 135 #define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C 136 #define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20 137 138 /* CL: Software Position Based FIFO Capability Registers */ 139 #define SOF_DSP_REG_CL_SPBFIFO \ 140 (SOF_HDA_ADSP_LOADER_BASE + 0x20) 141 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0 142 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4 143 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8 144 #define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc 145 146 /* Stream Number */ 147 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20 148 #define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \ 149 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\ 150 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT) 151 152 #define HDA_DSP_HDA_BAR 0 153 #define HDA_DSP_PP_BAR 1 154 #define HDA_DSP_SPIB_BAR 2 155 #define HDA_DSP_DRSM_BAR 3 156 #define HDA_DSP_BAR 4 157 158 #define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000) 159 160 #define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0) 161 162 #define HDA_DSP_PANIC_OFFSET(x) \ 163 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET) 164 165 /* SRAM window 0 FW "registers" */ 166 #define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0) 167 #define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4) 168 /* FW and ROM share offset 4 */ 169 #define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4) 170 #define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8) 171 #define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc) 172 173 #define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000 174 175 #define HDA_DSP_STREAM_RESET_TIMEOUT 300 176 /* 177 * Timeout in us, for setting the stream RUN bit, during 178 * start/stop the stream. The timeout expires if new RUN bit 179 * value cannot be read back within the specified time. 180 */ 181 #define HDA_DSP_STREAM_RUN_TIMEOUT 300 182 183 #define HDA_DSP_SPIB_ENABLE 1 184 #define HDA_DSP_SPIB_DISABLE 0 185 186 #define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE) 187 188 #define HDA_DSP_STACK_DUMP_SIZE 32 189 190 /* ROM/FW status register */ 191 #define FSR_STATE_MASK GENMASK(23, 0) 192 #define FSR_WAIT_STATE_MASK GENMASK(27, 24) 193 #define FSR_MODULE_MASK GENMASK(30, 28) 194 #define FSR_HALTED BIT(31) 195 #define FSR_TO_STATE_CODE(x) ((x) & FSR_STATE_MASK) 196 #define FSR_TO_WAIT_STATE_CODE(x) (((x) & FSR_WAIT_STATE_MASK) >> 24) 197 #define FSR_TO_MODULE_CODE(x) (((x) & FSR_MODULE_MASK) >> 28) 198 199 /* Wait states */ 200 #define FSR_WAIT_FOR_IPC_BUSY 0x1 201 #define FSR_WAIT_FOR_IPC_DONE 0x2 202 #define FSR_WAIT_FOR_CACHE_INVALIDATION 0x3 203 #define FSR_WAIT_FOR_LP_SRAM_OFF 0x4 204 #define FSR_WAIT_FOR_DMA_BUFFER_FULL 0x5 205 #define FSR_WAIT_FOR_CSE_CSR 0x6 206 207 /* Module codes */ 208 #define FSR_MOD_ROM 0x0 209 #define FSR_MOD_ROM_BYP 0x1 210 #define FSR_MOD_BASE_FW 0x2 211 #define FSR_MOD_LP_BOOT 0x3 212 #define FSR_MOD_BRNGUP 0x4 213 #define FSR_MOD_ROM_EXT 0x5 214 215 /* State codes (module dependent) */ 216 /* Module independent states */ 217 #define FSR_STATE_INIT 0x0 218 #define FSR_STATE_INIT_DONE 0x1 219 #define FSR_STATE_FW_ENTERED 0x5 220 221 /* ROM states */ 222 #define FSR_STATE_ROM_INIT FSR_STATE_INIT 223 #define FSR_STATE_ROM_INIT_DONE FSR_STATE_INIT_DONE 224 #define FSR_STATE_ROM_CSE_MANIFEST_LOADED 0x2 225 #define FSR_STATE_ROM_FW_MANIFEST_LOADED 0x3 226 #define FSR_STATE_ROM_FW_FW_LOADED 0x4 227 #define FSR_STATE_ROM_FW_ENTERED FSR_STATE_FW_ENTERED 228 #define FSR_STATE_ROM_VERIFY_FEATURE_MASK 0x6 229 #define FSR_STATE_ROM_GET_LOAD_OFFSET 0x7 230 #define FSR_STATE_ROM_FETCH_ROM_EXT 0x8 231 #define FSR_STATE_ROM_FETCH_ROM_EXT_DONE 0x9 232 233 /* (ROM) CSE states */ 234 #define FSR_STATE_ROM_CSE_IMR_REQUEST 0x10 235 #define FSR_STATE_ROM_CSE_IMR_GRANTED 0x11 236 #define FSR_STATE_ROM_CSE_VALIDATE_IMAGE_REQUEST 0x12 237 #define FSR_STATE_ROM_CSE_IMAGE_VALIDATED 0x13 238 239 #define FSR_STATE_ROM_CSE_IPC_IFACE_INIT 0x20 240 #define FSR_STATE_ROM_CSE_IPC_RESET_PHASE_1 0x21 241 #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL_ENTRY 0x22 242 #define FSR_STATE_ROM_CSE_IPC_OPERATIONAL 0x23 243 #define FSR_STATE_ROM_CSE_IPC_DOWN 0x24 244 245 /* BRINGUP (or BRNGUP) states */ 246 #define FSR_STATE_BRINGUP_INIT FSR_STATE_INIT 247 #define FSR_STATE_BRINGUP_INIT_DONE FSR_STATE_INIT_DONE 248 #define FSR_STATE_BRINGUP_HPSRAM_LOAD 0x2 249 #define FSR_STATE_BRINGUP_UNPACK_START 0X3 250 #define FSR_STATE_BRINGUP_IMR_RESTORE 0x4 251 #define FSR_STATE_BRINGUP_FW_ENTERED FSR_STATE_FW_ENTERED 252 253 /* ROM status/error values */ 254 #define HDA_DSP_ROM_CSE_ERROR 40 255 #define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41 256 #define HDA_DSP_ROM_IMR_TO_SMALL 42 257 #define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43 258 #define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44 259 #define HDA_DSP_ROM_IPC_FATAL_ERROR 45 260 #define HDA_DSP_ROM_L2_CACHE_ERROR 46 261 #define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47 262 #define HDA_DSP_ROM_API_PTR_INVALID 50 263 #define HDA_DSP_ROM_BASEFW_INCOMPAT 51 264 #define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000 265 #define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000 266 #define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000 267 #define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000 268 #define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000 269 #define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55 270 271 #define HDA_DSP_ROM_IPC_CONTROL 0x01000000 272 #define HDA_DSP_ROM_IPC_PURGE_FW 0x00004000 273 274 /* various timeout values */ 275 #define HDA_DSP_PU_TIMEOUT 50 276 #define HDA_DSP_PD_TIMEOUT 50 277 #define HDA_DSP_RESET_TIMEOUT_US 50000 278 #define HDA_DSP_BASEFW_TIMEOUT_US 3000000 279 #define HDA_DSP_INIT_TIMEOUT_US 500000 280 #define HDA_DSP_CTRL_RESET_TIMEOUT 100 281 #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ 282 #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ 283 #define HDA_DSP_REG_POLL_RETRY_COUNT 50 284 285 #define HDA_DSP_ADSPIC_IPC BIT(0) 286 #define HDA_DSP_ADSPIS_IPC BIT(0) 287 288 /* Intel HD Audio General DSP Registers */ 289 #define HDA_DSP_GEN_BASE 0x0 290 #define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04) 291 #define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08) 292 #define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C) 293 #define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10) 294 #define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14) 295 296 #define HDA_DSP_REG_ADSPIS2_SNDW BIT(5) 297 298 /* Intel HD Audio Inter-Processor Communication Registers */ 299 #define HDA_DSP_IPC_BASE 0x40 300 #define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00) 301 #define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04) 302 #define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08) 303 #define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C) 304 #define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10) 305 306 /* Intel Vendor Specific Registers */ 307 #define HDA_VS_INTEL_EM2 0x1030 308 #define HDA_VS_INTEL_EM2_L1SEN BIT(13) 309 #define HDA_VS_INTEL_LTRP_GB_MASK 0x3F 310 311 /* HIPCI */ 312 #define HDA_DSP_REG_HIPCI_BUSY BIT(31) 313 #define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF 314 315 /* HIPCIE */ 316 #define HDA_DSP_REG_HIPCIE_DONE BIT(30) 317 #define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF 318 319 /* HIPCCTL */ 320 #define HDA_DSP_REG_HIPCCTL_DONE BIT(1) 321 #define HDA_DSP_REG_HIPCCTL_BUSY BIT(0) 322 323 /* HIPCT */ 324 #define HDA_DSP_REG_HIPCT_BUSY BIT(31) 325 #define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF 326 327 /* HIPCTE */ 328 #define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF 329 330 #define HDA_DSP_ADSPIC_CL_DMA BIT(1) 331 #define HDA_DSP_ADSPIS_CL_DMA BIT(1) 332 333 /* Delay before scheduling D0i3 entry */ 334 #define BXT_D0I3_DELAY 5000 335 336 #define FW_CL_STREAM_NUMBER 0x1 337 #define HDA_FW_BOOT_ATTEMPTS 3 338 339 /* ADSPCS - Audio DSP Control & Status */ 340 341 /* 342 * Core Reset - asserted high 343 * CRST Mask for a given core mask pattern, cm 344 */ 345 #define HDA_DSP_ADSPCS_CRST_SHIFT 0 346 #define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT) 347 348 /* 349 * Core run/stall - when set to '1' core is stalled 350 * CSTALL Mask for a given core mask pattern, cm 351 */ 352 #define HDA_DSP_ADSPCS_CSTALL_SHIFT 8 353 #define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT) 354 355 /* 356 * Set Power Active - when set to '1' turn cores on 357 * SPA Mask for a given core mask pattern, cm 358 */ 359 #define HDA_DSP_ADSPCS_SPA_SHIFT 16 360 #define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT) 361 362 /* 363 * Current Power Active - power status of cores, set by hardware 364 * CPA Mask for a given core mask pattern, cm 365 */ 366 #define HDA_DSP_ADSPCS_CPA_SHIFT 24 367 #define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT) 368 369 /* 370 * Mask for a given number of cores 371 * nc = number of supported cores 372 */ 373 #define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0) 374 375 /* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/ 376 #define CNL_DSP_IPC_BASE 0xc0 377 #define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00) 378 #define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04) 379 #define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08) 380 #define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10) 381 #define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14) 382 #define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18) 383 #define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28) 384 385 /* HIPCI */ 386 #define CNL_DSP_REG_HIPCIDR_BUSY BIT(31) 387 #define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF 388 389 /* HIPCIE */ 390 #define CNL_DSP_REG_HIPCIDA_DONE BIT(31) 391 #define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF 392 393 /* HIPCCTL */ 394 #define CNL_DSP_REG_HIPCCTL_DONE BIT(1) 395 #define CNL_DSP_REG_HIPCCTL_BUSY BIT(0) 396 397 /* HIPCT */ 398 #define CNL_DSP_REG_HIPCTDR_BUSY BIT(31) 399 #define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF 400 401 /* HIPCTDA */ 402 #define CNL_DSP_REG_HIPCTDA_DONE BIT(31) 403 #define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF 404 405 /* HIPCTDD */ 406 #define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF 407 408 /* BDL */ 409 #define HDA_DSP_BDL_SIZE 4096 410 #define HDA_DSP_MAX_BDL_ENTRIES \ 411 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl)) 412 413 /* Number of DAIs */ 414 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 415 #define SOF_SKL_NUM_DAIS 15 416 #else 417 #define SOF_SKL_NUM_DAIS 8 418 #endif 419 420 /* Intel HD Audio SRAM Window 0*/ 421 #define HDA_ADSP_SRAM0_BASE_SKL 0x8000 422 423 /* Firmware status window */ 424 #define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL 425 #define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4) 426 427 /* Host Device Memory Space */ 428 #define APL_SSP_BASE_OFFSET 0x2000 429 #define CNL_SSP_BASE_OFFSET 0x10000 430 431 /* Host Device Memory Size of a Single SSP */ 432 #define SSP_DEV_MEM_SIZE 0x1000 433 434 /* SSP Count of the Platform */ 435 #define APL_SSP_COUNT 6 436 #define CNL_SSP_COUNT 3 437 #define ICL_SSP_COUNT 6 438 #define TGL_SSP_COUNT 3 439 #define MTL_SSP_COUNT 3 440 441 /* SSP Registers */ 442 #define SSP_SSC1_OFFSET 0x4 443 #define SSP_SET_SCLK_CONSUMER BIT(25) 444 #define SSP_SET_SFRM_CONSUMER BIT(24) 445 #define SSP_SET_CBP_CFP (SSP_SET_SCLK_CONSUMER | SSP_SET_SFRM_CONSUMER) 446 447 #define HDA_IDISP_ADDR 2 448 #define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR)) 449 450 struct sof_intel_dsp_bdl { 451 __le32 addr_l; 452 __le32 addr_h; 453 __le32 size; 454 __le32 ioc; 455 } __attribute((packed)); 456 457 #define SOF_HDA_PLAYBACK_STREAMS 16 458 #define SOF_HDA_CAPTURE_STREAMS 16 459 #define SOF_HDA_PLAYBACK 0 460 #define SOF_HDA_CAPTURE 1 461 462 /* stream flags */ 463 #define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1 464 465 /* 466 * Time in ms for opportunistic D0I3 entry delay. 467 * This has been deliberately chosen to be long to avoid race conditions. 468 * Could be optimized in future. 469 */ 470 #define SOF_HDA_D0I3_WORK_DELAY_MS 5000 471 472 /* HDA DSP D0 substate */ 473 enum sof_hda_D0_substate { 474 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */ 475 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */ 476 }; 477 478 /* represents DSP HDA controller frontend - i.e. host facing control */ 479 struct sof_intel_hda_dev { 480 bool imrboot_supported; 481 bool skip_imr_boot; 482 483 int boot_iteration; 484 485 struct hda_bus hbus; 486 487 /* hw config */ 488 const struct sof_intel_dsp_desc *desc; 489 490 /* trace */ 491 struct hdac_ext_stream *dtrace_stream; 492 493 /* if position update IPC needed */ 494 u32 no_ipc_position; 495 496 /* the maximum number of streams (playback + capture) supported */ 497 u32 stream_max; 498 499 /* PM related */ 500 bool l1_support_changed;/* during suspend, is L1SEN changed or not */ 501 502 /* DMIC device */ 503 struct platform_device *dmic_dev; 504 505 /* delayed work to enter D0I3 opportunistically */ 506 struct delayed_work d0i3_work; 507 508 /* ACPI information stored between scan and probe steps */ 509 struct sdw_intel_acpi_info info; 510 511 /* sdw context allocated by SoundWire driver */ 512 struct sdw_intel_ctx *sdw; 513 514 /* FW clock config, 0:HPRO, 1:LPRO */ 515 bool clk_config_lpro; 516 517 /* Intel NHLT information */ 518 struct nhlt_acpi_table *nhlt; 519 }; 520 521 static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s) 522 { 523 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 524 525 return &hda->hbus.core; 526 } 527 528 static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s) 529 { 530 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata; 531 532 return &hda->hbus; 533 } 534 535 struct sof_intel_hda_stream { 536 struct snd_sof_dev *sdev; 537 struct hdac_ext_stream hext_stream; 538 struct sof_intel_stream sof_intel_stream; 539 int host_reserved; /* reserve host DMA channel */ 540 u32 flags; 541 }; 542 543 #define hstream_to_sof_hda_stream(hstream) \ 544 container_of(hstream, struct sof_intel_hda_stream, hext_stream) 545 546 #define bus_to_sof_hda(bus) \ 547 container_of(bus, struct sof_intel_hda_dev, hbus.core) 548 549 #define SOF_STREAM_SD_OFFSET(s) \ 550 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \ 551 + SOF_HDA_ADSP_LOADER_BASE) 552 553 #define SOF_STREAM_SD_OFFSET_CRST 0x1 554 555 /* 556 * DSP Core services. 557 */ 558 int hda_dsp_probe(struct snd_sof_dev *sdev); 559 int hda_dsp_remove(struct snd_sof_dev *sdev); 560 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask); 561 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask); 562 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask); 563 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 564 unsigned int core_mask); 565 int hda_dsp_core_get(struct snd_sof_dev *sdev, int core); 566 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev); 567 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev); 568 569 int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 570 const struct sof_dsp_power_state *target_state); 571 572 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state); 573 int hda_dsp_resume(struct snd_sof_dev *sdev); 574 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev); 575 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev); 576 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev); 577 int hda_dsp_shutdown(struct snd_sof_dev *sdev); 578 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev); 579 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 580 void hda_ipc_dump(struct snd_sof_dev *sdev); 581 void hda_ipc_irq_dump(struct snd_sof_dev *sdev); 582 void hda_dsp_d0i3_work(struct work_struct *work); 583 584 /* 585 * DSP PCM Operations. 586 */ 587 u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate); 588 u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits); 589 int hda_dsp_pcm_open(struct snd_sof_dev *sdev, 590 struct snd_pcm_substream *substream); 591 int hda_dsp_pcm_close(struct snd_sof_dev *sdev, 592 struct snd_pcm_substream *substream); 593 int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev, 594 struct snd_pcm_substream *substream, 595 struct snd_pcm_hw_params *params, 596 struct snd_sof_platform_stream_params *platform_params); 597 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev, 598 struct snd_pcm_substream *substream); 599 int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev, 600 struct snd_pcm_substream *substream, int cmd); 601 snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev, 602 struct snd_pcm_substream *substream); 603 int hda_dsp_pcm_ack(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 604 605 /* 606 * DSP Stream Operations. 607 */ 608 609 int hda_dsp_stream_init(struct snd_sof_dev *sdev); 610 void hda_dsp_stream_free(struct snd_sof_dev *sdev); 611 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev, 612 struct hdac_ext_stream *hext_stream, 613 struct snd_dma_buffer *dmab, 614 struct snd_pcm_hw_params *params); 615 int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, 616 struct hdac_ext_stream *hext_stream, 617 struct snd_dma_buffer *dmab, 618 struct snd_pcm_hw_params *params); 619 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev, 620 struct hdac_ext_stream *hext_stream, int cmd); 621 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context); 622 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev, 623 struct snd_dma_buffer *dmab, 624 struct hdac_stream *hstream); 625 bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev); 626 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev); 627 628 snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream, 629 int direction, bool can_sleep); 630 631 struct hdac_ext_stream * 632 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags); 633 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag); 634 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev, 635 struct hdac_ext_stream *hext_stream, 636 int enable, u32 size); 637 638 int hda_ipc_msg_data(struct snd_sof_dev *sdev, 639 struct snd_pcm_substream *substream, 640 void *p, size_t sz); 641 int hda_set_stream_data_offset(struct snd_sof_dev *sdev, 642 struct snd_pcm_substream *substream, 643 size_t posn_offset); 644 645 /* 646 * DSP IPC Operations. 647 */ 648 int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, 649 struct snd_sof_ipc_msg *msg); 650 void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev); 651 int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 652 int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 653 654 irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); 655 int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); 656 657 /* 658 * DSP Code loader. 659 */ 660 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev); 661 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev); 662 int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream); 663 struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format, 664 unsigned int size, struct snd_dma_buffer *dmab, 665 int direction); 666 int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 667 struct hdac_ext_stream *hext_stream); 668 int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot); 669 #define HDA_CL_STREAM_FORMAT 0x40 670 671 /* pre and post fw run ops */ 672 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev); 673 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev); 674 675 /* parse platform specific ext manifest ops */ 676 int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev, 677 const struct sof_ext_man_elem_header *hdr); 678 679 /* 680 * HDA Controller Operations. 681 */ 682 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev); 683 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable); 684 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable); 685 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset); 686 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable); 687 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable); 688 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset); 689 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev); 690 /* 691 * HDA bus operations. 692 */ 693 void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev); 694 695 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 696 /* 697 * HDA Codec operations. 698 */ 699 void hda_codec_probe_bus(struct snd_sof_dev *sdev, 700 bool hda_codec_use_common_hdmi); 701 void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable); 702 void hda_codec_jack_check(struct snd_sof_dev *sdev); 703 704 #endif /* CONFIG_SND_SOC_SOF_HDA */ 705 706 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \ 707 (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \ 708 IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) 709 710 void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable); 711 int hda_codec_i915_init(struct snd_sof_dev *sdev); 712 int hda_codec_i915_exit(struct snd_sof_dev *sdev); 713 714 #else 715 716 static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev, 717 bool enable) { } 718 static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; } 719 static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; } 720 721 #endif 722 723 /* 724 * Trace Control. 725 */ 726 int hda_dsp_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 727 struct sof_ipc_dma_trace_params_ext *dtrace_params); 728 int hda_dsp_trace_release(struct snd_sof_dev *sdev); 729 int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); 730 731 /* 732 * SoundWire support 733 */ 734 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 735 736 int hda_sdw_startup(struct snd_sof_dev *sdev); 737 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable); 738 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev); 739 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev); 740 741 #else 742 743 static inline int hda_sdw_startup(struct snd_sof_dev *sdev) 744 { 745 return 0; 746 } 747 748 static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 749 { 750 } 751 752 static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 753 { 754 } 755 756 static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 757 { 758 return false; 759 } 760 761 #endif 762 763 /* common dai driver */ 764 extern struct snd_soc_dai_driver skl_dai[]; 765 int hda_dsp_dais_suspend(struct snd_sof_dev *sdev); 766 767 /* 768 * Platform Specific HW abstraction Ops. 769 */ 770 extern struct snd_sof_dsp_ops sof_hda_common_ops; 771 772 extern struct snd_sof_dsp_ops sof_apl_ops; 773 int sof_apl_ops_init(struct snd_sof_dev *sdev); 774 extern struct snd_sof_dsp_ops sof_cnl_ops; 775 int sof_cnl_ops_init(struct snd_sof_dev *sdev); 776 extern struct snd_sof_dsp_ops sof_tgl_ops; 777 int sof_tgl_ops_init(struct snd_sof_dev *sdev); 778 extern struct snd_sof_dsp_ops sof_icl_ops; 779 int sof_icl_ops_init(struct snd_sof_dev *sdev); 780 extern struct snd_sof_dsp_ops sof_mtl_ops; 781 int sof_mtl_ops_init(struct snd_sof_dev *sdev); 782 783 extern const struct sof_intel_dsp_desc apl_chip_info; 784 extern const struct sof_intel_dsp_desc cnl_chip_info; 785 extern const struct sof_intel_dsp_desc icl_chip_info; 786 extern const struct sof_intel_dsp_desc tgl_chip_info; 787 extern const struct sof_intel_dsp_desc tglh_chip_info; 788 extern const struct sof_intel_dsp_desc ehl_chip_info; 789 extern const struct sof_intel_dsp_desc jsl_chip_info; 790 extern const struct sof_intel_dsp_desc adls_chip_info; 791 extern const struct sof_intel_dsp_desc mtl_chip_info; 792 793 /* Probes support */ 794 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) 795 int hda_probes_register(struct snd_sof_dev *sdev); 796 void hda_probes_unregister(struct snd_sof_dev *sdev); 797 #else 798 static inline int hda_probes_register(struct snd_sof_dev *sdev) 799 { 800 return 0; 801 } 802 803 static inline void hda_probes_unregister(struct snd_sof_dev *sdev) 804 { 805 } 806 #endif /* CONFIG_SND_SOC_SOF_HDA_PROBES */ 807 808 /* SOF client registration for HDA platforms */ 809 int hda_register_clients(struct snd_sof_dev *sdev); 810 void hda_unregister_clients(struct snd_sof_dev *sdev); 811 812 /* machine driver select */ 813 struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev); 814 void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 815 struct snd_sof_dev *sdev); 816 817 /* PCI driver selection and probe */ 818 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id); 819 820 struct snd_sof_dai; 821 struct sof_ipc_dai_config; 822 int hda_ctrl_dai_widget_setup(struct snd_soc_dapm_widget *w, unsigned int quirk_flags, 823 struct snd_sof_dai_config_data *data); 824 int hda_ctrl_dai_widget_free(struct snd_soc_dapm_widget *w, unsigned int quirk_flags, 825 struct snd_sof_dai_config_data *data); 826 827 #define SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY (0) /* previous implementation */ 828 #define SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS (1) /* recommended if VC0 only */ 829 #define SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE (2) /* recommended with VC0 or VC1 */ 830 831 extern int sof_hda_position_quirk; 832 833 void hda_set_dai_drv_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *ops); 834 void hda_ops_free(struct snd_sof_dev *sdev); 835 836 /* IPC4 */ 837 irqreturn_t cnl_ipc4_irq_thread(int irq, void *context); 838 int cnl_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); 839 irqreturn_t hda_dsp_ipc4_irq_thread(int irq, void *context); 840 int hda_dsp_ipc4_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); 841 extern struct sdw_intel_ops sdw_callback; 842 843 #endif 844