1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <sound/hdaudio_ext.h> 19 #include <sound/hda_register.h> 20 21 #include <linux/acpi.h> 22 #include <linux/module.h> 23 #include <linux/soundwire/sdw.h> 24 #include <linux/soundwire/sdw_intel.h> 25 #include <sound/intel-dsp-config.h> 26 #include <sound/intel-nhlt.h> 27 #include <sound/sof.h> 28 #include <sound/sof/xtensa.h> 29 #include "../sof-audio.h" 30 #include "../sof-pci-dev.h" 31 #include "../ops.h" 32 #include "hda.h" 33 34 #define CREATE_TRACE_POINTS 35 #include <trace/events/sof_intel.h> 36 37 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 38 #include <sound/soc-acpi-intel-match.h> 39 #endif 40 41 /* platform specific devices */ 42 #include "shim.h" 43 44 #define EXCEPT_MAX_HDR_SIZE 0x400 45 #define HDA_EXT_ROM_STATUS_SIZE 8 46 47 static u32 hda_get_interface_mask(struct snd_sof_dev *sdev) 48 { 49 const struct sof_intel_dsp_desc *chip; 50 u32 interface_mask[2] = { 0 }; 51 52 chip = get_chip_info(sdev->pdata); 53 switch (chip->hw_ip_version) { 54 case SOF_INTEL_TANGIER: 55 case SOF_INTEL_BAYTRAIL: 56 case SOF_INTEL_BROADWELL: 57 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP); 58 break; 59 case SOF_INTEL_CAVS_1_5: 60 case SOF_INTEL_CAVS_1_5_PLUS: 61 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 62 BIT(SOF_DAI_INTEL_HDA); 63 interface_mask[1] = BIT(SOF_DAI_INTEL_HDA); 64 break; 65 case SOF_INTEL_CAVS_1_8: 66 case SOF_INTEL_CAVS_2_0: 67 case SOF_INTEL_CAVS_2_5: 68 case SOF_INTEL_ACE_1_0: 69 interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 70 BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH); 71 interface_mask[1] = BIT(SOF_DAI_INTEL_HDA); 72 break; 73 default: 74 break; 75 } 76 77 return interface_mask[sdev->dspless_mode_selected]; 78 } 79 80 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 81 82 /* 83 * The default for SoundWire clock stop quirks is to power gate the IP 84 * and do a Bus Reset, this will need to be modified when the DSP 85 * needs to remain in D0i3 so that the Master does not lose context 86 * and enumeration is not required on clock restart 87 */ 88 static int sdw_clock_stop_quirks = SDW_INTEL_CLK_STOP_BUS_RESET; 89 module_param(sdw_clock_stop_quirks, int, 0444); 90 MODULE_PARM_DESC(sdw_clock_stop_quirks, "SOF SoundWire clock stop quirks"); 91 92 static int sdw_params_stream(struct device *dev, 93 struct sdw_intel_stream_params_data *params_data) 94 { 95 struct snd_soc_dai *d = params_data->dai; 96 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, params_data->stream); 97 struct snd_sof_dai_config_data data = { 0 }; 98 99 data.dai_index = (params_data->link_id << 8) | d->id; 100 data.dai_data = params_data->alh_stream_id; 101 102 return hda_dai_config(w, SOF_DAI_CONFIG_FLAGS_HW_PARAMS, &data); 103 } 104 105 struct sdw_intel_ops sdw_callback = { 106 .params_stream = sdw_params_stream, 107 }; 108 109 void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 110 { 111 struct sof_intel_hda_dev *hdev; 112 113 hdev = sdev->pdata->hw_pdata; 114 115 if (!hdev->sdw) 116 return; 117 118 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC2, 119 HDA_DSP_REG_ADSPIC2_SNDW, 120 enable ? HDA_DSP_REG_ADSPIC2_SNDW : 0); 121 } 122 123 void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 124 { 125 u32 interface_mask = hda_get_interface_mask(sdev); 126 const struct sof_intel_dsp_desc *chip; 127 128 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 129 return; 130 131 chip = get_chip_info(sdev->pdata); 132 if (chip && chip->enable_sdw_irq) 133 chip->enable_sdw_irq(sdev, enable); 134 } 135 136 static int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 137 { 138 u32 interface_mask = hda_get_interface_mask(sdev); 139 struct sof_intel_hda_dev *hdev; 140 acpi_handle handle; 141 int ret; 142 143 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 144 return -EINVAL; 145 146 handle = ACPI_HANDLE(sdev->dev); 147 148 /* save ACPI info for the probe step */ 149 hdev = sdev->pdata->hw_pdata; 150 151 ret = sdw_intel_acpi_scan(handle, &hdev->info); 152 if (ret < 0) 153 return -EINVAL; 154 155 return 0; 156 } 157 158 static int hda_sdw_probe(struct snd_sof_dev *sdev) 159 { 160 struct sof_intel_hda_dev *hdev; 161 struct sdw_intel_res res; 162 void *sdw; 163 164 hdev = sdev->pdata->hw_pdata; 165 166 memset(&res, 0, sizeof(res)); 167 168 res.hw_ops = &sdw_intel_cnl_hw_ops; 169 res.mmio_base = sdev->bar[HDA_DSP_BAR]; 170 res.shim_base = hdev->desc->sdw_shim_base; 171 res.alh_base = hdev->desc->sdw_alh_base; 172 res.irq = sdev->ipc_irq; 173 res.handle = hdev->info.handle; 174 res.parent = sdev->dev; 175 res.ops = &sdw_callback; 176 res.dev = sdev->dev; 177 res.clock_stop_quirks = sdw_clock_stop_quirks; 178 179 /* 180 * ops and arg fields are not populated for now, 181 * they will be needed when the DAI callbacks are 182 * provided 183 */ 184 185 /* we could filter links here if needed, e.g for quirks */ 186 res.count = hdev->info.count; 187 res.link_mask = hdev->info.link_mask; 188 189 sdw = sdw_intel_probe(&res); 190 if (!sdw) { 191 dev_err(sdev->dev, "error: SoundWire probe failed\n"); 192 return -EINVAL; 193 } 194 195 /* save context */ 196 hdev->sdw = sdw; 197 198 return 0; 199 } 200 201 int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev) 202 { 203 struct sof_intel_hda_dev *hdev; 204 struct sdw_intel_ctx *ctx; 205 u32 caps; 206 207 hdev = sdev->pdata->hw_pdata; 208 ctx = hdev->sdw; 209 210 caps = snd_sof_dsp_read(sdev, HDA_DSP_BAR, ctx->shim_base + SDW_SHIM_LCAP); 211 caps &= SDW_SHIM_LCAP_LCOUNT_MASK; 212 213 /* Check HW supported vs property value */ 214 if (caps < ctx->count) { 215 dev_err(sdev->dev, 216 "BIOS master count %d is larger than hardware capabilities %d\n", 217 ctx->count, caps); 218 return -EINVAL; 219 } 220 221 return 0; 222 } 223 224 static int hda_sdw_check_lcount(struct snd_sof_dev *sdev) 225 { 226 const struct sof_intel_dsp_desc *chip; 227 228 chip = get_chip_info(sdev->pdata); 229 if (chip && chip->read_sdw_lcount) 230 return chip->read_sdw_lcount(sdev); 231 232 return 0; 233 } 234 235 int hda_sdw_startup(struct snd_sof_dev *sdev) 236 { 237 struct sof_intel_hda_dev *hdev; 238 struct snd_sof_pdata *pdata = sdev->pdata; 239 int ret; 240 241 hdev = sdev->pdata->hw_pdata; 242 243 if (!hdev->sdw) 244 return 0; 245 246 if (pdata->machine && !pdata->machine->mach_params.link_mask) 247 return 0; 248 249 ret = hda_sdw_check_lcount(sdev); 250 if (ret < 0) 251 return ret; 252 253 return sdw_intel_startup(hdev->sdw); 254 } 255 256 static int hda_sdw_exit(struct snd_sof_dev *sdev) 257 { 258 struct sof_intel_hda_dev *hdev; 259 260 hdev = sdev->pdata->hw_pdata; 261 262 hda_sdw_int_enable(sdev, false); 263 264 if (hdev->sdw) 265 sdw_intel_exit(hdev->sdw); 266 hdev->sdw = NULL; 267 268 return 0; 269 } 270 271 bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 272 { 273 struct sof_intel_hda_dev *hdev; 274 bool ret = false; 275 u32 irq_status; 276 277 hdev = sdev->pdata->hw_pdata; 278 279 if (!hdev->sdw) 280 return ret; 281 282 /* store status */ 283 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS2); 284 285 /* invalid message ? */ 286 if (irq_status == 0xffffffff) 287 goto out; 288 289 /* SDW message ? */ 290 if (irq_status & HDA_DSP_REG_ADSPIS2_SNDW) 291 ret = true; 292 293 out: 294 return ret; 295 } 296 297 static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 298 { 299 u32 interface_mask = hda_get_interface_mask(sdev); 300 const struct sof_intel_dsp_desc *chip; 301 302 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 303 return false; 304 305 chip = get_chip_info(sdev->pdata); 306 if (chip && chip->check_sdw_irq) 307 return chip->check_sdw_irq(sdev); 308 309 return false; 310 } 311 312 static irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 313 { 314 return sdw_intel_thread(irq, context); 315 } 316 317 static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 318 { 319 u32 interface_mask = hda_get_interface_mask(sdev); 320 struct sof_intel_hda_dev *hdev; 321 322 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 323 return false; 324 325 hdev = sdev->pdata->hw_pdata; 326 if (hdev->sdw && 327 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 328 hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS)) 329 return true; 330 331 return false; 332 } 333 334 void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 335 { 336 u32 interface_mask = hda_get_interface_mask(sdev); 337 struct sof_intel_hda_dev *hdev; 338 339 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 340 return; 341 342 hdev = sdev->pdata->hw_pdata; 343 if (!hdev->sdw) 344 return; 345 346 sdw_intel_process_wakeen_event(hdev->sdw); 347 } 348 349 #else /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 350 static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 351 { 352 return 0; 353 } 354 355 static inline int hda_sdw_probe(struct snd_sof_dev *sdev) 356 { 357 return 0; 358 } 359 360 static inline int hda_sdw_exit(struct snd_sof_dev *sdev) 361 { 362 return 0; 363 } 364 365 static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 366 { 367 return false; 368 } 369 370 static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 371 { 372 return IRQ_HANDLED; 373 } 374 375 static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 376 { 377 return false; 378 } 379 380 #endif /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 381 382 /* 383 * Debug 384 */ 385 386 struct hda_dsp_msg_code { 387 u32 code; 388 const char *text; 389 }; 390 391 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 392 static bool hda_use_msi = true; 393 module_param_named(use_msi, hda_use_msi, bool, 0444); 394 MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode"); 395 #else 396 #define hda_use_msi (1) 397 #endif 398 399 int sof_hda_position_quirk = SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS; 400 module_param_named(position_quirk, sof_hda_position_quirk, int, 0444); 401 MODULE_PARM_DESC(position_quirk, "SOF HDaudio position quirk"); 402 403 static char *hda_model; 404 module_param(hda_model, charp, 0444); 405 MODULE_PARM_DESC(hda_model, "Use the given HDA board model."); 406 407 static int dmic_num_override = -1; 408 module_param_named(dmic_num, dmic_num_override, int, 0444); 409 MODULE_PARM_DESC(dmic_num, "SOF HDA DMIC number"); 410 411 static int mclk_id_override = -1; 412 module_param_named(mclk_id, mclk_id_override, int, 0444); 413 MODULE_PARM_DESC(mclk_id, "SOF SSP mclk_id"); 414 415 static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = { 416 {HDA_DSP_ROM_CSE_ERROR, "error: cse error"}, 417 {HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"}, 418 {HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"}, 419 {HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"}, 420 {HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"}, 421 {HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"}, 422 {HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"}, 423 {HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"}, 424 {HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"}, 425 {HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"}, 426 {HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"}, 427 {HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"}, 428 {HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"}, 429 {HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"}, 430 {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"}, 431 {HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"}, 432 }; 433 434 #define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state} 435 static const struct hda_dsp_msg_code fsr_rom_state_names[] = { 436 FSR_ROM_STATE_ENTRY(INIT), 437 FSR_ROM_STATE_ENTRY(INIT_DONE), 438 FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED), 439 FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED), 440 FSR_ROM_STATE_ENTRY(FW_FW_LOADED), 441 FSR_ROM_STATE_ENTRY(FW_ENTERED), 442 FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK), 443 FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET), 444 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT), 445 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT_DONE), 446 /* CSE states */ 447 FSR_ROM_STATE_ENTRY(CSE_IMR_REQUEST), 448 FSR_ROM_STATE_ENTRY(CSE_IMR_GRANTED), 449 FSR_ROM_STATE_ENTRY(CSE_VALIDATE_IMAGE_REQUEST), 450 FSR_ROM_STATE_ENTRY(CSE_IMAGE_VALIDATED), 451 FSR_ROM_STATE_ENTRY(CSE_IPC_IFACE_INIT), 452 FSR_ROM_STATE_ENTRY(CSE_IPC_RESET_PHASE_1), 453 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL_ENTRY), 454 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL), 455 FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN), 456 }; 457 458 #define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state} 459 static const struct hda_dsp_msg_code fsr_bringup_state_names[] = { 460 FSR_BRINGUP_STATE_ENTRY(INIT), 461 FSR_BRINGUP_STATE_ENTRY(INIT_DONE), 462 FSR_BRINGUP_STATE_ENTRY(HPSRAM_LOAD), 463 FSR_BRINGUP_STATE_ENTRY(UNPACK_START), 464 FSR_BRINGUP_STATE_ENTRY(IMR_RESTORE), 465 FSR_BRINGUP_STATE_ENTRY(FW_ENTERED), 466 }; 467 468 #define FSR_WAIT_STATE_ENTRY(state) {FSR_WAIT_FOR_##state, #state} 469 static const struct hda_dsp_msg_code fsr_wait_state_names[] = { 470 FSR_WAIT_STATE_ENTRY(IPC_BUSY), 471 FSR_WAIT_STATE_ENTRY(IPC_DONE), 472 FSR_WAIT_STATE_ENTRY(CACHE_INVALIDATION), 473 FSR_WAIT_STATE_ENTRY(LP_SRAM_OFF), 474 FSR_WAIT_STATE_ENTRY(DMA_BUFFER_FULL), 475 FSR_WAIT_STATE_ENTRY(CSE_CSR), 476 }; 477 478 #define FSR_MODULE_NAME_ENTRY(mod) [FSR_MOD_##mod] = #mod 479 static const char * const fsr_module_names[] = { 480 FSR_MODULE_NAME_ENTRY(ROM), 481 FSR_MODULE_NAME_ENTRY(ROM_BYP), 482 FSR_MODULE_NAME_ENTRY(BASE_FW), 483 FSR_MODULE_NAME_ENTRY(LP_BOOT), 484 FSR_MODULE_NAME_ENTRY(BRNGUP), 485 FSR_MODULE_NAME_ENTRY(ROM_EXT), 486 }; 487 488 static const char * 489 hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code, 490 size_t array_size) 491 { 492 int i; 493 494 for (i = 0; i < array_size; i++) { 495 if (code == msg_code[i].code) 496 return msg_code[i].text; 497 } 498 499 return NULL; 500 } 501 502 static void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level) 503 { 504 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 505 const char *state_text, *error_text, *module_text; 506 u32 fsr, state, wait_state, module, error_code; 507 508 fsr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg); 509 state = FSR_TO_STATE_CODE(fsr); 510 wait_state = FSR_TO_WAIT_STATE_CODE(fsr); 511 module = FSR_TO_MODULE_CODE(fsr); 512 513 if (module > FSR_MOD_ROM_EXT) 514 module_text = "unknown"; 515 else 516 module_text = fsr_module_names[module]; 517 518 if (module == FSR_MOD_BRNGUP) 519 state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names, 520 ARRAY_SIZE(fsr_bringup_state_names)); 521 else 522 state_text = hda_dsp_get_state_text(state, fsr_rom_state_names, 523 ARRAY_SIZE(fsr_rom_state_names)); 524 525 /* not for us, must be generic sof message */ 526 if (!state_text) { 527 dev_printk(level, sdev->dev, "%#010x: unknown ROM status value\n", fsr); 528 return; 529 } 530 531 if (wait_state) { 532 const char *wait_state_text; 533 534 wait_state_text = hda_dsp_get_state_text(wait_state, fsr_wait_state_names, 535 ARRAY_SIZE(fsr_wait_state_names)); 536 if (!wait_state_text) 537 wait_state_text = "unknown"; 538 539 dev_printk(level, sdev->dev, 540 "%#010x: module: %s, state: %s, waiting for: %s, %s\n", 541 fsr, module_text, state_text, wait_state_text, 542 fsr & FSR_HALTED ? "not running" : "running"); 543 } else { 544 dev_printk(level, sdev->dev, "%#010x: module: %s, state: %s, %s\n", 545 fsr, module_text, state_text, 546 fsr & FSR_HALTED ? "not running" : "running"); 547 } 548 549 error_code = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + 4); 550 if (!error_code) 551 return; 552 553 error_text = hda_dsp_get_state_text(error_code, hda_dsp_rom_fw_error_texts, 554 ARRAY_SIZE(hda_dsp_rom_fw_error_texts)); 555 if (!error_text) 556 error_text = "unknown"; 557 558 if (state == FSR_STATE_FW_ENTERED) 559 dev_printk(level, sdev->dev, "status code: %#x (%s)\n", error_code, 560 error_text); 561 else 562 dev_printk(level, sdev->dev, "error code: %#x (%s)\n", error_code, 563 error_text); 564 } 565 566 static void hda_dsp_get_registers(struct snd_sof_dev *sdev, 567 struct sof_ipc_dsp_oops_xtensa *xoops, 568 struct sof_ipc_panic_info *panic_info, 569 u32 *stack, size_t stack_words) 570 { 571 u32 offset = sdev->dsp_oops_offset; 572 573 /* first read registers */ 574 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 575 576 /* note: variable AR register array is not read */ 577 578 /* then get panic info */ 579 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 580 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 581 xoops->arch_hdr.totalsize); 582 return; 583 } 584 offset += xoops->arch_hdr.totalsize; 585 sof_block_read(sdev, sdev->mmio_bar, offset, 586 panic_info, sizeof(*panic_info)); 587 588 /* then get the stack */ 589 offset += sizeof(*panic_info); 590 sof_block_read(sdev, sdev->mmio_bar, offset, stack, 591 stack_words * sizeof(u32)); 592 } 593 594 /* dump the first 8 dwords representing the extended ROM status */ 595 static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level, 596 u32 flags) 597 { 598 const struct sof_intel_dsp_desc *chip; 599 char msg[128]; 600 int len = 0; 601 u32 value; 602 int i; 603 604 chip = get_chip_info(sdev->pdata); 605 for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) { 606 value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4); 607 len += scnprintf(msg + len, sizeof(msg) - len, " 0x%x", value); 608 } 609 610 dev_printk(level, sdev->dev, "extended rom status: %s", msg); 611 612 } 613 614 void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 615 { 616 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 617 struct sof_ipc_dsp_oops_xtensa xoops; 618 struct sof_ipc_panic_info panic_info; 619 u32 stack[HDA_DSP_STACK_DUMP_SIZE]; 620 621 /* print ROM/FW status */ 622 hda_dsp_get_state(sdev, level); 623 624 /* The firmware register dump only available with IPC3 */ 625 if (flags & SOF_DBG_DUMP_REGS && sdev->pdata->ipc_type == SOF_IPC) { 626 u32 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_STATUS); 627 u32 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP); 628 629 hda_dsp_get_registers(sdev, &xoops, &panic_info, stack, 630 HDA_DSP_STACK_DUMP_SIZE); 631 sof_print_oops_and_stack(sdev, level, status, panic, &xoops, 632 &panic_info, stack, HDA_DSP_STACK_DUMP_SIZE); 633 } else { 634 hda_dsp_dump_ext_rom_status(sdev, level, flags); 635 } 636 } 637 638 static bool hda_check_ipc_irq(struct snd_sof_dev *sdev) 639 { 640 const struct sof_intel_dsp_desc *chip; 641 642 chip = get_chip_info(sdev->pdata); 643 if (chip && chip->check_ipc_irq) 644 return chip->check_ipc_irq(sdev); 645 646 return false; 647 } 648 649 void hda_ipc_irq_dump(struct snd_sof_dev *sdev) 650 { 651 u32 adspis; 652 u32 intsts; 653 u32 intctl; 654 u32 ppsts; 655 u8 rirbsts; 656 657 /* read key IRQ stats and config registers */ 658 adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS); 659 intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS); 660 intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL); 661 ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS); 662 rirbsts = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS); 663 664 dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n", 665 intsts, intctl, rirbsts); 666 dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis); 667 } 668 669 void hda_ipc_dump(struct snd_sof_dev *sdev) 670 { 671 u32 hipcie; 672 u32 hipct; 673 u32 hipcctl; 674 675 hda_ipc_irq_dump(sdev); 676 677 /* read IPC status */ 678 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 679 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 680 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 681 682 /* dump the IPC regs */ 683 /* TODO: parse the raw msg */ 684 dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", 685 hipcie, hipct, hipcctl); 686 } 687 688 void hda_ipc4_dump(struct snd_sof_dev *sdev) 689 { 690 u32 hipci, hipcie, hipct, hipcte, hipcctl; 691 692 hda_ipc_irq_dump(sdev); 693 694 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI); 695 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 696 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 697 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE); 698 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 699 700 /* dump the IPC regs */ 701 /* TODO: parse the raw msg */ 702 dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n", 703 hipci, hipcie, hipct, hipcte, hipcctl); 704 } 705 706 bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev) 707 { 708 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 709 const struct sof_intel_dsp_desc *chip = hda->desc; 710 u32 val; 711 712 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req); 713 714 return !!(val & chip->ipc_req_mask); 715 } 716 717 static int hda_init(struct snd_sof_dev *sdev) 718 { 719 struct hda_bus *hbus; 720 struct hdac_bus *bus; 721 struct pci_dev *pci = to_pci_dev(sdev->dev); 722 int ret; 723 724 hbus = sof_to_hbus(sdev); 725 bus = sof_to_bus(sdev); 726 727 /* HDA bus init */ 728 sof_hda_bus_init(sdev, &pci->dev); 729 730 if (sof_hda_position_quirk == SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS) 731 bus->use_posbuf = 0; 732 else 733 bus->use_posbuf = 1; 734 bus->bdl_pos_adj = 0; 735 bus->sync_write = 1; 736 737 mutex_init(&hbus->prepare_mutex); 738 hbus->pci = pci; 739 hbus->mixer_assigned = -1; 740 hbus->modelname = hda_model; 741 742 /* initialise hdac bus */ 743 bus->addr = pci_resource_start(pci, 0); 744 bus->remap_addr = pci_ioremap_bar(pci, 0); 745 if (!bus->remap_addr) { 746 dev_err(bus->dev, "error: ioremap error\n"); 747 return -ENXIO; 748 } 749 750 /* HDA base */ 751 sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr; 752 753 /* init i915 and HDMI codecs */ 754 ret = hda_codec_i915_init(sdev); 755 if (ret < 0) 756 dev_warn(sdev->dev, "init of i915 and HDMI codec failed\n"); 757 758 /* get controller capabilities */ 759 ret = hda_dsp_ctrl_get_caps(sdev); 760 if (ret < 0) 761 dev_err(sdev->dev, "error: get caps error\n"); 762 763 return ret; 764 } 765 766 static int check_dmic_num(struct snd_sof_dev *sdev) 767 { 768 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 769 struct nhlt_acpi_table *nhlt; 770 int dmic_num = 0; 771 772 nhlt = hdev->nhlt; 773 if (nhlt) 774 dmic_num = intel_nhlt_get_dmic_geo(sdev->dev, nhlt); 775 776 /* allow for module parameter override */ 777 if (dmic_num_override != -1) { 778 dev_dbg(sdev->dev, 779 "overriding DMICs detected in NHLT tables %d by kernel param %d\n", 780 dmic_num, dmic_num_override); 781 dmic_num = dmic_num_override; 782 } 783 784 if (dmic_num < 0 || dmic_num > 4) { 785 dev_dbg(sdev->dev, "invalid dmic_number %d\n", dmic_num); 786 dmic_num = 0; 787 } 788 789 return dmic_num; 790 } 791 792 static int check_nhlt_ssp_mask(struct snd_sof_dev *sdev) 793 { 794 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 795 struct nhlt_acpi_table *nhlt; 796 int ssp_mask = 0; 797 798 nhlt = hdev->nhlt; 799 if (!nhlt) 800 return ssp_mask; 801 802 if (intel_nhlt_has_endpoint_type(nhlt, NHLT_LINK_SSP)) { 803 ssp_mask = intel_nhlt_ssp_endpoint_mask(nhlt, NHLT_DEVICE_I2S); 804 if (ssp_mask) 805 dev_info(sdev->dev, "NHLT_DEVICE_I2S detected, ssp_mask %#x\n", ssp_mask); 806 } 807 808 return ssp_mask; 809 } 810 811 static int check_nhlt_ssp_mclk_mask(struct snd_sof_dev *sdev, int ssp_num) 812 { 813 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 814 struct nhlt_acpi_table *nhlt; 815 816 nhlt = hdev->nhlt; 817 if (!nhlt) 818 return 0; 819 820 return intel_nhlt_ssp_mclk_mask(nhlt, ssp_num); 821 } 822 823 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) || IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 824 825 static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 826 const char *sof_tplg_filename, 827 const char *idisp_str, 828 const char *dmic_str) 829 { 830 const char *tplg_filename = NULL; 831 char *filename, *tmp; 832 const char *split_ext; 833 834 filename = kstrdup(sof_tplg_filename, GFP_KERNEL); 835 if (!filename) 836 return NULL; 837 838 /* this assumes a .tplg extension */ 839 tmp = filename; 840 split_ext = strsep(&tmp, "."); 841 if (split_ext) 842 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 843 "%s%s%s.tplg", 844 split_ext, idisp_str, dmic_str); 845 kfree(filename); 846 847 return tplg_filename; 848 } 849 850 static int dmic_detect_topology_fixup(struct snd_sof_dev *sdev, 851 const char **tplg_filename, 852 const char *idisp_str, 853 int *dmic_found, 854 bool tplg_fixup) 855 { 856 const char *dmic_str; 857 int dmic_num; 858 859 /* first check for DMICs (using NHLT or module parameter) */ 860 dmic_num = check_dmic_num(sdev); 861 862 switch (dmic_num) { 863 case 1: 864 dmic_str = "-1ch"; 865 break; 866 case 2: 867 dmic_str = "-2ch"; 868 break; 869 case 3: 870 dmic_str = "-3ch"; 871 break; 872 case 4: 873 dmic_str = "-4ch"; 874 break; 875 default: 876 dmic_num = 0; 877 dmic_str = ""; 878 break; 879 } 880 881 if (tplg_fixup) { 882 const char *default_tplg_filename = *tplg_filename; 883 const char *fixed_tplg_filename; 884 885 fixed_tplg_filename = fixup_tplg_name(sdev, default_tplg_filename, 886 idisp_str, dmic_str); 887 if (!fixed_tplg_filename) 888 return -ENOMEM; 889 *tplg_filename = fixed_tplg_filename; 890 } 891 892 dev_info(sdev->dev, "DMICs detected in NHLT tables: %d\n", dmic_num); 893 *dmic_found = dmic_num; 894 895 return 0; 896 } 897 #endif 898 899 static int hda_init_caps(struct snd_sof_dev *sdev) 900 { 901 u32 interface_mask = hda_get_interface_mask(sdev); 902 struct hdac_bus *bus = sof_to_bus(sdev); 903 struct snd_sof_pdata *pdata = sdev->pdata; 904 struct sof_intel_hda_dev *hdev = pdata->hw_pdata; 905 u32 link_mask; 906 int ret = 0; 907 908 /* check if dsp is there */ 909 if (bus->ppcap) 910 dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n"); 911 912 /* Init HDA controller after i915 init */ 913 ret = hda_dsp_ctrl_init_chip(sdev); 914 if (ret < 0) { 915 dev_err(bus->dev, "error: init chip failed with ret: %d\n", 916 ret); 917 return ret; 918 } 919 920 hda_bus_ml_get_capabilities(bus); 921 922 /* Skip SoundWire if it is not supported */ 923 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 924 goto skip_soundwire; 925 926 /* scan SoundWire capabilities exposed by DSDT */ 927 ret = hda_sdw_acpi_scan(sdev); 928 if (ret < 0) { 929 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 930 goto skip_soundwire; 931 } 932 933 link_mask = hdev->info.link_mask; 934 if (!link_mask) { 935 dev_dbg(sdev->dev, "skipping SoundWire, no links enabled\n"); 936 goto skip_soundwire; 937 } 938 939 /* 940 * probe/allocate SoundWire resources. 941 * The hardware configuration takes place in hda_sdw_startup 942 * after power rails are enabled. 943 * It's entirely possible to have a mix of I2S/DMIC/SoundWire 944 * devices, so we allocate the resources in all cases. 945 */ 946 ret = hda_sdw_probe(sdev); 947 if (ret < 0) { 948 dev_err(sdev->dev, "error: SoundWire probe error\n"); 949 return ret; 950 } 951 952 skip_soundwire: 953 954 /* create codec instances */ 955 hda_codec_probe_bus(sdev); 956 957 if (!HDA_IDISP_CODEC(bus->codec_mask)) 958 hda_codec_i915_display_power(sdev, false); 959 960 hda_bus_ml_put_all(bus); 961 962 return 0; 963 } 964 965 static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context) 966 { 967 struct snd_sof_dev *sdev = context; 968 969 /* 970 * Get global interrupt status. It includes all hardware interrupt 971 * sources in the Intel HD Audio controller. 972 */ 973 if (snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS) & 974 SOF_HDA_INTSTS_GIS) { 975 976 /* disable GIE interrupt */ 977 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 978 SOF_HDA_INTCTL, 979 SOF_HDA_INT_GLOBAL_EN, 980 0); 981 982 return IRQ_WAKE_THREAD; 983 } 984 985 return IRQ_NONE; 986 } 987 988 static irqreturn_t hda_dsp_interrupt_thread(int irq, void *context) 989 { 990 struct snd_sof_dev *sdev = context; 991 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 992 993 /* deal with streams and controller first */ 994 if (hda_dsp_check_stream_irq(sdev)) { 995 trace_sof_intel_hda_irq(sdev, "stream"); 996 hda_dsp_stream_threaded_handler(irq, sdev); 997 } 998 999 if (hda_check_ipc_irq(sdev)) { 1000 trace_sof_intel_hda_irq(sdev, "ipc"); 1001 sof_ops(sdev)->irq_thread(irq, sdev); 1002 } 1003 1004 if (hda_dsp_check_sdw_irq(sdev)) { 1005 trace_sof_intel_hda_irq(sdev, "sdw"); 1006 hda_dsp_sdw_thread(irq, hdev->sdw); 1007 } 1008 1009 if (hda_sdw_check_wakeen_irq(sdev)) { 1010 trace_sof_intel_hda_irq(sdev, "wakeen"); 1011 hda_sdw_process_wakeen(sdev); 1012 } 1013 1014 hda_codec_check_for_state_change(sdev); 1015 1016 /* enable GIE interrupt */ 1017 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 1018 SOF_HDA_INTCTL, 1019 SOF_HDA_INT_GLOBAL_EN, 1020 SOF_HDA_INT_GLOBAL_EN); 1021 1022 return IRQ_HANDLED; 1023 } 1024 1025 int hda_dsp_probe(struct snd_sof_dev *sdev) 1026 { 1027 struct pci_dev *pci = to_pci_dev(sdev->dev); 1028 struct sof_intel_hda_dev *hdev; 1029 struct hdac_bus *bus; 1030 const struct sof_intel_dsp_desc *chip; 1031 int ret = 0; 1032 1033 if (!sdev->dspless_mode_selected) { 1034 /* 1035 * detect DSP by checking class/subclass/prog-id information 1036 * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required 1037 * class=04 subclass 01 prog-if 00: DSP is present 1038 * (and may be required e.g. for DMIC or SSP support) 1039 * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works 1040 */ 1041 if (pci->class == 0x040300) { 1042 dev_err(sdev->dev, "the DSP is not enabled on this platform, aborting probe\n"); 1043 return -ENODEV; 1044 } else if (pci->class != 0x040100 && pci->class != 0x040380) { 1045 dev_err(sdev->dev, "unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", 1046 pci->class); 1047 return -ENODEV; 1048 } 1049 dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", 1050 pci->class); 1051 } 1052 1053 chip = get_chip_info(sdev->pdata); 1054 if (!chip) { 1055 dev_err(sdev->dev, "error: no such device supported, chip id:%x\n", 1056 pci->device); 1057 ret = -EIO; 1058 goto err; 1059 } 1060 1061 sdev->num_cores = chip->cores_num; 1062 1063 hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL); 1064 if (!hdev) 1065 return -ENOMEM; 1066 sdev->pdata->hw_pdata = hdev; 1067 hdev->desc = chip; 1068 1069 hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 1070 PLATFORM_DEVID_NONE, 1071 NULL, 0); 1072 if (IS_ERR(hdev->dmic_dev)) { 1073 dev_err(sdev->dev, "error: failed to create DMIC device\n"); 1074 return PTR_ERR(hdev->dmic_dev); 1075 } 1076 1077 /* 1078 * use position update IPC if either it is forced 1079 * or we don't have other choice 1080 */ 1081 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION) 1082 hdev->no_ipc_position = 0; 1083 #else 1084 hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0; 1085 #endif 1086 1087 if (sdev->dspless_mode_selected) 1088 hdev->no_ipc_position = 1; 1089 1090 /* set up HDA base */ 1091 bus = sof_to_bus(sdev); 1092 ret = hda_init(sdev); 1093 if (ret < 0) 1094 goto hdac_bus_unmap; 1095 1096 if (sdev->dspless_mode_selected) 1097 goto skip_dsp_setup; 1098 1099 /* DSP base */ 1100 sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR); 1101 if (!sdev->bar[HDA_DSP_BAR]) { 1102 dev_err(sdev->dev, "error: ioremap error\n"); 1103 ret = -ENXIO; 1104 goto hdac_bus_unmap; 1105 } 1106 1107 sdev->mmio_bar = HDA_DSP_BAR; 1108 sdev->mailbox_bar = HDA_DSP_BAR; 1109 skip_dsp_setup: 1110 1111 /* allow 64bit DMA address if supported by H/W */ 1112 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(64))) { 1113 dev_dbg(sdev->dev, "DMA mask is 32 bit\n"); 1114 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1115 } 1116 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1117 1118 /* init streams */ 1119 ret = hda_dsp_stream_init(sdev); 1120 if (ret < 0) { 1121 dev_err(sdev->dev, "error: failed to init streams\n"); 1122 /* 1123 * not all errors are due to memory issues, but trying 1124 * to free everything does not harm 1125 */ 1126 goto free_streams; 1127 } 1128 1129 /* 1130 * register our IRQ 1131 * let's try to enable msi firstly 1132 * if it fails, use legacy interrupt mode 1133 * TODO: support msi multiple vectors 1134 */ 1135 if (hda_use_msi && pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) > 0) { 1136 dev_info(sdev->dev, "use msi interrupt mode\n"); 1137 sdev->ipc_irq = pci_irq_vector(pci, 0); 1138 /* initialised to "false" by kzalloc() */ 1139 sdev->msi_enabled = true; 1140 } 1141 1142 if (!sdev->msi_enabled) { 1143 dev_info(sdev->dev, "use legacy interrupt mode\n"); 1144 /* 1145 * in IO-APIC mode, hda->irq and ipc_irq are using the same 1146 * irq number of pci->irq 1147 */ 1148 sdev->ipc_irq = pci->irq; 1149 } 1150 1151 dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq); 1152 ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_interrupt_handler, 1153 hda_dsp_interrupt_thread, 1154 IRQF_SHARED, "AudioDSP", sdev); 1155 if (ret < 0) { 1156 dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n", 1157 sdev->ipc_irq); 1158 goto free_irq_vector; 1159 } 1160 1161 pci_set_master(pci); 1162 synchronize_irq(pci->irq); 1163 1164 /* 1165 * clear TCSEL to clear playback on some HD Audio 1166 * codecs. PCI TCSEL is defined in the Intel manuals. 1167 */ 1168 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 1169 1170 /* init HDA capabilities */ 1171 ret = hda_init_caps(sdev); 1172 if (ret < 0) 1173 goto free_ipc_irq; 1174 1175 if (!sdev->dspless_mode_selected) { 1176 /* enable ppcap interrupt */ 1177 hda_dsp_ctrl_ppcap_enable(sdev, true); 1178 hda_dsp_ctrl_ppcap_int_enable(sdev, true); 1179 1180 /* set default mailbox offset for FW ready message */ 1181 sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET; 1182 1183 INIT_DELAYED_WORK(&hdev->d0i3_work, hda_dsp_d0i3_work); 1184 } 1185 1186 init_waitqueue_head(&hdev->waitq); 1187 1188 hdev->nhlt = intel_nhlt_init(sdev->dev); 1189 1190 return 0; 1191 1192 free_ipc_irq: 1193 free_irq(sdev->ipc_irq, sdev); 1194 free_irq_vector: 1195 if (sdev->msi_enabled) 1196 pci_free_irq_vectors(pci); 1197 free_streams: 1198 hda_dsp_stream_free(sdev); 1199 /* dsp_unmap: not currently used */ 1200 if (!sdev->dspless_mode_selected) 1201 iounmap(sdev->bar[HDA_DSP_BAR]); 1202 hdac_bus_unmap: 1203 platform_device_unregister(hdev->dmic_dev); 1204 iounmap(bus->remap_addr); 1205 hda_codec_i915_exit(sdev); 1206 err: 1207 return ret; 1208 } 1209 1210 int hda_dsp_remove(struct snd_sof_dev *sdev) 1211 { 1212 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1213 const struct sof_intel_dsp_desc *chip = hda->desc; 1214 struct hdac_bus *bus = sof_to_bus(sdev); 1215 struct pci_dev *pci = to_pci_dev(sdev->dev); 1216 struct nhlt_acpi_table *nhlt = hda->nhlt; 1217 1218 if (nhlt) 1219 intel_nhlt_free(nhlt); 1220 1221 if (!sdev->dspless_mode_selected) 1222 /* cancel any attempt for DSP D0I3 */ 1223 cancel_delayed_work_sync(&hda->d0i3_work); 1224 1225 hda_codec_device_remove(sdev); 1226 1227 hda_sdw_exit(sdev); 1228 1229 if (!IS_ERR_OR_NULL(hda->dmic_dev)) 1230 platform_device_unregister(hda->dmic_dev); 1231 1232 if (!sdev->dspless_mode_selected) { 1233 /* disable DSP IRQ */ 1234 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 1235 SOF_HDA_PPCTL_PIE, 0); 1236 } 1237 1238 /* disable CIE and GIE interrupts */ 1239 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 1240 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0); 1241 1242 if (sdev->dspless_mode_selected) 1243 goto skip_disable_dsp; 1244 1245 /* no need to check for error as the DSP will be disabled anyway */ 1246 if (chip && chip->power_down_dsp) 1247 chip->power_down_dsp(sdev); 1248 1249 /* disable DSP */ 1250 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 1251 SOF_HDA_PPCTL_GPROCEN, 0); 1252 1253 skip_disable_dsp: 1254 free_irq(sdev->ipc_irq, sdev); 1255 if (sdev->msi_enabled) 1256 pci_free_irq_vectors(pci); 1257 1258 hda_dsp_stream_free(sdev); 1259 1260 hda_bus_ml_free(sof_to_bus(sdev)); 1261 1262 if (!sdev->dspless_mode_selected) 1263 iounmap(sdev->bar[HDA_DSP_BAR]); 1264 1265 iounmap(bus->remap_addr); 1266 1267 sof_hda_bus_exit(sdev); 1268 1269 hda_codec_i915_exit(sdev); 1270 1271 return 0; 1272 } 1273 1274 int hda_power_down_dsp(struct snd_sof_dev *sdev) 1275 { 1276 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1277 const struct sof_intel_dsp_desc *chip = hda->desc; 1278 1279 return hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask); 1280 } 1281 1282 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) 1283 static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1284 struct snd_soc_acpi_mach **mach) 1285 { 1286 struct hdac_bus *bus = sof_to_bus(sdev); 1287 struct snd_soc_acpi_mach_params *mach_params; 1288 struct snd_soc_acpi_mach *hda_mach; 1289 struct snd_sof_pdata *pdata = sdev->pdata; 1290 const char *tplg_filename; 1291 const char *idisp_str; 1292 int dmic_num = 0; 1293 int codec_num = 0; 1294 int ret; 1295 int i; 1296 1297 /* codec detection */ 1298 if (!bus->codec_mask) { 1299 dev_info(bus->dev, "no hda codecs found!\n"); 1300 } else { 1301 dev_info(bus->dev, "hda codecs found, mask %lx\n", 1302 bus->codec_mask); 1303 1304 for (i = 0; i < HDA_MAX_CODECS; i++) { 1305 if (bus->codec_mask & (1 << i)) 1306 codec_num++; 1307 } 1308 1309 /* 1310 * If no machine driver is found, then: 1311 * 1312 * generic hda machine driver can handle: 1313 * - one HDMI codec, and/or 1314 * - one external HDAudio codec 1315 */ 1316 if (!*mach && codec_num <= 2) { 1317 bool tplg_fixup; 1318 1319 hda_mach = snd_soc_acpi_intel_hda_machines; 1320 1321 dev_info(bus->dev, "using HDA machine driver %s now\n", 1322 hda_mach->drv_name); 1323 1324 if (codec_num == 1 && HDA_IDISP_CODEC(bus->codec_mask)) 1325 idisp_str = "-idisp"; 1326 else 1327 idisp_str = ""; 1328 1329 /* topology: use the info from hda_machines */ 1330 if (pdata->tplg_filename) { 1331 tplg_fixup = false; 1332 tplg_filename = pdata->tplg_filename; 1333 } else { 1334 tplg_fixup = true; 1335 tplg_filename = hda_mach->sof_tplg_filename; 1336 } 1337 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, idisp_str, &dmic_num, 1338 tplg_fixup); 1339 if (ret < 0) 1340 return; 1341 1342 hda_mach->mach_params.dmic_num = dmic_num; 1343 pdata->tplg_filename = tplg_filename; 1344 1345 if (codec_num == 2) { 1346 /* 1347 * Prevent SoundWire links from starting when an external 1348 * HDaudio codec is used 1349 */ 1350 hda_mach->mach_params.link_mask = 0; 1351 } 1352 1353 *mach = hda_mach; 1354 } 1355 } 1356 1357 /* used by hda machine driver to create dai links */ 1358 if (*mach) { 1359 mach_params = &(*mach)->mach_params; 1360 mach_params->codec_mask = bus->codec_mask; 1361 mach_params->common_hdmi_codec_drv = true; 1362 } 1363 } 1364 #else 1365 static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1366 struct snd_soc_acpi_mach **mach) 1367 { 1368 } 1369 #endif 1370 1371 #if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 1372 1373 #define SDW_CODEC_ADR_MASK(_adr) ((_adr) & (SDW_DISCO_LINK_ID_MASK | SDW_VERSION_MASK | \ 1374 SDW_MFG_ID_MASK | SDW_PART_ID_MASK)) 1375 1376 /* Check if all Slaves defined on the link can be found */ 1377 static bool link_slaves_found(struct snd_sof_dev *sdev, 1378 const struct snd_soc_acpi_link_adr *link, 1379 struct sdw_intel_ctx *sdw) 1380 { 1381 struct hdac_bus *bus = sof_to_bus(sdev); 1382 struct sdw_intel_slave_id *ids = sdw->ids; 1383 int num_slaves = sdw->num_slaves; 1384 unsigned int part_id, link_id, unique_id, mfg_id, version; 1385 int i, j, k; 1386 1387 for (i = 0; i < link->num_adr; i++) { 1388 u64 adr = link->adr_d[i].adr; 1389 int reported_part_count = 0; 1390 1391 mfg_id = SDW_MFG_ID(adr); 1392 part_id = SDW_PART_ID(adr); 1393 link_id = SDW_DISCO_LINK_ID(adr); 1394 version = SDW_VERSION(adr); 1395 1396 for (j = 0; j < num_slaves; j++) { 1397 /* find out how many identical parts were reported on that link */ 1398 if (ids[j].link_id == link_id && 1399 ids[j].id.part_id == part_id && 1400 ids[j].id.mfg_id == mfg_id && 1401 ids[j].id.sdw_version == version) 1402 reported_part_count++; 1403 } 1404 1405 for (j = 0; j < num_slaves; j++) { 1406 int expected_part_count = 0; 1407 1408 if (ids[j].link_id != link_id || 1409 ids[j].id.part_id != part_id || 1410 ids[j].id.mfg_id != mfg_id || 1411 ids[j].id.sdw_version != version) 1412 continue; 1413 1414 /* find out how many identical parts are expected */ 1415 for (k = 0; k < link->num_adr; k++) { 1416 u64 adr2 = link->adr_d[k].adr; 1417 1418 if (SDW_CODEC_ADR_MASK(adr2) == SDW_CODEC_ADR_MASK(adr)) 1419 expected_part_count++; 1420 } 1421 1422 if (reported_part_count == expected_part_count) { 1423 /* 1424 * we have to check unique id 1425 * if there is more than one 1426 * Slave on the link 1427 */ 1428 unique_id = SDW_UNIQUE_ID(adr); 1429 if (reported_part_count == 1 || 1430 ids[j].id.unique_id == unique_id) { 1431 dev_dbg(bus->dev, "found %x at link %d\n", 1432 part_id, link_id); 1433 break; 1434 } 1435 } else { 1436 dev_dbg(bus->dev, "part %x reported %d expected %d on link %d, skipping\n", 1437 part_id, reported_part_count, expected_part_count, link_id); 1438 } 1439 } 1440 if (j == num_slaves) { 1441 dev_dbg(bus->dev, 1442 "Slave %x not found\n", 1443 part_id); 1444 return false; 1445 } 1446 } 1447 return true; 1448 } 1449 1450 static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1451 { 1452 struct snd_sof_pdata *pdata = sdev->pdata; 1453 const struct snd_soc_acpi_link_adr *link; 1454 struct snd_soc_acpi_mach *mach; 1455 struct sof_intel_hda_dev *hdev; 1456 u32 link_mask; 1457 int i; 1458 1459 hdev = pdata->hw_pdata; 1460 link_mask = hdev->info.link_mask; 1461 1462 /* 1463 * Select SoundWire machine driver if needed using the 1464 * alternate tables. This case deals with SoundWire-only 1465 * machines, for mixed cases with I2C/I2S the detection relies 1466 * on the HID list. 1467 */ 1468 if (link_mask) { 1469 for (mach = pdata->desc->alt_machines; 1470 mach && mach->link_mask; mach++) { 1471 /* 1472 * On some platforms such as Up Extreme all links 1473 * are enabled but only one link can be used by 1474 * external codec. Instead of exact match of two masks, 1475 * first check whether link_mask of mach is subset of 1476 * link_mask supported by hw and then go on searching 1477 * link_adr 1478 */ 1479 if (~link_mask & mach->link_mask) 1480 continue; 1481 1482 /* No need to match adr if there is no links defined */ 1483 if (!mach->links) 1484 break; 1485 1486 link = mach->links; 1487 for (i = 0; i < hdev->info.count && link->num_adr; 1488 i++, link++) { 1489 /* 1490 * Try next machine if any expected Slaves 1491 * are not found on this link. 1492 */ 1493 if (!link_slaves_found(sdev, link, hdev->sdw)) 1494 break; 1495 } 1496 /* Found if all Slaves are checked */ 1497 if (i == hdev->info.count || !link->num_adr) 1498 break; 1499 } 1500 if (mach && mach->link_mask) { 1501 int dmic_num = 0; 1502 bool tplg_fixup; 1503 const char *tplg_filename; 1504 1505 mach->mach_params.links = mach->links; 1506 mach->mach_params.link_mask = mach->link_mask; 1507 mach->mach_params.platform = dev_name(sdev->dev); 1508 1509 if (pdata->tplg_filename) { 1510 tplg_fixup = false; 1511 } else { 1512 tplg_fixup = true; 1513 tplg_filename = mach->sof_tplg_filename; 1514 } 1515 1516 /* 1517 * DMICs use up to 4 pins and are typically pin-muxed with SoundWire 1518 * link 2 and 3, or link 1 and 2, thus we only try to enable dmics 1519 * if all conditions are true: 1520 * a) 2 or fewer links are used by SoundWire 1521 * b) the NHLT table reports the presence of microphones 1522 */ 1523 if (hweight_long(mach->link_mask) <= 2) { 1524 int ret; 1525 1526 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, "", 1527 &dmic_num, tplg_fixup); 1528 if (ret < 0) 1529 return NULL; 1530 } 1531 if (tplg_fixup) 1532 pdata->tplg_filename = tplg_filename; 1533 mach->mach_params.dmic_num = dmic_num; 1534 1535 dev_dbg(sdev->dev, 1536 "SoundWire machine driver %s topology %s\n", 1537 mach->drv_name, 1538 pdata->tplg_filename); 1539 1540 return mach; 1541 } 1542 1543 dev_info(sdev->dev, "No SoundWire machine driver found\n"); 1544 } 1545 1546 return NULL; 1547 } 1548 #else 1549 static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1550 { 1551 return NULL; 1552 } 1553 #endif 1554 1555 void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 1556 struct snd_sof_dev *sdev) 1557 { 1558 struct snd_sof_pdata *pdata = sdev->pdata; 1559 const struct sof_dev_desc *desc = pdata->desc; 1560 struct snd_soc_acpi_mach_params *mach_params; 1561 1562 mach_params = &mach->mach_params; 1563 mach_params->platform = dev_name(sdev->dev); 1564 mach_params->num_dai_drivers = desc->ops->num_drv; 1565 mach_params->dai_drivers = desc->ops->drv; 1566 } 1567 1568 struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev) 1569 { 1570 u32 interface_mask = hda_get_interface_mask(sdev); 1571 struct snd_sof_pdata *sof_pdata = sdev->pdata; 1572 const struct sof_dev_desc *desc = sof_pdata->desc; 1573 struct snd_soc_acpi_mach *mach = NULL; 1574 const char *tplg_filename; 1575 1576 /* Try I2S or DMIC if it is supported */ 1577 if (interface_mask & (BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC))) 1578 mach = snd_soc_acpi_find_machine(desc->machines); 1579 1580 if (mach) { 1581 bool add_extension = false; 1582 bool tplg_fixup = false; 1583 1584 /* 1585 * If tplg file name is overridden, use it instead of 1586 * the one set in mach table 1587 */ 1588 if (!sof_pdata->tplg_filename) { 1589 sof_pdata->tplg_filename = mach->sof_tplg_filename; 1590 tplg_fixup = true; 1591 } 1592 1593 /* report to machine driver if any DMICs are found */ 1594 mach->mach_params.dmic_num = check_dmic_num(sdev); 1595 1596 if (tplg_fixup && 1597 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_DMIC_NUMBER && 1598 mach->mach_params.dmic_num) { 1599 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1600 "%s%s%d%s", 1601 sof_pdata->tplg_filename, 1602 "-dmic", 1603 mach->mach_params.dmic_num, 1604 "ch"); 1605 if (!tplg_filename) 1606 return NULL; 1607 1608 sof_pdata->tplg_filename = tplg_filename; 1609 add_extension = true; 1610 } 1611 1612 if (mach->link_mask) { 1613 mach->mach_params.links = mach->links; 1614 mach->mach_params.link_mask = mach->link_mask; 1615 } 1616 1617 /* report SSP link mask to machine driver */ 1618 mach->mach_params.i2s_link_mask = check_nhlt_ssp_mask(sdev); 1619 1620 if (tplg_fixup && 1621 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_NUMBER && 1622 mach->mach_params.i2s_link_mask) { 1623 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 1624 int ssp_num; 1625 int mclk_mask; 1626 1627 if (hweight_long(mach->mach_params.i2s_link_mask) > 1 && 1628 !(mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_MSB)) 1629 dev_warn(sdev->dev, "More than one SSP exposed by NHLT, choosing MSB\n"); 1630 1631 /* fls returns 1-based results, SSPs indices are 0-based */ 1632 ssp_num = fls(mach->mach_params.i2s_link_mask) - 1; 1633 1634 if (ssp_num >= chip->ssp_count) { 1635 dev_err(sdev->dev, "Invalid SSP %d, max on this platform is %d\n", 1636 ssp_num, chip->ssp_count); 1637 return NULL; 1638 } 1639 1640 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1641 "%s%s%d", 1642 sof_pdata->tplg_filename, 1643 "-ssp", 1644 ssp_num); 1645 if (!tplg_filename) 1646 return NULL; 1647 1648 sof_pdata->tplg_filename = tplg_filename; 1649 add_extension = true; 1650 1651 mclk_mask = check_nhlt_ssp_mclk_mask(sdev, ssp_num); 1652 1653 if (mclk_mask < 0) { 1654 dev_err(sdev->dev, "Invalid MCLK configuration\n"); 1655 return NULL; 1656 } 1657 1658 dev_dbg(sdev->dev, "MCLK mask %#x found in NHLT\n", mclk_mask); 1659 1660 if (mclk_mask) { 1661 dev_info(sdev->dev, "Overriding topology with MCLK mask %#x from NHLT\n", mclk_mask); 1662 sdev->mclk_id_override = true; 1663 sdev->mclk_id_quirk = (mclk_mask & BIT(0)) ? 0 : 1; 1664 } 1665 } 1666 1667 if (tplg_fixup && add_extension) { 1668 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1669 "%s%s", 1670 sof_pdata->tplg_filename, 1671 ".tplg"); 1672 if (!tplg_filename) 1673 return NULL; 1674 1675 sof_pdata->tplg_filename = tplg_filename; 1676 } 1677 1678 /* check if mclk_id should be modified from topology defaults */ 1679 if (mclk_id_override >= 0) { 1680 dev_info(sdev->dev, "Overriding topology with MCLK %d from kernel_parameter\n", mclk_id_override); 1681 sdev->mclk_id_override = true; 1682 sdev->mclk_id_quirk = mclk_id_override; 1683 } 1684 } 1685 1686 /* If I2S fails, try SoundWire if it is supported */ 1687 if (!mach && (interface_mask & BIT(SOF_DAI_INTEL_ALH))) 1688 mach = hda_sdw_machine_select(sdev); 1689 1690 /* 1691 * Choose HDA generic machine driver if mach is NULL. 1692 * Otherwise, set certain mach params. 1693 */ 1694 hda_generic_machine_select(sdev, &mach); 1695 if (!mach) 1696 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 1697 1698 return mach; 1699 } 1700 1701 int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1702 { 1703 int ret; 1704 1705 ret = snd_intel_dsp_driver_probe(pci); 1706 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 1707 dev_dbg(&pci->dev, "SOF PCI driver not selected, aborting probe\n"); 1708 return -ENODEV; 1709 } 1710 1711 return sof_pci_probe(pci, pci_id); 1712 } 1713 EXPORT_SYMBOL_NS(hda_pci_intel_probe, SND_SOC_SOF_INTEL_HDA_COMMON); 1714 1715 int hda_register_clients(struct snd_sof_dev *sdev) 1716 { 1717 return hda_probes_register(sdev); 1718 } 1719 1720 void hda_unregister_clients(struct snd_sof_dev *sdev) 1721 { 1722 hda_probes_unregister(sdev); 1723 } 1724 1725 MODULE_LICENSE("Dual BSD/GPL"); 1726 MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV); 1727 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC); 1728 MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC_I915); 1729 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 1730 MODULE_IMPORT_NS(SND_INTEL_SOUNDWIRE_ACPI); 1731 MODULE_IMPORT_NS(SOUNDWIRE_INTEL_INIT); 1732 MODULE_IMPORT_NS(SOUNDWIRE_INTEL); 1733