1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <linux/module.h> 19 #include <sound/hdaudio_ext.h> 20 #include <sound/hda_register.h> 21 #include <trace/events/sof_intel.h> 22 #include "../sof-audio.h" 23 #include "../ops.h" 24 #include "hda.h" 25 #include "hda-ipc.h" 26 27 static bool hda_enable_trace_D0I3_S0; 28 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 29 module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444); 30 MODULE_PARM_DESC(enable_trace_D0I3_S0, 31 "SOF HDA enable trace when the DSP is in D0I3 in S0"); 32 #endif 33 34 /* 35 * DSP Core control. 36 */ 37 38 static int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask) 39 { 40 u32 adspcs; 41 u32 reset; 42 int ret; 43 44 /* set reset bits for cores */ 45 reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask); 46 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 47 HDA_DSP_REG_ADSPCS, 48 reset, reset); 49 50 /* poll with timeout to check if operation successful */ 51 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 52 HDA_DSP_REG_ADSPCS, adspcs, 53 ((adspcs & reset) == reset), 54 HDA_DSP_REG_POLL_INTERVAL_US, 55 HDA_DSP_RESET_TIMEOUT_US); 56 if (ret < 0) { 57 dev_err(sdev->dev, 58 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 59 __func__); 60 return ret; 61 } 62 63 /* has core entered reset ? */ 64 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 65 HDA_DSP_REG_ADSPCS); 66 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 67 HDA_DSP_ADSPCS_CRST_MASK(core_mask)) { 68 dev_err(sdev->dev, 69 "error: reset enter failed: core_mask %x adspcs 0x%x\n", 70 core_mask, adspcs); 71 ret = -EIO; 72 } 73 74 return ret; 75 } 76 77 static int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask) 78 { 79 unsigned int crst; 80 u32 adspcs; 81 int ret; 82 83 /* clear reset bits for cores */ 84 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 85 HDA_DSP_REG_ADSPCS, 86 HDA_DSP_ADSPCS_CRST_MASK(core_mask), 87 0); 88 89 /* poll with timeout to check if operation successful */ 90 crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask); 91 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 92 HDA_DSP_REG_ADSPCS, adspcs, 93 !(adspcs & crst), 94 HDA_DSP_REG_POLL_INTERVAL_US, 95 HDA_DSP_RESET_TIMEOUT_US); 96 97 if (ret < 0) { 98 dev_err(sdev->dev, 99 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 100 __func__); 101 return ret; 102 } 103 104 /* has core left reset ? */ 105 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 106 HDA_DSP_REG_ADSPCS); 107 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) { 108 dev_err(sdev->dev, 109 "error: reset leave failed: core_mask %x adspcs 0x%x\n", 110 core_mask, adspcs); 111 ret = -EIO; 112 } 113 114 return ret; 115 } 116 117 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask) 118 { 119 /* stall core */ 120 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 121 HDA_DSP_REG_ADSPCS, 122 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask), 123 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)); 124 125 /* set reset state */ 126 return hda_dsp_core_reset_enter(sdev, core_mask); 127 } 128 129 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask) 130 { 131 int val; 132 bool is_enable; 133 134 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS); 135 136 #define MASK_IS_EQUAL(v, m, field) ({ \ 137 u32 _m = field(m); \ 138 ((v) & _m) == _m; \ 139 }) 140 141 is_enable = MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_CPA_MASK) && 142 MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_SPA_MASK) && 143 !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) && 144 !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)); 145 146 #undef MASK_IS_EQUAL 147 148 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n", 149 is_enable, core_mask); 150 151 return is_enable; 152 } 153 154 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask) 155 { 156 int ret; 157 158 /* leave reset state */ 159 ret = hda_dsp_core_reset_leave(sdev, core_mask); 160 if (ret < 0) 161 return ret; 162 163 /* run core */ 164 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask); 165 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 166 HDA_DSP_REG_ADSPCS, 167 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask), 168 0); 169 170 /* is core now running ? */ 171 if (!hda_dsp_core_is_enabled(sdev, core_mask)) { 172 hda_dsp_core_stall_reset(sdev, core_mask); 173 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n", 174 core_mask); 175 ret = -EIO; 176 } 177 178 return ret; 179 } 180 181 /* 182 * Power Management. 183 */ 184 185 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask) 186 { 187 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 188 const struct sof_intel_dsp_desc *chip = hda->desc; 189 unsigned int cpa; 190 u32 adspcs; 191 int ret; 192 193 /* restrict core_mask to host managed cores mask */ 194 core_mask &= chip->host_managed_cores_mask; 195 /* return if core_mask is not valid */ 196 if (!core_mask) 197 return 0; 198 199 /* update bits */ 200 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS, 201 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 202 HDA_DSP_ADSPCS_SPA_MASK(core_mask)); 203 204 /* poll with timeout to check if operation successful */ 205 cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask); 206 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 207 HDA_DSP_REG_ADSPCS, adspcs, 208 (adspcs & cpa) == cpa, 209 HDA_DSP_REG_POLL_INTERVAL_US, 210 HDA_DSP_RESET_TIMEOUT_US); 211 if (ret < 0) { 212 dev_err(sdev->dev, 213 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 214 __func__); 215 return ret; 216 } 217 218 /* did core power up ? */ 219 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 220 HDA_DSP_REG_ADSPCS); 221 if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) != 222 HDA_DSP_ADSPCS_CPA_MASK(core_mask)) { 223 dev_err(sdev->dev, 224 "error: power up core failed core_mask %xadspcs 0x%x\n", 225 core_mask, adspcs); 226 ret = -EIO; 227 } 228 229 return ret; 230 } 231 232 static int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask) 233 { 234 u32 adspcs; 235 int ret; 236 237 /* update bits */ 238 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 239 HDA_DSP_REG_ADSPCS, 240 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0); 241 242 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 243 HDA_DSP_REG_ADSPCS, adspcs, 244 !(adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)), 245 HDA_DSP_REG_POLL_INTERVAL_US, 246 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC); 247 if (ret < 0) 248 dev_err(sdev->dev, 249 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 250 __func__); 251 252 return ret; 253 } 254 255 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask) 256 { 257 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 258 const struct sof_intel_dsp_desc *chip = hda->desc; 259 int ret; 260 261 /* restrict core_mask to host managed cores mask */ 262 core_mask &= chip->host_managed_cores_mask; 263 264 /* return if core_mask is not valid or cores are already enabled */ 265 if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask)) 266 return 0; 267 268 /* power up */ 269 ret = hda_dsp_core_power_up(sdev, core_mask); 270 if (ret < 0) { 271 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n", 272 core_mask); 273 return ret; 274 } 275 276 return hda_dsp_core_run(sdev, core_mask); 277 } 278 279 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 280 unsigned int core_mask) 281 { 282 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 283 const struct sof_intel_dsp_desc *chip = hda->desc; 284 int ret; 285 286 /* restrict core_mask to host managed cores mask */ 287 core_mask &= chip->host_managed_cores_mask; 288 289 /* return if core_mask is not valid */ 290 if (!core_mask) 291 return 0; 292 293 /* place core in reset prior to power down */ 294 ret = hda_dsp_core_stall_reset(sdev, core_mask); 295 if (ret < 0) { 296 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n", 297 core_mask); 298 return ret; 299 } 300 301 /* power down core */ 302 ret = hda_dsp_core_power_down(sdev, core_mask); 303 if (ret < 0) { 304 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n", 305 core_mask, ret); 306 return ret; 307 } 308 309 /* make sure we are in OFF state */ 310 if (hda_dsp_core_is_enabled(sdev, core_mask)) { 311 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n", 312 core_mask, ret); 313 ret = -EIO; 314 } 315 316 return ret; 317 } 318 319 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev) 320 { 321 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 322 const struct sof_intel_dsp_desc *chip = hda->desc; 323 324 /* enable IPC DONE and BUSY interrupts */ 325 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 326 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY, 327 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY); 328 329 /* enable IPC interrupt */ 330 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC, 331 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC); 332 } 333 334 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev) 335 { 336 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 337 const struct sof_intel_dsp_desc *chip = hda->desc; 338 339 /* disable IPC interrupt */ 340 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC, 341 HDA_DSP_ADSPIC_IPC, 0); 342 343 /* disable IPC BUSY and DONE interrupt */ 344 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 345 HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0); 346 } 347 348 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev) 349 { 350 int retry = HDA_DSP_REG_POLL_RETRY_COUNT; 351 352 while (snd_sof_dsp_readb(sdev, HDA_DSP_HDA_BAR, SOF_HDA_VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) { 353 if (!retry--) 354 return -ETIMEDOUT; 355 usleep_range(10, 15); 356 } 357 358 return 0; 359 } 360 361 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags) 362 { 363 struct sof_ipc_pm_gate pm_gate; 364 struct sof_ipc_reply reply; 365 366 memset(&pm_gate, 0, sizeof(pm_gate)); 367 368 /* configure pm_gate ipc message */ 369 pm_gate.hdr.size = sizeof(pm_gate); 370 pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE; 371 pm_gate.flags = flags; 372 373 /* send pm_gate ipc to dsp */ 374 return sof_ipc_tx_message_no_pm(sdev->ipc, &pm_gate, sizeof(pm_gate), 375 &reply, sizeof(reply)); 376 } 377 378 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value) 379 { 380 struct hdac_bus *bus = sof_to_bus(sdev); 381 int ret; 382 u8 reg; 383 384 /* Write to D0I3C after Command-In-Progress bit is cleared */ 385 ret = hda_dsp_wait_d0i3c_done(sdev); 386 if (ret < 0) { 387 dev_err(bus->dev, "CIP timeout before D0I3C update!\n"); 388 return ret; 389 } 390 391 /* Update D0I3C register */ 392 snd_sof_dsp_updateb(sdev, HDA_DSP_HDA_BAR, 393 SOF_HDA_VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value); 394 395 /* Wait for cmd in progress to be cleared before exiting the function */ 396 ret = hda_dsp_wait_d0i3c_done(sdev); 397 if (ret < 0) { 398 dev_err(bus->dev, "CIP timeout after D0I3C update!\n"); 399 return ret; 400 } 401 402 reg = snd_sof_dsp_readb(sdev, HDA_DSP_HDA_BAR, SOF_HDA_VS_D0I3C); 403 trace_sof_intel_D0I3C_updated(sdev, reg); 404 405 return 0; 406 } 407 408 static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev, 409 const struct sof_dsp_power_state *target_state) 410 { 411 u32 flags = 0; 412 int ret; 413 u8 value = 0; 414 415 /* 416 * Sanity check for illegal state transitions 417 * The only allowed transitions are: 418 * 1. D3 -> D0I0 419 * 2. D0I0 -> D0I3 420 * 3. D0I3 -> D0I0 421 */ 422 switch (sdev->dsp_power_state.state) { 423 case SOF_DSP_PM_D0: 424 /* Follow the sequence below for D0 substate transitions */ 425 break; 426 case SOF_DSP_PM_D3: 427 /* Follow regular flow for D3 -> D0 transition */ 428 return 0; 429 default: 430 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n", 431 sdev->dsp_power_state.state, target_state->state); 432 return -EINVAL; 433 } 434 435 /* Set flags and register value for D0 target substate */ 436 if (target_state->substate == SOF_HDA_DSP_PM_D0I3) { 437 value = SOF_HDA_VS_D0I3C_I3; 438 439 /* 440 * Trace DMA need to be disabled when the DSP enters 441 * D0I3 for S0Ix suspend, but it can be kept enabled 442 * when the DSP enters D0I3 while the system is in S0 443 * for debug purpose. 444 */ 445 if (!sdev->fw_trace_is_supported || 446 !hda_enable_trace_D0I3_S0 || 447 sdev->system_suspend_target != SOF_SUSPEND_NONE) 448 flags = HDA_PM_NO_DMA_TRACE; 449 } else { 450 /* prevent power gating in D0I0 */ 451 flags = HDA_PM_PPG; 452 } 453 454 /* update D0I3C register */ 455 ret = hda_dsp_update_d0i3c_register(sdev, value); 456 if (ret < 0) 457 return ret; 458 459 /* 460 * Notify the DSP of the state change. 461 * If this IPC fails, revert the D0I3C register update in order 462 * to prevent partial state change. 463 */ 464 ret = hda_dsp_send_pm_gate_ipc(sdev, flags); 465 if (ret < 0) { 466 dev_err(sdev->dev, 467 "error: PM_GATE ipc error %d\n", ret); 468 goto revert; 469 } 470 471 return ret; 472 473 revert: 474 /* fallback to the previous register value */ 475 value = value ? 0 : SOF_HDA_VS_D0I3C_I3; 476 477 /* 478 * This can fail but return the IPC error to signal that 479 * the state change failed. 480 */ 481 hda_dsp_update_d0i3c_register(sdev, value); 482 483 return ret; 484 } 485 486 /* helper to log DSP state */ 487 static void hda_dsp_state_log(struct snd_sof_dev *sdev) 488 { 489 switch (sdev->dsp_power_state.state) { 490 case SOF_DSP_PM_D0: 491 switch (sdev->dsp_power_state.substate) { 492 case SOF_HDA_DSP_PM_D0I0: 493 dev_dbg(sdev->dev, "Current DSP power state: D0I0\n"); 494 break; 495 case SOF_HDA_DSP_PM_D0I3: 496 dev_dbg(sdev->dev, "Current DSP power state: D0I3\n"); 497 break; 498 default: 499 dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n", 500 sdev->dsp_power_state.substate); 501 break; 502 } 503 break; 504 case SOF_DSP_PM_D1: 505 dev_dbg(sdev->dev, "Current DSP power state: D1\n"); 506 break; 507 case SOF_DSP_PM_D2: 508 dev_dbg(sdev->dev, "Current DSP power state: D2\n"); 509 break; 510 case SOF_DSP_PM_D3: 511 dev_dbg(sdev->dev, "Current DSP power state: D3\n"); 512 break; 513 default: 514 dev_dbg(sdev->dev, "Unknown DSP power state: %d\n", 515 sdev->dsp_power_state.state); 516 break; 517 } 518 } 519 520 /* 521 * All DSP power state transitions are initiated by the driver. 522 * If the requested state change fails, the error is simply returned. 523 * Further state transitions are attempted only when the set_power_save() op 524 * is called again either because of a new IPC sent to the DSP or 525 * during system suspend/resume. 526 */ 527 int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 528 const struct sof_dsp_power_state *target_state) 529 { 530 int ret = 0; 531 532 /* 533 * When the DSP is already in D0I3 and the target state is D0I3, 534 * it could be the case that the DSP is in D0I3 during S0 535 * and the system is suspending to S0Ix. Therefore, 536 * hda_dsp_set_D0_state() must be called to disable trace DMA 537 * by sending the PM_GATE IPC to the FW. 538 */ 539 if (target_state->substate == SOF_HDA_DSP_PM_D0I3 && 540 sdev->system_suspend_target == SOF_SUSPEND_S0IX) 541 goto set_state; 542 543 /* 544 * For all other cases, return without doing anything if 545 * the DSP is already in the target state. 546 */ 547 if (target_state->state == sdev->dsp_power_state.state && 548 target_state->substate == sdev->dsp_power_state.substate) 549 return 0; 550 551 set_state: 552 switch (target_state->state) { 553 case SOF_DSP_PM_D0: 554 ret = hda_dsp_set_D0_state(sdev, target_state); 555 break; 556 case SOF_DSP_PM_D3: 557 /* The only allowed transition is: D0I0 -> D3 */ 558 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 && 559 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0) 560 break; 561 562 dev_err(sdev->dev, 563 "error: transition from %d to %d not allowed\n", 564 sdev->dsp_power_state.state, target_state->state); 565 return -EINVAL; 566 default: 567 dev_err(sdev->dev, "error: target state unsupported %d\n", 568 target_state->state); 569 return -EINVAL; 570 } 571 if (ret < 0) { 572 dev_err(sdev->dev, 573 "failed to set requested target DSP state %d substate %d\n", 574 target_state->state, target_state->substate); 575 return ret; 576 } 577 578 sdev->dsp_power_state = *target_state; 579 hda_dsp_state_log(sdev); 580 return ret; 581 } 582 583 /* 584 * Audio DSP states may transform as below:- 585 * 586 * Opportunistic D0I3 in S0 587 * Runtime +---------------------+ Delayed D0i3 work timeout 588 * suspend | +--------------------+ 589 * +------------+ D0I0(active) | | 590 * | | <---------------+ | 591 * | +--------> | New IPC | | 592 * | |Runtime +--^--+---------^--+--+ (via mailbox) | | 593 * | |resume | | | | | | 594 * | | | | | | | | 595 * | | System| | | | | | 596 * | | resume| | S3/S0IX | | | | 597 * | | | | suspend | | S0IX | | 598 * | | | | | |suspend | | 599 * | | | | | | | | 600 * | | | | | | | | 601 * +-v---+-----------+--v-------+ | | +------+----v----+ 602 * | | | +-----------> | 603 * | D3 (suspended) | | | D0I3 | 604 * | | +--------------+ | 605 * | | System resume | | 606 * +----------------------------+ +----------------+ 607 * 608 * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams 609 * ignored the suspend trigger. Otherwise the DSP 610 * is in D3. 611 */ 612 613 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend) 614 { 615 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 616 const struct sof_intel_dsp_desc *chip = hda->desc; 617 struct hdac_bus *bus = sof_to_bus(sdev); 618 int ret, j; 619 620 /* 621 * The memory used for IMR boot loses its content in deeper than S3 state 622 * We must not try IMR boot on next power up (as it will fail). 623 * 624 * In case of firmware crash or boot failure set the skip_imr_boot to true 625 * as well in order to try to re-load the firmware to do a 'cold' boot. 626 */ 627 if (sdev->system_suspend_target > SOF_SUSPEND_S3 || 628 sdev->fw_state == SOF_FW_CRASHED || 629 sdev->fw_state == SOF_FW_BOOT_FAILED) 630 hda->skip_imr_boot = true; 631 632 ret = chip->disable_interrupts(sdev); 633 if (ret < 0) 634 return ret; 635 636 hda_codec_jack_wake_enable(sdev, runtime_suspend); 637 638 /* power down all hda links */ 639 hda_bus_ml_suspend(bus); 640 641 ret = chip->power_down_dsp(sdev); 642 if (ret < 0) { 643 dev_err(sdev->dev, "failed to power down DSP during suspend\n"); 644 return ret; 645 } 646 647 /* reset ref counts for all cores */ 648 for (j = 0; j < chip->cores_num; j++) 649 sdev->dsp_core_ref_count[j] = 0; 650 651 /* disable ppcap interrupt */ 652 hda_dsp_ctrl_ppcap_enable(sdev, false); 653 hda_dsp_ctrl_ppcap_int_enable(sdev, false); 654 655 /* disable hda bus irq and streams */ 656 hda_dsp_ctrl_stop_chip(sdev); 657 658 /* disable LP retention mode */ 659 snd_sof_pci_update_bits(sdev, PCI_PGCTL, 660 PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK); 661 662 /* reset controller */ 663 ret = hda_dsp_ctrl_link_reset(sdev, true); 664 if (ret < 0) { 665 dev_err(sdev->dev, 666 "error: failed to reset controller during suspend\n"); 667 return ret; 668 } 669 670 /* display codec can powered off after link reset */ 671 hda_codec_i915_display_power(sdev, false); 672 673 return 0; 674 } 675 676 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume) 677 { 678 int ret; 679 680 /* display codec must be powered before link reset */ 681 hda_codec_i915_display_power(sdev, true); 682 683 /* 684 * clear TCSEL to clear playback on some HD Audio 685 * codecs. PCI TCSEL is defined in the Intel manuals. 686 */ 687 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 688 689 /* reset and start hda controller */ 690 ret = hda_dsp_ctrl_init_chip(sdev); 691 if (ret < 0) { 692 dev_err(sdev->dev, 693 "error: failed to start controller after resume\n"); 694 goto cleanup; 695 } 696 697 /* check jack status */ 698 if (runtime_resume) { 699 hda_codec_jack_wake_enable(sdev, false); 700 if (sdev->system_suspend_target == SOF_SUSPEND_NONE) 701 hda_codec_jack_check(sdev); 702 } 703 704 /* enable ppcap interrupt */ 705 hda_dsp_ctrl_ppcap_enable(sdev, true); 706 hda_dsp_ctrl_ppcap_int_enable(sdev, true); 707 708 cleanup: 709 /* display codec can powered off after controller init */ 710 hda_codec_i915_display_power(sdev, false); 711 712 return 0; 713 } 714 715 int hda_dsp_resume(struct snd_sof_dev *sdev) 716 { 717 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 718 struct hdac_bus *bus = sof_to_bus(sdev); 719 struct pci_dev *pci = to_pci_dev(sdev->dev); 720 const struct sof_dsp_power_state target_state = { 721 .state = SOF_DSP_PM_D0, 722 .substate = SOF_HDA_DSP_PM_D0I0, 723 }; 724 int ret; 725 726 /* resume from D0I3 */ 727 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) { 728 ret = hda_bus_ml_resume(bus); 729 if (ret < 0) { 730 dev_err(sdev->dev, 731 "error %d in %s: failed to power up links", 732 ret, __func__); 733 return ret; 734 } 735 736 /* set up CORB/RIRB buffers if was on before suspend */ 737 hda_codec_resume_cmd_io(sdev); 738 739 /* Set DSP power state */ 740 ret = snd_sof_dsp_set_power_state(sdev, &target_state); 741 if (ret < 0) { 742 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n", 743 target_state.state, target_state.substate); 744 return ret; 745 } 746 747 /* restore L1SEN bit */ 748 if (hda->l1_support_changed) 749 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 750 HDA_VS_INTEL_EM2, 751 HDA_VS_INTEL_EM2_L1SEN, 0); 752 753 /* restore and disable the system wakeup */ 754 pci_restore_state(pci); 755 disable_irq_wake(pci->irq); 756 return 0; 757 } 758 759 /* init hda controller. DSP cores will be powered up during fw boot */ 760 ret = hda_resume(sdev, false); 761 if (ret < 0) 762 return ret; 763 764 return snd_sof_dsp_set_power_state(sdev, &target_state); 765 } 766 767 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev) 768 { 769 const struct sof_dsp_power_state target_state = { 770 .state = SOF_DSP_PM_D0, 771 }; 772 int ret; 773 774 /* init hda controller. DSP cores will be powered up during fw boot */ 775 ret = hda_resume(sdev, true); 776 if (ret < 0) 777 return ret; 778 779 return snd_sof_dsp_set_power_state(sdev, &target_state); 780 } 781 782 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev) 783 { 784 struct hdac_bus *hbus = sof_to_bus(sdev); 785 786 if (hbus->codec_powered) { 787 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n", 788 (unsigned int)hbus->codec_powered); 789 return -EBUSY; 790 } 791 792 return 0; 793 } 794 795 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev) 796 { 797 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 798 const struct sof_dsp_power_state target_state = { 799 .state = SOF_DSP_PM_D3, 800 }; 801 int ret; 802 803 /* cancel any attempt for DSP D0I3 */ 804 cancel_delayed_work_sync(&hda->d0i3_work); 805 806 /* stop hda controller and power dsp off */ 807 ret = hda_suspend(sdev, true); 808 if (ret < 0) 809 return ret; 810 811 return snd_sof_dsp_set_power_state(sdev, &target_state); 812 } 813 814 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state) 815 { 816 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 817 struct hdac_bus *bus = sof_to_bus(sdev); 818 struct pci_dev *pci = to_pci_dev(sdev->dev); 819 const struct sof_dsp_power_state target_dsp_state = { 820 .state = target_state, 821 .substate = target_state == SOF_DSP_PM_D0 ? 822 SOF_HDA_DSP_PM_D0I3 : 0, 823 }; 824 int ret; 825 826 /* cancel any attempt for DSP D0I3 */ 827 cancel_delayed_work_sync(&hda->d0i3_work); 828 829 if (target_state == SOF_DSP_PM_D0) { 830 /* Set DSP power state */ 831 ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 832 if (ret < 0) { 833 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n", 834 target_dsp_state.state, 835 target_dsp_state.substate); 836 return ret; 837 } 838 839 /* enable L1SEN to make sure the system can enter S0Ix */ 840 hda->l1_support_changed = 841 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 842 HDA_VS_INTEL_EM2, 843 HDA_VS_INTEL_EM2_L1SEN, 844 HDA_VS_INTEL_EM2_L1SEN); 845 846 /* stop the CORB/RIRB DMA if it is On */ 847 hda_codec_suspend_cmd_io(sdev); 848 849 /* no link can be powered in s0ix state */ 850 ret = hda_bus_ml_suspend(bus); 851 if (ret < 0) { 852 dev_err(sdev->dev, 853 "error %d in %s: failed to power down links", 854 ret, __func__); 855 return ret; 856 } 857 858 /* enable the system waking up via IPC IRQ */ 859 enable_irq_wake(pci->irq); 860 pci_save_state(pci); 861 return 0; 862 } 863 864 /* stop hda controller and power dsp off */ 865 ret = hda_suspend(sdev, false); 866 if (ret < 0) { 867 dev_err(bus->dev, "error: suspending dsp\n"); 868 return ret; 869 } 870 871 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); 872 } 873 874 int hda_dsp_shutdown(struct snd_sof_dev *sdev) 875 { 876 sdev->system_suspend_target = SOF_SUSPEND_S3; 877 return snd_sof_suspend(sdev->dev); 878 } 879 880 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev) 881 { 882 int ret; 883 884 /* make sure all DAI resources are freed */ 885 ret = hda_dsp_dais_suspend(sdev); 886 if (ret < 0) 887 dev_warn(sdev->dev, "%s: failure in hda_dsp_dais_suspend\n", __func__); 888 889 return ret; 890 } 891 892 void hda_dsp_d0i3_work(struct work_struct *work) 893 { 894 struct sof_intel_hda_dev *hdev = container_of(work, 895 struct sof_intel_hda_dev, 896 d0i3_work.work); 897 struct hdac_bus *bus = &hdev->hbus.core; 898 struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev); 899 struct sof_dsp_power_state target_state = { 900 .state = SOF_DSP_PM_D0, 901 .substate = SOF_HDA_DSP_PM_D0I3, 902 }; 903 int ret; 904 905 /* DSP can enter D0I3 iff only D0I3-compatible streams are active */ 906 if (!snd_sof_dsp_only_d0i3_compatible_stream_active(sdev)) 907 /* remain in D0I0 */ 908 return; 909 910 /* This can fail but error cannot be propagated */ 911 ret = snd_sof_dsp_set_power_state(sdev, &target_state); 912 if (ret < 0) 913 dev_err_ratelimited(sdev->dev, 914 "error: failed to set DSP state %d substate %d\n", 915 target_state.state, target_state.substate); 916 } 917 918 int hda_dsp_core_get(struct snd_sof_dev *sdev, int core) 919 { 920 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; 921 int ret, ret1; 922 923 /* power up core */ 924 ret = hda_dsp_enable_core(sdev, BIT(core)); 925 if (ret < 0) { 926 dev_err(sdev->dev, "failed to power up core %d with err: %d\n", 927 core, ret); 928 return ret; 929 } 930 931 /* No need to send IPC for primary core or if FW boot is not complete */ 932 if (sdev->fw_state != SOF_FW_BOOT_COMPLETE || core == SOF_DSP_PRIMARY_CORE) 933 return 0; 934 935 /* No need to continue the set_core_state ops is not available */ 936 if (!pm_ops->set_core_state) 937 return 0; 938 939 /* Now notify DSP for secondary cores */ 940 ret = pm_ops->set_core_state(sdev, core, true); 941 if (ret < 0) { 942 dev_err(sdev->dev, "failed to enable secondary core '%d' failed with %d\n", 943 core, ret); 944 goto power_down; 945 } 946 947 return ret; 948 949 power_down: 950 /* power down core if it is host managed and return the original error if this fails too */ 951 ret1 = hda_dsp_core_reset_power_down(sdev, BIT(core)); 952 if (ret1 < 0) 953 dev_err(sdev->dev, "failed to power down core: %d with err: %d\n", core, ret1); 954 955 return ret; 956 } 957 958 int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev) 959 { 960 hda_sdw_int_enable(sdev, false); 961 hda_dsp_ipc_int_disable(sdev); 962 963 return 0; 964 } 965