1747503b1SLiam Girdwood // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2747503b1SLiam Girdwood // 3747503b1SLiam Girdwood // This file is provided under a dual BSD/GPLv2 license. When using or 4747503b1SLiam Girdwood // redistributing this file, you may do so under either license. 5747503b1SLiam Girdwood // 6747503b1SLiam Girdwood // Copyright(c) 2018 Intel Corporation. All rights reserved. 7747503b1SLiam Girdwood // 8747503b1SLiam Girdwood // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9747503b1SLiam Girdwood // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10747503b1SLiam Girdwood // Rander Wang <rander.wang@intel.com> 11747503b1SLiam Girdwood // Keyon Jie <yang.jie@linux.intel.com> 12747503b1SLiam Girdwood // 13747503b1SLiam Girdwood 14747503b1SLiam Girdwood /* 15747503b1SLiam Girdwood * Hardware interface for generic Intel audio DSP HDA IP 16747503b1SLiam Girdwood */ 17747503b1SLiam Girdwood 18*851fd873SRanjani Sridharan #include <linux/module.h> 19747503b1SLiam Girdwood #include <sound/hdaudio_ext.h> 20747503b1SLiam Girdwood #include <sound/hda_register.h> 2163e51fd3SRanjani Sridharan #include "../sof-audio.h" 22747503b1SLiam Girdwood #include "../ops.h" 23747503b1SLiam Girdwood #include "hda.h" 24534037fdSKeyon Jie #include "hda-ipc.h" 25747503b1SLiam Girdwood 26*851fd873SRanjani Sridharan static bool hda_enable_trace_D0I3_S0; 27*851fd873SRanjani Sridharan #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 28*851fd873SRanjani Sridharan module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444); 29*851fd873SRanjani Sridharan MODULE_PARM_DESC(enable_trace_D0I3_S0, 30*851fd873SRanjani Sridharan "SOF HDA enable trace when the DSP is in D0I3 in S0"); 31*851fd873SRanjani Sridharan #endif 32*851fd873SRanjani Sridharan 33747503b1SLiam Girdwood /* 34747503b1SLiam Girdwood * DSP Core control. 35747503b1SLiam Girdwood */ 36747503b1SLiam Girdwood 37747503b1SLiam Girdwood int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask) 38747503b1SLiam Girdwood { 39747503b1SLiam Girdwood u32 adspcs; 40747503b1SLiam Girdwood u32 reset; 41747503b1SLiam Girdwood int ret; 42747503b1SLiam Girdwood 43747503b1SLiam Girdwood /* set reset bits for cores */ 44747503b1SLiam Girdwood reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask); 45747503b1SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 46747503b1SLiam Girdwood HDA_DSP_REG_ADSPCS, 47747503b1SLiam Girdwood reset, reset), 48747503b1SLiam Girdwood 49747503b1SLiam Girdwood /* poll with timeout to check if operation successful */ 50747503b1SLiam Girdwood ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 51747503b1SLiam Girdwood HDA_DSP_REG_ADSPCS, adspcs, 52747503b1SLiam Girdwood ((adspcs & reset) == reset), 53747503b1SLiam Girdwood HDA_DSP_REG_POLL_INTERVAL_US, 54747503b1SLiam Girdwood HDA_DSP_RESET_TIMEOUT_US); 556a414489SPierre-Louis Bossart if (ret < 0) { 566a414489SPierre-Louis Bossart dev_err(sdev->dev, 576a414489SPierre-Louis Bossart "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 586a414489SPierre-Louis Bossart __func__); 596a414489SPierre-Louis Bossart return ret; 606a414489SPierre-Louis Bossart } 61747503b1SLiam Girdwood 62747503b1SLiam Girdwood /* has core entered reset ? */ 63747503b1SLiam Girdwood adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 64747503b1SLiam Girdwood HDA_DSP_REG_ADSPCS); 65747503b1SLiam Girdwood if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 66747503b1SLiam Girdwood HDA_DSP_ADSPCS_CRST_MASK(core_mask)) { 67747503b1SLiam Girdwood dev_err(sdev->dev, 68747503b1SLiam Girdwood "error: reset enter failed: core_mask %x adspcs 0x%x\n", 69747503b1SLiam Girdwood core_mask, adspcs); 70747503b1SLiam Girdwood ret = -EIO; 71747503b1SLiam Girdwood } 72747503b1SLiam Girdwood 73747503b1SLiam Girdwood return ret; 74747503b1SLiam Girdwood } 75747503b1SLiam Girdwood 76747503b1SLiam Girdwood int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask) 77747503b1SLiam Girdwood { 78747503b1SLiam Girdwood unsigned int crst; 79747503b1SLiam Girdwood u32 adspcs; 80747503b1SLiam Girdwood int ret; 81747503b1SLiam Girdwood 82747503b1SLiam Girdwood /* clear reset bits for cores */ 83747503b1SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 84747503b1SLiam Girdwood HDA_DSP_REG_ADSPCS, 85747503b1SLiam Girdwood HDA_DSP_ADSPCS_CRST_MASK(core_mask), 86747503b1SLiam Girdwood 0); 87747503b1SLiam Girdwood 88747503b1SLiam Girdwood /* poll with timeout to check if operation successful */ 89747503b1SLiam Girdwood crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask); 90747503b1SLiam Girdwood ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 91747503b1SLiam Girdwood HDA_DSP_REG_ADSPCS, adspcs, 92747503b1SLiam Girdwood !(adspcs & crst), 93747503b1SLiam Girdwood HDA_DSP_REG_POLL_INTERVAL_US, 94747503b1SLiam Girdwood HDA_DSP_RESET_TIMEOUT_US); 95747503b1SLiam Girdwood 966a414489SPierre-Louis Bossart if (ret < 0) { 976a414489SPierre-Louis Bossart dev_err(sdev->dev, 986a414489SPierre-Louis Bossart "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 996a414489SPierre-Louis Bossart __func__); 1006a414489SPierre-Louis Bossart return ret; 1016a414489SPierre-Louis Bossart } 1026a414489SPierre-Louis Bossart 103747503b1SLiam Girdwood /* has core left reset ? */ 104747503b1SLiam Girdwood adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 105747503b1SLiam Girdwood HDA_DSP_REG_ADSPCS); 106747503b1SLiam Girdwood if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) { 107747503b1SLiam Girdwood dev_err(sdev->dev, 108747503b1SLiam Girdwood "error: reset leave failed: core_mask %x adspcs 0x%x\n", 109747503b1SLiam Girdwood core_mask, adspcs); 110747503b1SLiam Girdwood ret = -EIO; 111747503b1SLiam Girdwood } 112747503b1SLiam Girdwood 113747503b1SLiam Girdwood return ret; 114747503b1SLiam Girdwood } 115747503b1SLiam Girdwood 116747503b1SLiam Girdwood int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask) 117747503b1SLiam Girdwood { 118747503b1SLiam Girdwood /* stall core */ 119747503b1SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 120747503b1SLiam Girdwood HDA_DSP_REG_ADSPCS, 121747503b1SLiam Girdwood HDA_DSP_ADSPCS_CSTALL_MASK(core_mask), 122747503b1SLiam Girdwood HDA_DSP_ADSPCS_CSTALL_MASK(core_mask)); 123747503b1SLiam Girdwood 124747503b1SLiam Girdwood /* set reset state */ 125747503b1SLiam Girdwood return hda_dsp_core_reset_enter(sdev, core_mask); 126747503b1SLiam Girdwood } 127747503b1SLiam Girdwood 128747503b1SLiam Girdwood int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask) 129747503b1SLiam Girdwood { 130747503b1SLiam Girdwood int ret; 131747503b1SLiam Girdwood 132747503b1SLiam Girdwood /* leave reset state */ 133747503b1SLiam Girdwood ret = hda_dsp_core_reset_leave(sdev, core_mask); 134747503b1SLiam Girdwood if (ret < 0) 135747503b1SLiam Girdwood return ret; 136747503b1SLiam Girdwood 137747503b1SLiam Girdwood /* run core */ 138747503b1SLiam Girdwood dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask); 139747503b1SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 140747503b1SLiam Girdwood HDA_DSP_REG_ADSPCS, 141747503b1SLiam Girdwood HDA_DSP_ADSPCS_CSTALL_MASK(core_mask), 142747503b1SLiam Girdwood 0); 143747503b1SLiam Girdwood 144747503b1SLiam Girdwood /* is core now running ? */ 145747503b1SLiam Girdwood if (!hda_dsp_core_is_enabled(sdev, core_mask)) { 146747503b1SLiam Girdwood hda_dsp_core_stall_reset(sdev, core_mask); 147747503b1SLiam Girdwood dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n", 148747503b1SLiam Girdwood core_mask); 149747503b1SLiam Girdwood ret = -EIO; 150747503b1SLiam Girdwood } 151747503b1SLiam Girdwood 152747503b1SLiam Girdwood return ret; 153747503b1SLiam Girdwood } 154747503b1SLiam Girdwood 155747503b1SLiam Girdwood /* 156747503b1SLiam Girdwood * Power Management. 157747503b1SLiam Girdwood */ 158747503b1SLiam Girdwood 159747503b1SLiam Girdwood int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask) 160747503b1SLiam Girdwood { 161747503b1SLiam Girdwood unsigned int cpa; 162747503b1SLiam Girdwood u32 adspcs; 163747503b1SLiam Girdwood int ret; 164747503b1SLiam Girdwood 165747503b1SLiam Girdwood /* update bits */ 166747503b1SLiam Girdwood snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS, 167747503b1SLiam Girdwood HDA_DSP_ADSPCS_SPA_MASK(core_mask), 168747503b1SLiam Girdwood HDA_DSP_ADSPCS_SPA_MASK(core_mask)); 169747503b1SLiam Girdwood 170747503b1SLiam Girdwood /* poll with timeout to check if operation successful */ 171747503b1SLiam Girdwood cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask); 172747503b1SLiam Girdwood ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 173747503b1SLiam Girdwood HDA_DSP_REG_ADSPCS, adspcs, 174747503b1SLiam Girdwood (adspcs & cpa) == cpa, 175747503b1SLiam Girdwood HDA_DSP_REG_POLL_INTERVAL_US, 176747503b1SLiam Girdwood HDA_DSP_RESET_TIMEOUT_US); 1776a414489SPierre-Louis Bossart if (ret < 0) { 1786a414489SPierre-Louis Bossart dev_err(sdev->dev, 1796a414489SPierre-Louis Bossart "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 1806a414489SPierre-Louis Bossart __func__); 1816a414489SPierre-Louis Bossart return ret; 1826a414489SPierre-Louis Bossart } 183747503b1SLiam Girdwood 184747503b1SLiam Girdwood /* did core power up ? */ 185747503b1SLiam Girdwood adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, 186747503b1SLiam Girdwood HDA_DSP_REG_ADSPCS); 187747503b1SLiam Girdwood if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) != 188747503b1SLiam Girdwood HDA_DSP_ADSPCS_CPA_MASK(core_mask)) { 189747503b1SLiam Girdwood dev_err(sdev->dev, 190747503b1SLiam Girdwood "error: power up core failed core_mask %xadspcs 0x%x\n", 191747503b1SLiam Girdwood core_mask, adspcs); 192747503b1SLiam Girdwood ret = -EIO; 193747503b1SLiam Girdwood } 194747503b1SLiam Girdwood 195747503b1SLiam Girdwood return ret; 196747503b1SLiam Girdwood } 197747503b1SLiam Girdwood 198747503b1SLiam Girdwood int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask) 199747503b1SLiam Girdwood { 200747503b1SLiam Girdwood u32 adspcs; 2016a414489SPierre-Louis Bossart int ret; 202747503b1SLiam Girdwood 203747503b1SLiam Girdwood /* update bits */ 204747503b1SLiam Girdwood snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, 205747503b1SLiam Girdwood HDA_DSP_REG_ADSPCS, 206747503b1SLiam Girdwood HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0); 207747503b1SLiam Girdwood 2086a414489SPierre-Louis Bossart ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, 209747503b1SLiam Girdwood HDA_DSP_REG_ADSPCS, adspcs, 210747503b1SLiam Girdwood !(adspcs & HDA_DSP_ADSPCS_SPA_MASK(core_mask)), 211747503b1SLiam Girdwood HDA_DSP_REG_POLL_INTERVAL_US, 212747503b1SLiam Girdwood HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC); 2136a414489SPierre-Louis Bossart if (ret < 0) 2146a414489SPierre-Louis Bossart dev_err(sdev->dev, 2156a414489SPierre-Louis Bossart "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n", 2166a414489SPierre-Louis Bossart __func__); 2176a414489SPierre-Louis Bossart 2186a414489SPierre-Louis Bossart return ret; 219747503b1SLiam Girdwood } 220747503b1SLiam Girdwood 221747503b1SLiam Girdwood bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, 222747503b1SLiam Girdwood unsigned int core_mask) 223747503b1SLiam Girdwood { 224747503b1SLiam Girdwood int val; 225747503b1SLiam Girdwood bool is_enable; 226747503b1SLiam Girdwood 227747503b1SLiam Girdwood val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS); 228747503b1SLiam Girdwood 229747503b1SLiam Girdwood is_enable = ((val & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) && 230747503b1SLiam Girdwood (val & HDA_DSP_ADSPCS_SPA_MASK(core_mask)) && 231747503b1SLiam Girdwood !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) && 232747503b1SLiam Girdwood !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask))); 233747503b1SLiam Girdwood 234747503b1SLiam Girdwood dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n", 235747503b1SLiam Girdwood is_enable, core_mask); 236747503b1SLiam Girdwood 237747503b1SLiam Girdwood return is_enable; 238747503b1SLiam Girdwood } 239747503b1SLiam Girdwood 240747503b1SLiam Girdwood int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask) 241747503b1SLiam Girdwood { 242747503b1SLiam Girdwood int ret; 243747503b1SLiam Girdwood 244747503b1SLiam Girdwood /* return if core is already enabled */ 245747503b1SLiam Girdwood if (hda_dsp_core_is_enabled(sdev, core_mask)) 246747503b1SLiam Girdwood return 0; 247747503b1SLiam Girdwood 248747503b1SLiam Girdwood /* power up */ 249747503b1SLiam Girdwood ret = hda_dsp_core_power_up(sdev, core_mask); 250747503b1SLiam Girdwood if (ret < 0) { 251747503b1SLiam Girdwood dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n", 252747503b1SLiam Girdwood core_mask); 253747503b1SLiam Girdwood return ret; 254747503b1SLiam Girdwood } 255747503b1SLiam Girdwood 256747503b1SLiam Girdwood return hda_dsp_core_run(sdev, core_mask); 257747503b1SLiam Girdwood } 258747503b1SLiam Girdwood 259747503b1SLiam Girdwood int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev, 260747503b1SLiam Girdwood unsigned int core_mask) 261747503b1SLiam Girdwood { 262747503b1SLiam Girdwood int ret; 263747503b1SLiam Girdwood 264747503b1SLiam Girdwood /* place core in reset prior to power down */ 265747503b1SLiam Girdwood ret = hda_dsp_core_stall_reset(sdev, core_mask); 266747503b1SLiam Girdwood if (ret < 0) { 267747503b1SLiam Girdwood dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n", 268747503b1SLiam Girdwood core_mask); 269747503b1SLiam Girdwood return ret; 270747503b1SLiam Girdwood } 271747503b1SLiam Girdwood 272747503b1SLiam Girdwood /* power down core */ 273747503b1SLiam Girdwood ret = hda_dsp_core_power_down(sdev, core_mask); 274747503b1SLiam Girdwood if (ret < 0) { 275747503b1SLiam Girdwood dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n", 276747503b1SLiam Girdwood core_mask, ret); 277747503b1SLiam Girdwood return ret; 278747503b1SLiam Girdwood } 279747503b1SLiam Girdwood 280747503b1SLiam Girdwood /* make sure we are in OFF state */ 281747503b1SLiam Girdwood if (hda_dsp_core_is_enabled(sdev, core_mask)) { 282747503b1SLiam Girdwood dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n", 283747503b1SLiam Girdwood core_mask, ret); 284747503b1SLiam Girdwood ret = -EIO; 285747503b1SLiam Girdwood } 286747503b1SLiam Girdwood 287747503b1SLiam Girdwood return ret; 288747503b1SLiam Girdwood } 289747503b1SLiam Girdwood 290747503b1SLiam Girdwood void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev) 291747503b1SLiam Girdwood { 292747503b1SLiam Girdwood struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 293747503b1SLiam Girdwood const struct sof_intel_dsp_desc *chip = hda->desc; 294747503b1SLiam Girdwood 295747503b1SLiam Girdwood /* enable IPC DONE and BUSY interrupts */ 296747503b1SLiam Girdwood snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 297747503b1SLiam Girdwood HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY, 298747503b1SLiam Girdwood HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY); 299747503b1SLiam Girdwood 300747503b1SLiam Girdwood /* enable IPC interrupt */ 301747503b1SLiam Girdwood snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC, 302747503b1SLiam Girdwood HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC); 303747503b1SLiam Girdwood } 304747503b1SLiam Girdwood 305747503b1SLiam Girdwood void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev) 306747503b1SLiam Girdwood { 307747503b1SLiam Girdwood struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 308747503b1SLiam Girdwood const struct sof_intel_dsp_desc *chip = hda->desc; 309747503b1SLiam Girdwood 310747503b1SLiam Girdwood /* disable IPC interrupt */ 311747503b1SLiam Girdwood snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC, 312747503b1SLiam Girdwood HDA_DSP_ADSPIC_IPC, 0); 313747503b1SLiam Girdwood 314747503b1SLiam Girdwood /* disable IPC BUSY and DONE interrupt */ 315747503b1SLiam Girdwood snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl, 316747503b1SLiam Girdwood HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0); 317747503b1SLiam Girdwood } 318747503b1SLiam Girdwood 31965c56f5dSRanjani Sridharan static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev) 32062f8f766SKeyon Jie { 32162f8f766SKeyon Jie struct hdac_bus *bus = sof_to_bus(sdev); 32265c56f5dSRanjani Sridharan int retry = HDA_DSP_REG_POLL_RETRY_COUNT; 32362f8f766SKeyon Jie 32462f8f766SKeyon Jie while (snd_hdac_chip_readb(bus, VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) { 32562f8f766SKeyon Jie if (!retry--) 32662f8f766SKeyon Jie return -ETIMEDOUT; 32762f8f766SKeyon Jie usleep_range(10, 15); 32862f8f766SKeyon Jie } 32962f8f766SKeyon Jie 33062f8f766SKeyon Jie return 0; 33162f8f766SKeyon Jie } 33262f8f766SKeyon Jie 333534037fdSKeyon Jie static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags) 334534037fdSKeyon Jie { 335534037fdSKeyon Jie struct sof_ipc_pm_gate pm_gate; 336534037fdSKeyon Jie struct sof_ipc_reply reply; 337534037fdSKeyon Jie 338534037fdSKeyon Jie memset(&pm_gate, 0, sizeof(pm_gate)); 339534037fdSKeyon Jie 340534037fdSKeyon Jie /* configure pm_gate ipc message */ 341534037fdSKeyon Jie pm_gate.hdr.size = sizeof(pm_gate); 342534037fdSKeyon Jie pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE; 343534037fdSKeyon Jie pm_gate.flags = flags; 344534037fdSKeyon Jie 345534037fdSKeyon Jie /* send pm_gate ipc to dsp */ 34663e51fd3SRanjani Sridharan return sof_ipc_tx_message_no_pm(sdev->ipc, pm_gate.hdr.cmd, 34763e51fd3SRanjani Sridharan &pm_gate, sizeof(pm_gate), &reply, 34863e51fd3SRanjani Sridharan sizeof(reply)); 349534037fdSKeyon Jie } 350534037fdSKeyon Jie 35161e285caSRanjani Sridharan static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value) 35262f8f766SKeyon Jie { 35362f8f766SKeyon Jie struct hdac_bus *bus = sof_to_bus(sdev); 35462f8f766SKeyon Jie int ret; 35562f8f766SKeyon Jie 35662f8f766SKeyon Jie /* Write to D0I3C after Command-In-Progress bit is cleared */ 35765c56f5dSRanjani Sridharan ret = hda_dsp_wait_d0i3c_done(sdev); 35862f8f766SKeyon Jie if (ret < 0) { 359aae7c82dSKeyon Jie dev_err(bus->dev, "CIP timeout before D0I3C update!\n"); 36062f8f766SKeyon Jie return ret; 36162f8f766SKeyon Jie } 36262f8f766SKeyon Jie 36362f8f766SKeyon Jie /* Update D0I3C register */ 36462f8f766SKeyon Jie snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value); 36562f8f766SKeyon Jie 36662f8f766SKeyon Jie /* Wait for cmd in progress to be cleared before exiting the function */ 36765c56f5dSRanjani Sridharan ret = hda_dsp_wait_d0i3c_done(sdev); 36862f8f766SKeyon Jie if (ret < 0) { 369aae7c82dSKeyon Jie dev_err(bus->dev, "CIP timeout after D0I3C update!\n"); 37062f8f766SKeyon Jie return ret; 37162f8f766SKeyon Jie } 37262f8f766SKeyon Jie 37362f8f766SKeyon Jie dev_vdbg(bus->dev, "D0I3C updated, register = 0x%x\n", 37462f8f766SKeyon Jie snd_hdac_chip_readb(bus, VS_D0I3C)); 37562f8f766SKeyon Jie 37661e285caSRanjani Sridharan return 0; 37761e285caSRanjani Sridharan } 378534037fdSKeyon Jie 37961e285caSRanjani Sridharan static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev, 38061e285caSRanjani Sridharan const struct sof_dsp_power_state *target_state) 38161e285caSRanjani Sridharan { 38261e285caSRanjani Sridharan u32 flags = 0; 38361e285caSRanjani Sridharan int ret; 38461e285caSRanjani Sridharan u8 value = 0; 38561e285caSRanjani Sridharan 38661e285caSRanjani Sridharan /* 38761e285caSRanjani Sridharan * Sanity check for illegal state transitions 38861e285caSRanjani Sridharan * The only allowed transitions are: 38961e285caSRanjani Sridharan * 1. D3 -> D0I0 39061e285caSRanjani Sridharan * 2. D0I0 -> D0I3 39161e285caSRanjani Sridharan * 3. D0I3 -> D0I0 39261e285caSRanjani Sridharan */ 39361e285caSRanjani Sridharan switch (sdev->dsp_power_state.state) { 39461e285caSRanjani Sridharan case SOF_DSP_PM_D0: 39561e285caSRanjani Sridharan /* Follow the sequence below for D0 substate transitions */ 39661e285caSRanjani Sridharan break; 39761e285caSRanjani Sridharan case SOF_DSP_PM_D3: 39861e285caSRanjani Sridharan /* Follow regular flow for D3 -> D0 transition */ 39961e285caSRanjani Sridharan return 0; 40061e285caSRanjani Sridharan default: 40161e285caSRanjani Sridharan dev_err(sdev->dev, "error: transition from %d to %d not allowed\n", 40261e285caSRanjani Sridharan sdev->dsp_power_state.state, target_state->state); 40361e285caSRanjani Sridharan return -EINVAL; 40461e285caSRanjani Sridharan } 40561e285caSRanjani Sridharan 40661e285caSRanjani Sridharan /* Set flags and register value for D0 target substate */ 40761e285caSRanjani Sridharan if (target_state->substate == SOF_HDA_DSP_PM_D0I3) { 40861e285caSRanjani Sridharan value = SOF_HDA_VS_D0I3C_I3; 40961e285caSRanjani Sridharan 410*851fd873SRanjani Sridharan /* 411*851fd873SRanjani Sridharan * Trace DMA is disabled by default when the DSP enters D0I3. 412*851fd873SRanjani Sridharan * But it can be kept enabled when the DSP enters D0I3 while the 413*851fd873SRanjani Sridharan * system is in S0 for debug. 414*851fd873SRanjani Sridharan */ 415*851fd873SRanjani Sridharan if (hda_enable_trace_D0I3_S0 && 416*851fd873SRanjani Sridharan sdev->system_suspend_target != SOF_SUSPEND_NONE) 41761e285caSRanjani Sridharan flags = HDA_PM_NO_DMA_TRACE; 41861e285caSRanjani Sridharan } else { 41961e285caSRanjani Sridharan /* prevent power gating in D0I0 */ 42061e285caSRanjani Sridharan flags = HDA_PM_PPG; 42161e285caSRanjani Sridharan } 42261e285caSRanjani Sridharan 42361e285caSRanjani Sridharan /* update D0I3C register */ 42461e285caSRanjani Sridharan ret = hda_dsp_update_d0i3c_register(sdev, value); 425534037fdSKeyon Jie if (ret < 0) 42661e285caSRanjani Sridharan return ret; 42761e285caSRanjani Sridharan 42861e285caSRanjani Sridharan /* 42961e285caSRanjani Sridharan * Notify the DSP of the state change. 43061e285caSRanjani Sridharan * If this IPC fails, revert the D0I3C register update in order 43161e285caSRanjani Sridharan * to prevent partial state change. 43261e285caSRanjani Sridharan */ 43361e285caSRanjani Sridharan ret = hda_dsp_send_pm_gate_ipc(sdev, flags); 43461e285caSRanjani Sridharan if (ret < 0) { 435534037fdSKeyon Jie dev_err(sdev->dev, 436534037fdSKeyon Jie "error: PM_GATE ipc error %d\n", ret); 43761e285caSRanjani Sridharan goto revert; 43861e285caSRanjani Sridharan } 43961e285caSRanjani Sridharan 44061e285caSRanjani Sridharan return ret; 44161e285caSRanjani Sridharan 44261e285caSRanjani Sridharan revert: 44361e285caSRanjani Sridharan /* fallback to the previous register value */ 44461e285caSRanjani Sridharan value = value ? 0 : SOF_HDA_VS_D0I3C_I3; 44561e285caSRanjani Sridharan 44661e285caSRanjani Sridharan /* 44761e285caSRanjani Sridharan * This can fail but return the IPC error to signal that 44861e285caSRanjani Sridharan * the state change failed. 44961e285caSRanjani Sridharan */ 45061e285caSRanjani Sridharan hda_dsp_update_d0i3c_register(sdev, value); 451534037fdSKeyon Jie 452534037fdSKeyon Jie return ret; 45362f8f766SKeyon Jie } 45462f8f766SKeyon Jie 45561e285caSRanjani Sridharan /* 45661e285caSRanjani Sridharan * All DSP power state transitions are initiated by the driver. 45761e285caSRanjani Sridharan * If the requested state change fails, the error is simply returned. 45861e285caSRanjani Sridharan * Further state transitions are attempted only when the set_power_save() op 45961e285caSRanjani Sridharan * is called again either because of a new IPC sent to the DSP or 46061e285caSRanjani Sridharan * during system suspend/resume. 46161e285caSRanjani Sridharan */ 46261e285caSRanjani Sridharan int hda_dsp_set_power_state(struct snd_sof_dev *sdev, 46361e285caSRanjani Sridharan const struct sof_dsp_power_state *target_state) 46461e285caSRanjani Sridharan { 46561e285caSRanjani Sridharan int ret = 0; 46661e285caSRanjani Sridharan 467*851fd873SRanjani Sridharan /* 468*851fd873SRanjani Sridharan * When the DSP is already in D0I3 and the target state is D0I3, 469*851fd873SRanjani Sridharan * it could be the case that the DSP is in D0I3 during S0 470*851fd873SRanjani Sridharan * and the system is suspending to S0Ix. Therefore, 471*851fd873SRanjani Sridharan * hda_dsp_set_D0_state() must be called to disable trace DMA 472*851fd873SRanjani Sridharan * by sending the PM_GATE IPC to the FW. 473*851fd873SRanjani Sridharan */ 474*851fd873SRanjani Sridharan if (target_state->substate == SOF_HDA_DSP_PM_D0I3 && 475*851fd873SRanjani Sridharan sdev->system_suspend_target == SOF_SUSPEND_S0IX) 476*851fd873SRanjani Sridharan goto set_state; 477*851fd873SRanjani Sridharan 478*851fd873SRanjani Sridharan /* 479*851fd873SRanjani Sridharan * For all other cases, return without doing anything if 480*851fd873SRanjani Sridharan * the DSP is already in the target state. 481*851fd873SRanjani Sridharan */ 48261e285caSRanjani Sridharan if (target_state->state == sdev->dsp_power_state.state && 48361e285caSRanjani Sridharan target_state->substate == sdev->dsp_power_state.substate) 48461e285caSRanjani Sridharan return 0; 48561e285caSRanjani Sridharan 486*851fd873SRanjani Sridharan set_state: 48761e285caSRanjani Sridharan switch (target_state->state) { 48861e285caSRanjani Sridharan case SOF_DSP_PM_D0: 48961e285caSRanjani Sridharan ret = hda_dsp_set_D0_state(sdev, target_state); 49061e285caSRanjani Sridharan break; 49161e285caSRanjani Sridharan case SOF_DSP_PM_D3: 49261e285caSRanjani Sridharan /* The only allowed transition is: D0I0 -> D3 */ 49361e285caSRanjani Sridharan if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 && 49461e285caSRanjani Sridharan sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0) 49561e285caSRanjani Sridharan break; 49661e285caSRanjani Sridharan 49761e285caSRanjani Sridharan dev_err(sdev->dev, 49861e285caSRanjani Sridharan "error: transition from %d to %d not allowed\n", 49961e285caSRanjani Sridharan sdev->dsp_power_state.state, target_state->state); 50061e285caSRanjani Sridharan return -EINVAL; 50161e285caSRanjani Sridharan default: 50261e285caSRanjani Sridharan dev_err(sdev->dev, "error: target state unsupported %d\n", 50361e285caSRanjani Sridharan target_state->state); 50461e285caSRanjani Sridharan return -EINVAL; 50561e285caSRanjani Sridharan } 50661e285caSRanjani Sridharan if (ret < 0) { 50761e285caSRanjani Sridharan dev_err(sdev->dev, 50861e285caSRanjani Sridharan "failed to set requested target DSP state %d substate %d\n", 50961e285caSRanjani Sridharan target_state->state, target_state->substate); 51061e285caSRanjani Sridharan return ret; 51161e285caSRanjani Sridharan } 51261e285caSRanjani Sridharan 51361e285caSRanjani Sridharan sdev->dsp_power_state = *target_state; 51461e285caSRanjani Sridharan dev_dbg(sdev->dev, "New DSP state %d substate %d\n", 51561e285caSRanjani Sridharan target_state->state, target_state->substate); 51661e285caSRanjani Sridharan return ret; 51761e285caSRanjani Sridharan } 51861e285caSRanjani Sridharan 51961e285caSRanjani Sridharan /* 52061e285caSRanjani Sridharan * Audio DSP states may transform as below:- 52161e285caSRanjani Sridharan * 522207bf12fSRanjani Sridharan * Opportunistic D0I3 in S0 523207bf12fSRanjani Sridharan * Runtime +---------------------+ Delayed D0i3 work timeout 52461e285caSRanjani Sridharan * suspend | +--------------------+ 525207bf12fSRanjani Sridharan * +------------+ D0I0(active) | | 52661e285caSRanjani Sridharan * | | <---------------+ | 527207bf12fSRanjani Sridharan * | +--------> | New IPC | | 528207bf12fSRanjani Sridharan * | |Runtime +--^--+---------^--+--+ (via mailbox) | | 529207bf12fSRanjani Sridharan * | |resume | | | | | | 530207bf12fSRanjani Sridharan * | | | | | | | | 531207bf12fSRanjani Sridharan * | | System| | | | | | 532207bf12fSRanjani Sridharan * | | resume| | S3/S0IX | | | | 533207bf12fSRanjani Sridharan * | | | | suspend | | S0IX | | 53461e285caSRanjani Sridharan * | | | | | |suspend | | 53561e285caSRanjani Sridharan * | | | | | | | | 53661e285caSRanjani Sridharan * | | | | | | | | 53761e285caSRanjani Sridharan * +-v---+-----------+--v-------+ | | +------+----v----+ 53861e285caSRanjani Sridharan * | | | +-----------> | 539207bf12fSRanjani Sridharan * | D3 (suspended) | | | D0I3 | 540207bf12fSRanjani Sridharan * | | +--------------+ | 541207bf12fSRanjani Sridharan * | | System resume | | 542207bf12fSRanjani Sridharan * +----------------------------+ +----------------+ 54361e285caSRanjani Sridharan * 544207bf12fSRanjani Sridharan * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams 545207bf12fSRanjani Sridharan * ignored the suspend trigger. Otherwise the DSP 546207bf12fSRanjani Sridharan * is in D3. 54761e285caSRanjani Sridharan */ 54861e285caSRanjani Sridharan 5491c38c922SFred Oh static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend) 550747503b1SLiam Girdwood { 551747503b1SLiam Girdwood struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 552747503b1SLiam Girdwood const struct sof_intel_dsp_desc *chip = hda->desc; 553747503b1SLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 554747503b1SLiam Girdwood struct hdac_bus *bus = sof_to_bus(sdev); 555747503b1SLiam Girdwood #endif 556747503b1SLiam Girdwood int ret; 557747503b1SLiam Girdwood 558747503b1SLiam Girdwood /* disable IPC interrupts */ 559747503b1SLiam Girdwood hda_dsp_ipc_int_disable(sdev); 560747503b1SLiam Girdwood 561747503b1SLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 562fd15f2f5SRander Wang if (runtime_suspend) 563fd15f2f5SRander Wang hda_codec_jack_wake_enable(sdev); 564fd15f2f5SRander Wang 565747503b1SLiam Girdwood /* power down all hda link */ 566747503b1SLiam Girdwood snd_hdac_ext_bus_link_power_down_all(bus); 567747503b1SLiam Girdwood #endif 568747503b1SLiam Girdwood 569747503b1SLiam Girdwood /* power down DSP */ 570747503b1SLiam Girdwood ret = hda_dsp_core_reset_power_down(sdev, chip->cores_mask); 571747503b1SLiam Girdwood if (ret < 0) { 572747503b1SLiam Girdwood dev_err(sdev->dev, 573747503b1SLiam Girdwood "error: failed to power down core during suspend\n"); 574747503b1SLiam Girdwood return ret; 575747503b1SLiam Girdwood } 576747503b1SLiam Girdwood 577747503b1SLiam Girdwood /* disable ppcap interrupt */ 578747503b1SLiam Girdwood hda_dsp_ctrl_ppcap_enable(sdev, false); 579747503b1SLiam Girdwood hda_dsp_ctrl_ppcap_int_enable(sdev, false); 580747503b1SLiam Girdwood 5819a50ee58SZhu Yingjiang /* disable hda bus irq and streams */ 5829a50ee58SZhu Yingjiang hda_dsp_ctrl_stop_chip(sdev); 583747503b1SLiam Girdwood 584747503b1SLiam Girdwood /* disable LP retention mode */ 585747503b1SLiam Girdwood snd_sof_pci_update_bits(sdev, PCI_PGCTL, 586747503b1SLiam Girdwood PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK); 587747503b1SLiam Girdwood 588747503b1SLiam Girdwood /* reset controller */ 589747503b1SLiam Girdwood ret = hda_dsp_ctrl_link_reset(sdev, true); 590747503b1SLiam Girdwood if (ret < 0) { 591747503b1SLiam Girdwood dev_err(sdev->dev, 592747503b1SLiam Girdwood "error: failed to reset controller during suspend\n"); 593747503b1SLiam Girdwood return ret; 594747503b1SLiam Girdwood } 595747503b1SLiam Girdwood 596747503b1SLiam Girdwood return 0; 597747503b1SLiam Girdwood } 598747503b1SLiam Girdwood 599fd15f2f5SRander Wang static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume) 600747503b1SLiam Girdwood { 601747503b1SLiam Girdwood #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 602747503b1SLiam Girdwood struct hdac_bus *bus = sof_to_bus(sdev); 603747503b1SLiam Girdwood struct hdac_ext_link *hlink = NULL; 604747503b1SLiam Girdwood #endif 605747503b1SLiam Girdwood int ret; 606747503b1SLiam Girdwood 607747503b1SLiam Girdwood /* 608747503b1SLiam Girdwood * clear TCSEL to clear playback on some HD Audio 609747503b1SLiam Girdwood * codecs. PCI TCSEL is defined in the Intel manuals. 610747503b1SLiam Girdwood */ 611747503b1SLiam Girdwood snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 612747503b1SLiam Girdwood 613747503b1SLiam Girdwood /* reset and start hda controller */ 614747503b1SLiam Girdwood ret = hda_dsp_ctrl_init_chip(sdev, true); 615747503b1SLiam Girdwood if (ret < 0) { 616747503b1SLiam Girdwood dev_err(sdev->dev, 617747503b1SLiam Girdwood "error: failed to start controller after resume\n"); 618747503b1SLiam Girdwood return ret; 619747503b1SLiam Girdwood } 620747503b1SLiam Girdwood 621fd15f2f5SRander Wang #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 622fd15f2f5SRander Wang /* check jack status */ 623fd15f2f5SRander Wang if (runtime_resume) 624fd15f2f5SRander Wang hda_codec_jack_check(sdev); 6256aa232e1SRander Wang 6266aa232e1SRander Wang /* turn off the links that were off before suspend */ 6276aa232e1SRander Wang list_for_each_entry(hlink, &bus->hlink_list, list) { 6286aa232e1SRander Wang if (!hlink->ref_count) 6296aa232e1SRander Wang snd_hdac_ext_bus_link_power_down(hlink); 6306aa232e1SRander Wang } 6316aa232e1SRander Wang 6326aa232e1SRander Wang /* check dma status and clean up CORB/RIRB buffers */ 6336aa232e1SRander Wang if (!bus->cmd_dma_state) 6346aa232e1SRander Wang snd_hdac_bus_stop_cmd_io(bus); 63524b6ff68SZhu Yingjiang #endif 636747503b1SLiam Girdwood 637747503b1SLiam Girdwood /* enable ppcap interrupt */ 638747503b1SLiam Girdwood hda_dsp_ctrl_ppcap_enable(sdev, true); 639747503b1SLiam Girdwood hda_dsp_ctrl_ppcap_int_enable(sdev, true); 640747503b1SLiam Girdwood 641747503b1SLiam Girdwood return 0; 642747503b1SLiam Girdwood } 643747503b1SLiam Girdwood 644747503b1SLiam Girdwood int hda_dsp_resume(struct snd_sof_dev *sdev) 645747503b1SLiam Girdwood { 64616299326SKeyon Jie struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 64766e40876SKeyon Jie struct pci_dev *pci = to_pci_dev(sdev->dev); 64861e285caSRanjani Sridharan const struct sof_dsp_power_state target_state = { 64961e285caSRanjani Sridharan .state = SOF_DSP_PM_D0, 65061e285caSRanjani Sridharan .substate = SOF_HDA_DSP_PM_D0I0, 65161e285caSRanjani Sridharan }; 65261e285caSRanjani Sridharan int ret; 65366e40876SKeyon Jie 65461e285caSRanjani Sridharan /* resume from D0I3 */ 65561e285caSRanjani Sridharan if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) { 65661e285caSRanjani Sridharan /* Set DSP power state */ 65761e285caSRanjani Sridharan ret = hda_dsp_set_power_state(sdev, &target_state); 65861e285caSRanjani Sridharan if (ret < 0) { 65961e285caSRanjani Sridharan dev_err(sdev->dev, "error: setting dsp state %d substate %d\n", 66061e285caSRanjani Sridharan target_state.state, target_state.substate); 66161e285caSRanjani Sridharan return ret; 66261e285caSRanjani Sridharan } 66361e285caSRanjani Sridharan 66416299326SKeyon Jie /* restore L1SEN bit */ 66516299326SKeyon Jie if (hda->l1_support_changed) 66616299326SKeyon Jie snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 66716299326SKeyon Jie HDA_VS_INTEL_EM2, 66816299326SKeyon Jie HDA_VS_INTEL_EM2_L1SEN, 0); 66916299326SKeyon Jie 67066e40876SKeyon Jie /* restore and disable the system wakeup */ 67166e40876SKeyon Jie pci_restore_state(pci); 67266e40876SKeyon Jie disable_irq_wake(pci->irq); 67366e40876SKeyon Jie return 0; 67466e40876SKeyon Jie } 67566e40876SKeyon Jie 676747503b1SLiam Girdwood /* init hda controller. DSP cores will be powered up during fw boot */ 67761e285caSRanjani Sridharan ret = hda_resume(sdev, false); 67861e285caSRanjani Sridharan if (ret < 0) 67961e285caSRanjani Sridharan return ret; 68061e285caSRanjani Sridharan 68161e285caSRanjani Sridharan hda_dsp_set_power_state(sdev, &target_state); 68261e285caSRanjani Sridharan return ret; 683747503b1SLiam Girdwood } 684747503b1SLiam Girdwood 685747503b1SLiam Girdwood int hda_dsp_runtime_resume(struct snd_sof_dev *sdev) 686747503b1SLiam Girdwood { 68761e285caSRanjani Sridharan const struct sof_dsp_power_state target_state = { 68861e285caSRanjani Sridharan .state = SOF_DSP_PM_D0, 68961e285caSRanjani Sridharan }; 69061e285caSRanjani Sridharan int ret; 69161e285caSRanjani Sridharan 692747503b1SLiam Girdwood /* init hda controller. DSP cores will be powered up during fw boot */ 69361e285caSRanjani Sridharan ret = hda_resume(sdev, true); 69461e285caSRanjani Sridharan if (ret < 0) 69561e285caSRanjani Sridharan return ret; 69661e285caSRanjani Sridharan 69761e285caSRanjani Sridharan return hda_dsp_set_power_state(sdev, &target_state); 698747503b1SLiam Girdwood } 699747503b1SLiam Girdwood 70087a6fe80SKai Vehmanen int hda_dsp_runtime_idle(struct snd_sof_dev *sdev) 70187a6fe80SKai Vehmanen { 70287a6fe80SKai Vehmanen struct hdac_bus *hbus = sof_to_bus(sdev); 70387a6fe80SKai Vehmanen 70487a6fe80SKai Vehmanen if (hbus->codec_powered) { 70587a6fe80SKai Vehmanen dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n", 70687a6fe80SKai Vehmanen (unsigned int)hbus->codec_powered); 70787a6fe80SKai Vehmanen return -EBUSY; 70887a6fe80SKai Vehmanen } 70987a6fe80SKai Vehmanen 71087a6fe80SKai Vehmanen return 0; 71187a6fe80SKai Vehmanen } 71287a6fe80SKai Vehmanen 7131c38c922SFred Oh int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev) 714747503b1SLiam Girdwood { 71561e285caSRanjani Sridharan const struct sof_dsp_power_state target_state = { 71661e285caSRanjani Sridharan .state = SOF_DSP_PM_D3, 71761e285caSRanjani Sridharan }; 71861e285caSRanjani Sridharan int ret; 71961e285caSRanjani Sridharan 720747503b1SLiam Girdwood /* stop hda controller and power dsp off */ 72161e285caSRanjani Sridharan ret = hda_suspend(sdev, true); 72261e285caSRanjani Sridharan if (ret < 0) 72361e285caSRanjani Sridharan return ret; 72461e285caSRanjani Sridharan 72561e285caSRanjani Sridharan return hda_dsp_set_power_state(sdev, &target_state); 726747503b1SLiam Girdwood } 727747503b1SLiam Girdwood 72861e285caSRanjani Sridharan int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state) 729747503b1SLiam Girdwood { 73016299326SKeyon Jie struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 731747503b1SLiam Girdwood struct hdac_bus *bus = sof_to_bus(sdev); 73266e40876SKeyon Jie struct pci_dev *pci = to_pci_dev(sdev->dev); 73361e285caSRanjani Sridharan const struct sof_dsp_power_state target_dsp_state = { 73461e285caSRanjani Sridharan .state = target_state, 73561e285caSRanjani Sridharan .substate = target_state == SOF_DSP_PM_D0 ? 73661e285caSRanjani Sridharan SOF_HDA_DSP_PM_D0I3 : 0, 73761e285caSRanjani Sridharan }; 738747503b1SLiam Girdwood int ret; 739747503b1SLiam Girdwood 74063e51fd3SRanjani Sridharan /* cancel any attempt for DSP D0I3 */ 74163e51fd3SRanjani Sridharan cancel_delayed_work_sync(&hda->d0i3_work); 74263e51fd3SRanjani Sridharan 74361e285caSRanjani Sridharan if (target_state == SOF_DSP_PM_D0) { 74461e285caSRanjani Sridharan /* Set DSP power state */ 74561e285caSRanjani Sridharan ret = hda_dsp_set_power_state(sdev, &target_dsp_state); 74661e285caSRanjani Sridharan if (ret < 0) { 74761e285caSRanjani Sridharan dev_err(sdev->dev, "error: setting dsp state %d substate %d\n", 74861e285caSRanjani Sridharan target_dsp_state.state, 74961e285caSRanjani Sridharan target_dsp_state.substate); 75061e285caSRanjani Sridharan return ret; 75161e285caSRanjani Sridharan } 75261e285caSRanjani Sridharan 75316299326SKeyon Jie /* enable L1SEN to make sure the system can enter S0Ix */ 75416299326SKeyon Jie hda->l1_support_changed = 75516299326SKeyon Jie snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 75616299326SKeyon Jie HDA_VS_INTEL_EM2, 75716299326SKeyon Jie HDA_VS_INTEL_EM2_L1SEN, 75816299326SKeyon Jie HDA_VS_INTEL_EM2_L1SEN); 75916299326SKeyon Jie 76066e40876SKeyon Jie /* enable the system waking up via IPC IRQ */ 76166e40876SKeyon Jie enable_irq_wake(pci->irq); 76266e40876SKeyon Jie pci_save_state(pci); 76366e40876SKeyon Jie return 0; 76466e40876SKeyon Jie } 76566e40876SKeyon Jie 766747503b1SLiam Girdwood /* stop hda controller and power dsp off */ 7671c38c922SFred Oh ret = hda_suspend(sdev, false); 768747503b1SLiam Girdwood if (ret < 0) { 769747503b1SLiam Girdwood dev_err(bus->dev, "error: suspending dsp\n"); 770747503b1SLiam Girdwood return ret; 771747503b1SLiam Girdwood } 772747503b1SLiam Girdwood 77361e285caSRanjani Sridharan return hda_dsp_set_power_state(sdev, &target_dsp_state); 774747503b1SLiam Girdwood } 775ed3baacdSRanjani Sridharan 7767077a07aSRanjani Sridharan int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev) 777ed3baacdSRanjani Sridharan { 7787077a07aSRanjani Sridharan #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 779a3ebccb5SKai Vehmanen struct hdac_bus *bus = sof_to_bus(sdev); 7807077a07aSRanjani Sridharan struct snd_soc_pcm_runtime *rtd; 781a3ebccb5SKai Vehmanen struct hdac_ext_stream *stream; 7827077a07aSRanjani Sridharan struct hdac_ext_link *link; 783a3ebccb5SKai Vehmanen struct hdac_stream *s; 7847077a07aSRanjani Sridharan const char *name; 7857077a07aSRanjani Sridharan int stream_tag; 7867077a07aSRanjani Sridharan 787ed3baacdSRanjani Sridharan /* set internal flag for BE */ 788ed3baacdSRanjani Sridharan list_for_each_entry(s, &bus->stream_list, list) { 789ed3baacdSRanjani Sridharan stream = stream_to_hdac_ext_stream(s); 790a3ebccb5SKai Vehmanen 7917077a07aSRanjani Sridharan /* 792934bf822SRander Wang * clear stream. This should already be taken care for running 793934bf822SRander Wang * streams when the SUSPEND trigger is called. But paused 794934bf822SRander Wang * streams do not get suspended, so this needs to be done 795934bf822SRander Wang * explicitly during suspend. 7967077a07aSRanjani Sridharan */ 7977077a07aSRanjani Sridharan if (stream->link_substream) { 7987077a07aSRanjani Sridharan rtd = snd_pcm_substream_chip(stream->link_substream); 7997077a07aSRanjani Sridharan name = rtd->codec_dai->component->name; 8007077a07aSRanjani Sridharan link = snd_hdac_ext_bus_get_link(bus, name); 8017077a07aSRanjani Sridharan if (!link) 8027077a07aSRanjani Sridharan return -EINVAL; 803810dbea3SRander Wang 804810dbea3SRander Wang stream->link_prepared = 0; 805810dbea3SRander Wang 806810dbea3SRander Wang if (hdac_stream(stream)->direction == 807810dbea3SRander Wang SNDRV_PCM_STREAM_CAPTURE) 808810dbea3SRander Wang continue; 809810dbea3SRander Wang 8107077a07aSRanjani Sridharan stream_tag = hdac_stream(stream)->stream_tag; 8117077a07aSRanjani Sridharan snd_hdac_ext_link_clear_stream_id(link, stream_tag); 812a3ebccb5SKai Vehmanen } 813ed3baacdSRanjani Sridharan } 8147077a07aSRanjani Sridharan #endif 8157077a07aSRanjani Sridharan return 0; 816ed3baacdSRanjani Sridharan } 81763e51fd3SRanjani Sridharan 81863e51fd3SRanjani Sridharan void hda_dsp_d0i3_work(struct work_struct *work) 81963e51fd3SRanjani Sridharan { 82063e51fd3SRanjani Sridharan struct sof_intel_hda_dev *hdev = container_of(work, 82163e51fd3SRanjani Sridharan struct sof_intel_hda_dev, 82263e51fd3SRanjani Sridharan d0i3_work.work); 82363e51fd3SRanjani Sridharan struct hdac_bus *bus = &hdev->hbus.core; 82463e51fd3SRanjani Sridharan struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev); 82563e51fd3SRanjani Sridharan struct sof_dsp_power_state target_state; 82663e51fd3SRanjani Sridharan int ret; 82763e51fd3SRanjani Sridharan 82863e51fd3SRanjani Sridharan target_state.state = SOF_DSP_PM_D0; 82963e51fd3SRanjani Sridharan 83063e51fd3SRanjani Sridharan /* DSP can enter D0I3 iff only D0I3-compatible streams are active */ 83163e51fd3SRanjani Sridharan if (snd_sof_dsp_only_d0i3_compatible_stream_active(sdev)) 83263e51fd3SRanjani Sridharan target_state.substate = SOF_HDA_DSP_PM_D0I3; 83363e51fd3SRanjani Sridharan else 83463e51fd3SRanjani Sridharan target_state.substate = SOF_HDA_DSP_PM_D0I0; 83563e51fd3SRanjani Sridharan 83663e51fd3SRanjani Sridharan /* remain in D0I0 */ 83763e51fd3SRanjani Sridharan if (target_state.substate == SOF_HDA_DSP_PM_D0I0) 83863e51fd3SRanjani Sridharan return; 83963e51fd3SRanjani Sridharan 84063e51fd3SRanjani Sridharan /* This can fail but error cannot be propagated */ 84163e51fd3SRanjani Sridharan ret = hda_dsp_set_power_state(sdev, &target_state); 84263e51fd3SRanjani Sridharan if (ret < 0) 84363e51fd3SRanjani Sridharan dev_err_ratelimited(sdev->dev, 84463e51fd3SRanjani Sridharan "error: failed to set DSP state %d substate %d\n", 84563e51fd3SRanjani Sridharan target_state.state, target_state.substate); 84663e51fd3SRanjani Sridharan } 847