1 // SPDX-License-Identifier: GPL-2.0-only 2 /* sound/soc/rockchip/rockchip_i2s.c 3 * 4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver 5 * 6 * Copyright (c) 2014 Rockchip Electronics Co. Ltd. 7 * Author: Jianqun <jay.xu@rock-chips.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/delay.h> 13 #include <linux/of_gpio.h> 14 #include <linux/of_device.h> 15 #include <linux/clk.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/spinlock.h> 20 #include <sound/pcm_params.h> 21 #include <sound/dmaengine_pcm.h> 22 23 #include "rockchip_i2s.h" 24 25 #define DRV_NAME "rockchip-i2s" 26 27 struct rk_i2s_pins { 28 u32 reg_offset; 29 u32 shift; 30 }; 31 32 struct rk_i2s_dev { 33 struct device *dev; 34 35 struct clk *hclk; 36 struct clk *mclk; 37 38 struct snd_dmaengine_dai_dma_data capture_dma_data; 39 struct snd_dmaengine_dai_dma_data playback_dma_data; 40 41 struct regmap *regmap; 42 struct regmap *grf; 43 44 bool has_capture; 45 bool has_playback; 46 47 /* 48 * Used to indicate the tx/rx status. 49 * I2S controller hopes to start the tx and rx together, 50 * also to stop them when they are both try to stop. 51 */ 52 bool tx_start; 53 bool rx_start; 54 bool is_master_mode; 55 const struct rk_i2s_pins *pins; 56 unsigned int bclk_ratio; 57 spinlock_t lock; /* tx/rx lock */ 58 struct pinctrl *pinctrl; 59 struct pinctrl_state *bclk_on; 60 struct pinctrl_state *bclk_off; 61 }; 62 63 static int i2s_pinctrl_select_bclk_on(struct rk_i2s_dev *i2s) 64 { 65 int ret = 0; 66 67 if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_on)) 68 ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_on); 69 70 if (ret) 71 dev_err(i2s->dev, "bclk enable failed %d\n", ret); 72 73 return ret; 74 } 75 76 static int i2s_pinctrl_select_bclk_off(struct rk_i2s_dev *i2s) 77 { 78 79 int ret = 0; 80 81 if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_off)) 82 ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_off); 83 84 if (ret) 85 dev_err(i2s->dev, "bclk disable failed %d\n", ret); 86 87 return ret; 88 } 89 90 static int i2s_runtime_suspend(struct device *dev) 91 { 92 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 93 94 regcache_cache_only(i2s->regmap, true); 95 clk_disable_unprepare(i2s->mclk); 96 97 return 0; 98 } 99 100 static int i2s_runtime_resume(struct device *dev) 101 { 102 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 103 int ret; 104 105 ret = clk_prepare_enable(i2s->mclk); 106 if (ret) { 107 dev_err(i2s->dev, "clock enable failed %d\n", ret); 108 return ret; 109 } 110 111 regcache_cache_only(i2s->regmap, false); 112 regcache_mark_dirty(i2s->regmap); 113 114 ret = regcache_sync(i2s->regmap); 115 if (ret) 116 clk_disable_unprepare(i2s->mclk); 117 118 return ret; 119 } 120 121 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai) 122 { 123 return snd_soc_dai_get_drvdata(dai); 124 } 125 126 static int rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) 127 { 128 unsigned int val = 0; 129 int retry = 10; 130 int ret = 0; 131 132 spin_lock(&i2s->lock); 133 if (on) { 134 ret = regmap_update_bits(i2s->regmap, I2S_DMACR, 135 I2S_DMACR_TDE_ENABLE, 136 I2S_DMACR_TDE_ENABLE); 137 if (ret < 0) 138 goto end; 139 ret = regmap_update_bits(i2s->regmap, I2S_XFER, 140 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 141 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 142 if (ret < 0) 143 goto end; 144 i2s->tx_start = true; 145 } else { 146 i2s->tx_start = false; 147 148 ret = regmap_update_bits(i2s->regmap, I2S_DMACR, 149 I2S_DMACR_TDE_ENABLE, 150 I2S_DMACR_TDE_DISABLE); 151 if (ret < 0) 152 goto end; 153 154 if (!i2s->rx_start) { 155 ret = regmap_update_bits(i2s->regmap, I2S_XFER, 156 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 157 I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); 158 if (ret < 0) 159 goto end; 160 udelay(150); 161 ret = regmap_update_bits(i2s->regmap, I2S_CLR, 162 I2S_CLR_TXC | I2S_CLR_RXC, 163 I2S_CLR_TXC | I2S_CLR_RXC); 164 if (ret < 0) 165 goto end; 166 regmap_read(i2s->regmap, I2S_CLR, &val); 167 168 /* Should wait for clear operation to finish */ 169 while (val) { 170 regmap_read(i2s->regmap, I2S_CLR, &val); 171 retry--; 172 if (!retry) { 173 dev_warn(i2s->dev, "fail to clear\n"); 174 break; 175 } 176 } 177 } 178 } 179 end: 180 spin_unlock(&i2s->lock); 181 if (ret < 0) 182 dev_err(i2s->dev, "lrclk update failed\n"); 183 184 return ret; 185 } 186 187 static int rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) 188 { 189 unsigned int val = 0; 190 int retry = 10; 191 int ret = 0; 192 193 spin_lock(&i2s->lock); 194 if (on) { 195 ret = regmap_update_bits(i2s->regmap, I2S_DMACR, 196 I2S_DMACR_RDE_ENABLE, 197 I2S_DMACR_RDE_ENABLE); 198 if (ret < 0) 199 goto end; 200 201 ret = regmap_update_bits(i2s->regmap, I2S_XFER, 202 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 203 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 204 if (ret < 0) 205 goto end; 206 i2s->rx_start = true; 207 } else { 208 i2s->rx_start = false; 209 210 ret = regmap_update_bits(i2s->regmap, I2S_DMACR, 211 I2S_DMACR_RDE_ENABLE, 212 I2S_DMACR_RDE_DISABLE); 213 if (ret < 0) 214 goto end; 215 216 if (!i2s->tx_start) { 217 ret = regmap_update_bits(i2s->regmap, I2S_XFER, 218 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 219 I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); 220 if (ret < 0) 221 goto end; 222 udelay(150); 223 ret = regmap_update_bits(i2s->regmap, I2S_CLR, 224 I2S_CLR_TXC | I2S_CLR_RXC, 225 I2S_CLR_TXC | I2S_CLR_RXC); 226 if (ret < 0) 227 goto end; 228 regmap_read(i2s->regmap, I2S_CLR, &val); 229 /* Should wait for clear operation to finish */ 230 while (val) { 231 regmap_read(i2s->regmap, I2S_CLR, &val); 232 retry--; 233 if (!retry) { 234 dev_warn(i2s->dev, "fail to clear\n"); 235 break; 236 } 237 } 238 } 239 } 240 end: 241 spin_unlock(&i2s->lock); 242 if (ret < 0) 243 dev_err(i2s->dev, "lrclk update failed\n"); 244 245 return ret; 246 } 247 248 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, 249 unsigned int fmt) 250 { 251 struct rk_i2s_dev *i2s = to_info(cpu_dai); 252 unsigned int mask = 0, val = 0; 253 int ret = 0; 254 255 pm_runtime_get_sync(cpu_dai->dev); 256 mask = I2S_CKR_MSS_MASK; 257 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 258 case SND_SOC_DAIFMT_BP_FP: 259 /* Set source clock in Master mode */ 260 val = I2S_CKR_MSS_MASTER; 261 i2s->is_master_mode = true; 262 break; 263 case SND_SOC_DAIFMT_BC_FC: 264 val = I2S_CKR_MSS_SLAVE; 265 i2s->is_master_mode = false; 266 break; 267 default: 268 ret = -EINVAL; 269 goto err_pm_put; 270 } 271 272 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); 273 274 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK; 275 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 276 case SND_SOC_DAIFMT_NB_NF: 277 val = I2S_CKR_CKP_NORMAL | 278 I2S_CKR_TLP_NORMAL | 279 I2S_CKR_RLP_NORMAL; 280 break; 281 case SND_SOC_DAIFMT_NB_IF: 282 val = I2S_CKR_CKP_NORMAL | 283 I2S_CKR_TLP_INVERTED | 284 I2S_CKR_RLP_INVERTED; 285 break; 286 case SND_SOC_DAIFMT_IB_NF: 287 val = I2S_CKR_CKP_INVERTED | 288 I2S_CKR_TLP_NORMAL | 289 I2S_CKR_RLP_NORMAL; 290 break; 291 case SND_SOC_DAIFMT_IB_IF: 292 val = I2S_CKR_CKP_INVERTED | 293 I2S_CKR_TLP_INVERTED | 294 I2S_CKR_RLP_INVERTED; 295 break; 296 default: 297 ret = -EINVAL; 298 goto err_pm_put; 299 } 300 301 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); 302 303 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK; 304 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 305 case SND_SOC_DAIFMT_RIGHT_J: 306 val = I2S_TXCR_IBM_RSJM; 307 break; 308 case SND_SOC_DAIFMT_LEFT_J: 309 val = I2S_TXCR_IBM_LSJM; 310 break; 311 case SND_SOC_DAIFMT_I2S: 312 val = I2S_TXCR_IBM_NORMAL; 313 break; 314 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */ 315 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1); 316 break; 317 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */ 318 val = I2S_TXCR_TFS_PCM; 319 break; 320 default: 321 ret = -EINVAL; 322 goto err_pm_put; 323 } 324 325 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val); 326 327 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK; 328 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 329 case SND_SOC_DAIFMT_RIGHT_J: 330 val = I2S_RXCR_IBM_RSJM; 331 break; 332 case SND_SOC_DAIFMT_LEFT_J: 333 val = I2S_RXCR_IBM_LSJM; 334 break; 335 case SND_SOC_DAIFMT_I2S: 336 val = I2S_RXCR_IBM_NORMAL; 337 break; 338 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */ 339 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1); 340 break; 341 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */ 342 val = I2S_RXCR_TFS_PCM; 343 break; 344 default: 345 ret = -EINVAL; 346 goto err_pm_put; 347 } 348 349 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val); 350 351 err_pm_put: 352 pm_runtime_put(cpu_dai->dev); 353 354 return ret; 355 } 356 357 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, 358 struct snd_pcm_hw_params *params, 359 struct snd_soc_dai *dai) 360 { 361 struct rk_i2s_dev *i2s = to_info(dai); 362 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 363 unsigned int val = 0; 364 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck; 365 366 if (i2s->is_master_mode) { 367 mclk_rate = clk_get_rate(i2s->mclk); 368 bclk_rate = i2s->bclk_ratio * params_rate(params); 369 if (!bclk_rate) 370 return -EINVAL; 371 372 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate); 373 div_lrck = bclk_rate / params_rate(params); 374 regmap_update_bits(i2s->regmap, I2S_CKR, 375 I2S_CKR_MDIV_MASK, 376 I2S_CKR_MDIV(div_bclk)); 377 378 regmap_update_bits(i2s->regmap, I2S_CKR, 379 I2S_CKR_TSD_MASK | 380 I2S_CKR_RSD_MASK, 381 I2S_CKR_TSD(div_lrck) | 382 I2S_CKR_RSD(div_lrck)); 383 } 384 385 switch (params_format(params)) { 386 case SNDRV_PCM_FORMAT_S8: 387 val |= I2S_TXCR_VDW(8); 388 break; 389 case SNDRV_PCM_FORMAT_S16_LE: 390 val |= I2S_TXCR_VDW(16); 391 break; 392 case SNDRV_PCM_FORMAT_S20_3LE: 393 val |= I2S_TXCR_VDW(20); 394 break; 395 case SNDRV_PCM_FORMAT_S24_LE: 396 val |= I2S_TXCR_VDW(24); 397 break; 398 case SNDRV_PCM_FORMAT_S32_LE: 399 val |= I2S_TXCR_VDW(32); 400 break; 401 default: 402 return -EINVAL; 403 } 404 405 switch (params_channels(params)) { 406 case 8: 407 val |= I2S_CHN_8; 408 break; 409 case 6: 410 val |= I2S_CHN_6; 411 break; 412 case 4: 413 val |= I2S_CHN_4; 414 break; 415 case 2: 416 val |= I2S_CHN_2; 417 break; 418 default: 419 dev_err(i2s->dev, "invalid channel: %d\n", 420 params_channels(params)); 421 return -EINVAL; 422 } 423 424 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 425 regmap_update_bits(i2s->regmap, I2S_RXCR, 426 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 427 val); 428 else 429 regmap_update_bits(i2s->regmap, I2S_TXCR, 430 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 431 val); 432 433 if (!IS_ERR(i2s->grf) && i2s->pins) { 434 regmap_read(i2s->regmap, I2S_TXCR, &val); 435 val &= I2S_TXCR_CSR_MASK; 436 437 switch (val) { 438 case I2S_CHN_4: 439 val = I2S_IO_4CH_OUT_6CH_IN; 440 break; 441 case I2S_CHN_6: 442 val = I2S_IO_6CH_OUT_4CH_IN; 443 break; 444 case I2S_CHN_8: 445 val = I2S_IO_8CH_OUT_2CH_IN; 446 break; 447 default: 448 val = I2S_IO_2CH_OUT_8CH_IN; 449 break; 450 } 451 452 val <<= i2s->pins->shift; 453 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16; 454 regmap_write(i2s->grf, i2s->pins->reg_offset, val); 455 } 456 457 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK, 458 I2S_DMACR_TDL(16)); 459 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, 460 I2S_DMACR_RDL(16)); 461 462 val = I2S_CKR_TRCM_TXRX; 463 if (dai->driver->symmetric_rate && rtd->dai_link->symmetric_rate) 464 val = I2S_CKR_TRCM_TXONLY; 465 466 regmap_update_bits(i2s->regmap, I2S_CKR, 467 I2S_CKR_TRCM_MASK, 468 val); 469 return 0; 470 } 471 472 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, 473 int cmd, struct snd_soc_dai *dai) 474 { 475 struct rk_i2s_dev *i2s = to_info(dai); 476 int ret = 0; 477 478 switch (cmd) { 479 case SNDRV_PCM_TRIGGER_START: 480 case SNDRV_PCM_TRIGGER_RESUME: 481 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 482 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 483 ret = rockchip_snd_rxctrl(i2s, 1); 484 else 485 ret = rockchip_snd_txctrl(i2s, 1); 486 if (ret < 0) 487 return ret; 488 i2s_pinctrl_select_bclk_on(i2s); 489 break; 490 case SNDRV_PCM_TRIGGER_SUSPEND: 491 case SNDRV_PCM_TRIGGER_STOP: 492 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 493 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 494 if (!i2s->tx_start) 495 i2s_pinctrl_select_bclk_off(i2s); 496 ret = rockchip_snd_rxctrl(i2s, 0); 497 } else { 498 if (!i2s->rx_start) 499 i2s_pinctrl_select_bclk_off(i2s); 500 ret = rockchip_snd_txctrl(i2s, 0); 501 } 502 break; 503 default: 504 ret = -EINVAL; 505 break; 506 } 507 508 return ret; 509 } 510 511 static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai, 512 unsigned int ratio) 513 { 514 struct rk_i2s_dev *i2s = to_info(dai); 515 516 i2s->bclk_ratio = ratio; 517 518 return 0; 519 } 520 521 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, 522 unsigned int freq, int dir) 523 { 524 struct rk_i2s_dev *i2s = to_info(cpu_dai); 525 int ret; 526 527 if (freq == 0) 528 return 0; 529 530 ret = clk_set_rate(i2s->mclk, freq); 531 if (ret) 532 dev_err(i2s->dev, "Fail to set mclk %d\n", ret); 533 534 return ret; 535 } 536 537 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai) 538 { 539 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); 540 541 snd_soc_dai_init_dma_data(dai, 542 i2s->has_playback ? &i2s->playback_dma_data : NULL, 543 i2s->has_capture ? &i2s->capture_dma_data : NULL); 544 545 return 0; 546 } 547 548 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = { 549 .hw_params = rockchip_i2s_hw_params, 550 .set_bclk_ratio = rockchip_i2s_set_bclk_ratio, 551 .set_sysclk = rockchip_i2s_set_sysclk, 552 .set_fmt = rockchip_i2s_set_fmt, 553 .trigger = rockchip_i2s_trigger, 554 }; 555 556 static struct snd_soc_dai_driver rockchip_i2s_dai = { 557 .probe = rockchip_i2s_dai_probe, 558 .ops = &rockchip_i2s_dai_ops, 559 .symmetric_rate = 1, 560 }; 561 562 static const struct snd_soc_component_driver rockchip_i2s_component = { 563 .name = DRV_NAME, 564 }; 565 566 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg) 567 { 568 switch (reg) { 569 case I2S_TXCR: 570 case I2S_RXCR: 571 case I2S_CKR: 572 case I2S_DMACR: 573 case I2S_INTCR: 574 case I2S_XFER: 575 case I2S_CLR: 576 case I2S_TXDR: 577 return true; 578 default: 579 return false; 580 } 581 } 582 583 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg) 584 { 585 switch (reg) { 586 case I2S_TXCR: 587 case I2S_RXCR: 588 case I2S_CKR: 589 case I2S_DMACR: 590 case I2S_INTCR: 591 case I2S_XFER: 592 case I2S_CLR: 593 case I2S_TXDR: 594 case I2S_RXDR: 595 case I2S_FIFOLR: 596 case I2S_INTSR: 597 return true; 598 default: 599 return false; 600 } 601 } 602 603 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg) 604 { 605 switch (reg) { 606 case I2S_INTSR: 607 case I2S_CLR: 608 case I2S_FIFOLR: 609 case I2S_TXDR: 610 case I2S_RXDR: 611 return true; 612 default: 613 return false; 614 } 615 } 616 617 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg) 618 { 619 switch (reg) { 620 case I2S_RXDR: 621 return true; 622 default: 623 return false; 624 } 625 } 626 627 static const struct reg_default rockchip_i2s_reg_defaults[] = { 628 {0x00, 0x0000000f}, 629 {0x04, 0x0000000f}, 630 {0x08, 0x00071f1f}, 631 {0x10, 0x001f0000}, 632 {0x14, 0x01f00000}, 633 }; 634 635 static const struct regmap_config rockchip_i2s_regmap_config = { 636 .reg_bits = 32, 637 .reg_stride = 4, 638 .val_bits = 32, 639 .max_register = I2S_RXDR, 640 .reg_defaults = rockchip_i2s_reg_defaults, 641 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults), 642 .writeable_reg = rockchip_i2s_wr_reg, 643 .readable_reg = rockchip_i2s_rd_reg, 644 .volatile_reg = rockchip_i2s_volatile_reg, 645 .precious_reg = rockchip_i2s_precious_reg, 646 .cache_type = REGCACHE_FLAT, 647 }; 648 649 static const struct rk_i2s_pins rk3399_i2s_pins = { 650 .reg_offset = 0xe220, 651 .shift = 11, 652 }; 653 654 static const struct of_device_id rockchip_i2s_match[] __maybe_unused = { 655 { .compatible = "rockchip,px30-i2s", }, 656 { .compatible = "rockchip,rk1808-i2s", }, 657 { .compatible = "rockchip,rk3036-i2s", }, 658 { .compatible = "rockchip,rk3066-i2s", }, 659 { .compatible = "rockchip,rk3128-i2s", }, 660 { .compatible = "rockchip,rk3188-i2s", }, 661 { .compatible = "rockchip,rk3228-i2s", }, 662 { .compatible = "rockchip,rk3288-i2s", }, 663 { .compatible = "rockchip,rk3308-i2s", }, 664 { .compatible = "rockchip,rk3328-i2s", }, 665 { .compatible = "rockchip,rk3366-i2s", }, 666 { .compatible = "rockchip,rk3368-i2s", }, 667 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins }, 668 { .compatible = "rockchip,rv1126-i2s", }, 669 {}, 670 }; 671 672 static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res, 673 struct snd_soc_dai_driver **dp) 674 { 675 struct device_node *node = i2s->dev->of_node; 676 struct snd_soc_dai_driver *dai; 677 struct property *dma_names; 678 const char *dma_name; 679 unsigned int val; 680 681 of_property_for_each_string(node, "dma-names", dma_names, dma_name) { 682 if (!strcmp(dma_name, "tx")) 683 i2s->has_playback = true; 684 if (!strcmp(dma_name, "rx")) 685 i2s->has_capture = true; 686 } 687 688 dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai, 689 sizeof(*dai), GFP_KERNEL); 690 if (!dai) 691 return -ENOMEM; 692 693 if (i2s->has_playback) { 694 dai->playback.stream_name = "Playback"; 695 dai->playback.channels_min = 2; 696 dai->playback.channels_max = 8; 697 dai->playback.rates = SNDRV_PCM_RATE_8000_192000; 698 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 | 699 SNDRV_PCM_FMTBIT_S16_LE | 700 SNDRV_PCM_FMTBIT_S20_3LE | 701 SNDRV_PCM_FMTBIT_S24_LE | 702 SNDRV_PCM_FMTBIT_S32_LE; 703 704 i2s->playback_dma_data.addr = res->start + I2S_TXDR; 705 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 706 i2s->playback_dma_data.maxburst = 8; 707 708 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) { 709 if (val >= 2 && val <= 8) 710 dai->playback.channels_max = val; 711 } 712 } 713 714 if (i2s->has_capture) { 715 dai->capture.stream_name = "Capture"; 716 dai->capture.channels_min = 2; 717 dai->capture.channels_max = 8; 718 dai->capture.rates = SNDRV_PCM_RATE_8000_192000; 719 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 | 720 SNDRV_PCM_FMTBIT_S16_LE | 721 SNDRV_PCM_FMTBIT_S20_3LE | 722 SNDRV_PCM_FMTBIT_S24_LE | 723 SNDRV_PCM_FMTBIT_S32_LE; 724 725 i2s->capture_dma_data.addr = res->start + I2S_RXDR; 726 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 727 i2s->capture_dma_data.maxburst = 8; 728 729 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) { 730 if (val >= 2 && val <= 8) 731 dai->capture.channels_max = val; 732 } 733 } 734 735 if (dp) 736 *dp = dai; 737 738 return 0; 739 } 740 741 static int rockchip_i2s_probe(struct platform_device *pdev) 742 { 743 struct device_node *node = pdev->dev.of_node; 744 const struct of_device_id *of_id; 745 struct rk_i2s_dev *i2s; 746 struct snd_soc_dai_driver *dai; 747 struct resource *res; 748 void __iomem *regs; 749 int ret; 750 751 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 752 if (!i2s) 753 return -ENOMEM; 754 755 spin_lock_init(&i2s->lock); 756 i2s->dev = &pdev->dev; 757 758 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf"); 759 if (!IS_ERR(i2s->grf)) { 760 of_id = of_match_device(rockchip_i2s_match, &pdev->dev); 761 if (!of_id || !of_id->data) 762 return -EINVAL; 763 764 i2s->pins = of_id->data; 765 } 766 767 /* try to prepare related clocks */ 768 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk"); 769 if (IS_ERR(i2s->hclk)) { 770 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n"); 771 return PTR_ERR(i2s->hclk); 772 } 773 ret = clk_prepare_enable(i2s->hclk); 774 if (ret) { 775 dev_err(i2s->dev, "hclock enable failed %d\n", ret); 776 return ret; 777 } 778 779 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk"); 780 if (IS_ERR(i2s->mclk)) { 781 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n"); 782 ret = PTR_ERR(i2s->mclk); 783 goto err_clk; 784 } 785 786 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 787 if (IS_ERR(regs)) { 788 ret = PTR_ERR(regs); 789 goto err_clk; 790 } 791 792 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 793 &rockchip_i2s_regmap_config); 794 if (IS_ERR(i2s->regmap)) { 795 dev_err(&pdev->dev, 796 "Failed to initialise managed register map\n"); 797 ret = PTR_ERR(i2s->regmap); 798 goto err_clk; 799 } 800 801 i2s->bclk_ratio = 64; 802 i2s->pinctrl = devm_pinctrl_get(&pdev->dev); 803 804 if (!IS_ERR(i2s->pinctrl)) { 805 i2s->bclk_on = pinctrl_lookup_state(i2s->pinctrl, "bclk_on"); 806 if (!IS_ERR_OR_NULL(i2s->bclk_on)) { 807 i2s->bclk_off = pinctrl_lookup_state(i2s->pinctrl, "bclk_off"); 808 if (IS_ERR_OR_NULL(i2s->bclk_off)) { 809 dev_err(&pdev->dev, "failed to find i2s bclk_off\n"); 810 ret = -EINVAL; 811 goto err_clk; 812 } 813 } 814 } else { 815 dev_err(&pdev->dev, "failed to find i2s pinctrl\n"); 816 } 817 818 i2s_pinctrl_select_bclk_off(i2s); 819 820 i2s->playback_dma_data.addr = res->start + I2S_TXDR; 821 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 822 i2s->playback_dma_data.maxburst = 4; 823 824 i2s->capture_dma_data.addr = res->start + I2S_RXDR; 825 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 826 i2s->capture_dma_data.maxburst = 4; 827 828 dev_set_drvdata(&pdev->dev, i2s); 829 830 pm_runtime_enable(&pdev->dev); 831 if (!pm_runtime_enabled(&pdev->dev)) { 832 ret = i2s_runtime_resume(&pdev->dev); 833 if (ret) 834 goto err_pm_disable; 835 } 836 837 ret = rockchip_i2s_init_dai(i2s, res, &dai); 838 if (ret) 839 goto err_pm_disable; 840 841 ret = devm_snd_soc_register_component(&pdev->dev, 842 &rockchip_i2s_component, 843 dai, 1); 844 845 if (ret) { 846 dev_err(&pdev->dev, "Could not register DAI\n"); 847 goto err_suspend; 848 } 849 850 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 851 if (ret) { 852 dev_err(&pdev->dev, "Could not register PCM\n"); 853 goto err_suspend; 854 } 855 856 return 0; 857 858 err_suspend: 859 if (!pm_runtime_status_suspended(&pdev->dev)) 860 i2s_runtime_suspend(&pdev->dev); 861 err_pm_disable: 862 pm_runtime_disable(&pdev->dev); 863 err_clk: 864 clk_disable_unprepare(i2s->hclk); 865 return ret; 866 } 867 868 static int rockchip_i2s_remove(struct platform_device *pdev) 869 { 870 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev); 871 872 pm_runtime_disable(&pdev->dev); 873 if (!pm_runtime_status_suspended(&pdev->dev)) 874 i2s_runtime_suspend(&pdev->dev); 875 876 clk_disable_unprepare(i2s->hclk); 877 878 return 0; 879 } 880 881 static const struct dev_pm_ops rockchip_i2s_pm_ops = { 882 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume, 883 NULL) 884 }; 885 886 static struct platform_driver rockchip_i2s_driver = { 887 .probe = rockchip_i2s_probe, 888 .remove = rockchip_i2s_remove, 889 .driver = { 890 .name = DRV_NAME, 891 .of_match_table = of_match_ptr(rockchip_i2s_match), 892 .pm = &rockchip_i2s_pm_ops, 893 }, 894 }; 895 module_platform_driver(rockchip_i2s_driver); 896 897 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface"); 898 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>"); 899 MODULE_LICENSE("GPL v2"); 900 MODULE_ALIAS("platform:" DRV_NAME); 901 MODULE_DEVICE_TABLE(of, rockchip_i2s_match); 902