1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __AUDIOREACH_H__ 4 #define __AUDIOREACH_H__ 5 #include <linux/types.h> 6 #include <linux/soc/qcom/apr.h> 7 #include <sound/soc.h> 8 struct q6apm; 9 struct q6apm_graph; 10 11 /* Module IDs */ 12 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 13 #define MODULE_ID_RD_SHARED_MEM_EP 0x07001001 14 #define MODULE_ID_GAIN 0x07001002 15 #define MODULE_ID_PCM_CNV 0x07001003 16 #define MODULE_ID_PCM_ENC 0x07001004 17 #define MODULE_ID_PCM_DEC 0x07001005 18 #define MODULE_ID_PLACEHOLDER_ENCODER 0x07001008 19 #define MODULE_ID_PLACEHOLDER_DECODER 0x07001009 20 #define MODULE_ID_SAL 0x07001010 21 #define MODULE_ID_MFC 0x07001015 22 #define MODULE_ID_CODEC_DMA_SINK 0x07001023 23 #define MODULE_ID_CODEC_DMA_SOURCE 0x07001024 24 #define MODULE_ID_I2S_SINK 0x0700100A 25 #define MODULE_ID_I2S_SOURCE 0x0700100B 26 #define MODULE_ID_DATA_LOGGING 0x0700101A 27 #define MODULE_ID_AAC_DEC 0x0700101F 28 #define MODULE_ID_FLAC_DEC 0x0700102F 29 #define MODULE_ID_MP3_DECODE 0x0700103B 30 #define MODULE_ID_DISPLAY_PORT_SINK 0x07001069 31 32 #define APM_CMD_GET_SPF_STATE 0x01001021 33 #define APM_CMD_RSP_GET_SPF_STATE 0x02001007 34 35 #define APM_MODULE_INSTANCE_ID 0x00000001 36 #define PRM_MODULE_INSTANCE_ID 0x00000002 37 #define AMDB_MODULE_INSTANCE_ID 0x00000003 38 #define VCPM_MODULE_INSTANCE_ID 0x00000004 39 #define AR_MODULE_INSTANCE_ID_START 0x00006000 40 #define AR_MODULE_INSTANCE_ID_END 0x00007000 41 #define AR_MODULE_DYNAMIC_INSTANCE_ID_START 0x00007000 42 #define AR_MODULE_DYNAMIC_INSTANCE_ID_END 0x00008000 43 #define AR_CONT_INSTANCE_ID_START 0x00005000 44 #define AR_CONT_INSTANCE_ID_END 0x00006000 45 #define AR_SG_INSTANCE_ID_START 0x00004000 46 47 #define APM_CMD_GRAPH_OPEN 0x01001000 48 #define APM_CMD_GRAPH_PREPARE 0x01001001 49 #define APM_CMD_GRAPH_START 0x01001002 50 #define APM_CMD_GRAPH_STOP 0x01001003 51 #define APM_CMD_GRAPH_CLOSE 0x01001004 52 #define APM_CMD_GRAPH_FLUSH 0x01001005 53 #define APM_CMD_SET_CFG 0x01001006 54 #define APM_CMD_GET_CFG 0x01001007 55 #define APM_CMD_SHARED_MEM_MAP_REGIONS 0x0100100C 56 #define APM_CMD_SHARED_MEM_UNMAP_REGIONS 0x0100100D 57 #define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS 0x02001001 58 #define APM_CMD_RSP_GET_CFG 0x02001000 59 #define APM_CMD_CLOSE_ALL 0x01001013 60 #define APM_CMD_REGISTER_SHARED_CFG 0x0100100A 61 62 #define APM_MEMORY_MAP_SHMEM8_4K_POOL 3 63 64 struct apm_cmd_shared_mem_map_regions { 65 uint16_t mem_pool_id; 66 uint16_t num_regions; 67 uint32_t property_flag; 68 } __packed; 69 70 struct apm_shared_map_region_payload { 71 uint32_t shm_addr_lsw; 72 uint32_t shm_addr_msw; 73 uint32_t mem_size_bytes; 74 } __packed; 75 76 struct apm_cmd_shared_mem_unmap_regions { 77 uint32_t mem_map_handle; 78 } __packed; 79 80 struct apm_cmd_rsp_shared_mem_map_regions { 81 uint32_t mem_map_handle; 82 } __packed; 83 84 /* APM module */ 85 #define APM_PARAM_ID_SUB_GRAPH_LIST 0x08001005 86 87 #define APM_PARAM_ID_MODULE_LIST 0x08001002 88 89 struct apm_param_id_modules_list { 90 uint32_t num_modules_list; 91 } __packed; 92 93 #define APM_PARAM_ID_MODULE_PROP 0x08001003 94 95 struct apm_param_id_module_prop { 96 uint32_t num_modules_prop_cfg; 97 } __packed; 98 99 struct apm_module_prop_cfg { 100 uint32_t instance_id; 101 uint32_t num_props; 102 } __packed; 103 104 #define APM_PARAM_ID_MODULE_CONN 0x08001004 105 106 struct apm_param_id_module_conn { 107 uint32_t num_connections; 108 } __packed; 109 110 struct apm_module_conn_obj { 111 uint32_t src_mod_inst_id; 112 uint32_t src_mod_op_port_id; 113 uint32_t dst_mod_inst_id; 114 uint32_t dst_mod_ip_port_id; 115 } __packed; 116 117 #define APM_PARAM_ID_GAIN 0x08001006 118 119 struct param_id_gain_cfg { 120 uint16_t gain; 121 uint16_t reserved; 122 } __packed; 123 124 #define PARAM_ID_PCM_OUTPUT_FORMAT_CFG 0x08001008 125 126 struct param_id_pcm_output_format_cfg { 127 uint32_t data_format; 128 uint32_t fmt_id; 129 uint32_t payload_size; 130 } __packed; 131 132 struct payload_pcm_output_format_cfg { 133 uint16_t bit_width; 134 uint16_t alignment; 135 uint16_t bits_per_sample; 136 uint16_t q_factor; 137 uint16_t endianness; 138 uint16_t interleaved; 139 uint16_t reserved; 140 uint16_t num_channels; 141 uint8_t channel_mapping[]; 142 } __packed; 143 144 #define PARAM_ID_ENC_BITRATE 0x08001052 145 146 struct param_id_enc_bitrate_param { 147 uint32_t bitrate; 148 } __packed; 149 150 #define DATA_FORMAT_FIXED_POINT 1 151 #define DATA_FORMAT_GENERIC_COMPRESSED 5 152 #define DATA_FORMAT_RAW_COMPRESSED 6 153 #define PCM_LSB_ALIGNED 1 154 #define PCM_MSB_ALIGNED 2 155 #define PCM_LITTLE_ENDIAN 1 156 #define PCM_BIT_ENDIAN 2 157 158 #define MEDIA_FMT_ID_PCM 0x09001000 159 #define MEDIA_FMT_ID_MP3 0x09001009 160 #define PCM_CHANNEL_L 1 161 #define PCM_CHANNEL_R 2 162 #define SAMPLE_RATE_48K 48000 163 #define BIT_WIDTH_16 16 164 165 #define APM_PARAM_ID_PROP_PORT_INFO 0x08001015 166 167 struct apm_modules_prop_info { 168 uint32_t max_ip_port; 169 uint32_t max_op_port; 170 } __packed; 171 172 /* Shared memory module */ 173 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER 0x04001000 174 #define WR_SH_MEM_EP_TIMESTAMP_VALID_FLAG BIT(31) 175 #define WR_SH_MEM_EP_LAST_BUFFER_FLAG BIT(30) 176 #define WR_SH_MEM_EP_TS_CONTINUE_FLAG BIT(29) 177 #define WR_SH_MEM_EP_EOF_FLAG BIT(4) 178 179 struct apm_data_cmd_wr_sh_mem_ep_data_buffer { 180 uint32_t buf_addr_lsw; 181 uint32_t buf_addr_msw; 182 uint32_t mem_map_handle; 183 uint32_t buf_size; 184 uint32_t timestamp_lsw; 185 uint32_t timestamp_msw; 186 uint32_t flags; 187 } __packed; 188 189 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2 0x0400100A 190 191 struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 { 192 uint32_t buf_addr_lsw; 193 uint32_t buf_addr_msw; 194 uint32_t mem_map_handle; 195 uint32_t buf_size; 196 uint32_t timestamp_lsw; 197 uint32_t timestamp_msw; 198 uint32_t flags; 199 uint32_t md_addr_lsw; 200 uint32_t md_addr_msw; 201 uint32_t md_map_handle; 202 uint32_t md_buf_size; 203 } __packed; 204 205 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE 0x05001000 206 207 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done { 208 uint32_t buf_addr_lsw; 209 uint32_t buf_addr_msw; 210 uint32_t mem_map_handle; 211 uint32_t status; 212 213 } __packed; 214 215 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2 0x05001004 216 217 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 { 218 uint32_t buf_addr_lsw; 219 uint32_t buf_addr_msw; 220 uint32_t mem_map_handle; 221 uint32_t status; 222 uint32_t md_buf_addr_lsw; 223 uint32_t md_buf_addr_msw; 224 uint32_t md_mem_map_handle; 225 uint32_t md_status; 226 } __packed; 227 228 #define PARAM_ID_MEDIA_FORMAT 0x0800100C 229 #define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT 0x04001001 230 231 struct apm_media_format { 232 uint32_t data_format; 233 uint32_t fmt_id; 234 uint32_t payload_size; 235 } __packed; 236 237 #define MEDIA_FMT_ID_FLAC 0x09001004 238 239 struct payload_media_fmt_flac_t { 240 uint16_t num_channels; 241 uint16_t sample_size; 242 uint16_t min_blk_size; 243 uint16_t max_blk_size; 244 uint32_t sample_rate; 245 uint32_t min_frame_size; 246 uint32_t max_frame_size; 247 } __packed; 248 249 #define MEDIA_FMT_ID_AAC 0x09001001 250 251 struct payload_media_fmt_aac_t { 252 uint16_t aac_fmt_flag; 253 uint16_t audio_obj_type; 254 uint16_t num_channels; 255 uint16_t total_size_of_PCE_bits; 256 uint32_t sample_rate; 257 } __packed; 258 259 #define DATA_CMD_WR_SH_MEM_EP_EOS 0x04001002 260 #define WR_SH_MEM_EP_EOS_POLICY_LAST 1 261 #define WR_SH_MEM_EP_EOS_POLICY_EACH 2 262 263 struct data_cmd_wr_sh_mem_ep_eos { 264 uint32_t policy; 265 266 } __packed; 267 268 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER 0x04001003 269 270 struct data_cmd_rd_sh_mem_ep_data_buffer { 271 uint32_t buf_addr_lsw; 272 uint32_t buf_addr_msw; 273 uint32_t mem_map_handle; 274 uint32_t buf_size; 275 } __packed; 276 277 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER 0x05001002 278 279 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done { 280 uint32_t status; 281 uint32_t buf_addr_lsw; 282 uint32_t buf_addr_msw; 283 uint32_t mem_map_handle; 284 uint32_t data_size; 285 uint32_t offset; 286 uint32_t timestamp_lsw; 287 uint32_t timestamp_msw; 288 uint32_t flags; 289 uint32_t num_frames; 290 } __packed; 291 292 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2 0x0400100B 293 294 struct data_cmd_rd_sh_mem_ep_data_buffer_v2 { 295 uint32_t buf_addr_lsw; 296 uint32_t buf_addr_msw; 297 uint32_t mem_map_handle; 298 uint32_t buf_size; 299 uint32_t md_buf_addr_lsw; 300 uint32_t md_buf_addr_msw; 301 uint32_t md_mem_map_handle; 302 uint32_t md_buf_size; 303 } __packed; 304 305 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2 0x05001005 306 307 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 { 308 uint32_t status; 309 uint32_t buf_addr_lsw; 310 uint32_t buf_addr_msw; 311 uint32_t mem_map_handle; 312 uint32_t data_size; 313 uint32_t offset; 314 uint32_t timestamp_lsw; 315 uint32_t timestamp_msw; 316 uint32_t flags; 317 uint32_t num_frames; 318 uint32_t md_status; 319 uint32_t md_buf_addr_lsw; 320 uint32_t md_buf_addr_msw; 321 uint32_t md_mem_map_handle; 322 uint32_t md_size; 323 } __packed; 324 325 #define PARAM_ID_RD_SH_MEM_CFG 0x08001007 326 327 struct param_id_rd_sh_mem_cfg { 328 uint32_t num_frames_per_buffer; 329 uint32_t metadata_control_flags; 330 331 } __packed; 332 333 #define DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED 0x05001001 334 335 struct data_cmd_wr_sh_mem_ep_eos_rendered { 336 uint32_t module_instance_id; 337 uint32_t render_status; 338 } __packed; 339 340 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 341 342 struct apm_cmd_header { 343 uint32_t payload_address_lsw; 344 uint32_t payload_address_msw; 345 uint32_t mem_map_handle; 346 uint32_t payload_size; 347 } __packed; 348 349 #define APM_CMD_HDR_SIZE sizeof(struct apm_cmd_header) 350 351 struct apm_module_param_data { 352 uint32_t module_instance_id; 353 uint32_t param_id; 354 uint32_t param_size; 355 uint32_t error_code; 356 } __packed; 357 358 #define APM_MODULE_PARAM_DATA_SIZE sizeof(struct apm_module_param_data) 359 360 struct apm_module_param_shared_data { 361 uint32_t param_id; 362 uint32_t param_size; 363 } __packed; 364 365 struct apm_prop_data { 366 uint32_t prop_id; 367 uint32_t prop_size; 368 } __packed; 369 370 /* Sub-Graph Properties */ 371 #define APM_PARAM_ID_SUB_GRAPH_CONFIG 0x08001001 372 373 struct apm_param_id_sub_graph_cfg { 374 uint32_t num_sub_graphs; 375 } __packed; 376 377 struct apm_sub_graph_cfg { 378 uint32_t sub_graph_id; 379 uint32_t num_sub_graph_prop; 380 } __packed; 381 382 #define APM_SUB_GRAPH_PROP_ID_PERF_MODE 0x0800100E 383 384 struct apm_sg_prop_id_perf_mode { 385 uint32_t perf_mode; 386 } __packed; 387 388 #define APM_SG_PROP_ID_PERF_MODE_SIZE 4 389 390 #define APM_SUB_GRAPH_PROP_ID_DIRECTION 0x0800100F 391 392 struct apm_sg_prop_id_direction { 393 uint32_t direction; 394 } __packed; 395 396 #define APM_SG_PROP_ID_DIR_SIZE 4 397 398 #define APM_SUB_GRAPH_PROP_ID_SCENARIO_ID 0x08001010 399 #define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1 400 #define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2 401 #define APM_SUB_GRAPH_SID_AUDIO_VOICE_CALL 0x3 402 403 struct apm_sg_prop_id_scenario_id { 404 uint32_t scenario_id; 405 } __packed; 406 407 #define APM_SG_PROP_ID_SID_SIZE 4 408 /* container api */ 409 #define APM_PARAM_ID_CONTAINER_CONFIG 0x08001000 410 411 struct apm_param_id_container_cfg { 412 uint32_t num_containers; 413 } __packed; 414 415 struct apm_container_cfg { 416 uint32_t container_id; 417 uint32_t num_prop; 418 } __packed; 419 420 struct apm_cont_capability { 421 uint32_t capability_id; 422 } __packed; 423 424 #define APM_CONTAINER_PROP_ID_CAPABILITY_LIST 0x08001011 425 #define APM_CONTAINER_PROP_ID_CAPABILITY_SIZE 8 426 427 #define APM_PROP_ID_INVALID 0x0 428 #define APM_CONTAINER_CAP_ID_PP 0x1 429 #define APM_CONTAINER_CAP_ID_PP 0x1 430 431 struct apm_cont_prop_id_cap_list { 432 uint32_t num_capability_id; 433 } __packed; 434 435 #define APM_CONTAINER_PROP_ID_GRAPH_POS 0x08001012 436 437 struct apm_cont_prop_id_graph_pos { 438 uint32_t graph_pos; 439 } __packed; 440 441 #define APM_CONTAINER_PROP_ID_STACK_SIZE 0x08001013 442 443 struct apm_cont_prop_id_stack_size { 444 uint32_t stack_size; 445 } __packed; 446 447 #define APM_CONTAINER_PROP_ID_PROC_DOMAIN 0x08001014 448 449 struct apm_cont_prop_id_domain { 450 uint32_t proc_domain; 451 } __packed; 452 453 #define CONFIG_I2S_WS_SRC_EXTERNAL 0x0 454 #define CONFIG_I2S_WS_SRC_INTERNAL 0x1 455 456 #define PARAM_ID_I2S_INTF_CFG 0x08001019 457 struct param_id_i2s_intf_cfg { 458 uint32_t lpaif_type; 459 uint32_t intf_idx; 460 uint16_t sd_line_idx; 461 uint16_t ws_src; 462 } __packed; 463 464 #define I2S_INTF_TYPE_PRIMARY 0 465 #define I2S_INTF_TYPE_SECOINDARY 1 466 #define I2S_INTF_TYPE_TERTINARY 2 467 #define I2S_INTF_TYPE_QUATERNARY 3 468 #define I2S_INTF_TYPE_QUINARY 4 469 #define I2S_SD0 1 470 #define I2S_SD1 2 471 #define I2S_SD2 3 472 #define I2S_SD3 4 473 474 #define PORT_ID_I2S_INPUT 2 475 #define PORT_ID_I2S_OUPUT 1 476 #define I2S_STACK_SIZE 2048 477 478 #define PARAM_ID_DISPLAY_PORT_INTF_CFG 0x08001154 479 480 struct param_id_display_port_intf_cfg { 481 uint32_t channel_allocation; 482 /* Multi-Steam Transport index */ 483 uint32_t mst_idx; 484 uint32_t dptx_idx; 485 } __packed; 486 487 #define PARAM_ID_HW_EP_MF_CFG 0x08001017 488 struct param_id_hw_ep_mf { 489 uint32_t sample_rate; 490 uint16_t bit_width; 491 uint16_t num_channels; 492 uint32_t data_format; 493 } __packed; 494 495 #define PARAM_ID_HW_EP_FRAME_SIZE_FACTOR 0x08001018 496 497 struct param_id_fram_size_factor { 498 uint32_t frame_size_factor; 499 } __packed; 500 501 #define APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID 0x080010CB 502 503 struct apm_cont_prop_id_parent_container { 504 uint32_t parent_container_id; 505 } __packed; 506 507 #define APM_CONTAINER_PROP_ID_HEAP_ID 0x08001174 508 #define APM_CONT_HEAP_DEFAULT 0x1 509 #define APM_CONT_HEAP_LOW_POWER 0x2 510 511 struct apm_cont_prop_id_headp_id { 512 uint32_t heap_id; 513 } __packed; 514 515 struct apm_modules_list { 516 uint32_t sub_graph_id; 517 uint32_t container_id; 518 uint32_t num_modules; 519 } __packed; 520 521 struct apm_module_obj { 522 uint32_t module_id; 523 uint32_t instance_id; 524 } __packed; 525 526 #define APM_MODULE_PROP_ID_PORT_INFO 0x08001015 527 #define APM_MODULE_PROP_ID_PORT_INFO_SZ 8 528 struct apm_module_prop_id_port_info { 529 uint32_t max_ip_port; 530 uint32_t max_op_port; 531 } __packed; 532 533 #define DATA_LOGGING_MAX_INPUT_PORTS 0x1 534 #define DATA_LOGGING_MAX_OUTPUT_PORTS 0x1 535 #define DATA_LOGGING_STACK_SIZE 2048 536 #define PARAM_ID_DATA_LOGGING_CONFIG 0x08001031 537 538 struct data_logging_config { 539 uint32_t log_code; 540 uint32_t log_tap_point_id; 541 uint32_t mode; 542 } __packed; 543 544 #define PARAM_ID_SAL_OUTPUT_CFG 0x08001016 545 struct param_id_sal_output_config { 546 uint32_t bits_per_sample; 547 } __packed; 548 549 #define PARAM_ID_SAL_LIMITER_ENABLE 0x0800101E 550 struct param_id_sal_limiter_enable { 551 uint32_t enable_lim; 552 } __packed; 553 554 #define PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT 0x08001024 555 556 struct param_id_mfc_media_format { 557 uint32_t sample_rate; 558 uint16_t bit_width; 559 uint16_t num_channels; 560 uint16_t channel_mapping[]; 561 } __packed; 562 563 struct media_format { 564 uint32_t data_format; 565 uint32_t fmt_id; 566 uint32_t payload_size; 567 } __packed; 568 569 struct payload_media_fmt_pcm { 570 uint32_t sample_rate; 571 uint16_t bit_width; 572 uint16_t alignment; 573 uint16_t bits_per_sample; 574 uint16_t q_factor; 575 uint16_t endianness; 576 uint16_t num_channels; 577 uint8_t channel_mapping[]; 578 } __packed; 579 580 #define PARAM_ID_MODULE_ENABLE 0x08001026 581 struct param_id_module_enable { 582 uint32_t enable; 583 } __packed; 584 585 #define PARAM_ID_CODEC_DMA_INTF_CFG 0x08001063 586 587 struct param_id_codec_dma_intf_cfg { 588 /* 1 - RXTX 589 * 2 - WSA 590 * 3 - VA 591 * 4 - AXI 592 */ 593 uint32_t lpaif_type; 594 /* 595 * RX0 | TX0 = 1 596 * RX1 | TX1 = 2 597 * RX2 | TX2 = 3... so on 598 */ 599 uint32_t intf_index; 600 uint32_t active_channels_mask; 601 } __packed; 602 603 struct audio_hw_clk_cfg { 604 uint32_t clock_id; 605 uint32_t clock_freq; 606 uint32_t clock_attri; 607 uint32_t clock_root; 608 } __packed; 609 610 struct audio_hw_clk_rel_cfg { 611 uint32_t clock_id; 612 } __packed; 613 614 #define PARAM_ID_HW_EP_POWER_MODE_CFG 0x8001176 615 #define AR_HW_EP_POWER_MODE_0 0 /* default */ 616 #define AR_HW_EP_POWER_MODE_1 1 /* XO Shutdown allowed */ 617 #define AR_HW_EP_POWER_MODE_2 2 /* XO Shutdown not allowed */ 618 619 struct param_id_hw_ep_power_mode_cfg { 620 uint32_t power_mode; 621 } __packed; 622 623 #define PARAM_ID_HW_EP_DMA_DATA_ALIGN 0x08001233 624 #define AR_HW_EP_DMA_DATA_ALIGN_MSB 0 625 #define AR_HW_EP_DMA_DATA_ALIGN_LSB 1 626 #define AR_PCM_MAX_NUM_CHANNEL 8 627 628 struct param_id_hw_ep_dma_data_align { 629 uint32_t dma_data_align; 630 } __packed; 631 632 #define PARAM_ID_VOL_CTRL_MASTER_GAIN 0x08001035 633 #define VOL_CTRL_DEFAULT_GAIN 0x2000 634 635 struct param_id_vol_ctrl_master_gain { 636 uint16_t master_gain; 637 uint16_t reserved; 638 } __packed; 639 640 641 #define PARAM_ID_REMOVE_INITIAL_SILENCE 0x0800114B 642 #define PARAM_ID_REMOVE_TRAILING_SILENCE 0x0800115D 643 644 #define PARAM_ID_REAL_MODULE_ID 0x0800100B 645 646 struct param_id_placeholder_real_module_id { 647 uint32_t real_module_id; 648 } __packed; 649 650 /* Graph */ 651 struct audioreach_connection { 652 /* Connections */ 653 uint32_t src_mod_inst_id; 654 uint32_t src_mod_op_port_id; 655 uint32_t dst_mod_inst_id; 656 uint32_t dst_mod_ip_port_id; 657 struct list_head node; 658 }; 659 660 struct audioreach_graph_info { 661 int id; 662 uint32_t num_sub_graphs; 663 struct list_head sg_list; 664 /* DPCM connection from FE Graph to BE graph */ 665 uint32_t src_mod_inst_id; 666 uint32_t src_mod_op_port_id; 667 uint32_t dst_mod_inst_id; 668 uint32_t dst_mod_ip_port_id; 669 }; 670 671 struct audioreach_sub_graph { 672 uint32_t sub_graph_id; 673 uint32_t perf_mode; 674 uint32_t direction; 675 uint32_t scenario_id; 676 struct list_head node; 677 678 struct audioreach_graph_info *info; 679 uint32_t num_containers; 680 struct list_head container_list; 681 }; 682 683 struct audioreach_container { 684 uint32_t container_id; 685 uint32_t capability_id; 686 uint32_t graph_pos; 687 uint32_t stack_size; 688 uint32_t proc_domain; 689 struct list_head node; 690 691 uint32_t num_modules; 692 struct list_head modules_list; 693 struct audioreach_sub_graph *sub_graph; 694 }; 695 696 #define AR_MAX_MOD_LINKS 8 697 698 struct audioreach_module { 699 uint32_t module_id; 700 uint32_t instance_id; 701 702 uint32_t max_ip_port; 703 uint32_t max_op_port; 704 705 uint32_t in_port; 706 uint32_t out_port; 707 708 uint32_t num_connections; 709 /* Connections */ 710 uint32_t src_mod_inst_id; 711 uint32_t src_mod_op_port_id[AR_MAX_MOD_LINKS]; 712 uint32_t dst_mod_inst_id[AR_MAX_MOD_LINKS]; 713 uint32_t dst_mod_ip_port_id[AR_MAX_MOD_LINKS]; 714 715 /* Format specifics */ 716 uint32_t ch_fmt; 717 uint32_t rate; 718 uint32_t bit_depth; 719 720 /* I2S module */ 721 uint32_t hw_interface_idx; 722 uint32_t sd_line_idx; 723 uint32_t ws_src; 724 uint32_t frame_size_factor; 725 uint32_t data_format; 726 uint32_t hw_interface_type; 727 728 /* PCM module specific */ 729 uint32_t interleave_type; 730 731 /* GAIN/Vol Control Module */ 732 uint16_t gain; 733 734 /* Logging */ 735 uint32_t log_code; 736 uint32_t log_tap_point_id; 737 uint32_t log_mode; 738 739 /* bookkeeping */ 740 struct list_head node; 741 struct audioreach_container *container; 742 struct snd_soc_dapm_widget *widget; 743 }; 744 745 struct audioreach_module_config { 746 int direction; 747 u32 sample_rate; 748 u16 bit_width; 749 u16 bits_per_sample; 750 751 u16 data_format; 752 u16 num_channels; 753 u16 active_channels_mask; 754 u16 dp_idx; 755 u32 channel_allocation; 756 u32 sd_line_mask; 757 int fmt; 758 struct snd_codec codec; 759 u8 channel_map[AR_PCM_MAX_NUM_CHANNEL]; 760 }; 761 762 /* Packet Allocation routines */ 763 void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t 764 token); 765 void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode, 766 uint32_t token, uint32_t src_port, 767 uint32_t dest_port); 768 void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token, 769 uint32_t src_port); 770 void *audioreach_alloc_pkt(int payload_size, uint32_t opcode, 771 uint32_t token, uint32_t src_port, 772 uint32_t dest_port); 773 void *audioreach_alloc_graph_pkt(struct q6apm *apm, struct audioreach_graph_info 774 *info); 775 /* Topology specific */ 776 int audioreach_tplg_init(struct snd_soc_component *component); 777 778 /* Module specific */ 779 void audioreach_graph_free_buf(struct q6apm_graph *graph); 780 int audioreach_map_memory_regions(struct q6apm_graph *graph, 781 unsigned int dir, size_t period_sz, 782 unsigned int periods, 783 bool is_contiguous); 784 int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev, struct gpr_ibasic_rsp_result_t *result, 785 struct mutex *cmd_lock, gpr_port_t *port, wait_queue_head_t *cmd_wait, 786 struct gpr_pkt *pkt, uint32_t rsp_opcode); 787 int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, struct gpr_pkt *pkt, 788 uint32_t rsp_opcode); 789 int audioreach_set_media_format(struct q6apm_graph *graph, 790 struct audioreach_module *module, 791 struct audioreach_module_config *cfg); 792 int audioreach_shared_memory_send_eos(struct q6apm_graph *graph); 793 int audioreach_gain_set_vol_ctrl(struct q6apm *apm, 794 struct audioreach_module *module, int vol); 795 int audioreach_send_u32_param(struct q6apm_graph *graph, struct audioreach_module *module, 796 uint32_t param_id, uint32_t param_val); 797 int audioreach_compr_set_param(struct q6apm_graph *graph, struct audioreach_module_config *mcfg); 798 799 #endif /* __AUDIOREACH_H__ */ 800