1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef __AUDIOREACH_H__ 4 #define __AUDIOREACH_H__ 5 #include <linux/types.h> 6 #include <linux/soc/qcom/apr.h> 7 #include <sound/soc.h> 8 struct q6apm; 9 struct q6apm_graph; 10 11 /* Module IDs */ 12 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 13 #define MODULE_ID_RD_SHARED_MEM_EP 0x07001001 14 #define MODULE_ID_GAIN 0x07001002 15 #define MODULE_ID_PCM_CNV 0x07001003 16 #define MODULE_ID_PCM_ENC 0x07001004 17 #define MODULE_ID_PCM_DEC 0x07001005 18 #define MODULE_ID_PLACEHOLDER_ENCODER 0x07001008 19 #define MODULE_ID_PLACEHOLDER_DECODER 0x07001009 20 #define MODULE_ID_SAL 0x07001010 21 #define MODULE_ID_MFC 0x07001015 22 #define MODULE_ID_CODEC_DMA_SINK 0x07001023 23 #define MODULE_ID_CODEC_DMA_SOURCE 0x07001024 24 #define MODULE_ID_I2S_SINK 0x0700100A 25 #define MODULE_ID_I2S_SOURCE 0x0700100B 26 #define MODULE_ID_DATA_LOGGING 0x0700101A 27 #define MODULE_ID_AAC_DEC 0x0700101F 28 #define MODULE_ID_FLAC_DEC 0x0700102F 29 #define MODULE_ID_MP3_DECODE 0x0700103B 30 #define MODULE_ID_DISPLAY_PORT_SINK 0x07001069 31 32 #define APM_CMD_GET_SPF_STATE 0x01001021 33 #define APM_CMD_RSP_GET_SPF_STATE 0x02001007 34 35 #define APM_MODULE_INSTANCE_ID 0x00000001 36 #define PRM_MODULE_INSTANCE_ID 0x00000002 37 #define AMDB_MODULE_INSTANCE_ID 0x00000003 38 #define VCPM_MODULE_INSTANCE_ID 0x00000004 39 #define AR_MODULE_INSTANCE_ID_START 0x00006000 40 #define AR_MODULE_INSTANCE_ID_END 0x00007000 41 #define AR_MODULE_DYNAMIC_INSTANCE_ID_START 0x00007000 42 #define AR_MODULE_DYNAMIC_INSTANCE_ID_END 0x00008000 43 #define AR_CONT_INSTANCE_ID_START 0x00005000 44 #define AR_CONT_INSTANCE_ID_END 0x00006000 45 #define AR_SG_INSTANCE_ID_START 0x00004000 46 47 #define APM_CMD_GRAPH_OPEN 0x01001000 48 #define APM_CMD_GRAPH_PREPARE 0x01001001 49 #define APM_CMD_GRAPH_START 0x01001002 50 #define APM_CMD_GRAPH_STOP 0x01001003 51 #define APM_CMD_GRAPH_CLOSE 0x01001004 52 #define APM_CMD_GRAPH_FLUSH 0x01001005 53 #define APM_CMD_SET_CFG 0x01001006 54 #define APM_CMD_GET_CFG 0x01001007 55 #define APM_CMD_SHARED_MEM_MAP_REGIONS 0x0100100C 56 #define APM_CMD_SHARED_MEM_UNMAP_REGIONS 0x0100100D 57 #define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS 0x02001001 58 #define APM_CMD_RSP_GET_CFG 0x02001000 59 #define APM_CMD_CLOSE_ALL 0x01001013 60 #define APM_CMD_REGISTER_SHARED_CFG 0x0100100A 61 62 #define APM_MEMORY_MAP_SHMEM8_4K_POOL 3 63 64 struct apm_cmd_shared_mem_map_regions { 65 uint16_t mem_pool_id; 66 uint16_t num_regions; 67 uint32_t property_flag; 68 } __packed; 69 70 struct apm_shared_map_region_payload { 71 uint32_t shm_addr_lsw; 72 uint32_t shm_addr_msw; 73 uint32_t mem_size_bytes; 74 } __packed; 75 76 struct apm_cmd_shared_mem_unmap_regions { 77 uint32_t mem_map_handle; 78 } __packed; 79 80 struct apm_cmd_rsp_shared_mem_map_regions { 81 uint32_t mem_map_handle; 82 } __packed; 83 84 /* APM module */ 85 #define APM_PARAM_ID_SUB_GRAPH_LIST 0x08001005 86 87 #define APM_PARAM_ID_MODULE_LIST 0x08001002 88 89 struct apm_param_id_modules_list { 90 uint32_t num_modules_list; 91 } __packed; 92 93 #define APM_PARAM_ID_MODULE_PROP 0x08001003 94 95 struct apm_param_id_module_prop { 96 uint32_t num_modules_prop_cfg; 97 } __packed; 98 99 struct apm_module_prop_cfg { 100 uint32_t instance_id; 101 uint32_t num_props; 102 } __packed; 103 104 #define APM_PARAM_ID_MODULE_CONN 0x08001004 105 106 struct apm_param_id_module_conn { 107 uint32_t num_connections; 108 } __packed; 109 110 struct apm_module_conn_obj { 111 uint32_t src_mod_inst_id; 112 uint32_t src_mod_op_port_id; 113 uint32_t dst_mod_inst_id; 114 uint32_t dst_mod_ip_port_id; 115 } __packed; 116 117 #define APM_PARAM_ID_GAIN 0x08001006 118 119 struct param_id_gain_cfg { 120 uint16_t gain; 121 uint16_t reserved; 122 } __packed; 123 124 #define PARAM_ID_PCM_OUTPUT_FORMAT_CFG 0x08001008 125 126 struct param_id_pcm_output_format_cfg { 127 uint32_t data_format; 128 uint32_t fmt_id; 129 uint32_t payload_size; 130 } __packed; 131 132 struct payload_pcm_output_format_cfg { 133 uint16_t bit_width; 134 uint16_t alignment; 135 uint16_t bits_per_sample; 136 uint16_t q_factor; 137 uint16_t endianness; 138 uint16_t interleaved; 139 uint16_t reserved; 140 uint16_t num_channels; 141 uint8_t channel_mapping[]; 142 } __packed; 143 144 #define PARAM_ID_ENC_BITRATE 0x08001052 145 146 struct param_id_enc_bitrate_param { 147 uint32_t bitrate; 148 } __packed; 149 150 #define DATA_FORMAT_FIXED_POINT 1 151 #define PCM_LSB_ALIGNED 1 152 #define PCM_MSB_ALIGNED 2 153 #define PCM_LITTLE_ENDIAN 1 154 #define PCM_BIT_ENDIAN 2 155 156 #define MEDIA_FMT_ID_PCM 0x09001000 157 #define PCM_CHANNEL_L 1 158 #define PCM_CHANNEL_R 2 159 #define SAMPLE_RATE_48K 48000 160 #define BIT_WIDTH_16 16 161 162 #define APM_PARAM_ID_PROP_PORT_INFO 0x08001015 163 164 struct apm_modules_prop_info { 165 uint32_t max_ip_port; 166 uint32_t max_op_port; 167 } __packed; 168 169 /* Shared memory module */ 170 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER 0x04001000 171 #define WR_SH_MEM_EP_TIMESTAMP_VALID_FLAG BIT(31) 172 #define WR_SH_MEM_EP_LAST_BUFFER_FLAG BIT(30) 173 #define WR_SH_MEM_EP_TS_CONTINUE_FLAG BIT(29) 174 #define WR_SH_MEM_EP_EOF_FLAG BIT(4) 175 176 struct apm_data_cmd_wr_sh_mem_ep_data_buffer { 177 uint32_t buf_addr_lsw; 178 uint32_t buf_addr_msw; 179 uint32_t mem_map_handle; 180 uint32_t buf_size; 181 uint32_t timestamp_lsw; 182 uint32_t timestamp_msw; 183 uint32_t flags; 184 } __packed; 185 186 #define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2 0x0400100A 187 188 struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 { 189 uint32_t buf_addr_lsw; 190 uint32_t buf_addr_msw; 191 uint32_t mem_map_handle; 192 uint32_t buf_size; 193 uint32_t timestamp_lsw; 194 uint32_t timestamp_msw; 195 uint32_t flags; 196 uint32_t md_addr_lsw; 197 uint32_t md_addr_msw; 198 uint32_t md_map_handle; 199 uint32_t md_buf_size; 200 } __packed; 201 202 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE 0x05001000 203 204 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done { 205 uint32_t buf_addr_lsw; 206 uint32_t buf_addr_msw; 207 uint32_t mem_map_handle; 208 uint32_t status; 209 210 } __packed; 211 212 #define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2 0x05001004 213 214 struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 { 215 uint32_t buf_addr_lsw; 216 uint32_t buf_addr_msw; 217 uint32_t mem_map_handle; 218 uint32_t status; 219 uint32_t md_buf_addr_lsw; 220 uint32_t md_buf_addr_msw; 221 uint32_t md_mem_map_handle; 222 uint32_t md_status; 223 } __packed; 224 225 #define PARAM_ID_MEDIA_FORMAT 0x0800100C 226 #define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT 0x04001001 227 228 struct apm_media_format { 229 uint32_t data_format; 230 uint32_t fmt_id; 231 uint32_t payload_size; 232 } __packed; 233 234 #define DATA_CMD_WR_SH_MEM_EP_EOS 0x04001002 235 #define WR_SH_MEM_EP_EOS_POLICY_LAST 1 236 #define WR_SH_MEM_EP_EOS_POLICY_EACH 2 237 238 struct data_cmd_wr_sh_mem_ep_eos { 239 uint32_t policy; 240 241 } __packed; 242 243 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER 0x04001003 244 245 struct data_cmd_rd_sh_mem_ep_data_buffer { 246 uint32_t buf_addr_lsw; 247 uint32_t buf_addr_msw; 248 uint32_t mem_map_handle; 249 uint32_t buf_size; 250 } __packed; 251 252 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER 0x05001002 253 254 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done { 255 uint32_t status; 256 uint32_t buf_addr_lsw; 257 uint32_t buf_addr_msw; 258 uint32_t mem_map_handle; 259 uint32_t data_size; 260 uint32_t offset; 261 uint32_t timestamp_lsw; 262 uint32_t timestamp_msw; 263 uint32_t flags; 264 uint32_t num_frames; 265 } __packed; 266 267 #define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2 0x0400100B 268 269 struct data_cmd_rd_sh_mem_ep_data_buffer_v2 { 270 uint32_t buf_addr_lsw; 271 uint32_t buf_addr_msw; 272 uint32_t mem_map_handle; 273 uint32_t buf_size; 274 uint32_t md_buf_addr_lsw; 275 uint32_t md_buf_addr_msw; 276 uint32_t md_mem_map_handle; 277 uint32_t md_buf_size; 278 } __packed; 279 280 #define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2 0x05001005 281 282 struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 { 283 uint32_t status; 284 uint32_t buf_addr_lsw; 285 uint32_t buf_addr_msw; 286 uint32_t mem_map_handle; 287 uint32_t data_size; 288 uint32_t offset; 289 uint32_t timestamp_lsw; 290 uint32_t timestamp_msw; 291 uint32_t flags; 292 uint32_t num_frames; 293 uint32_t md_status; 294 uint32_t md_buf_addr_lsw; 295 uint32_t md_buf_addr_msw; 296 uint32_t md_mem_map_handle; 297 uint32_t md_size; 298 } __packed; 299 300 #define PARAM_ID_RD_SH_MEM_CFG 0x08001007 301 302 struct param_id_rd_sh_mem_cfg { 303 uint32_t num_frames_per_buffer; 304 uint32_t metadata_control_flags; 305 306 } __packed; 307 308 #define DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED 0x05001001 309 310 struct data_cmd_wr_sh_mem_ep_eos_rendered { 311 uint32_t module_instance_id; 312 uint32_t render_status; 313 } __packed; 314 315 #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 316 317 struct apm_cmd_header { 318 uint32_t payload_address_lsw; 319 uint32_t payload_address_msw; 320 uint32_t mem_map_handle; 321 uint32_t payload_size; 322 } __packed; 323 324 #define APM_CMD_HDR_SIZE sizeof(struct apm_cmd_header) 325 326 struct apm_module_param_data { 327 uint32_t module_instance_id; 328 uint32_t param_id; 329 uint32_t param_size; 330 uint32_t error_code; 331 } __packed; 332 333 #define APM_MODULE_PARAM_DATA_SIZE sizeof(struct apm_module_param_data) 334 335 struct apm_module_param_shared_data { 336 uint32_t param_id; 337 uint32_t param_size; 338 } __packed; 339 340 struct apm_prop_data { 341 uint32_t prop_id; 342 uint32_t prop_size; 343 } __packed; 344 345 /* Sub-Graph Properties */ 346 #define APM_PARAM_ID_SUB_GRAPH_CONFIG 0x08001001 347 348 struct apm_param_id_sub_graph_cfg { 349 uint32_t num_sub_graphs; 350 } __packed; 351 352 struct apm_sub_graph_cfg { 353 uint32_t sub_graph_id; 354 uint32_t num_sub_graph_prop; 355 } __packed; 356 357 #define APM_SUB_GRAPH_PROP_ID_PERF_MODE 0x0800100E 358 359 struct apm_sg_prop_id_perf_mode { 360 uint32_t perf_mode; 361 } __packed; 362 363 #define APM_SG_PROP_ID_PERF_MODE_SIZE 4 364 365 #define APM_SUB_GRAPH_PROP_ID_DIRECTION 0x0800100F 366 367 struct apm_sg_prop_id_direction { 368 uint32_t direction; 369 } __packed; 370 371 #define APM_SG_PROP_ID_DIR_SIZE 4 372 373 #define APM_SUB_GRAPH_PROP_ID_SCENARIO_ID 0x08001010 374 #define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1 375 #define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2 376 #define APM_SUB_GRAPH_SID_AUDIO_VOICE_CALL 0x3 377 378 struct apm_sg_prop_id_scenario_id { 379 uint32_t scenario_id; 380 } __packed; 381 382 #define APM_SG_PROP_ID_SID_SIZE 4 383 /* container api */ 384 #define APM_PARAM_ID_CONTAINER_CONFIG 0x08001000 385 386 struct apm_param_id_container_cfg { 387 uint32_t num_containers; 388 } __packed; 389 390 struct apm_container_cfg { 391 uint32_t container_id; 392 uint32_t num_prop; 393 } __packed; 394 395 struct apm_cont_capability { 396 uint32_t capability_id; 397 } __packed; 398 399 #define APM_CONTAINER_PROP_ID_CAPABILITY_LIST 0x08001011 400 #define APM_CONTAINER_PROP_ID_CAPABILITY_SIZE 8 401 402 #define APM_PROP_ID_INVALID 0x0 403 #define APM_CONTAINER_CAP_ID_PP 0x1 404 #define APM_CONTAINER_CAP_ID_PP 0x1 405 406 struct apm_cont_prop_id_cap_list { 407 uint32_t num_capability_id; 408 } __packed; 409 410 #define APM_CONTAINER_PROP_ID_GRAPH_POS 0x08001012 411 412 struct apm_cont_prop_id_graph_pos { 413 uint32_t graph_pos; 414 } __packed; 415 416 #define APM_CONTAINER_PROP_ID_STACK_SIZE 0x08001013 417 418 struct apm_cont_prop_id_stack_size { 419 uint32_t stack_size; 420 } __packed; 421 422 #define APM_CONTAINER_PROP_ID_PROC_DOMAIN 0x08001014 423 424 struct apm_cont_prop_id_domain { 425 uint32_t proc_domain; 426 } __packed; 427 428 #define CONFIG_I2S_WS_SRC_EXTERNAL 0x0 429 #define CONFIG_I2S_WS_SRC_INTERNAL 0x1 430 431 #define PARAM_ID_I2S_INTF_CFG 0x08001019 432 struct param_id_i2s_intf_cfg { 433 uint32_t lpaif_type; 434 uint32_t intf_idx; 435 uint16_t sd_line_idx; 436 uint16_t ws_src; 437 } __packed; 438 439 #define I2S_INTF_TYPE_PRIMARY 0 440 #define I2S_INTF_TYPE_SECOINDARY 1 441 #define I2S_INTF_TYPE_TERTINARY 2 442 #define I2S_INTF_TYPE_QUATERNARY 3 443 #define I2S_INTF_TYPE_QUINARY 4 444 #define I2S_SD0 1 445 #define I2S_SD1 2 446 #define I2S_SD2 3 447 #define I2S_SD3 4 448 449 #define PORT_ID_I2S_INPUT 2 450 #define PORT_ID_I2S_OUPUT 1 451 #define I2S_STACK_SIZE 2048 452 453 #define PARAM_ID_DISPLAY_PORT_INTF_CFG 0x08001154 454 455 struct param_id_display_port_intf_cfg { 456 uint32_t channel_allocation; 457 /* Multi-Steam Transport index */ 458 uint32_t mst_idx; 459 uint32_t dptx_idx; 460 } __packed; 461 462 #define PARAM_ID_HW_EP_MF_CFG 0x08001017 463 struct param_id_hw_ep_mf { 464 uint32_t sample_rate; 465 uint16_t bit_width; 466 uint16_t num_channels; 467 uint32_t data_format; 468 } __packed; 469 470 #define PARAM_ID_HW_EP_FRAME_SIZE_FACTOR 0x08001018 471 472 struct param_id_fram_size_factor { 473 uint32_t frame_size_factor; 474 } __packed; 475 476 #define APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID 0x080010CB 477 478 struct apm_cont_prop_id_parent_container { 479 uint32_t parent_container_id; 480 } __packed; 481 482 #define APM_CONTAINER_PROP_ID_HEAP_ID 0x08001174 483 #define APM_CONT_HEAP_DEFAULT 0x1 484 #define APM_CONT_HEAP_LOW_POWER 0x2 485 486 struct apm_cont_prop_id_headp_id { 487 uint32_t heap_id; 488 } __packed; 489 490 struct apm_modules_list { 491 uint32_t sub_graph_id; 492 uint32_t container_id; 493 uint32_t num_modules; 494 } __packed; 495 496 struct apm_module_obj { 497 uint32_t module_id; 498 uint32_t instance_id; 499 } __packed; 500 501 #define APM_MODULE_PROP_ID_PORT_INFO 0x08001015 502 #define APM_MODULE_PROP_ID_PORT_INFO_SZ 8 503 struct apm_module_prop_id_port_info { 504 uint32_t max_ip_port; 505 uint32_t max_op_port; 506 } __packed; 507 508 #define DATA_LOGGING_MAX_INPUT_PORTS 0x1 509 #define DATA_LOGGING_MAX_OUTPUT_PORTS 0x1 510 #define DATA_LOGGING_STACK_SIZE 2048 511 #define PARAM_ID_DATA_LOGGING_CONFIG 0x08001031 512 513 struct data_logging_config { 514 uint32_t log_code; 515 uint32_t log_tap_point_id; 516 uint32_t mode; 517 } __packed; 518 519 #define PARAM_ID_SAL_OUTPUT_CFG 0x08001016 520 struct param_id_sal_output_config { 521 uint32_t bits_per_sample; 522 } __packed; 523 524 #define PARAM_ID_SAL_LIMITER_ENABLE 0x0800101E 525 struct param_id_sal_limiter_enable { 526 uint32_t enable_lim; 527 } __packed; 528 529 #define PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT 0x08001024 530 531 struct param_id_mfc_media_format { 532 uint32_t sample_rate; 533 uint16_t bit_width; 534 uint16_t num_channels; 535 uint16_t channel_mapping[]; 536 } __packed; 537 538 struct media_format { 539 uint32_t data_format; 540 uint32_t fmt_id; 541 uint32_t payload_size; 542 } __packed; 543 544 struct payload_media_fmt_pcm { 545 uint32_t sample_rate; 546 uint16_t bit_width; 547 uint16_t alignment; 548 uint16_t bits_per_sample; 549 uint16_t q_factor; 550 uint16_t endianness; 551 uint16_t num_channels; 552 uint8_t channel_mapping[]; 553 } __packed; 554 555 #define PARAM_ID_MODULE_ENABLE 0x08001026 556 struct param_id_module_enable { 557 uint32_t enable; 558 } __packed; 559 560 #define PARAM_ID_CODEC_DMA_INTF_CFG 0x08001063 561 562 struct param_id_codec_dma_intf_cfg { 563 /* 1 - RXTX 564 * 2 - WSA 565 * 3 - VA 566 * 4 - AXI 567 */ 568 uint32_t lpaif_type; 569 /* 570 * RX0 | TX0 = 1 571 * RX1 | TX1 = 2 572 * RX2 | TX2 = 3... so on 573 */ 574 uint32_t intf_index; 575 uint32_t active_channels_mask; 576 } __packed; 577 578 struct audio_hw_clk_cfg { 579 uint32_t clock_id; 580 uint32_t clock_freq; 581 uint32_t clock_attri; 582 uint32_t clock_root; 583 } __packed; 584 585 struct audio_hw_clk_rel_cfg { 586 uint32_t clock_id; 587 } __packed; 588 589 #define PARAM_ID_HW_EP_POWER_MODE_CFG 0x8001176 590 #define AR_HW_EP_POWER_MODE_0 0 /* default */ 591 #define AR_HW_EP_POWER_MODE_1 1 /* XO Shutdown allowed */ 592 #define AR_HW_EP_POWER_MODE_2 2 /* XO Shutdown not allowed */ 593 594 struct param_id_hw_ep_power_mode_cfg { 595 uint32_t power_mode; 596 } __packed; 597 598 #define PARAM_ID_HW_EP_DMA_DATA_ALIGN 0x08001233 599 #define AR_HW_EP_DMA_DATA_ALIGN_MSB 0 600 #define AR_HW_EP_DMA_DATA_ALIGN_LSB 1 601 #define AR_PCM_MAX_NUM_CHANNEL 8 602 603 struct param_id_hw_ep_dma_data_align { 604 uint32_t dma_data_align; 605 } __packed; 606 607 #define PARAM_ID_VOL_CTRL_MASTER_GAIN 0x08001035 608 #define VOL_CTRL_DEFAULT_GAIN 0x2000 609 610 struct param_id_vol_ctrl_master_gain { 611 uint16_t master_gain; 612 uint16_t reserved; 613 } __packed; 614 615 616 #define PARAM_ID_REMOVE_INITIAL_SILENCE 0x0800114B 617 #define PARAM_ID_REMOVE_TRAILING_SILENCE 0x0800115D 618 619 #define PARAM_ID_REAL_MODULE_ID 0x0800100B 620 621 struct param_id_placeholder_real_module_id { 622 uint32_t real_module_id; 623 } __packed; 624 625 /* Graph */ 626 struct audioreach_connection { 627 /* Connections */ 628 uint32_t src_mod_inst_id; 629 uint32_t src_mod_op_port_id; 630 uint32_t dst_mod_inst_id; 631 uint32_t dst_mod_ip_port_id; 632 struct list_head node; 633 }; 634 635 struct audioreach_graph_info { 636 int id; 637 uint32_t num_sub_graphs; 638 struct list_head sg_list; 639 /* DPCM connection from FE Graph to BE graph */ 640 uint32_t src_mod_inst_id; 641 uint32_t src_mod_op_port_id; 642 uint32_t dst_mod_inst_id; 643 uint32_t dst_mod_ip_port_id; 644 }; 645 646 struct audioreach_sub_graph { 647 uint32_t sub_graph_id; 648 uint32_t perf_mode; 649 uint32_t direction; 650 uint32_t scenario_id; 651 struct list_head node; 652 653 struct audioreach_graph_info *info; 654 uint32_t num_containers; 655 struct list_head container_list; 656 }; 657 658 struct audioreach_container { 659 uint32_t container_id; 660 uint32_t capability_id; 661 uint32_t graph_pos; 662 uint32_t stack_size; 663 uint32_t proc_domain; 664 struct list_head node; 665 666 uint32_t num_modules; 667 struct list_head modules_list; 668 struct audioreach_sub_graph *sub_graph; 669 }; 670 671 #define AR_MAX_MOD_LINKS 8 672 673 struct audioreach_module { 674 uint32_t module_id; 675 uint32_t instance_id; 676 677 uint32_t max_ip_port; 678 uint32_t max_op_port; 679 680 uint32_t in_port; 681 uint32_t out_port; 682 683 uint32_t num_connections; 684 /* Connections */ 685 uint32_t src_mod_inst_id; 686 uint32_t src_mod_op_port_id[AR_MAX_MOD_LINKS]; 687 uint32_t dst_mod_inst_id[AR_MAX_MOD_LINKS]; 688 uint32_t dst_mod_ip_port_id[AR_MAX_MOD_LINKS]; 689 690 /* Format specifics */ 691 uint32_t ch_fmt; 692 uint32_t rate; 693 uint32_t bit_depth; 694 695 /* I2S module */ 696 uint32_t hw_interface_idx; 697 uint32_t sd_line_idx; 698 uint32_t ws_src; 699 uint32_t frame_size_factor; 700 uint32_t data_format; 701 uint32_t hw_interface_type; 702 703 /* PCM module specific */ 704 uint32_t interleave_type; 705 706 /* GAIN/Vol Control Module */ 707 uint16_t gain; 708 709 /* Logging */ 710 uint32_t log_code; 711 uint32_t log_tap_point_id; 712 uint32_t log_mode; 713 714 /* bookkeeping */ 715 struct list_head node; 716 struct audioreach_container *container; 717 struct snd_soc_dapm_widget *widget; 718 }; 719 720 struct audioreach_module_config { 721 int direction; 722 u32 sample_rate; 723 u16 bit_width; 724 u16 bits_per_sample; 725 726 u16 data_format; 727 u16 num_channels; 728 u16 active_channels_mask; 729 u16 dp_idx; 730 u32 channel_allocation; 731 u32 sd_line_mask; 732 int fmt; 733 u8 channel_map[AR_PCM_MAX_NUM_CHANNEL]; 734 }; 735 736 /* Packet Allocation routines */ 737 void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t 738 token); 739 void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode, 740 uint32_t token, uint32_t src_port, 741 uint32_t dest_port); 742 void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token, 743 uint32_t src_port); 744 void *audioreach_alloc_pkt(int payload_size, uint32_t opcode, 745 uint32_t token, uint32_t src_port, 746 uint32_t dest_port); 747 void *audioreach_alloc_graph_pkt(struct q6apm *apm, struct audioreach_graph_info 748 *info); 749 /* Topology specific */ 750 int audioreach_tplg_init(struct snd_soc_component *component); 751 752 /* Module specific */ 753 void audioreach_graph_free_buf(struct q6apm_graph *graph); 754 int audioreach_map_memory_regions(struct q6apm_graph *graph, 755 unsigned int dir, size_t period_sz, 756 unsigned int periods, 757 bool is_contiguous); 758 int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev, struct gpr_ibasic_rsp_result_t *result, 759 struct mutex *cmd_lock, gpr_port_t *port, wait_queue_head_t *cmd_wait, 760 struct gpr_pkt *pkt, uint32_t rsp_opcode); 761 int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, struct gpr_pkt *pkt, 762 uint32_t rsp_opcode); 763 int audioreach_set_media_format(struct q6apm_graph *graph, 764 struct audioreach_module *module, 765 struct audioreach_module_config *cfg); 766 int audioreach_shared_memory_send_eos(struct q6apm_graph *graph); 767 int audioreach_gain_set_vol_ctrl(struct q6apm *apm, 768 struct audioreach_module *module, int vol); 769 int audioreach_send_u32_param(struct q6apm_graph *graph, struct audioreach_module *module, 770 uint32_t param_id, uint32_t param_val); 771 #endif /* __AUDIOREACH_H__ */ 772