1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. 4 * 5 * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <sound/pcm.h> 15 #include <sound/pcm_params.h> 16 #include <linux/regmap.h> 17 #include <sound/soc.h> 18 #include <sound/soc-dai.h> 19 #include "lpass-lpaif-reg.h" 20 #include "lpass.h" 21 22 #define LPASS_CPU_MAX_MI2S_LINES 4 23 #define LPASS_CPU_I2S_SD0_MASK BIT(0) 24 #define LPASS_CPU_I2S_SD1_MASK BIT(1) 25 #define LPASS_CPU_I2S_SD2_MASK BIT(2) 26 #define LPASS_CPU_I2S_SD3_MASK BIT(3) 27 #define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0) 28 #define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2) 29 #define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0) 30 #define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0) 31 32 static int lpass_cpu_init_i2sctl_bitfields(struct device *dev, 33 struct lpaif_i2sctl *i2sctl, struct regmap *map) 34 { 35 struct lpass_data *drvdata = dev_get_drvdata(dev); 36 struct lpass_variant *v = drvdata->variant; 37 38 i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback); 39 i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken); 40 i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode); 41 i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono); 42 i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen); 43 i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode); 44 i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono); 45 i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc); 46 i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth); 47 48 if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) || 49 IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) || 50 IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) || 51 IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) || 52 IS_ERR(i2sctl->bitwidth)) 53 return -EINVAL; 54 55 return 0; 56 } 57 58 static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id, 59 unsigned int freq, int dir) 60 { 61 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 62 int ret; 63 64 ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq); 65 if (ret) 66 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n", 67 freq, ret); 68 69 return ret; 70 } 71 72 static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream, 73 struct snd_soc_dai *dai) 74 { 75 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 76 int ret; 77 78 ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]); 79 if (ret) { 80 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret); 81 return ret; 82 } 83 ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]); 84 if (ret) { 85 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); 86 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); 87 return ret; 88 } 89 return 0; 90 } 91 92 static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream, 93 struct snd_soc_dai *dai) 94 { 95 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 96 97 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]); 98 clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]); 99 } 100 101 static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream, 102 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 103 { 104 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 105 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; 106 unsigned int id = dai->driver->id; 107 snd_pcm_format_t format = params_format(params); 108 unsigned int channels = params_channels(params); 109 unsigned int rate = params_rate(params); 110 unsigned int mode; 111 unsigned int regval; 112 int bitwidth, ret; 113 114 bitwidth = snd_pcm_format_width(format); 115 if (bitwidth < 0) { 116 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth); 117 return bitwidth; 118 } 119 120 ret = regmap_fields_write(i2sctl->loopback, id, 121 LPAIF_I2SCTL_LOOPBACK_DISABLE); 122 if (ret) { 123 dev_err(dai->dev, "error updating loopback field: %d\n", ret); 124 return ret; 125 } 126 127 ret = regmap_fields_write(i2sctl->wssrc, id, 128 LPAIF_I2SCTL_WSSRC_INTERNAL); 129 if (ret) { 130 dev_err(dai->dev, "error updating wssrc field: %d\n", ret); 131 return ret; 132 } 133 134 switch (bitwidth) { 135 case 16: 136 regval = LPAIF_I2SCTL_BITWIDTH_16; 137 break; 138 case 24: 139 regval = LPAIF_I2SCTL_BITWIDTH_24; 140 break; 141 case 32: 142 regval = LPAIF_I2SCTL_BITWIDTH_32; 143 break; 144 default: 145 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth); 146 return -EINVAL; 147 } 148 149 ret = regmap_fields_write(i2sctl->bitwidth, id, regval); 150 if (ret) { 151 dev_err(dai->dev, "error updating bitwidth field: %d\n", ret); 152 return ret; 153 } 154 155 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 156 mode = drvdata->mi2s_playback_sd_mode[id]; 157 else 158 mode = drvdata->mi2s_capture_sd_mode[id]; 159 160 if (!mode) { 161 dev_err(dai->dev, "no line is assigned\n"); 162 return -EINVAL; 163 } 164 165 switch (channels) { 166 case 1: 167 case 2: 168 switch (mode) { 169 case LPAIF_I2SCTL_MODE_QUAD01: 170 case LPAIF_I2SCTL_MODE_6CH: 171 case LPAIF_I2SCTL_MODE_8CH: 172 mode = LPAIF_I2SCTL_MODE_SD0; 173 break; 174 case LPAIF_I2SCTL_MODE_QUAD23: 175 mode = LPAIF_I2SCTL_MODE_SD2; 176 break; 177 } 178 179 break; 180 case 4: 181 if (mode < LPAIF_I2SCTL_MODE_QUAD01) { 182 dev_err(dai->dev, "cannot configure 4 channels with mode %d\n", 183 mode); 184 return -EINVAL; 185 } 186 187 switch (mode) { 188 case LPAIF_I2SCTL_MODE_6CH: 189 case LPAIF_I2SCTL_MODE_8CH: 190 mode = LPAIF_I2SCTL_MODE_QUAD01; 191 break; 192 } 193 break; 194 case 6: 195 if (mode < LPAIF_I2SCTL_MODE_6CH) { 196 dev_err(dai->dev, "cannot configure 6 channels with mode %d\n", 197 mode); 198 return -EINVAL; 199 } 200 201 switch (mode) { 202 case LPAIF_I2SCTL_MODE_8CH: 203 mode = LPAIF_I2SCTL_MODE_6CH; 204 break; 205 } 206 break; 207 case 8: 208 if (mode < LPAIF_I2SCTL_MODE_8CH) { 209 dev_err(dai->dev, "cannot configure 8 channels with mode %d\n", 210 mode); 211 return -EINVAL; 212 } 213 break; 214 default: 215 dev_err(dai->dev, "invalid channels given: %u\n", channels); 216 return -EINVAL; 217 } 218 219 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 220 ret = regmap_fields_write(i2sctl->spkmode, id, 221 LPAIF_I2SCTL_SPKMODE(mode)); 222 if (ret) { 223 dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n", 224 ret); 225 return ret; 226 } 227 if (channels >= 2) 228 ret = regmap_fields_write(i2sctl->spkmono, id, 229 LPAIF_I2SCTL_SPKMONO_STEREO); 230 else 231 ret = regmap_fields_write(i2sctl->spkmono, id, 232 LPAIF_I2SCTL_SPKMONO_MONO); 233 } else { 234 ret = regmap_fields_write(i2sctl->micmode, id, 235 LPAIF_I2SCTL_MICMODE(mode)); 236 if (ret) { 237 dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n", 238 ret); 239 return ret; 240 } 241 if (channels >= 2) 242 ret = regmap_fields_write(i2sctl->micmono, id, 243 LPAIF_I2SCTL_MICMONO_STEREO); 244 else 245 ret = regmap_fields_write(i2sctl->micmono, id, 246 LPAIF_I2SCTL_MICMONO_MONO); 247 } 248 249 if (ret) { 250 dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n", 251 ret); 252 return ret; 253 } 254 255 ret = clk_set_rate(drvdata->mi2s_bit_clk[id], 256 rate * bitwidth * 2); 257 if (ret) { 258 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n", 259 rate * bitwidth * 2, ret); 260 return ret; 261 } 262 263 return 0; 264 } 265 266 static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream, 267 int cmd, struct snd_soc_dai *dai) 268 { 269 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 270 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl; 271 unsigned int id = dai->driver->id; 272 int ret = -EINVAL; 273 274 switch (cmd) { 275 case SNDRV_PCM_TRIGGER_START: 276 case SNDRV_PCM_TRIGGER_RESUME: 277 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 278 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 279 ret = regmap_fields_write(i2sctl->spken, id, 280 LPAIF_I2SCTL_SPKEN_ENABLE); 281 } else { 282 ret = regmap_fields_write(i2sctl->micen, id, 283 LPAIF_I2SCTL_MICEN_ENABLE); 284 } 285 if (ret) 286 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", 287 ret); 288 289 if (drvdata->bit_clk_state[id] == LPAIF_BIT_CLK_DISABLE) { 290 ret = clk_enable(drvdata->mi2s_bit_clk[id]); 291 if (ret) { 292 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret); 293 clk_disable(drvdata->mi2s_osr_clk[id]); 294 return ret; 295 } 296 drvdata->bit_clk_state[id] = LPAIF_BIT_CLK_ENABLE; 297 } 298 299 break; 300 case SNDRV_PCM_TRIGGER_STOP: 301 case SNDRV_PCM_TRIGGER_SUSPEND: 302 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 303 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 304 ret = regmap_fields_write(i2sctl->spken, id, 305 LPAIF_I2SCTL_SPKEN_DISABLE); 306 } else { 307 ret = regmap_fields_write(i2sctl->micen, id, 308 LPAIF_I2SCTL_MICEN_DISABLE); 309 } 310 if (ret) 311 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", 312 ret); 313 if (drvdata->bit_clk_state[id] == LPAIF_BIT_CLK_ENABLE) { 314 clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]); 315 drvdata->bit_clk_state[id] = LPAIF_BIT_CLK_DISABLE; 316 } 317 break; 318 } 319 320 return ret; 321 } 322 323 const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = { 324 .set_sysclk = lpass_cpu_daiops_set_sysclk, 325 .startup = lpass_cpu_daiops_startup, 326 .shutdown = lpass_cpu_daiops_shutdown, 327 .hw_params = lpass_cpu_daiops_hw_params, 328 .trigger = lpass_cpu_daiops_trigger, 329 }; 330 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops); 331 332 int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai) 333 { 334 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); 335 int ret; 336 337 /* ensure audio hardware is disabled */ 338 ret = regmap_write(drvdata->lpaif_map, 339 LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0); 340 if (ret) 341 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret); 342 343 return ret; 344 } 345 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe); 346 347 static const struct snd_soc_component_driver lpass_cpu_comp_driver = { 348 .name = "lpass-cpu", 349 }; 350 351 static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg) 352 { 353 struct lpass_data *drvdata = dev_get_drvdata(dev); 354 struct lpass_variant *v = drvdata->variant; 355 int i; 356 357 for (i = 0; i < v->i2s_ports; ++i) 358 if (reg == LPAIF_I2SCTL_REG(v, i)) 359 return true; 360 361 for (i = 0; i < v->irq_ports; ++i) { 362 if (reg == LPAIF_IRQEN_REG(v, i)) 363 return true; 364 if (reg == LPAIF_IRQCLEAR_REG(v, i)) 365 return true; 366 } 367 368 for (i = 0; i < v->rdma_channels; ++i) { 369 if (reg == LPAIF_RDMACTL_REG(v, i)) 370 return true; 371 if (reg == LPAIF_RDMABASE_REG(v, i)) 372 return true; 373 if (reg == LPAIF_RDMABUFF_REG(v, i)) 374 return true; 375 if (reg == LPAIF_RDMAPER_REG(v, i)) 376 return true; 377 } 378 379 for (i = 0; i < v->wrdma_channels; ++i) { 380 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) 381 return true; 382 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) 383 return true; 384 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) 385 return true; 386 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) 387 return true; 388 } 389 390 return false; 391 } 392 393 static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg) 394 { 395 struct lpass_data *drvdata = dev_get_drvdata(dev); 396 struct lpass_variant *v = drvdata->variant; 397 int i; 398 399 for (i = 0; i < v->i2s_ports; ++i) 400 if (reg == LPAIF_I2SCTL_REG(v, i)) 401 return true; 402 403 for (i = 0; i < v->irq_ports; ++i) { 404 if (reg == LPAIF_IRQEN_REG(v, i)) 405 return true; 406 if (reg == LPAIF_IRQSTAT_REG(v, i)) 407 return true; 408 } 409 410 for (i = 0; i < v->rdma_channels; ++i) { 411 if (reg == LPAIF_RDMACTL_REG(v, i)) 412 return true; 413 if (reg == LPAIF_RDMABASE_REG(v, i)) 414 return true; 415 if (reg == LPAIF_RDMABUFF_REG(v, i)) 416 return true; 417 if (reg == LPAIF_RDMACURR_REG(v, i)) 418 return true; 419 if (reg == LPAIF_RDMAPER_REG(v, i)) 420 return true; 421 } 422 423 for (i = 0; i < v->wrdma_channels; ++i) { 424 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) 425 return true; 426 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) 427 return true; 428 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) 429 return true; 430 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) 431 return true; 432 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) 433 return true; 434 } 435 436 return false; 437 } 438 439 static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg) 440 { 441 struct lpass_data *drvdata = dev_get_drvdata(dev); 442 struct lpass_variant *v = drvdata->variant; 443 int i; 444 445 for (i = 0; i < v->irq_ports; ++i) 446 if (reg == LPAIF_IRQSTAT_REG(v, i)) 447 return true; 448 449 for (i = 0; i < v->rdma_channels; ++i) 450 if (reg == LPAIF_RDMACURR_REG(v, i)) 451 return true; 452 453 for (i = 0; i < v->wrdma_channels; ++i) 454 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) 455 return true; 456 457 return false; 458 } 459 460 static struct regmap_config lpass_cpu_regmap_config = { 461 .name = "lpass_cpu", 462 .reg_bits = 32, 463 .reg_stride = 4, 464 .val_bits = 32, 465 .writeable_reg = lpass_cpu_regmap_writeable, 466 .readable_reg = lpass_cpu_regmap_readable, 467 .volatile_reg = lpass_cpu_regmap_volatile, 468 .cache_type = REGCACHE_FLAT, 469 }; 470 471 static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map) 472 { 473 struct lpass_data *drvdata = dev_get_drvdata(dev); 474 struct lpass_variant *v = drvdata->variant; 475 unsigned int i; 476 struct lpass_hdmi_tx_ctl *tx_ctl; 477 struct regmap_field *legacy_en; 478 struct lpass_vbit_ctrl *vbit_ctl; 479 struct regmap_field *tx_parity; 480 struct lpass_dp_metadata_ctl *meta_ctl; 481 struct lpass_sstream_ctl *sstream_ctl; 482 struct regmap_field *ch_msb; 483 struct regmap_field *ch_lsb; 484 struct lpass_hdmitx_dmactl *tx_dmactl; 485 int rval; 486 487 tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL); 488 if (!tx_ctl) 489 return -ENOMEM; 490 491 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset); 492 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset); 493 drvdata->tx_ctl = tx_ctl; 494 495 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en); 496 drvdata->hdmitx_legacy_en = legacy_en; 497 498 vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL); 499 if (!vbit_ctl) 500 return -ENOMEM; 501 502 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit); 503 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream); 504 drvdata->vbit_ctl = vbit_ctl; 505 506 507 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity); 508 drvdata->hdmitx_parity_calc_en = tx_parity; 509 510 meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL); 511 if (!meta_ctl) 512 return -ENOMEM; 513 514 rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7); 515 if (rval) 516 return rval; 517 drvdata->meta_ctl = meta_ctl; 518 519 sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL); 520 if (!sstream_ctl) 521 return -ENOMEM; 522 523 rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9); 524 if (rval) 525 return rval; 526 527 drvdata->sstream_ctl = sstream_ctl; 528 529 for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) { 530 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb); 531 drvdata->hdmitx_ch_msb[i] = ch_msb; 532 533 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb); 534 drvdata->hdmitx_ch_lsb[i] = ch_lsb; 535 536 tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL); 537 if (!tx_dmactl) 538 return -ENOMEM; 539 540 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs); 541 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr); 542 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel); 543 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel); 544 drvdata->hdmi_tx_dmactl[i] = tx_dmactl; 545 } 546 return 0; 547 } 548 549 static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg) 550 { 551 struct lpass_data *drvdata = dev_get_drvdata(dev); 552 struct lpass_variant *v = drvdata->variant; 553 int i; 554 555 if (reg == LPASS_HDMI_TX_CTL_ADDR(v)) 556 return true; 557 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 558 return true; 559 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) 560 return true; 561 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v)) 562 return true; 563 if (reg == LPASS_HDMI_TX_DP_ADDR(v)) 564 return true; 565 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v)) 566 return true; 567 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v)) 568 return true; 569 if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v)) 570 return true; 571 572 for (i = 0; i < v->hdmi_rdma_channels; i++) { 573 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) 574 return true; 575 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) 576 return true; 577 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) 578 return true; 579 } 580 581 for (i = 0; i < v->rdma_channels; ++i) { 582 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i)) 583 return true; 584 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i)) 585 return true; 586 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i)) 587 return true; 588 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i)) 589 return true; 590 } 591 return false; 592 } 593 594 static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg) 595 { 596 struct lpass_data *drvdata = dev_get_drvdata(dev); 597 struct lpass_variant *v = drvdata->variant; 598 int i; 599 600 if (reg == LPASS_HDMI_TX_CTL_ADDR(v)) 601 return true; 602 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 603 return true; 604 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) 605 return true; 606 607 for (i = 0; i < v->hdmi_rdma_channels; i++) { 608 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) 609 return true; 610 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) 611 return true; 612 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) 613 return true; 614 } 615 616 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v)) 617 return true; 618 if (reg == LPASS_HDMI_TX_DP_ADDR(v)) 619 return true; 620 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v)) 621 return true; 622 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v)) 623 return true; 624 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v)) 625 return true; 626 627 for (i = 0; i < v->rdma_channels; ++i) { 628 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i)) 629 return true; 630 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i)) 631 return true; 632 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i)) 633 return true; 634 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i)) 635 return true; 636 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) 637 return true; 638 } 639 640 return false; 641 } 642 643 static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg) 644 { 645 struct lpass_data *drvdata = dev_get_drvdata(dev); 646 struct lpass_variant *v = drvdata->variant; 647 int i; 648 649 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v)) 650 return true; 651 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) 652 return true; 653 654 for (i = 0; i < v->rdma_channels; ++i) { 655 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) 656 return true; 657 } 658 return false; 659 } 660 661 static struct regmap_config lpass_hdmi_regmap_config = { 662 .name = "lpass_hdmi", 663 .reg_bits = 32, 664 .reg_stride = 4, 665 .val_bits = 32, 666 .writeable_reg = lpass_hdmi_regmap_writeable, 667 .readable_reg = lpass_hdmi_regmap_readable, 668 .volatile_reg = lpass_hdmi_regmap_volatile, 669 .cache_type = REGCACHE_FLAT, 670 }; 671 672 static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev, 673 struct device_node *node, 674 const char *name) 675 { 676 unsigned int lines[LPASS_CPU_MAX_MI2S_LINES]; 677 unsigned int sd_line_mask = 0; 678 int num_lines, i; 679 680 num_lines = of_property_read_variable_u32_array(node, name, lines, 0, 681 LPASS_CPU_MAX_MI2S_LINES); 682 if (num_lines < 0) 683 return LPAIF_I2SCTL_MODE_NONE; 684 685 for (i = 0; i < num_lines; i++) 686 sd_line_mask |= BIT(lines[i]); 687 688 switch (sd_line_mask) { 689 case LPASS_CPU_I2S_SD0_MASK: 690 return LPAIF_I2SCTL_MODE_SD0; 691 case LPASS_CPU_I2S_SD1_MASK: 692 return LPAIF_I2SCTL_MODE_SD1; 693 case LPASS_CPU_I2S_SD2_MASK: 694 return LPAIF_I2SCTL_MODE_SD2; 695 case LPASS_CPU_I2S_SD3_MASK: 696 return LPAIF_I2SCTL_MODE_SD3; 697 case LPASS_CPU_I2S_SD0_1_MASK: 698 return LPAIF_I2SCTL_MODE_QUAD01; 699 case LPASS_CPU_I2S_SD2_3_MASK: 700 return LPAIF_I2SCTL_MODE_QUAD23; 701 case LPASS_CPU_I2S_SD0_1_2_MASK: 702 return LPAIF_I2SCTL_MODE_6CH; 703 case LPASS_CPU_I2S_SD0_1_2_3_MASK: 704 return LPAIF_I2SCTL_MODE_8CH; 705 default: 706 dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask); 707 return LPAIF_I2SCTL_MODE_NONE; 708 } 709 } 710 711 static void of_lpass_cpu_parse_dai_data(struct device *dev, 712 struct lpass_data *data) 713 { 714 struct device_node *node; 715 int ret, id; 716 717 /* Allow all channels by default for backwards compatibility */ 718 for (id = 0; id < data->variant->num_dai; id++) { 719 data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH; 720 data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH; 721 } 722 723 for_each_child_of_node(dev->of_node, node) { 724 ret = of_property_read_u32(node, "reg", &id); 725 if (ret || id < 0 || id >= data->variant->num_dai) { 726 dev_err(dev, "valid dai id not found: %d\n", ret); 727 continue; 728 } 729 if (id == LPASS_DP_RX) { 730 data->hdmi_port_enable = 1; 731 } else { 732 data->mi2s_playback_sd_mode[id] = 733 of_lpass_cpu_parse_sd_lines(dev, node, 734 "qcom,playback-sd-lines"); 735 data->mi2s_capture_sd_mode[id] = 736 of_lpass_cpu_parse_sd_lines(dev, node, 737 "qcom,capture-sd-lines"); 738 } 739 } 740 } 741 742 int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) 743 { 744 struct lpass_data *drvdata; 745 struct device_node *dsp_of_node; 746 struct resource *res; 747 struct lpass_variant *variant; 748 struct device *dev = &pdev->dev; 749 const struct of_device_id *match; 750 int ret, i, dai_id; 751 752 dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0); 753 if (dsp_of_node) { 754 dev_err(dev, "DSP exists and holds audio resources\n"); 755 return -EBUSY; 756 } 757 758 drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL); 759 if (!drvdata) 760 return -ENOMEM; 761 platform_set_drvdata(pdev, drvdata); 762 763 match = of_match_device(dev->driver->of_match_table, dev); 764 if (!match || !match->data) 765 return -EINVAL; 766 767 drvdata->variant = (struct lpass_variant *)match->data; 768 variant = drvdata->variant; 769 770 of_lpass_cpu_parse_dai_data(dev, drvdata); 771 772 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif"); 773 774 drvdata->lpaif = devm_ioremap_resource(dev, res); 775 if (IS_ERR(drvdata->lpaif)) 776 return PTR_ERR(drvdata->lpaif); 777 778 lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant, 779 variant->wrdma_channels + 780 variant->wrdma_channel_start); 781 782 drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif, 783 &lpass_cpu_regmap_config); 784 if (IS_ERR(drvdata->lpaif_map)) { 785 dev_err(dev, "error initializing regmap: %ld\n", 786 PTR_ERR(drvdata->lpaif_map)); 787 return PTR_ERR(drvdata->lpaif_map); 788 } 789 790 if (drvdata->hdmi_port_enable) { 791 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-hdmiif"); 792 793 drvdata->hdmiif = devm_ioremap_resource(dev, res); 794 if (IS_ERR(drvdata->hdmiif)) 795 return PTR_ERR(drvdata->hdmiif); 796 797 lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant, 798 variant->hdmi_rdma_channels); 799 drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif, 800 &lpass_hdmi_regmap_config); 801 if (IS_ERR(drvdata->hdmiif_map)) { 802 dev_err(dev, "error initializing regmap: %ld\n", 803 PTR_ERR(drvdata->hdmiif_map)); 804 return PTR_ERR(drvdata->hdmiif_map); 805 } 806 } 807 808 if (variant->init) { 809 ret = variant->init(pdev); 810 if (ret) { 811 dev_err(dev, "error initializing variant: %d\n", ret); 812 return ret; 813 } 814 } 815 816 for (i = 0; i < variant->num_dai; i++) { 817 dai_id = variant->dai_driver[i].id; 818 if (dai_id == LPASS_DP_RX) 819 continue; 820 821 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(dev, 822 variant->dai_osr_clk_names[i]); 823 if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) { 824 dev_warn(dev, 825 "%s() error getting optional %s: %ld\n", 826 __func__, 827 variant->dai_osr_clk_names[i], 828 PTR_ERR(drvdata->mi2s_osr_clk[dai_id])); 829 830 drvdata->mi2s_osr_clk[dai_id] = NULL; 831 } 832 833 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev, 834 variant->dai_bit_clk_names[i]); 835 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) { 836 dev_err(dev, 837 "error getting %s: %ld\n", 838 variant->dai_bit_clk_names[i], 839 PTR_ERR(drvdata->mi2s_bit_clk[dai_id])); 840 return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]); 841 } 842 drvdata->bit_clk_state[dai_id] = LPAIF_BIT_CLK_DISABLE; 843 } 844 845 /* Allocation for i2sctl regmap fields */ 846 drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl), 847 GFP_KERNEL); 848 849 /* Initialize bitfields for dai I2SCTL register */ 850 ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl, 851 drvdata->lpaif_map); 852 if (ret) { 853 dev_err(dev, "error init i2sctl field: %d\n", ret); 854 return ret; 855 } 856 857 if (drvdata->hdmi_port_enable) { 858 ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map); 859 if (ret) { 860 dev_err(dev, "%s error hdmi init failed\n", __func__); 861 return ret; 862 } 863 } 864 ret = devm_snd_soc_register_component(dev, 865 &lpass_cpu_comp_driver, 866 variant->dai_driver, 867 variant->num_dai); 868 if (ret) { 869 dev_err(dev, "error registering cpu driver: %d\n", ret); 870 goto err; 871 } 872 873 ret = asoc_qcom_lpass_platform_register(pdev); 874 if (ret) { 875 dev_err(dev, "error registering platform driver: %d\n", ret); 876 goto err; 877 } 878 879 err: 880 return ret; 881 } 882 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe); 883 884 int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev) 885 { 886 struct lpass_data *drvdata = platform_get_drvdata(pdev); 887 888 if (drvdata->variant->exit) 889 drvdata->variant->exit(pdev); 890 891 892 return 0; 893 } 894 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove); 895 896 void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev) 897 { 898 struct lpass_data *drvdata = platform_get_drvdata(pdev); 899 900 if (drvdata->variant->exit) 901 drvdata->variant->exit(pdev); 902 903 } 904 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_shutdown); 905 906 MODULE_DESCRIPTION("QTi LPASS CPU Driver"); 907 MODULE_LICENSE("GPL v2"); 908