11a59d1b8SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2fa375d42SZhangfei Gao /* 3fa375d42SZhangfei Gao * linux/sound/soc/pxa/mmp-sspa.c 4fa375d42SZhangfei Gao * Base on pxa2xx-ssp.c 5fa375d42SZhangfei Gao * 6fa375d42SZhangfei Gao * Copyright (C) 2011 Marvell International Ltd. 7fa375d42SZhangfei Gao */ 8fa375d42SZhangfei Gao #include <linux/init.h> 9fa375d42SZhangfei Gao #include <linux/module.h> 10fa375d42SZhangfei Gao #include <linux/platform_device.h> 11fa375d42SZhangfei Gao #include <linux/delay.h> 12fa375d42SZhangfei Gao #include <linux/clk.h> 13fa375d42SZhangfei Gao #include <linux/slab.h> 14fa375d42SZhangfei Gao #include <linux/pxa2xx_ssp.h> 15fa375d42SZhangfei Gao #include <linux/io.h> 16d65a1458SDaniel Mack #include <linux/dmaengine.h> 17d65a1458SDaniel Mack 18fa375d42SZhangfei Gao #include <sound/core.h> 19fa375d42SZhangfei Gao #include <sound/pcm.h> 20fa375d42SZhangfei Gao #include <sound/initval.h> 21fa375d42SZhangfei Gao #include <sound/pcm_params.h> 22fa375d42SZhangfei Gao #include <sound/soc.h> 23fa375d42SZhangfei Gao #include <sound/pxa2xx-lib.h> 24d65a1458SDaniel Mack #include <sound/dmaengine_pcm.h> 25fa375d42SZhangfei Gao #include "mmp-sspa.h" 26fa375d42SZhangfei Gao 27fa375d42SZhangfei Gao /* 28fa375d42SZhangfei Gao * SSPA audio private data 29fa375d42SZhangfei Gao */ 30fa375d42SZhangfei Gao struct sspa_priv { 31fa375d42SZhangfei Gao struct ssp_device *sspa; 32c9aeda1cSLubomir Rintel struct snd_dmaengine_dai_dma_data playback_dma_data; 33c9aeda1cSLubomir Rintel struct snd_dmaengine_dai_dma_data capture_dma_data; 34fa375d42SZhangfei Gao struct clk *audio_clk; 35fa375d42SZhangfei Gao struct clk *sysclk; 36fa375d42SZhangfei Gao int dai_fmt; 37fa375d42SZhangfei Gao int running_cnt; 38fa375d42SZhangfei Gao }; 39fa375d42SZhangfei Gao 40fa375d42SZhangfei Gao static void mmp_sspa_write_reg(struct ssp_device *sspa, u32 reg, u32 val) 41fa375d42SZhangfei Gao { 42fa375d42SZhangfei Gao __raw_writel(val, sspa->mmio_base + reg); 43fa375d42SZhangfei Gao } 44fa375d42SZhangfei Gao 45fa375d42SZhangfei Gao static u32 mmp_sspa_read_reg(struct ssp_device *sspa, u32 reg) 46fa375d42SZhangfei Gao { 47fa375d42SZhangfei Gao return __raw_readl(sspa->mmio_base + reg); 48fa375d42SZhangfei Gao } 49fa375d42SZhangfei Gao 50fa375d42SZhangfei Gao static void mmp_sspa_tx_enable(struct ssp_device *sspa) 51fa375d42SZhangfei Gao { 52fa375d42SZhangfei Gao unsigned int sspa_sp; 53fa375d42SZhangfei Gao 54fa375d42SZhangfei Gao sspa_sp = mmp_sspa_read_reg(sspa, SSPA_TXSP); 55fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_S_EN; 56fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_WEN; 57fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp); 58fa375d42SZhangfei Gao } 59fa375d42SZhangfei Gao 60fa375d42SZhangfei Gao static void mmp_sspa_tx_disable(struct ssp_device *sspa) 61fa375d42SZhangfei Gao { 62fa375d42SZhangfei Gao unsigned int sspa_sp; 63fa375d42SZhangfei Gao 64fa375d42SZhangfei Gao sspa_sp = mmp_sspa_read_reg(sspa, SSPA_TXSP); 65fa375d42SZhangfei Gao sspa_sp &= ~SSPA_SP_S_EN; 66fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_WEN; 67fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp); 68fa375d42SZhangfei Gao } 69fa375d42SZhangfei Gao 70fa375d42SZhangfei Gao static void mmp_sspa_rx_enable(struct ssp_device *sspa) 71fa375d42SZhangfei Gao { 72fa375d42SZhangfei Gao unsigned int sspa_sp; 73fa375d42SZhangfei Gao 74fa375d42SZhangfei Gao sspa_sp = mmp_sspa_read_reg(sspa, SSPA_RXSP); 75fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_S_EN; 76fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_WEN; 77fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_RXSP, sspa_sp); 78fa375d42SZhangfei Gao } 79fa375d42SZhangfei Gao 80fa375d42SZhangfei Gao static void mmp_sspa_rx_disable(struct ssp_device *sspa) 81fa375d42SZhangfei Gao { 82fa375d42SZhangfei Gao unsigned int sspa_sp; 83fa375d42SZhangfei Gao 84fa375d42SZhangfei Gao sspa_sp = mmp_sspa_read_reg(sspa, SSPA_RXSP); 85fa375d42SZhangfei Gao sspa_sp &= ~SSPA_SP_S_EN; 86fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_WEN; 87fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_RXSP, sspa_sp); 88fa375d42SZhangfei Gao } 89fa375d42SZhangfei Gao 90fa375d42SZhangfei Gao static int mmp_sspa_startup(struct snd_pcm_substream *substream, 91fa375d42SZhangfei Gao struct snd_soc_dai *dai) 92fa375d42SZhangfei Gao { 93fa375d42SZhangfei Gao struct sspa_priv *priv = snd_soc_dai_get_drvdata(dai); 94fa375d42SZhangfei Gao 95fa375d42SZhangfei Gao clk_enable(priv->sysclk); 96fa375d42SZhangfei Gao clk_enable(priv->sspa->clk); 97fa375d42SZhangfei Gao 98fa375d42SZhangfei Gao return 0; 99fa375d42SZhangfei Gao } 100fa375d42SZhangfei Gao 101fa375d42SZhangfei Gao static void mmp_sspa_shutdown(struct snd_pcm_substream *substream, 102fa375d42SZhangfei Gao struct snd_soc_dai *dai) 103fa375d42SZhangfei Gao { 104fa375d42SZhangfei Gao struct sspa_priv *priv = snd_soc_dai_get_drvdata(dai); 105fa375d42SZhangfei Gao 106fa375d42SZhangfei Gao clk_disable(priv->sspa->clk); 107fa375d42SZhangfei Gao clk_disable(priv->sysclk); 108fa375d42SZhangfei Gao 109fa375d42SZhangfei Gao } 110fa375d42SZhangfei Gao 111fa375d42SZhangfei Gao /* 112fa375d42SZhangfei Gao * Set the SSP ports SYSCLK. 113fa375d42SZhangfei Gao */ 114fa375d42SZhangfei Gao static int mmp_sspa_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 115fa375d42SZhangfei Gao int clk_id, unsigned int freq, int dir) 116fa375d42SZhangfei Gao { 117fa375d42SZhangfei Gao struct sspa_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); 118fa375d42SZhangfei Gao int ret = 0; 119fa375d42SZhangfei Gao 120fa375d42SZhangfei Gao switch (clk_id) { 121fa375d42SZhangfei Gao case MMP_SSPA_CLK_AUDIO: 122fa375d42SZhangfei Gao ret = clk_set_rate(priv->audio_clk, freq); 123fa375d42SZhangfei Gao if (ret) 124fa375d42SZhangfei Gao return ret; 125fa375d42SZhangfei Gao break; 126fa375d42SZhangfei Gao case MMP_SSPA_CLK_PLL: 127fa375d42SZhangfei Gao case MMP_SSPA_CLK_VCXO: 128fa375d42SZhangfei Gao /* not support yet */ 129fa375d42SZhangfei Gao return -EINVAL; 130fa375d42SZhangfei Gao default: 131fa375d42SZhangfei Gao return -EINVAL; 132fa375d42SZhangfei Gao } 133fa375d42SZhangfei Gao 134fa375d42SZhangfei Gao return 0; 135fa375d42SZhangfei Gao } 136fa375d42SZhangfei Gao 137fa375d42SZhangfei Gao static int mmp_sspa_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id, 138fa375d42SZhangfei Gao int source, unsigned int freq_in, 139fa375d42SZhangfei Gao unsigned int freq_out) 140fa375d42SZhangfei Gao { 141fa375d42SZhangfei Gao struct sspa_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); 142fa375d42SZhangfei Gao int ret = 0; 143fa375d42SZhangfei Gao 144fa375d42SZhangfei Gao switch (pll_id) { 145fa375d42SZhangfei Gao case MMP_SYSCLK: 146fa375d42SZhangfei Gao ret = clk_set_rate(priv->sysclk, freq_out); 147fa375d42SZhangfei Gao if (ret) 148fa375d42SZhangfei Gao return ret; 149fa375d42SZhangfei Gao break; 150fa375d42SZhangfei Gao case MMP_SSPA_CLK: 151fa375d42SZhangfei Gao ret = clk_set_rate(priv->sspa->clk, freq_out); 152fa375d42SZhangfei Gao if (ret) 153fa375d42SZhangfei Gao return ret; 154fa375d42SZhangfei Gao break; 155fa375d42SZhangfei Gao default: 156fa375d42SZhangfei Gao return -ENODEV; 157fa375d42SZhangfei Gao } 158fa375d42SZhangfei Gao 159fa375d42SZhangfei Gao return 0; 160fa375d42SZhangfei Gao } 161fa375d42SZhangfei Gao 162fa375d42SZhangfei Gao /* 163fa375d42SZhangfei Gao * Set up the sspa dai format. The sspa port must be inactive 164fa375d42SZhangfei Gao * before calling this function as the physical 165fa375d42SZhangfei Gao * interface format is changed. 166fa375d42SZhangfei Gao */ 167fa375d42SZhangfei Gao static int mmp_sspa_set_dai_fmt(struct snd_soc_dai *cpu_dai, 168fa375d42SZhangfei Gao unsigned int fmt) 169fa375d42SZhangfei Gao { 170fa375d42SZhangfei Gao struct sspa_priv *sspa_priv = snd_soc_dai_get_drvdata(cpu_dai); 171fa375d42SZhangfei Gao struct ssp_device *sspa = sspa_priv->sspa; 172fa375d42SZhangfei Gao u32 sspa_sp, sspa_ctrl; 173fa375d42SZhangfei Gao 174fa375d42SZhangfei Gao /* check if we need to change anything at all */ 175fa375d42SZhangfei Gao if (sspa_priv->dai_fmt == fmt) 176fa375d42SZhangfei Gao return 0; 177fa375d42SZhangfei Gao 178fa375d42SZhangfei Gao /* we can only change the settings if the port is not in use */ 179fa375d42SZhangfei Gao if ((mmp_sspa_read_reg(sspa, SSPA_TXSP) & SSPA_SP_S_EN) || 180fa375d42SZhangfei Gao (mmp_sspa_read_reg(sspa, SSPA_RXSP) & SSPA_SP_S_EN)) { 1814f3d9577SAndy Shevchenko dev_err(sspa->dev, 182fa375d42SZhangfei Gao "can't change hardware dai format: stream is in use\n"); 183fa375d42SZhangfei Gao return -EINVAL; 184fa375d42SZhangfei Gao } 185fa375d42SZhangfei Gao 186fa375d42SZhangfei Gao /* reset port settings */ 187fa375d42SZhangfei Gao sspa_sp = SSPA_SP_WEN | SSPA_SP_S_RST | SSPA_SP_FFLUSH; 188fa375d42SZhangfei Gao sspa_ctrl = 0; 189fa375d42SZhangfei Gao 190fa375d42SZhangfei Gao switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 191fa375d42SZhangfei Gao case SND_SOC_DAIFMT_CBS_CFS: 192fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_MSL; 193fa375d42SZhangfei Gao break; 194fa375d42SZhangfei Gao case SND_SOC_DAIFMT_CBM_CFM: 195fa375d42SZhangfei Gao break; 196fa375d42SZhangfei Gao default: 197fa375d42SZhangfei Gao return -EINVAL; 198fa375d42SZhangfei Gao } 199fa375d42SZhangfei Gao 200fa375d42SZhangfei Gao switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 201fa375d42SZhangfei Gao case SND_SOC_DAIFMT_NB_NF: 202fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_FSP; 203fa375d42SZhangfei Gao break; 204fa375d42SZhangfei Gao default: 205fa375d42SZhangfei Gao return -EINVAL; 206fa375d42SZhangfei Gao } 207fa375d42SZhangfei Gao 208fa375d42SZhangfei Gao switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 209fa375d42SZhangfei Gao case SND_SOC_DAIFMT_I2S: 210fa375d42SZhangfei Gao sspa_sp |= SSPA_TXSP_FPER(63); 211fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_FWID(31); 212fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XDATDLY(1); 213fa375d42SZhangfei Gao break; 214fa375d42SZhangfei Gao default: 215fa375d42SZhangfei Gao return -EINVAL; 216fa375d42SZhangfei Gao } 217fa375d42SZhangfei Gao 218fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp); 219fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_RXSP, sspa_sp); 220fa375d42SZhangfei Gao 221fa375d42SZhangfei Gao sspa_sp &= ~(SSPA_SP_S_RST | SSPA_SP_FFLUSH); 222fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp); 223fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_RXSP, sspa_sp); 224fa375d42SZhangfei Gao 225fa375d42SZhangfei Gao /* 226fa375d42SZhangfei Gao * FIXME: hw issue, for the tx serial port, 227fa375d42SZhangfei Gao * can not config the master/slave mode; 228fa375d42SZhangfei Gao * so must clean this bit. 229fa375d42SZhangfei Gao * The master/slave mode has been set in the 230fa375d42SZhangfei Gao * rx port. 231fa375d42SZhangfei Gao */ 232fa375d42SZhangfei Gao sspa_sp &= ~SSPA_SP_MSL; 233fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp); 234fa375d42SZhangfei Gao 235fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXCTL, sspa_ctrl); 236fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_RXCTL, sspa_ctrl); 237fa375d42SZhangfei Gao 238fa375d42SZhangfei Gao /* Since we are configuring the timings for the format by hand 239fa375d42SZhangfei Gao * we have to defer some things until hw_params() where we 240fa375d42SZhangfei Gao * know parameters like the sample size. 241fa375d42SZhangfei Gao */ 242fa375d42SZhangfei Gao sspa_priv->dai_fmt = fmt; 243fa375d42SZhangfei Gao return 0; 244fa375d42SZhangfei Gao } 245fa375d42SZhangfei Gao 246fa375d42SZhangfei Gao /* 247fa375d42SZhangfei Gao * Set the SSPA audio DMA parameters and sample size. 248fa375d42SZhangfei Gao * Can be called multiple times by oss emulation. 249fa375d42SZhangfei Gao */ 250fa375d42SZhangfei Gao static int mmp_sspa_hw_params(struct snd_pcm_substream *substream, 251fa375d42SZhangfei Gao struct snd_pcm_hw_params *params, 252fa375d42SZhangfei Gao struct snd_soc_dai *dai) 253fa375d42SZhangfei Gao { 254fa375d42SZhangfei Gao struct sspa_priv *sspa_priv = snd_soc_dai_get_drvdata(dai); 255fa375d42SZhangfei Gao struct ssp_device *sspa = sspa_priv->sspa; 256fa375d42SZhangfei Gao u32 sspa_ctrl; 257fa375d42SZhangfei Gao 258fa375d42SZhangfei Gao if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 259fa375d42SZhangfei Gao sspa_ctrl = mmp_sspa_read_reg(sspa, SSPA_TXCTL); 260fa375d42SZhangfei Gao else 261fa375d42SZhangfei Gao sspa_ctrl = mmp_sspa_read_reg(sspa, SSPA_RXCTL); 262fa375d42SZhangfei Gao 263fa375d42SZhangfei Gao sspa_ctrl &= ~SSPA_CTL_XFRLEN1_MASK; 264fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XFRLEN1(params_channels(params) - 1); 265fa375d42SZhangfei Gao sspa_ctrl &= ~SSPA_CTL_XWDLEN1_MASK; 266fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XWDLEN1(SSPA_CTL_32_BITS); 267fa375d42SZhangfei Gao sspa_ctrl &= ~SSPA_CTL_XSSZ1_MASK; 268fa375d42SZhangfei Gao 269fa375d42SZhangfei Gao switch (params_format(params)) { 270fa375d42SZhangfei Gao case SNDRV_PCM_FORMAT_S8: 271fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XSSZ1(SSPA_CTL_8_BITS); 272fa375d42SZhangfei Gao break; 273fa375d42SZhangfei Gao case SNDRV_PCM_FORMAT_S16_LE: 274fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XSSZ1(SSPA_CTL_16_BITS); 275fa375d42SZhangfei Gao break; 276fa375d42SZhangfei Gao case SNDRV_PCM_FORMAT_S24_3LE: 277fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XSSZ1(SSPA_CTL_24_BITS); 278fa375d42SZhangfei Gao break; 279fa375d42SZhangfei Gao case SNDRV_PCM_FORMAT_S32_LE: 280fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XSSZ1(SSPA_CTL_32_BITS); 281fa375d42SZhangfei Gao break; 282fa375d42SZhangfei Gao default: 283fa375d42SZhangfei Gao return -EINVAL; 284fa375d42SZhangfei Gao } 285fa375d42SZhangfei Gao 286fa375d42SZhangfei Gao if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 287fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXCTL, sspa_ctrl); 288fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXFIFO_LL, 0x1); 289fa375d42SZhangfei Gao } else { 290fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_RXCTL, sspa_ctrl); 291fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_RXFIFO_UL, 0x0); 292fa375d42SZhangfei Gao } 293fa375d42SZhangfei Gao 294fa375d42SZhangfei Gao return 0; 295fa375d42SZhangfei Gao } 296fa375d42SZhangfei Gao 297fa375d42SZhangfei Gao static int mmp_sspa_trigger(struct snd_pcm_substream *substream, int cmd, 298fa375d42SZhangfei Gao struct snd_soc_dai *dai) 299fa375d42SZhangfei Gao { 300fa375d42SZhangfei Gao struct sspa_priv *sspa_priv = snd_soc_dai_get_drvdata(dai); 301fa375d42SZhangfei Gao struct ssp_device *sspa = sspa_priv->sspa; 302fa375d42SZhangfei Gao int ret = 0; 303fa375d42SZhangfei Gao 304fa375d42SZhangfei Gao switch (cmd) { 305fa375d42SZhangfei Gao case SNDRV_PCM_TRIGGER_START: 306fa375d42SZhangfei Gao case SNDRV_PCM_TRIGGER_RESUME: 307fa375d42SZhangfei Gao case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 308fa375d42SZhangfei Gao /* 309fa375d42SZhangfei Gao * whatever playback or capture, must enable rx. 310fa375d42SZhangfei Gao * this is a hw issue, so need check if rx has been 311fa375d42SZhangfei Gao * enabled or not; if has been enabled by another 312fa375d42SZhangfei Gao * stream, do not enable again. 313fa375d42SZhangfei Gao */ 314fa375d42SZhangfei Gao if (!sspa_priv->running_cnt) 315fa375d42SZhangfei Gao mmp_sspa_rx_enable(sspa); 316fa375d42SZhangfei Gao 317fa375d42SZhangfei Gao if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 318fa375d42SZhangfei Gao mmp_sspa_tx_enable(sspa); 319fa375d42SZhangfei Gao 320fa375d42SZhangfei Gao sspa_priv->running_cnt++; 321fa375d42SZhangfei Gao break; 322fa375d42SZhangfei Gao 323fa375d42SZhangfei Gao case SNDRV_PCM_TRIGGER_STOP: 324fa375d42SZhangfei Gao case SNDRV_PCM_TRIGGER_SUSPEND: 325fa375d42SZhangfei Gao case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 326fa375d42SZhangfei Gao sspa_priv->running_cnt--; 327fa375d42SZhangfei Gao 328fa375d42SZhangfei Gao if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 329fa375d42SZhangfei Gao mmp_sspa_tx_disable(sspa); 330fa375d42SZhangfei Gao 331fa375d42SZhangfei Gao /* have no capture stream, disable rx port */ 332fa375d42SZhangfei Gao if (!sspa_priv->running_cnt) 333fa375d42SZhangfei Gao mmp_sspa_rx_disable(sspa); 334fa375d42SZhangfei Gao break; 335fa375d42SZhangfei Gao 336fa375d42SZhangfei Gao default: 337fa375d42SZhangfei Gao ret = -EINVAL; 338fa375d42SZhangfei Gao } 339fa375d42SZhangfei Gao 340fa375d42SZhangfei Gao return ret; 341fa375d42SZhangfei Gao } 342fa375d42SZhangfei Gao 343fa375d42SZhangfei Gao static int mmp_sspa_probe(struct snd_soc_dai *dai) 344fa375d42SZhangfei Gao { 345fa375d42SZhangfei Gao struct sspa_priv *priv = dev_get_drvdata(dai->dev); 346fa375d42SZhangfei Gao 347c9aeda1cSLubomir Rintel snd_soc_dai_init_dma_data(dai, 348c9aeda1cSLubomir Rintel &priv->playback_dma_data, 349c9aeda1cSLubomir Rintel &priv->capture_dma_data); 350c9aeda1cSLubomir Rintel 351fa375d42SZhangfei Gao snd_soc_dai_set_drvdata(dai, priv); 352fa375d42SZhangfei Gao return 0; 353fa375d42SZhangfei Gao 354fa375d42SZhangfei Gao } 355fa375d42SZhangfei Gao 356fa375d42SZhangfei Gao #define MMP_SSPA_RATES SNDRV_PCM_RATE_8000_192000 357fa375d42SZhangfei Gao #define MMP_SSPA_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 358fa375d42SZhangfei Gao SNDRV_PCM_FMTBIT_S16_LE | \ 35900a1aca2SLubomir Rintel SNDRV_PCM_FMTBIT_S24_3LE | \ 360fa375d42SZhangfei Gao SNDRV_PCM_FMTBIT_S32_LE) 361fa375d42SZhangfei Gao 362cb753443SGustavo A. R. Silva static const struct snd_soc_dai_ops mmp_sspa_dai_ops = { 363fa375d42SZhangfei Gao .startup = mmp_sspa_startup, 364fa375d42SZhangfei Gao .shutdown = mmp_sspa_shutdown, 365fa375d42SZhangfei Gao .trigger = mmp_sspa_trigger, 366fa375d42SZhangfei Gao .hw_params = mmp_sspa_hw_params, 367fa375d42SZhangfei Gao .set_sysclk = mmp_sspa_set_dai_sysclk, 368fa375d42SZhangfei Gao .set_pll = mmp_sspa_set_dai_pll, 369fa375d42SZhangfei Gao .set_fmt = mmp_sspa_set_dai_fmt, 370fa375d42SZhangfei Gao }; 371fa375d42SZhangfei Gao 3725d9ff402SLars-Peter Clausen static struct snd_soc_dai_driver mmp_sspa_dai = { 373fa375d42SZhangfei Gao .probe = mmp_sspa_probe, 374fa375d42SZhangfei Gao .playback = { 375fa375d42SZhangfei Gao .channels_min = 1, 376fa375d42SZhangfei Gao .channels_max = 128, 377fa375d42SZhangfei Gao .rates = MMP_SSPA_RATES, 378fa375d42SZhangfei Gao .formats = MMP_SSPA_FORMATS, 379fa375d42SZhangfei Gao }, 380fa375d42SZhangfei Gao .capture = { 381fa375d42SZhangfei Gao .channels_min = 1, 382fa375d42SZhangfei Gao .channels_max = 2, 383fa375d42SZhangfei Gao .rates = MMP_SSPA_RATES, 384fa375d42SZhangfei Gao .formats = MMP_SSPA_FORMATS, 385fa375d42SZhangfei Gao }, 386fa375d42SZhangfei Gao .ops = &mmp_sspa_dai_ops, 387fa375d42SZhangfei Gao }; 388fa375d42SZhangfei Gao 389*724da053SLubomir Rintel #define MMP_PCM_INFO (SNDRV_PCM_INFO_MMAP | \ 390*724da053SLubomir Rintel SNDRV_PCM_INFO_MMAP_VALID | \ 391*724da053SLubomir Rintel SNDRV_PCM_INFO_INTERLEAVED | \ 392*724da053SLubomir Rintel SNDRV_PCM_INFO_PAUSE | \ 393*724da053SLubomir Rintel SNDRV_PCM_INFO_RESUME | \ 394*724da053SLubomir Rintel SNDRV_PCM_INFO_NO_PERIOD_WAKEUP) 395*724da053SLubomir Rintel 396*724da053SLubomir Rintel static const struct snd_pcm_hardware mmp_pcm_hardware[] = { 397*724da053SLubomir Rintel { 398*724da053SLubomir Rintel .info = MMP_PCM_INFO, 399*724da053SLubomir Rintel .period_bytes_min = 1024, 400*724da053SLubomir Rintel .period_bytes_max = 2048, 401*724da053SLubomir Rintel .periods_min = 2, 402*724da053SLubomir Rintel .periods_max = 32, 403*724da053SLubomir Rintel .buffer_bytes_max = 4096, 404*724da053SLubomir Rintel .fifo_size = 32, 405*724da053SLubomir Rintel }, 406*724da053SLubomir Rintel { 407*724da053SLubomir Rintel .info = MMP_PCM_INFO, 408*724da053SLubomir Rintel .period_bytes_min = 1024, 409*724da053SLubomir Rintel .period_bytes_max = 2048, 410*724da053SLubomir Rintel .periods_min = 2, 411*724da053SLubomir Rintel .periods_max = 32, 412*724da053SLubomir Rintel .buffer_bytes_max = 4096, 413*724da053SLubomir Rintel .fifo_size = 32, 414*724da053SLubomir Rintel }, 415*724da053SLubomir Rintel }; 416*724da053SLubomir Rintel 417*724da053SLubomir Rintel static const struct snd_dmaengine_pcm_config mmp_pcm_config = { 418*724da053SLubomir Rintel .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 419*724da053SLubomir Rintel .pcm_hardware = mmp_pcm_hardware, 420*724da053SLubomir Rintel .prealloc_buffer_size = 4096, 421*724da053SLubomir Rintel }; 422*724da053SLubomir Rintel 423*724da053SLubomir Rintel static int mmp_pcm_mmap(struct snd_soc_component *component, 424*724da053SLubomir Rintel struct snd_pcm_substream *substream, 425*724da053SLubomir Rintel struct vm_area_struct *vma) 426*724da053SLubomir Rintel { 427*724da053SLubomir Rintel vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP; 428*724da053SLubomir Rintel vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 429*724da053SLubomir Rintel return remap_pfn_range(vma, vma->vm_start, 430*724da053SLubomir Rintel substream->dma_buffer.addr >> PAGE_SHIFT, 431*724da053SLubomir Rintel vma->vm_end - vma->vm_start, vma->vm_page_prot); 432*724da053SLubomir Rintel } 433*724da053SLubomir Rintel 434425f3708SKuninori Morimoto static const struct snd_soc_component_driver mmp_sspa_component = { 435425f3708SKuninori Morimoto .name = "mmp-sspa", 436*724da053SLubomir Rintel .mmap = mmp_pcm_mmap, 437425f3708SKuninori Morimoto }; 438425f3708SKuninori Morimoto 439570f6fe1SBill Pemberton static int asoc_mmp_sspa_probe(struct platform_device *pdev) 440fa375d42SZhangfei Gao { 441fa375d42SZhangfei Gao struct sspa_priv *priv; 442fa375d42SZhangfei Gao 443fa375d42SZhangfei Gao priv = devm_kzalloc(&pdev->dev, 444fa375d42SZhangfei Gao sizeof(struct sspa_priv), GFP_KERNEL); 445fa375d42SZhangfei Gao if (!priv) 446fa375d42SZhangfei Gao return -ENOMEM; 447fa375d42SZhangfei Gao 448fa375d42SZhangfei Gao priv->sspa = devm_kzalloc(&pdev->dev, 449fa375d42SZhangfei Gao sizeof(struct ssp_device), GFP_KERNEL); 450fa375d42SZhangfei Gao if (priv->sspa == NULL) 451fa375d42SZhangfei Gao return -ENOMEM; 452fa375d42SZhangfei Gao 45372d09322SYueHaibing priv->sspa->mmio_base = devm_platform_ioremap_resource(pdev, 0); 454b25b5aa0SThierry Reding if (IS_ERR(priv->sspa->mmio_base)) 455b25b5aa0SThierry Reding return PTR_ERR(priv->sspa->mmio_base); 456fa375d42SZhangfei Gao 457fa375d42SZhangfei Gao priv->sspa->clk = devm_clk_get(&pdev->dev, NULL); 458fa375d42SZhangfei Gao if (IS_ERR(priv->sspa->clk)) 459fa375d42SZhangfei Gao return PTR_ERR(priv->sspa->clk); 460fa375d42SZhangfei Gao 461fa375d42SZhangfei Gao priv->audio_clk = clk_get(NULL, "mmp-audio"); 462fa375d42SZhangfei Gao if (IS_ERR(priv->audio_clk)) 463fa375d42SZhangfei Gao return PTR_ERR(priv->audio_clk); 464fa375d42SZhangfei Gao 465fa375d42SZhangfei Gao priv->sysclk = clk_get(NULL, "mmp-sysclk"); 466fa375d42SZhangfei Gao if (IS_ERR(priv->sysclk)) { 467fa375d42SZhangfei Gao clk_put(priv->audio_clk); 468fa375d42SZhangfei Gao return PTR_ERR(priv->sysclk); 469fa375d42SZhangfei Gao } 470fa375d42SZhangfei Gao clk_enable(priv->audio_clk); 471fa375d42SZhangfei Gao priv->dai_fmt = (unsigned int) -1; 472fa375d42SZhangfei Gao platform_set_drvdata(pdev, priv); 473fa375d42SZhangfei Gao 474*724da053SLubomir Rintel priv->playback_dma_data.maxburst = 4; 475*724da053SLubomir Rintel priv->capture_dma_data.maxburst = 4; 476c9aeda1cSLubomir Rintel /* You know, these addresses are actually ignored. */ 477c9aeda1cSLubomir Rintel priv->playback_dma_data.addr = SSPA_TXD; 478c9aeda1cSLubomir Rintel priv->capture_dma_data.addr = SSPA_RXD; 479c9aeda1cSLubomir Rintel 480*724da053SLubomir Rintel if (pdev->dev.of_node) { 481*724da053SLubomir Rintel int ret; 482*724da053SLubomir Rintel 483*724da053SLubomir Rintel ret = devm_snd_dmaengine_pcm_register(&pdev->dev, 484*724da053SLubomir Rintel &mmp_pcm_config, 0); 485*724da053SLubomir Rintel if (ret) 486*724da053SLubomir Rintel return ret; 487*724da053SLubomir Rintel } 488*724da053SLubomir Rintel 4899ff50721SSachin Kamat return devm_snd_soc_register_component(&pdev->dev, &mmp_sspa_component, 490425f3708SKuninori Morimoto &mmp_sspa_dai, 1); 491fa375d42SZhangfei Gao } 492fa375d42SZhangfei Gao 493570f6fe1SBill Pemberton static int asoc_mmp_sspa_remove(struct platform_device *pdev) 494fa375d42SZhangfei Gao { 495fa375d42SZhangfei Gao struct sspa_priv *priv = platform_get_drvdata(pdev); 496fa375d42SZhangfei Gao 497fa375d42SZhangfei Gao clk_disable(priv->audio_clk); 498fa375d42SZhangfei Gao clk_put(priv->audio_clk); 499fa375d42SZhangfei Gao clk_put(priv->sysclk); 500fa375d42SZhangfei Gao return 0; 501fa375d42SZhangfei Gao } 502fa375d42SZhangfei Gao 503fa375d42SZhangfei Gao static struct platform_driver asoc_mmp_sspa_driver = { 504fa375d42SZhangfei Gao .driver = { 505fa375d42SZhangfei Gao .name = "mmp-sspa-dai", 506fa375d42SZhangfei Gao }, 507fa375d42SZhangfei Gao .probe = asoc_mmp_sspa_probe, 508570f6fe1SBill Pemberton .remove = asoc_mmp_sspa_remove, 509fa375d42SZhangfei Gao }; 510fa375d42SZhangfei Gao 511fa375d42SZhangfei Gao module_platform_driver(asoc_mmp_sspa_driver); 512fa375d42SZhangfei Gao 513fa375d42SZhangfei Gao MODULE_AUTHOR("Leo Yan <leoy@marvell.com>"); 514fa375d42SZhangfei Gao MODULE_DESCRIPTION("MMP SSPA SoC Interface"); 515fa375d42SZhangfei Gao MODULE_LICENSE("GPL"); 516e5b7d71aSAndrea Adami MODULE_ALIAS("platform:mmp-sspa-dai"); 517