1fa375d42SZhangfei Gao /* 2fa375d42SZhangfei Gao * linux/sound/soc/pxa/mmp-sspa.c 3fa375d42SZhangfei Gao * Base on pxa2xx-ssp.c 4fa375d42SZhangfei Gao * 5fa375d42SZhangfei Gao * Copyright (C) 2011 Marvell International Ltd. 6fa375d42SZhangfei Gao * 7fa375d42SZhangfei Gao * This program is free software; you can redistribute it and/or modify 8fa375d42SZhangfei Gao * it under the terms of the GNU General Public License as published by 9fa375d42SZhangfei Gao * the Free Software Foundation; either version 2 of the License, or 10fa375d42SZhangfei Gao * (at your option) any later version. 11fa375d42SZhangfei Gao * 12fa375d42SZhangfei Gao * This program is distributed in the hope that it will be useful, 13fa375d42SZhangfei Gao * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fa375d42SZhangfei Gao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15fa375d42SZhangfei Gao * GNU General Public License for more details. 16fa375d42SZhangfei Gao * 17fa375d42SZhangfei Gao * You should have received a copy of the GNU General Public License 18fa375d42SZhangfei Gao * along with this program; if not, write to the Free Software 19fa375d42SZhangfei Gao * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20fa375d42SZhangfei Gao * 21fa375d42SZhangfei Gao */ 22fa375d42SZhangfei Gao #include <linux/init.h> 23fa375d42SZhangfei Gao #include <linux/module.h> 24fa375d42SZhangfei Gao #include <linux/platform_device.h> 25fa375d42SZhangfei Gao #include <linux/delay.h> 26fa375d42SZhangfei Gao #include <linux/clk.h> 27fa375d42SZhangfei Gao #include <linux/slab.h> 28fa375d42SZhangfei Gao #include <linux/pxa2xx_ssp.h> 29fa375d42SZhangfei Gao #include <linux/io.h> 30fa375d42SZhangfei Gao #include <sound/core.h> 31fa375d42SZhangfei Gao #include <sound/pcm.h> 32fa375d42SZhangfei Gao #include <sound/initval.h> 33fa375d42SZhangfei Gao #include <sound/pcm_params.h> 34fa375d42SZhangfei Gao #include <sound/soc.h> 35fa375d42SZhangfei Gao #include <sound/pxa2xx-lib.h> 36fa375d42SZhangfei Gao #include "mmp-sspa.h" 37fa375d42SZhangfei Gao 38fa375d42SZhangfei Gao /* 39fa375d42SZhangfei Gao * SSPA audio private data 40fa375d42SZhangfei Gao */ 41fa375d42SZhangfei Gao struct sspa_priv { 42fa375d42SZhangfei Gao struct ssp_device *sspa; 43fa375d42SZhangfei Gao struct pxa2xx_pcm_dma_params *dma_params; 44fa375d42SZhangfei Gao struct clk *audio_clk; 45fa375d42SZhangfei Gao struct clk *sysclk; 46fa375d42SZhangfei Gao int dai_fmt; 47fa375d42SZhangfei Gao int running_cnt; 48fa375d42SZhangfei Gao }; 49fa375d42SZhangfei Gao 50fa375d42SZhangfei Gao static void mmp_sspa_write_reg(struct ssp_device *sspa, u32 reg, u32 val) 51fa375d42SZhangfei Gao { 52fa375d42SZhangfei Gao __raw_writel(val, sspa->mmio_base + reg); 53fa375d42SZhangfei Gao } 54fa375d42SZhangfei Gao 55fa375d42SZhangfei Gao static u32 mmp_sspa_read_reg(struct ssp_device *sspa, u32 reg) 56fa375d42SZhangfei Gao { 57fa375d42SZhangfei Gao return __raw_readl(sspa->mmio_base + reg); 58fa375d42SZhangfei Gao } 59fa375d42SZhangfei Gao 60fa375d42SZhangfei Gao static void mmp_sspa_tx_enable(struct ssp_device *sspa) 61fa375d42SZhangfei Gao { 62fa375d42SZhangfei Gao unsigned int sspa_sp; 63fa375d42SZhangfei Gao 64fa375d42SZhangfei Gao sspa_sp = mmp_sspa_read_reg(sspa, SSPA_TXSP); 65fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_S_EN; 66fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_WEN; 67fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp); 68fa375d42SZhangfei Gao } 69fa375d42SZhangfei Gao 70fa375d42SZhangfei Gao static void mmp_sspa_tx_disable(struct ssp_device *sspa) 71fa375d42SZhangfei Gao { 72fa375d42SZhangfei Gao unsigned int sspa_sp; 73fa375d42SZhangfei Gao 74fa375d42SZhangfei Gao sspa_sp = mmp_sspa_read_reg(sspa, SSPA_TXSP); 75fa375d42SZhangfei Gao sspa_sp &= ~SSPA_SP_S_EN; 76fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_WEN; 77fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp); 78fa375d42SZhangfei Gao } 79fa375d42SZhangfei Gao 80fa375d42SZhangfei Gao static void mmp_sspa_rx_enable(struct ssp_device *sspa) 81fa375d42SZhangfei Gao { 82fa375d42SZhangfei Gao unsigned int sspa_sp; 83fa375d42SZhangfei Gao 84fa375d42SZhangfei Gao sspa_sp = mmp_sspa_read_reg(sspa, SSPA_RXSP); 85fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_S_EN; 86fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_WEN; 87fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_RXSP, sspa_sp); 88fa375d42SZhangfei Gao } 89fa375d42SZhangfei Gao 90fa375d42SZhangfei Gao static void mmp_sspa_rx_disable(struct ssp_device *sspa) 91fa375d42SZhangfei Gao { 92fa375d42SZhangfei Gao unsigned int sspa_sp; 93fa375d42SZhangfei Gao 94fa375d42SZhangfei Gao sspa_sp = mmp_sspa_read_reg(sspa, SSPA_RXSP); 95fa375d42SZhangfei Gao sspa_sp &= ~SSPA_SP_S_EN; 96fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_WEN; 97fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_RXSP, sspa_sp); 98fa375d42SZhangfei Gao } 99fa375d42SZhangfei Gao 100fa375d42SZhangfei Gao static int mmp_sspa_startup(struct snd_pcm_substream *substream, 101fa375d42SZhangfei Gao struct snd_soc_dai *dai) 102fa375d42SZhangfei Gao { 103fa375d42SZhangfei Gao struct sspa_priv *priv = snd_soc_dai_get_drvdata(dai); 104fa375d42SZhangfei Gao 105fa375d42SZhangfei Gao clk_enable(priv->sysclk); 106fa375d42SZhangfei Gao clk_enable(priv->sspa->clk); 107fa375d42SZhangfei Gao 108fa375d42SZhangfei Gao return 0; 109fa375d42SZhangfei Gao } 110fa375d42SZhangfei Gao 111fa375d42SZhangfei Gao static void mmp_sspa_shutdown(struct snd_pcm_substream *substream, 112fa375d42SZhangfei Gao struct snd_soc_dai *dai) 113fa375d42SZhangfei Gao { 114fa375d42SZhangfei Gao struct sspa_priv *priv = snd_soc_dai_get_drvdata(dai); 115fa375d42SZhangfei Gao 116fa375d42SZhangfei Gao clk_disable(priv->sspa->clk); 117fa375d42SZhangfei Gao clk_disable(priv->sysclk); 118fa375d42SZhangfei Gao 119fa375d42SZhangfei Gao return; 120fa375d42SZhangfei Gao } 121fa375d42SZhangfei Gao 122fa375d42SZhangfei Gao /* 123fa375d42SZhangfei Gao * Set the SSP ports SYSCLK. 124fa375d42SZhangfei Gao */ 125fa375d42SZhangfei Gao static int mmp_sspa_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 126fa375d42SZhangfei Gao int clk_id, unsigned int freq, int dir) 127fa375d42SZhangfei Gao { 128fa375d42SZhangfei Gao struct sspa_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); 129fa375d42SZhangfei Gao int ret = 0; 130fa375d42SZhangfei Gao 131fa375d42SZhangfei Gao switch (clk_id) { 132fa375d42SZhangfei Gao case MMP_SSPA_CLK_AUDIO: 133fa375d42SZhangfei Gao ret = clk_set_rate(priv->audio_clk, freq); 134fa375d42SZhangfei Gao if (ret) 135fa375d42SZhangfei Gao return ret; 136fa375d42SZhangfei Gao break; 137fa375d42SZhangfei Gao case MMP_SSPA_CLK_PLL: 138fa375d42SZhangfei Gao case MMP_SSPA_CLK_VCXO: 139fa375d42SZhangfei Gao /* not support yet */ 140fa375d42SZhangfei Gao return -EINVAL; 141fa375d42SZhangfei Gao default: 142fa375d42SZhangfei Gao return -EINVAL; 143fa375d42SZhangfei Gao } 144fa375d42SZhangfei Gao 145fa375d42SZhangfei Gao return 0; 146fa375d42SZhangfei Gao } 147fa375d42SZhangfei Gao 148fa375d42SZhangfei Gao static int mmp_sspa_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id, 149fa375d42SZhangfei Gao int source, unsigned int freq_in, 150fa375d42SZhangfei Gao unsigned int freq_out) 151fa375d42SZhangfei Gao { 152fa375d42SZhangfei Gao struct sspa_priv *priv = snd_soc_dai_get_drvdata(cpu_dai); 153fa375d42SZhangfei Gao int ret = 0; 154fa375d42SZhangfei Gao 155fa375d42SZhangfei Gao switch (pll_id) { 156fa375d42SZhangfei Gao case MMP_SYSCLK: 157fa375d42SZhangfei Gao ret = clk_set_rate(priv->sysclk, freq_out); 158fa375d42SZhangfei Gao if (ret) 159fa375d42SZhangfei Gao return ret; 160fa375d42SZhangfei Gao break; 161fa375d42SZhangfei Gao case MMP_SSPA_CLK: 162fa375d42SZhangfei Gao ret = clk_set_rate(priv->sspa->clk, freq_out); 163fa375d42SZhangfei Gao if (ret) 164fa375d42SZhangfei Gao return ret; 165fa375d42SZhangfei Gao break; 166fa375d42SZhangfei Gao default: 167fa375d42SZhangfei Gao return -ENODEV; 168fa375d42SZhangfei Gao } 169fa375d42SZhangfei Gao 170fa375d42SZhangfei Gao return 0; 171fa375d42SZhangfei Gao } 172fa375d42SZhangfei Gao 173fa375d42SZhangfei Gao /* 174fa375d42SZhangfei Gao * Set up the sspa dai format. The sspa port must be inactive 175fa375d42SZhangfei Gao * before calling this function as the physical 176fa375d42SZhangfei Gao * interface format is changed. 177fa375d42SZhangfei Gao */ 178fa375d42SZhangfei Gao static int mmp_sspa_set_dai_fmt(struct snd_soc_dai *cpu_dai, 179fa375d42SZhangfei Gao unsigned int fmt) 180fa375d42SZhangfei Gao { 181fa375d42SZhangfei Gao struct sspa_priv *sspa_priv = snd_soc_dai_get_drvdata(cpu_dai); 182fa375d42SZhangfei Gao struct ssp_device *sspa = sspa_priv->sspa; 183fa375d42SZhangfei Gao u32 sspa_sp, sspa_ctrl; 184fa375d42SZhangfei Gao 185fa375d42SZhangfei Gao /* check if we need to change anything at all */ 186fa375d42SZhangfei Gao if (sspa_priv->dai_fmt == fmt) 187fa375d42SZhangfei Gao return 0; 188fa375d42SZhangfei Gao 189fa375d42SZhangfei Gao /* we can only change the settings if the port is not in use */ 190fa375d42SZhangfei Gao if ((mmp_sspa_read_reg(sspa, SSPA_TXSP) & SSPA_SP_S_EN) || 191fa375d42SZhangfei Gao (mmp_sspa_read_reg(sspa, SSPA_RXSP) & SSPA_SP_S_EN)) { 192fa375d42SZhangfei Gao dev_err(&sspa->pdev->dev, 193fa375d42SZhangfei Gao "can't change hardware dai format: stream is in use\n"); 194fa375d42SZhangfei Gao return -EINVAL; 195fa375d42SZhangfei Gao } 196fa375d42SZhangfei Gao 197fa375d42SZhangfei Gao /* reset port settings */ 198fa375d42SZhangfei Gao sspa_sp = SSPA_SP_WEN | SSPA_SP_S_RST | SSPA_SP_FFLUSH; 199fa375d42SZhangfei Gao sspa_ctrl = 0; 200fa375d42SZhangfei Gao 201fa375d42SZhangfei Gao switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 202fa375d42SZhangfei Gao case SND_SOC_DAIFMT_CBS_CFS: 203fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_MSL; 204fa375d42SZhangfei Gao break; 205fa375d42SZhangfei Gao case SND_SOC_DAIFMT_CBM_CFM: 206fa375d42SZhangfei Gao break; 207fa375d42SZhangfei Gao default: 208fa375d42SZhangfei Gao return -EINVAL; 209fa375d42SZhangfei Gao } 210fa375d42SZhangfei Gao 211fa375d42SZhangfei Gao switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 212fa375d42SZhangfei Gao case SND_SOC_DAIFMT_NB_NF: 213fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_FSP; 214fa375d42SZhangfei Gao break; 215fa375d42SZhangfei Gao default: 216fa375d42SZhangfei Gao return -EINVAL; 217fa375d42SZhangfei Gao } 218fa375d42SZhangfei Gao 219fa375d42SZhangfei Gao switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 220fa375d42SZhangfei Gao case SND_SOC_DAIFMT_I2S: 221fa375d42SZhangfei Gao sspa_sp |= SSPA_TXSP_FPER(63); 222fa375d42SZhangfei Gao sspa_sp |= SSPA_SP_FWID(31); 223fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XDATDLY(1); 224fa375d42SZhangfei Gao break; 225fa375d42SZhangfei Gao default: 226fa375d42SZhangfei Gao return -EINVAL; 227fa375d42SZhangfei Gao } 228fa375d42SZhangfei Gao 229fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp); 230fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_RXSP, sspa_sp); 231fa375d42SZhangfei Gao 232fa375d42SZhangfei Gao sspa_sp &= ~(SSPA_SP_S_RST | SSPA_SP_FFLUSH); 233fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp); 234fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_RXSP, sspa_sp); 235fa375d42SZhangfei Gao 236fa375d42SZhangfei Gao /* 237fa375d42SZhangfei Gao * FIXME: hw issue, for the tx serial port, 238fa375d42SZhangfei Gao * can not config the master/slave mode; 239fa375d42SZhangfei Gao * so must clean this bit. 240fa375d42SZhangfei Gao * The master/slave mode has been set in the 241fa375d42SZhangfei Gao * rx port. 242fa375d42SZhangfei Gao */ 243fa375d42SZhangfei Gao sspa_sp &= ~SSPA_SP_MSL; 244fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXSP, sspa_sp); 245fa375d42SZhangfei Gao 246fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXCTL, sspa_ctrl); 247fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_RXCTL, sspa_ctrl); 248fa375d42SZhangfei Gao 249fa375d42SZhangfei Gao /* Since we are configuring the timings for the format by hand 250fa375d42SZhangfei Gao * we have to defer some things until hw_params() where we 251fa375d42SZhangfei Gao * know parameters like the sample size. 252fa375d42SZhangfei Gao */ 253fa375d42SZhangfei Gao sspa_priv->dai_fmt = fmt; 254fa375d42SZhangfei Gao return 0; 255fa375d42SZhangfei Gao } 256fa375d42SZhangfei Gao 257fa375d42SZhangfei Gao /* 258fa375d42SZhangfei Gao * Set the SSPA audio DMA parameters and sample size. 259fa375d42SZhangfei Gao * Can be called multiple times by oss emulation. 260fa375d42SZhangfei Gao */ 261fa375d42SZhangfei Gao static int mmp_sspa_hw_params(struct snd_pcm_substream *substream, 262fa375d42SZhangfei Gao struct snd_pcm_hw_params *params, 263fa375d42SZhangfei Gao struct snd_soc_dai *dai) 264fa375d42SZhangfei Gao { 265fa375d42SZhangfei Gao struct snd_soc_pcm_runtime *rtd = substream->private_data; 266fa375d42SZhangfei Gao struct snd_soc_dai *cpu_dai = rtd->cpu_dai; 267fa375d42SZhangfei Gao struct sspa_priv *sspa_priv = snd_soc_dai_get_drvdata(dai); 268fa375d42SZhangfei Gao struct ssp_device *sspa = sspa_priv->sspa; 269fa375d42SZhangfei Gao struct pxa2xx_pcm_dma_params *dma_params; 270fa375d42SZhangfei Gao u32 sspa_ctrl; 271fa375d42SZhangfei Gao 272fa375d42SZhangfei Gao if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 273fa375d42SZhangfei Gao sspa_ctrl = mmp_sspa_read_reg(sspa, SSPA_TXCTL); 274fa375d42SZhangfei Gao else 275fa375d42SZhangfei Gao sspa_ctrl = mmp_sspa_read_reg(sspa, SSPA_RXCTL); 276fa375d42SZhangfei Gao 277fa375d42SZhangfei Gao sspa_ctrl &= ~SSPA_CTL_XFRLEN1_MASK; 278fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XFRLEN1(params_channels(params) - 1); 279fa375d42SZhangfei Gao sspa_ctrl &= ~SSPA_CTL_XWDLEN1_MASK; 280fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XWDLEN1(SSPA_CTL_32_BITS); 281fa375d42SZhangfei Gao sspa_ctrl &= ~SSPA_CTL_XSSZ1_MASK; 282fa375d42SZhangfei Gao 283fa375d42SZhangfei Gao switch (params_format(params)) { 284fa375d42SZhangfei Gao case SNDRV_PCM_FORMAT_S8: 285fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XSSZ1(SSPA_CTL_8_BITS); 286fa375d42SZhangfei Gao break; 287fa375d42SZhangfei Gao case SNDRV_PCM_FORMAT_S16_LE: 288fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XSSZ1(SSPA_CTL_16_BITS); 289fa375d42SZhangfei Gao break; 290fa375d42SZhangfei Gao case SNDRV_PCM_FORMAT_S20_3LE: 291fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XSSZ1(SSPA_CTL_20_BITS); 292fa375d42SZhangfei Gao break; 293fa375d42SZhangfei Gao case SNDRV_PCM_FORMAT_S24_3LE: 294fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XSSZ1(SSPA_CTL_24_BITS); 295fa375d42SZhangfei Gao break; 296fa375d42SZhangfei Gao case SNDRV_PCM_FORMAT_S32_LE: 297fa375d42SZhangfei Gao sspa_ctrl |= SSPA_CTL_XSSZ1(SSPA_CTL_32_BITS); 298fa375d42SZhangfei Gao break; 299fa375d42SZhangfei Gao default: 300fa375d42SZhangfei Gao return -EINVAL; 301fa375d42SZhangfei Gao } 302fa375d42SZhangfei Gao 303fa375d42SZhangfei Gao if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 304fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXCTL, sspa_ctrl); 305fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_TXFIFO_LL, 0x1); 306fa375d42SZhangfei Gao } else { 307fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_RXCTL, sspa_ctrl); 308fa375d42SZhangfei Gao mmp_sspa_write_reg(sspa, SSPA_RXFIFO_UL, 0x0); 309fa375d42SZhangfei Gao } 310fa375d42SZhangfei Gao 311fa375d42SZhangfei Gao dma_params = &sspa_priv->dma_params[substream->stream]; 312fa375d42SZhangfei Gao dma_params->dev_addr = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 313fa375d42SZhangfei Gao (sspa->phys_base + SSPA_TXD) : 314fa375d42SZhangfei Gao (sspa->phys_base + SSPA_RXD); 315fa375d42SZhangfei Gao snd_soc_dai_set_dma_data(cpu_dai, substream, dma_params); 316fa375d42SZhangfei Gao return 0; 317fa375d42SZhangfei Gao } 318fa375d42SZhangfei Gao 319fa375d42SZhangfei Gao static int mmp_sspa_trigger(struct snd_pcm_substream *substream, int cmd, 320fa375d42SZhangfei Gao struct snd_soc_dai *dai) 321fa375d42SZhangfei Gao { 322fa375d42SZhangfei Gao struct sspa_priv *sspa_priv = snd_soc_dai_get_drvdata(dai); 323fa375d42SZhangfei Gao struct ssp_device *sspa = sspa_priv->sspa; 324fa375d42SZhangfei Gao int ret = 0; 325fa375d42SZhangfei Gao 326fa375d42SZhangfei Gao switch (cmd) { 327fa375d42SZhangfei Gao case SNDRV_PCM_TRIGGER_START: 328fa375d42SZhangfei Gao case SNDRV_PCM_TRIGGER_RESUME: 329fa375d42SZhangfei Gao case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 330fa375d42SZhangfei Gao /* 331fa375d42SZhangfei Gao * whatever playback or capture, must enable rx. 332fa375d42SZhangfei Gao * this is a hw issue, so need check if rx has been 333fa375d42SZhangfei Gao * enabled or not; if has been enabled by another 334fa375d42SZhangfei Gao * stream, do not enable again. 335fa375d42SZhangfei Gao */ 336fa375d42SZhangfei Gao if (!sspa_priv->running_cnt) 337fa375d42SZhangfei Gao mmp_sspa_rx_enable(sspa); 338fa375d42SZhangfei Gao 339fa375d42SZhangfei Gao if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 340fa375d42SZhangfei Gao mmp_sspa_tx_enable(sspa); 341fa375d42SZhangfei Gao 342fa375d42SZhangfei Gao sspa_priv->running_cnt++; 343fa375d42SZhangfei Gao break; 344fa375d42SZhangfei Gao 345fa375d42SZhangfei Gao case SNDRV_PCM_TRIGGER_STOP: 346fa375d42SZhangfei Gao case SNDRV_PCM_TRIGGER_SUSPEND: 347fa375d42SZhangfei Gao case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 348fa375d42SZhangfei Gao sspa_priv->running_cnt--; 349fa375d42SZhangfei Gao 350fa375d42SZhangfei Gao if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 351fa375d42SZhangfei Gao mmp_sspa_tx_disable(sspa); 352fa375d42SZhangfei Gao 353fa375d42SZhangfei Gao /* have no capture stream, disable rx port */ 354fa375d42SZhangfei Gao if (!sspa_priv->running_cnt) 355fa375d42SZhangfei Gao mmp_sspa_rx_disable(sspa); 356fa375d42SZhangfei Gao break; 357fa375d42SZhangfei Gao 358fa375d42SZhangfei Gao default: 359fa375d42SZhangfei Gao ret = -EINVAL; 360fa375d42SZhangfei Gao } 361fa375d42SZhangfei Gao 362fa375d42SZhangfei Gao return ret; 363fa375d42SZhangfei Gao } 364fa375d42SZhangfei Gao 365fa375d42SZhangfei Gao static int mmp_sspa_probe(struct snd_soc_dai *dai) 366fa375d42SZhangfei Gao { 367fa375d42SZhangfei Gao struct sspa_priv *priv = dev_get_drvdata(dai->dev); 368fa375d42SZhangfei Gao 369fa375d42SZhangfei Gao snd_soc_dai_set_drvdata(dai, priv); 370fa375d42SZhangfei Gao return 0; 371fa375d42SZhangfei Gao 372fa375d42SZhangfei Gao } 373fa375d42SZhangfei Gao 374fa375d42SZhangfei Gao #define MMP_SSPA_RATES SNDRV_PCM_RATE_8000_192000 375fa375d42SZhangfei Gao #define MMP_SSPA_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 376fa375d42SZhangfei Gao SNDRV_PCM_FMTBIT_S16_LE | \ 377fa375d42SZhangfei Gao SNDRV_PCM_FMTBIT_S24_LE | \ 378fa375d42SZhangfei Gao SNDRV_PCM_FMTBIT_S24_LE | \ 379fa375d42SZhangfei Gao SNDRV_PCM_FMTBIT_S32_LE) 380fa375d42SZhangfei Gao 381fa375d42SZhangfei Gao static struct snd_soc_dai_ops mmp_sspa_dai_ops = { 382fa375d42SZhangfei Gao .startup = mmp_sspa_startup, 383fa375d42SZhangfei Gao .shutdown = mmp_sspa_shutdown, 384fa375d42SZhangfei Gao .trigger = mmp_sspa_trigger, 385fa375d42SZhangfei Gao .hw_params = mmp_sspa_hw_params, 386fa375d42SZhangfei Gao .set_sysclk = mmp_sspa_set_dai_sysclk, 387fa375d42SZhangfei Gao .set_pll = mmp_sspa_set_dai_pll, 388fa375d42SZhangfei Gao .set_fmt = mmp_sspa_set_dai_fmt, 389fa375d42SZhangfei Gao }; 390fa375d42SZhangfei Gao 391fa375d42SZhangfei Gao struct snd_soc_dai_driver mmp_sspa_dai = { 392fa375d42SZhangfei Gao .probe = mmp_sspa_probe, 393fa375d42SZhangfei Gao .playback = { 394fa375d42SZhangfei Gao .channels_min = 1, 395fa375d42SZhangfei Gao .channels_max = 128, 396fa375d42SZhangfei Gao .rates = MMP_SSPA_RATES, 397fa375d42SZhangfei Gao .formats = MMP_SSPA_FORMATS, 398fa375d42SZhangfei Gao }, 399fa375d42SZhangfei Gao .capture = { 400fa375d42SZhangfei Gao .channels_min = 1, 401fa375d42SZhangfei Gao .channels_max = 2, 402fa375d42SZhangfei Gao .rates = MMP_SSPA_RATES, 403fa375d42SZhangfei Gao .formats = MMP_SSPA_FORMATS, 404fa375d42SZhangfei Gao }, 405fa375d42SZhangfei Gao .ops = &mmp_sspa_dai_ops, 406fa375d42SZhangfei Gao }; 407fa375d42SZhangfei Gao 408*425f3708SKuninori Morimoto static const struct snd_soc_component_driver mmp_sspa_component = { 409*425f3708SKuninori Morimoto .name = "mmp-sspa", 410*425f3708SKuninori Morimoto }; 411*425f3708SKuninori Morimoto 412570f6fe1SBill Pemberton static int asoc_mmp_sspa_probe(struct platform_device *pdev) 413fa375d42SZhangfei Gao { 414fa375d42SZhangfei Gao struct sspa_priv *priv; 415fa375d42SZhangfei Gao struct resource *res; 416fa375d42SZhangfei Gao 417fa375d42SZhangfei Gao priv = devm_kzalloc(&pdev->dev, 418fa375d42SZhangfei Gao sizeof(struct sspa_priv), GFP_KERNEL); 419fa375d42SZhangfei Gao if (!priv) 420fa375d42SZhangfei Gao return -ENOMEM; 421fa375d42SZhangfei Gao 422fa375d42SZhangfei Gao priv->sspa = devm_kzalloc(&pdev->dev, 423fa375d42SZhangfei Gao sizeof(struct ssp_device), GFP_KERNEL); 424fa375d42SZhangfei Gao if (priv->sspa == NULL) 425fa375d42SZhangfei Gao return -ENOMEM; 426fa375d42SZhangfei Gao 427fa375d42SZhangfei Gao priv->dma_params = devm_kzalloc(&pdev->dev, 428fa375d42SZhangfei Gao 2 * sizeof(struct pxa2xx_pcm_dma_params), GFP_KERNEL); 429fa375d42SZhangfei Gao if (priv->dma_params == NULL) 430fa375d42SZhangfei Gao return -ENOMEM; 431fa375d42SZhangfei Gao 432fa375d42SZhangfei Gao res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 433fa375d42SZhangfei Gao if (res == NULL) 434fa375d42SZhangfei Gao return -ENOMEM; 435fa375d42SZhangfei Gao 436b25b5aa0SThierry Reding priv->sspa->mmio_base = devm_ioremap_resource(&pdev->dev, res); 437b25b5aa0SThierry Reding if (IS_ERR(priv->sspa->mmio_base)) 438b25b5aa0SThierry Reding return PTR_ERR(priv->sspa->mmio_base); 439fa375d42SZhangfei Gao 440fa375d42SZhangfei Gao priv->sspa->clk = devm_clk_get(&pdev->dev, NULL); 441fa375d42SZhangfei Gao if (IS_ERR(priv->sspa->clk)) 442fa375d42SZhangfei Gao return PTR_ERR(priv->sspa->clk); 443fa375d42SZhangfei Gao 444fa375d42SZhangfei Gao priv->audio_clk = clk_get(NULL, "mmp-audio"); 445fa375d42SZhangfei Gao if (IS_ERR(priv->audio_clk)) 446fa375d42SZhangfei Gao return PTR_ERR(priv->audio_clk); 447fa375d42SZhangfei Gao 448fa375d42SZhangfei Gao priv->sysclk = clk_get(NULL, "mmp-sysclk"); 449fa375d42SZhangfei Gao if (IS_ERR(priv->sysclk)) { 450fa375d42SZhangfei Gao clk_put(priv->audio_clk); 451fa375d42SZhangfei Gao return PTR_ERR(priv->sysclk); 452fa375d42SZhangfei Gao } 453fa375d42SZhangfei Gao clk_enable(priv->audio_clk); 454fa375d42SZhangfei Gao priv->dai_fmt = (unsigned int) -1; 455fa375d42SZhangfei Gao platform_set_drvdata(pdev, priv); 456fa375d42SZhangfei Gao 457*425f3708SKuninori Morimoto return snd_soc_register_component(&pdev->dev, &mmp_sspa_component, 458*425f3708SKuninori Morimoto &mmp_sspa_dai, 1); 459fa375d42SZhangfei Gao } 460fa375d42SZhangfei Gao 461570f6fe1SBill Pemberton static int asoc_mmp_sspa_remove(struct platform_device *pdev) 462fa375d42SZhangfei Gao { 463fa375d42SZhangfei Gao struct sspa_priv *priv = platform_get_drvdata(pdev); 464fa375d42SZhangfei Gao 465fa375d42SZhangfei Gao clk_disable(priv->audio_clk); 466fa375d42SZhangfei Gao clk_put(priv->audio_clk); 467fa375d42SZhangfei Gao clk_put(priv->sysclk); 468*425f3708SKuninori Morimoto snd_soc_unregister_component(&pdev->dev); 469fa375d42SZhangfei Gao return 0; 470fa375d42SZhangfei Gao } 471fa375d42SZhangfei Gao 472fa375d42SZhangfei Gao static struct platform_driver asoc_mmp_sspa_driver = { 473fa375d42SZhangfei Gao .driver = { 474fa375d42SZhangfei Gao .name = "mmp-sspa-dai", 475fa375d42SZhangfei Gao .owner = THIS_MODULE, 476fa375d42SZhangfei Gao }, 477fa375d42SZhangfei Gao .probe = asoc_mmp_sspa_probe, 478570f6fe1SBill Pemberton .remove = asoc_mmp_sspa_remove, 479fa375d42SZhangfei Gao }; 480fa375d42SZhangfei Gao 481fa375d42SZhangfei Gao module_platform_driver(asoc_mmp_sspa_driver); 482fa375d42SZhangfei Gao 483fa375d42SZhangfei Gao MODULE_AUTHOR("Leo Yan <leoy@marvell.com>"); 484fa375d42SZhangfei Gao MODULE_DESCRIPTION("MMP SSPA SoC Interface"); 485fa375d42SZhangfei Gao MODULE_LICENSE("GPL"); 486