1*16216333SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 22a24f2ceSDong Aisheng /* 32a24f2ceSDong Aisheng * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. 42a24f2ceSDong Aisheng */ 52a24f2ceSDong Aisheng 62a24f2ceSDong Aisheng 72a24f2ceSDong Aisheng #ifndef _MXS_SAIF_H 82a24f2ceSDong Aisheng #define _MXS_SAIF_H 92a24f2ceSDong Aisheng 102a24f2ceSDong Aisheng #define SAIF_CTRL 0x0 112a24f2ceSDong Aisheng #define SAIF_STAT 0x10 122a24f2ceSDong Aisheng #define SAIF_DATA 0x20 132a24f2ceSDong Aisheng #define SAIF_VERSION 0X30 142a24f2ceSDong Aisheng 152a24f2ceSDong Aisheng /* SAIF_CTRL */ 162a24f2ceSDong Aisheng #define BM_SAIF_CTRL_SFTRST 0x80000000 172a24f2ceSDong Aisheng #define BM_SAIF_CTRL_CLKGATE 0x40000000 182a24f2ceSDong Aisheng #define BP_SAIF_CTRL_BITCLK_MULT_RATE 27 192a24f2ceSDong Aisheng #define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000 202a24f2ceSDong Aisheng #define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \ 212a24f2ceSDong Aisheng (((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE) 222a24f2ceSDong Aisheng #define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x04000000 232a24f2ceSDong Aisheng #define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x02000000 242a24f2ceSDong Aisheng #define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x01000000 252a24f2ceSDong Aisheng #define BP_SAIF_CTRL_RSRVD2 21 262a24f2ceSDong Aisheng #define BM_SAIF_CTRL_RSRVD2 0x00E00000 272a24f2ceSDong Aisheng 282a24f2ceSDong Aisheng #define BP_SAIF_CTRL_DMAWAIT_COUNT 16 292a24f2ceSDong Aisheng #define BM_SAIF_CTRL_DMAWAIT_COUNT 0x001F0000 302a24f2ceSDong Aisheng #define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \ 312a24f2ceSDong Aisheng (((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT) 322a24f2ceSDong Aisheng #define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14 332a24f2ceSDong Aisheng #define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0x0000C000 342a24f2ceSDong Aisheng #define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \ 352a24f2ceSDong Aisheng (((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT) 362a24f2ceSDong Aisheng #define BM_SAIF_CTRL_LRCLK_PULSE 0x00002000 372a24f2ceSDong Aisheng #define BM_SAIF_CTRL_BIT_ORDER 0x00001000 382a24f2ceSDong Aisheng #define BM_SAIF_CTRL_DELAY 0x00000800 392a24f2ceSDong Aisheng #define BM_SAIF_CTRL_JUSTIFY 0x00000400 402a24f2ceSDong Aisheng #define BM_SAIF_CTRL_LRCLK_POLARITY 0x00000200 412a24f2ceSDong Aisheng #define BM_SAIF_CTRL_BITCLK_EDGE 0x00000100 422a24f2ceSDong Aisheng #define BP_SAIF_CTRL_WORD_LENGTH 4 432a24f2ceSDong Aisheng #define BM_SAIF_CTRL_WORD_LENGTH 0x000000F0 442a24f2ceSDong Aisheng #define BF_SAIF_CTRL_WORD_LENGTH(v) \ 452a24f2ceSDong Aisheng (((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH) 462a24f2ceSDong Aisheng #define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x00000008 472a24f2ceSDong Aisheng #define BM_SAIF_CTRL_SLAVE_MODE 0x00000004 482a24f2ceSDong Aisheng #define BM_SAIF_CTRL_READ_MODE 0x00000002 492a24f2ceSDong Aisheng #define BM_SAIF_CTRL_RUN 0x00000001 502a24f2ceSDong Aisheng 512a24f2ceSDong Aisheng /* SAIF_STAT */ 522a24f2ceSDong Aisheng #define BM_SAIF_STAT_PRESENT 0x80000000 532a24f2ceSDong Aisheng #define BP_SAIF_STAT_RSRVD2 17 542a24f2ceSDong Aisheng #define BM_SAIF_STAT_RSRVD2 0x7FFE0000 552a24f2ceSDong Aisheng #define BF_SAIF_STAT_RSRVD2(v) \ 562a24f2ceSDong Aisheng (((v) << 17) & BM_SAIF_STAT_RSRVD2) 572a24f2ceSDong Aisheng #define BM_SAIF_STAT_DMA_PREQ 0x00010000 582a24f2ceSDong Aisheng #define BP_SAIF_STAT_RSRVD1 7 592a24f2ceSDong Aisheng #define BM_SAIF_STAT_RSRVD1 0x0000FF80 602a24f2ceSDong Aisheng #define BF_SAIF_STAT_RSRVD1(v) \ 612a24f2ceSDong Aisheng (((v) << 7) & BM_SAIF_STAT_RSRVD1) 622a24f2ceSDong Aisheng 632a24f2ceSDong Aisheng #define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x00000040 642a24f2ceSDong Aisheng #define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x00000020 652a24f2ceSDong Aisheng #define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x00000010 662a24f2ceSDong Aisheng #define BP_SAIF_STAT_RSRVD0 1 672a24f2ceSDong Aisheng #define BM_SAIF_STAT_RSRVD0 0x0000000E 682a24f2ceSDong Aisheng #define BF_SAIF_STAT_RSRVD0(v) \ 692a24f2ceSDong Aisheng (((v) << 1) & BM_SAIF_STAT_RSRVD0) 702a24f2ceSDong Aisheng #define BM_SAIF_STAT_BUSY 0x00000001 712a24f2ceSDong Aisheng 722a24f2ceSDong Aisheng /* SAFI_DATA */ 732a24f2ceSDong Aisheng #define BP_SAIF_DATA_PCM_RIGHT 16 742a24f2ceSDong Aisheng #define BM_SAIF_DATA_PCM_RIGHT 0xFFFF0000 752a24f2ceSDong Aisheng #define BF_SAIF_DATA_PCM_RIGHT(v) \ 762a24f2ceSDong Aisheng (((v) << 16) & BM_SAIF_DATA_PCM_RIGHT) 772a24f2ceSDong Aisheng #define BP_SAIF_DATA_PCM_LEFT 0 782a24f2ceSDong Aisheng #define BM_SAIF_DATA_PCM_LEFT 0x0000FFFF 792a24f2ceSDong Aisheng #define BF_SAIF_DATA_PCM_LEFT(v) \ 802a24f2ceSDong Aisheng (((v) << 0) & BM_SAIF_DATA_PCM_LEFT) 812a24f2ceSDong Aisheng 822a24f2ceSDong Aisheng /* SAIF_VERSION */ 832a24f2ceSDong Aisheng #define BP_SAIF_VERSION_MAJOR 24 842a24f2ceSDong Aisheng #define BM_SAIF_VERSION_MAJOR 0xFF000000 852a24f2ceSDong Aisheng #define BF_SAIF_VERSION_MAJOR(v) \ 862a24f2ceSDong Aisheng (((v) << 24) & BM_SAIF_VERSION_MAJOR) 872a24f2ceSDong Aisheng #define BP_SAIF_VERSION_MINOR 16 882a24f2ceSDong Aisheng #define BM_SAIF_VERSION_MINOR 0x00FF0000 892a24f2ceSDong Aisheng #define BF_SAIF_VERSION_MINOR(v) \ 902a24f2ceSDong Aisheng (((v) << 16) & BM_SAIF_VERSION_MINOR) 912a24f2ceSDong Aisheng #define BP_SAIF_VERSION_STEP 0 922a24f2ceSDong Aisheng #define BM_SAIF_VERSION_STEP 0x0000FFFF 932a24f2ceSDong Aisheng #define BF_SAIF_VERSION_STEP(v) \ 942a24f2ceSDong Aisheng (((v) << 0) & BM_SAIF_VERSION_STEP) 952a24f2ceSDong Aisheng 962a24f2ceSDong Aisheng #define MXS_SAIF_MCLK 0 972a24f2ceSDong Aisheng 982a24f2ceSDong Aisheng #include "mxs-pcm.h" 992a24f2ceSDong Aisheng 1002a24f2ceSDong Aisheng struct mxs_saif { 1012a24f2ceSDong Aisheng struct device *dev; 1022a24f2ceSDong Aisheng struct clk *clk; 1032a24f2ceSDong Aisheng unsigned int mclk; 1042a24f2ceSDong Aisheng unsigned int mclk_in_use; 1052a24f2ceSDong Aisheng void __iomem *base; 10676067540SDong Aisheng unsigned int id; 10776067540SDong Aisheng unsigned int master_id; 10876067540SDong Aisheng unsigned int cur_rate; 10976067540SDong Aisheng unsigned int ongoing; 1102a24f2ceSDong Aisheng 1112a24f2ceSDong Aisheng u32 fifo_underrun; 1122a24f2ceSDong Aisheng u32 fifo_overrun; 11388cf632aSMarkus Pargmann 11488cf632aSMarkus Pargmann enum { 11588cf632aSMarkus Pargmann MXS_SAIF_STATE_STOPPED, 11688cf632aSMarkus Pargmann MXS_SAIF_STATE_RUNNING, 11788cf632aSMarkus Pargmann } state; 1182a24f2ceSDong Aisheng }; 1192a24f2ceSDong Aisheng 1202a24f2ceSDong Aisheng extern int mxs_saif_put_mclk(unsigned int saif_id); 1212a24f2ceSDong Aisheng extern int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 1222a24f2ceSDong Aisheng unsigned int rate); 1232a24f2ceSDong Aisheng #endif 124