1*f6b02647STrevor Wu /* SPDX-License-Identifier: GPL-2.0 */ 2*f6b02647STrevor Wu /* 3*f6b02647STrevor Wu * mt8188-afe-clk.h -- MediaTek 8188 afe clock ctrl definition 4*f6b02647STrevor Wu * 5*f6b02647STrevor Wu * Copyright (c) 2022 MediaTek Inc. 6*f6b02647STrevor Wu * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7*f6b02647STrevor Wu * Trevor Wu <trevor.wu@mediatek.com> 8*f6b02647STrevor Wu * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9*f6b02647STrevor Wu */ 10*f6b02647STrevor Wu 11*f6b02647STrevor Wu #ifndef _MT8188_AFE_CLK_H_ 12*f6b02647STrevor Wu #define _MT8188_AFE_CLK_H_ 13*f6b02647STrevor Wu 14*f6b02647STrevor Wu /* APLL */ 15*f6b02647STrevor Wu #define APLL1_W_NAME "APLL1" 16*f6b02647STrevor Wu #define APLL2_W_NAME "APLL2" 17*f6b02647STrevor Wu 18*f6b02647STrevor Wu enum { 19*f6b02647STrevor Wu /* xtal */ 20*f6b02647STrevor Wu MT8188_CLK_XTAL_26M, 21*f6b02647STrevor Wu /* pll */ 22*f6b02647STrevor Wu MT8188_CLK_APMIXED_APLL1, 23*f6b02647STrevor Wu MT8188_CLK_APMIXED_APLL2, 24*f6b02647STrevor Wu /* divider */ 25*f6b02647STrevor Wu MT8188_CLK_TOP_APLL1_D4, 26*f6b02647STrevor Wu MT8188_CLK_TOP_APLL2_D4, 27*f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV0, 28*f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV1, 29*f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV2, 30*f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV3, 31*f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV4, 32*f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV9, 33*f6b02647STrevor Wu /* mux */ 34*f6b02647STrevor Wu MT8188_CLK_TOP_A1SYS_HP_SEL, 35*f6b02647STrevor Wu MT8188_CLK_TOP_A2SYS_SEL, 36*f6b02647STrevor Wu MT8188_CLK_TOP_AUD_IEC_SEL, 37*f6b02647STrevor Wu MT8188_CLK_TOP_AUD_INTBUS_SEL, 38*f6b02647STrevor Wu MT8188_CLK_TOP_AUDIO_H_SEL, 39*f6b02647STrevor Wu MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL, 40*f6b02647STrevor Wu MT8188_CLK_TOP_DPTX_M_SEL, 41*f6b02647STrevor Wu MT8188_CLK_TOP_I2SO1_M_SEL, 42*f6b02647STrevor Wu MT8188_CLK_TOP_I2SO2_M_SEL, 43*f6b02647STrevor Wu MT8188_CLK_TOP_I2SI1_M_SEL, 44*f6b02647STrevor Wu MT8188_CLK_TOP_I2SI2_M_SEL, 45*f6b02647STrevor Wu /* clock gate */ 46*f6b02647STrevor Wu MT8188_CLK_ADSP_AUDIO_26M, 47*f6b02647STrevor Wu MT8188_CLK_AUD_AFE, 48*f6b02647STrevor Wu MT8188_CLK_AUD_APLL1_TUNER, 49*f6b02647STrevor Wu MT8188_CLK_AUD_APLL2_TUNER, 50*f6b02647STrevor Wu MT8188_CLK_AUD_TOP0_SPDF, 51*f6b02647STrevor Wu MT8188_CLK_AUD_APLL, 52*f6b02647STrevor Wu MT8188_CLK_AUD_APLL2, 53*f6b02647STrevor Wu MT8188_CLK_AUD_DAC, 54*f6b02647STrevor Wu MT8188_CLK_AUD_ADC, 55*f6b02647STrevor Wu MT8188_CLK_AUD_DAC_HIRES, 56*f6b02647STrevor Wu MT8188_CLK_AUD_A1SYS_HP, 57*f6b02647STrevor Wu MT8188_CLK_AUD_ADC_HIRES, 58*f6b02647STrevor Wu MT8188_CLK_AUD_I2SIN, 59*f6b02647STrevor Wu MT8188_CLK_AUD_TDM_IN, 60*f6b02647STrevor Wu MT8188_CLK_AUD_I2S_OUT, 61*f6b02647STrevor Wu MT8188_CLK_AUD_TDM_OUT, 62*f6b02647STrevor Wu MT8188_CLK_AUD_HDMI_OUT, 63*f6b02647STrevor Wu MT8188_CLK_AUD_ASRC11, 64*f6b02647STrevor Wu MT8188_CLK_AUD_ASRC12, 65*f6b02647STrevor Wu MT8188_CLK_AUD_A1SYS, 66*f6b02647STrevor Wu MT8188_CLK_AUD_A2SYS, 67*f6b02647STrevor Wu MT8188_CLK_AUD_PCMIF, 68*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL1, 69*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL2, 70*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL3, 71*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL4, 72*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL5, 73*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL6, 74*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL8, 75*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL9, 76*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL10, 77*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL2, 78*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL3, 79*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL6, 80*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL7, 81*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL8, 82*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL10, 83*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL11, 84*f6b02647STrevor Wu MT8188_CLK_NUM, 85*f6b02647STrevor Wu }; 86*f6b02647STrevor Wu 87*f6b02647STrevor Wu enum { 88*f6b02647STrevor Wu MT8188_AUD_PLL1, 89*f6b02647STrevor Wu MT8188_AUD_PLL2, 90*f6b02647STrevor Wu MT8188_AUD_PLL3, 91*f6b02647STrevor Wu MT8188_AUD_PLL4, 92*f6b02647STrevor Wu MT8188_AUD_PLL5, 93*f6b02647STrevor Wu MT8188_AUD_PLL_NUM, 94*f6b02647STrevor Wu }; 95*f6b02647STrevor Wu 96*f6b02647STrevor Wu enum { 97*f6b02647STrevor Wu MT8188_MCK_SEL_26M, 98*f6b02647STrevor Wu MT8188_MCK_SEL_APLL1, 99*f6b02647STrevor Wu MT8188_MCK_SEL_APLL2, 100*f6b02647STrevor Wu MT8188_MCK_SEL_APLL3, 101*f6b02647STrevor Wu MT8188_MCK_SEL_APLL4, 102*f6b02647STrevor Wu MT8188_MCK_SEL_APLL5, 103*f6b02647STrevor Wu MT8188_MCK_SEL_NUM, 104*f6b02647STrevor Wu }; 105*f6b02647STrevor Wu 106*f6b02647STrevor Wu struct mtk_base_afe; 107*f6b02647STrevor Wu 108*f6b02647STrevor Wu int mt8188_afe_get_mclk_source_clk_id(int sel); 109*f6b02647STrevor Wu int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll); 110*f6b02647STrevor Wu int mt8188_afe_get_default_mclk_source_by_rate(int rate); 111*f6b02647STrevor Wu int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate); 112*f6b02647STrevor Wu int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name); 113*f6b02647STrevor Wu int mt8188_afe_init_clock(struct mtk_base_afe *afe); 114*f6b02647STrevor Wu int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk); 115 void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk); 116 int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, 117 unsigned int rate); 118 int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, 119 struct clk *parent); 120 int mt8188_apll1_enable(struct mtk_base_afe *afe); 121 int mt8188_apll1_disable(struct mtk_base_afe *afe); 122 int mt8188_apll2_enable(struct mtk_base_afe *afe); 123 int mt8188_apll2_disable(struct mtk_base_afe *afe); 124 int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe); 125 int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe); 126 int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe); 127 int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe); 128 129 #endif 130