1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // MediaTek ALSA SoC Audio DAI I2S Control 4 // 5 // Copyright (c) 2022 MediaTek Inc. 6 // Author: Jiaxin Yu <jiaxin.yu@mediatek.com> 7 8 #include <linux/bitops.h> 9 #include <linux/regmap.h> 10 #include <sound/pcm_params.h> 11 #include "mt8186-afe-clk.h" 12 #include "mt8186-afe-common.h" 13 #include "mt8186-afe-gpio.h" 14 #include "mt8186-interconnection.h" 15 16 enum { 17 I2S_FMT_EIAJ = 0, 18 I2S_FMT_I2S = 1, 19 }; 20 21 enum { 22 I2S_WLEN_16_BIT = 0, 23 I2S_WLEN_32_BIT = 1, 24 }; 25 26 enum { 27 I2S_HD_NORMAL = 0, 28 I2S_HD_LOW_JITTER = 1, 29 }; 30 31 enum { 32 I2S1_SEL_O28_O29 = 0, 33 I2S1_SEL_O03_O04 = 1, 34 }; 35 36 enum { 37 I2S_IN_PAD_CONNSYS = 0, 38 I2S_IN_PAD_IO_MUX = 1, 39 }; 40 41 struct mtk_afe_i2s_priv { 42 int id; 43 int rate; /* for determine which apll to use */ 44 int low_jitter_en; 45 int master; /* only i2s0 has slave mode*/ 46 47 const char *share_property_name; 48 int share_i2s_id; 49 50 int mclk_id; 51 int mclk_rate; 52 int mclk_apll; 53 }; 54 55 static unsigned int get_i2s_wlen(snd_pcm_format_t format) 56 { 57 return snd_pcm_format_physical_width(format) <= 16 ? 58 I2S_WLEN_16_BIT : I2S_WLEN_32_BIT; 59 } 60 61 #define MTK_AFE_I2S0_KCONTROL_NAME "I2S0_HD_Mux" 62 #define MTK_AFE_I2S1_KCONTROL_NAME "I2S1_HD_Mux" 63 #define MTK_AFE_I2S2_KCONTROL_NAME "I2S2_HD_Mux" 64 #define MTK_AFE_I2S3_KCONTROL_NAME "I2S3_HD_Mux" 65 #define MTK_AFE_I2S0_SRC_KCONTROL_NAME "I2S0_SRC_Mux" 66 67 #define I2S0_HD_EN_W_NAME "I2S0_HD_EN" 68 #define I2S1_HD_EN_W_NAME "I2S1_HD_EN" 69 #define I2S2_HD_EN_W_NAME "I2S2_HD_EN" 70 #define I2S3_HD_EN_W_NAME "I2S3_HD_EN" 71 72 #define I2S0_MCLK_EN_W_NAME "I2S0_MCLK_EN" 73 #define I2S1_MCLK_EN_W_NAME "I2S1_MCLK_EN" 74 #define I2S2_MCLK_EN_W_NAME "I2S2_MCLK_EN" 75 #define I2S3_MCLK_EN_W_NAME "I2S3_MCLK_EN" 76 77 static int get_i2s_id_by_name(struct mtk_base_afe *afe, 78 const char *name) 79 { 80 if (strncmp(name, "I2S0", 4) == 0) 81 return MT8186_DAI_I2S_0; 82 else if (strncmp(name, "I2S1", 4) == 0) 83 return MT8186_DAI_I2S_1; 84 else if (strncmp(name, "I2S2", 4) == 0) 85 return MT8186_DAI_I2S_2; 86 else if (strncmp(name, "I2S3", 4) == 0) 87 return MT8186_DAI_I2S_3; 88 89 return -EINVAL; 90 } 91 92 static struct mtk_afe_i2s_priv *get_i2s_priv_by_name(struct mtk_base_afe *afe, 93 const char *name) 94 { 95 struct mt8186_afe_private *afe_priv = afe->platform_priv; 96 int dai_id = get_i2s_id_by_name(afe, name); 97 98 if (dai_id < 0) 99 return NULL; 100 101 return afe_priv->dai_priv[dai_id]; 102 } 103 104 /* low jitter control */ 105 static const char * const mt8186_i2s_hd_str[] = { 106 "Normal", "Low_Jitter" 107 }; 108 109 static const struct soc_enum mt8186_i2s_enum[] = { 110 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8186_i2s_hd_str), 111 mt8186_i2s_hd_str), 112 }; 113 114 static int mt8186_i2s_hd_get(struct snd_kcontrol *kcontrol, 115 struct snd_ctl_elem_value *ucontrol) 116 { 117 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 118 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 119 struct mtk_afe_i2s_priv *i2s_priv; 120 121 i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name); 122 123 if (!i2s_priv) { 124 dev_err(afe->dev, "%s(), i2s_priv == NULL", __func__); 125 return -EINVAL; 126 } 127 128 ucontrol->value.integer.value[0] = i2s_priv->low_jitter_en; 129 130 return 0; 131 } 132 133 static int mt8186_i2s_hd_set(struct snd_kcontrol *kcontrol, 134 struct snd_ctl_elem_value *ucontrol) 135 { 136 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 137 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 138 struct mtk_afe_i2s_priv *i2s_priv; 139 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 140 int hd_en; 141 142 if (ucontrol->value.enumerated.item[0] >= e->items) 143 return -EINVAL; 144 145 hd_en = ucontrol->value.integer.value[0]; 146 147 dev_dbg(afe->dev, "%s(), kcontrol name %s, hd_en %d\n", 148 __func__, kcontrol->id.name, hd_en); 149 150 i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name); 151 152 if (!i2s_priv) { 153 dev_err(afe->dev, "%s(), i2s_priv == NULL", __func__); 154 return -EINVAL; 155 } 156 157 if (i2s_priv->low_jitter_en == hd_en) 158 return 0; 159 160 i2s_priv->low_jitter_en = hd_en; 161 162 return 1; 163 } 164 165 static const struct snd_kcontrol_new mtk_dai_i2s_controls[] = { 166 SOC_ENUM_EXT(MTK_AFE_I2S0_KCONTROL_NAME, mt8186_i2s_enum[0], 167 mt8186_i2s_hd_get, mt8186_i2s_hd_set), 168 SOC_ENUM_EXT(MTK_AFE_I2S1_KCONTROL_NAME, mt8186_i2s_enum[0], 169 mt8186_i2s_hd_get, mt8186_i2s_hd_set), 170 SOC_ENUM_EXT(MTK_AFE_I2S2_KCONTROL_NAME, mt8186_i2s_enum[0], 171 mt8186_i2s_hd_get, mt8186_i2s_hd_set), 172 SOC_ENUM_EXT(MTK_AFE_I2S3_KCONTROL_NAME, mt8186_i2s_enum[0], 173 mt8186_i2s_hd_get, mt8186_i2s_hd_set), 174 }; 175 176 /* dai component */ 177 /* i2s virtual mux to output widget */ 178 static const char * const i2s_mux_map[] = { 179 "Normal", "Dummy_Widget", 180 }; 181 182 static int i2s_mux_map_value[] = { 183 0, 1, 184 }; 185 186 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s_mux_map_enum, 187 SND_SOC_NOPM, 188 0, 189 1, 190 i2s_mux_map, 191 i2s_mux_map_value); 192 193 static const struct snd_kcontrol_new i2s0_in_mux_control = 194 SOC_DAPM_ENUM("I2S0 In Select", i2s_mux_map_enum); 195 196 static const struct snd_kcontrol_new i2s1_out_mux_control = 197 SOC_DAPM_ENUM("I2S1 Out Select", i2s_mux_map_enum); 198 199 static const struct snd_kcontrol_new i2s2_in_mux_control = 200 SOC_DAPM_ENUM("I2S2 In Select", i2s_mux_map_enum); 201 202 static const struct snd_kcontrol_new i2s3_out_mux_control = 203 SOC_DAPM_ENUM("I2S3 Out Select", i2s_mux_map_enum); 204 205 /* i2s in lpbk */ 206 static const char * const i2s_lpbk_mux_map[] = { 207 "Normal", "Lpbk", 208 }; 209 210 static int i2s_lpbk_mux_map_value[] = { 211 0, 1, 212 }; 213 214 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s0_lpbk_mux_map_enum, 215 AFE_I2S_CON, 216 I2S_LOOPBACK_SFT, 217 1, 218 i2s_lpbk_mux_map, 219 i2s_lpbk_mux_map_value); 220 221 static const struct snd_kcontrol_new i2s0_lpbk_mux_control = 222 SOC_DAPM_ENUM("I2S Lpbk Select", i2s0_lpbk_mux_map_enum); 223 224 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s2_lpbk_mux_map_enum, 225 AFE_I2S_CON2, 226 I2S3_LOOPBACK_SFT, 227 1, 228 i2s_lpbk_mux_map, 229 i2s_lpbk_mux_map_value); 230 231 static const struct snd_kcontrol_new i2s2_lpbk_mux_control = 232 SOC_DAPM_ENUM("I2S Lpbk Select", i2s2_lpbk_mux_map_enum); 233 234 /* interconnection */ 235 static const struct snd_kcontrol_new mtk_i2s3_ch1_mix[] = { 236 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN0, 237 I_DL1_CH1, 1, 0), 238 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN0, 239 I_DL2_CH1, 1, 0), 240 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN0, 241 I_DL3_CH1, 1, 0), 242 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN0, 243 I_DL12_CH1, 1, 0), 244 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN0, 245 I_DL12_CH3, 1, 0), 246 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN0_1, 247 I_DL6_CH1, 1, 0), 248 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN0_1, 249 I_DL4_CH1, 1, 0), 250 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN0_1, 251 I_DL5_CH1, 1, 0), 252 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN0_1, 253 I_DL8_CH1, 1, 0), 254 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN0, 255 I_GAIN1_OUT_CH1, 1, 0), 256 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN0, 257 I_ADDA_UL_CH1, 1, 0), 258 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN0, 259 I_ADDA_UL_CH2, 1, 0), 260 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN0, 261 I_ADDA_UL_CH3, 1, 0), 262 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN0, 263 I_PCM_1_CAP_CH1, 1, 0), 264 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN0_1, 265 I_SRC_1_OUT_CH1, 1, 0), 266 }; 267 268 static const struct snd_kcontrol_new mtk_i2s3_ch2_mix[] = { 269 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN1, 270 I_DL1_CH2, 1, 0), 271 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN1, 272 I_DL2_CH2, 1, 0), 273 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN1, 274 I_DL3_CH2, 1, 0), 275 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN1, 276 I_DL12_CH2, 1, 0), 277 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN1, 278 I_DL12_CH4, 1, 0), 279 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN1_1, 280 I_DL6_CH2, 1, 0), 281 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN1_1, 282 I_DL4_CH2, 1, 0), 283 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN1_1, 284 I_DL5_CH2, 1, 0), 285 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN1_1, 286 I_DL8_CH2, 1, 0), 287 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN1, 288 I_GAIN1_OUT_CH2, 1, 0), 289 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN1, 290 I_ADDA_UL_CH1, 1, 0), 291 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN1, 292 I_ADDA_UL_CH2, 1, 0), 293 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN1, 294 I_ADDA_UL_CH3, 1, 0), 295 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN1, 296 I_PCM_1_CAP_CH2, 1, 0), 297 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN1, 298 I_PCM_2_CAP_CH2, 1, 0), 299 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN1_1, 300 I_SRC_1_OUT_CH2, 1, 0), 301 }; 302 303 static const struct snd_kcontrol_new mtk_i2s1_ch1_mix[] = { 304 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN28, 305 I_DL1_CH1, 1, 0), 306 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN28, 307 I_DL2_CH1, 1, 0), 308 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN28, 309 I_DL3_CH1, 1, 0), 310 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN28, 311 I_DL12_CH1, 1, 0), 312 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN28, 313 I_DL12_CH3, 1, 0), 314 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN28_1, 315 I_DL6_CH1, 1, 0), 316 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN28_1, 317 I_DL4_CH1, 1, 0), 318 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN28_1, 319 I_DL5_CH1, 1, 0), 320 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN28_1, 321 I_DL8_CH1, 1, 0), 322 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN28, 323 I_GAIN1_OUT_CH1, 1, 0), 324 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN28, 325 I_ADDA_UL_CH1, 1, 0), 326 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN28, 327 I_PCM_1_CAP_CH1, 1, 0), 328 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN28_1, 329 I_SRC_1_OUT_CH1, 1, 0), 330 }; 331 332 static const struct snd_kcontrol_new mtk_i2s1_ch2_mix[] = { 333 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN29, 334 I_DL1_CH2, 1, 0), 335 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN29, 336 I_DL2_CH2, 1, 0), 337 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN29, 338 I_DL3_CH2, 1, 0), 339 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN29, 340 I_DL12_CH2, 1, 0), 341 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN29, 342 I_DL12_CH4, 1, 0), 343 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN29_1, 344 I_DL6_CH2, 1, 0), 345 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN29_1, 346 I_DL4_CH2, 1, 0), 347 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN29_1, 348 I_DL5_CH2, 1, 0), 349 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN29_1, 350 I_DL8_CH2, 1, 0), 351 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN29, 352 I_GAIN1_OUT_CH2, 1, 0), 353 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN29, 354 I_ADDA_UL_CH2, 1, 0), 355 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN29, 356 I_PCM_1_CAP_CH2, 1, 0), 357 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN29, 358 I_PCM_2_CAP_CH2, 1, 0), 359 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN29_1, 360 I_SRC_1_OUT_CH2, 1, 0), 361 }; 362 363 enum { 364 SUPPLY_SEQ_APLL, 365 SUPPLY_SEQ_I2S_MCLK_EN, 366 SUPPLY_SEQ_I2S_HD_EN, 367 SUPPLY_SEQ_I2S_EN, 368 }; 369 370 static int mtk_i2s_en_event(struct snd_soc_dapm_widget *w, 371 struct snd_kcontrol *kcontrol, 372 int event) 373 { 374 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 375 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 376 struct mtk_afe_i2s_priv *i2s_priv; 377 378 i2s_priv = get_i2s_priv_by_name(afe, w->name); 379 380 if (!i2s_priv) { 381 dev_err(afe->dev, "%s(), i2s_priv == NULL", __func__); 382 return -EINVAL; 383 } 384 385 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 386 __func__, w->name, event); 387 388 switch (event) { 389 case SND_SOC_DAPM_PRE_PMU: 390 mt8186_afe_gpio_request(afe->dev, true, i2s_priv->id, 0); 391 break; 392 case SND_SOC_DAPM_POST_PMD: 393 mt8186_afe_gpio_request(afe->dev, false, i2s_priv->id, 0); 394 break; 395 default: 396 break; 397 } 398 399 return 0; 400 } 401 402 static int mtk_apll_event(struct snd_soc_dapm_widget *w, 403 struct snd_kcontrol *kcontrol, 404 int event) 405 { 406 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 407 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 408 409 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 410 __func__, w->name, event); 411 412 switch (event) { 413 case SND_SOC_DAPM_PRE_PMU: 414 if (strcmp(w->name, APLL1_W_NAME) == 0) 415 mt8186_apll1_enable(afe); 416 else 417 mt8186_apll2_enable(afe); 418 break; 419 case SND_SOC_DAPM_POST_PMD: 420 if (strcmp(w->name, APLL1_W_NAME) == 0) 421 mt8186_apll1_disable(afe); 422 else 423 mt8186_apll2_disable(afe); 424 break; 425 default: 426 break; 427 } 428 429 return 0; 430 } 431 432 static int mtk_mclk_en_event(struct snd_soc_dapm_widget *w, 433 struct snd_kcontrol *kcontrol, 434 int event) 435 { 436 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 437 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 438 struct mtk_afe_i2s_priv *i2s_priv; 439 440 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n", 441 __func__, w->name, event); 442 443 i2s_priv = get_i2s_priv_by_name(afe, w->name); 444 445 if (!i2s_priv) { 446 dev_err(afe->dev, "%s(), i2s_priv == NULL", __func__); 447 return -EINVAL; 448 } 449 450 switch (event) { 451 case SND_SOC_DAPM_PRE_PMU: 452 mt8186_mck_enable(afe, i2s_priv->mclk_id, i2s_priv->mclk_rate); 453 break; 454 case SND_SOC_DAPM_POST_PMD: 455 i2s_priv->mclk_rate = 0; 456 mt8186_mck_disable(afe, i2s_priv->mclk_id); 457 break; 458 default: 459 break; 460 } 461 462 return 0; 463 } 464 465 static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = { 466 SND_SOC_DAPM_INPUT("CONNSYS"), 467 468 SND_SOC_DAPM_MIXER("I2S1_CH1", SND_SOC_NOPM, 0, 0, 469 mtk_i2s1_ch1_mix, 470 ARRAY_SIZE(mtk_i2s1_ch1_mix)), 471 SND_SOC_DAPM_MIXER("I2S1_CH2", SND_SOC_NOPM, 0, 0, 472 mtk_i2s1_ch2_mix, 473 ARRAY_SIZE(mtk_i2s1_ch2_mix)), 474 475 SND_SOC_DAPM_MIXER("I2S3_CH1", SND_SOC_NOPM, 0, 0, 476 mtk_i2s3_ch1_mix, 477 ARRAY_SIZE(mtk_i2s3_ch1_mix)), 478 SND_SOC_DAPM_MIXER("I2S3_CH2", SND_SOC_NOPM, 0, 0, 479 mtk_i2s3_ch2_mix, 480 ARRAY_SIZE(mtk_i2s3_ch2_mix)), 481 482 /* i2s en*/ 483 SND_SOC_DAPM_SUPPLY_S("I2S0_EN", SUPPLY_SEQ_I2S_EN, 484 AFE_I2S_CON, I2S_EN_SFT, 0, 485 mtk_i2s_en_event, 486 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 487 SND_SOC_DAPM_SUPPLY_S("I2S1_EN", SUPPLY_SEQ_I2S_EN, 488 AFE_I2S_CON1, I2S_EN_SFT, 0, 489 mtk_i2s_en_event, 490 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 491 SND_SOC_DAPM_SUPPLY_S("I2S2_EN", SUPPLY_SEQ_I2S_EN, 492 AFE_I2S_CON2, I2S_EN_SFT, 0, 493 mtk_i2s_en_event, 494 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 495 SND_SOC_DAPM_SUPPLY_S("I2S3_EN", SUPPLY_SEQ_I2S_EN, 496 AFE_I2S_CON3, I2S_EN_SFT, 0, 497 mtk_i2s_en_event, 498 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 499 /* i2s hd en */ 500 SND_SOC_DAPM_SUPPLY_S(I2S0_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 501 AFE_I2S_CON, I2S1_HD_EN_SFT, 0, NULL, 502 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 503 SND_SOC_DAPM_SUPPLY_S(I2S1_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 504 AFE_I2S_CON1, I2S2_HD_EN_SFT, 0, NULL, 505 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 506 SND_SOC_DAPM_SUPPLY_S(I2S2_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 507 AFE_I2S_CON2, I2S3_HD_EN_SFT, 0, NULL, 508 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 509 SND_SOC_DAPM_SUPPLY_S(I2S3_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN, 510 AFE_I2S_CON3, I2S4_HD_EN_SFT, 0, NULL, 511 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 512 513 /* i2s mclk en */ 514 SND_SOC_DAPM_SUPPLY_S(I2S0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 515 SND_SOC_NOPM, 0, 0, 516 mtk_mclk_en_event, 517 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 518 SND_SOC_DAPM_SUPPLY_S(I2S1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 519 SND_SOC_NOPM, 0, 0, 520 mtk_mclk_en_event, 521 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 522 SND_SOC_DAPM_SUPPLY_S(I2S2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 523 SND_SOC_NOPM, 0, 0, 524 mtk_mclk_en_event, 525 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 526 SND_SOC_DAPM_SUPPLY_S(I2S3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN, 527 SND_SOC_NOPM, 0, 0, 528 mtk_mclk_en_event, 529 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 530 531 /* apll */ 532 SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL, 533 SND_SOC_NOPM, 0, 0, 534 mtk_apll_event, 535 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 536 SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL, 537 SND_SOC_NOPM, 0, 0, 538 mtk_apll_event, 539 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 540 541 /* allow i2s on without codec on */ 542 SND_SOC_DAPM_OUTPUT("I2S_DUMMY_OUT"), 543 SND_SOC_DAPM_MUX("I2S1_Out_Mux", 544 SND_SOC_NOPM, 0, 0, &i2s1_out_mux_control), 545 SND_SOC_DAPM_MUX("I2S3_Out_Mux", 546 SND_SOC_NOPM, 0, 0, &i2s3_out_mux_control), 547 SND_SOC_DAPM_INPUT("I2S_DUMMY_IN"), 548 SND_SOC_DAPM_MUX("I2S0_In_Mux", 549 SND_SOC_NOPM, 0, 0, &i2s0_in_mux_control), 550 SND_SOC_DAPM_MUX("I2S2_In_Mux", 551 SND_SOC_NOPM, 0, 0, &i2s2_in_mux_control), 552 553 /* i2s in lpbk */ 554 SND_SOC_DAPM_MUX("I2S0_Lpbk_Mux", 555 SND_SOC_NOPM, 0, 0, &i2s0_lpbk_mux_control), 556 SND_SOC_DAPM_MUX("I2S2_Lpbk_Mux", 557 SND_SOC_NOPM, 0, 0, &i2s2_lpbk_mux_control), 558 }; 559 560 static int mtk_afe_i2s_share_connect(struct snd_soc_dapm_widget *source, 561 struct snd_soc_dapm_widget *sink) 562 { 563 struct snd_soc_dapm_widget *w = sink; 564 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 565 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 566 struct mtk_afe_i2s_priv *i2s_priv; 567 568 i2s_priv = get_i2s_priv_by_name(afe, sink->name); 569 570 if (!i2s_priv) { 571 dev_err(afe->dev, "%s(), i2s_priv == NULL", __func__); 572 return 0; 573 } 574 575 if (i2s_priv->share_i2s_id < 0) 576 return 0; 577 578 return i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name); 579 } 580 581 static int mtk_afe_i2s_hd_connect(struct snd_soc_dapm_widget *source, 582 struct snd_soc_dapm_widget *sink) 583 { 584 struct snd_soc_dapm_widget *w = sink; 585 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 586 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 587 struct mtk_afe_i2s_priv *i2s_priv; 588 589 i2s_priv = get_i2s_priv_by_name(afe, sink->name); 590 591 if (!i2s_priv) { 592 dev_err(afe->dev, "%s(), i2s_priv == NULL", __func__); 593 return 0; 594 } 595 596 if (get_i2s_id_by_name(afe, sink->name) == 597 get_i2s_id_by_name(afe, source->name)) 598 return i2s_priv->low_jitter_en; 599 600 /* check if share i2s need hd en */ 601 if (i2s_priv->share_i2s_id < 0) 602 return 0; 603 604 if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name)) 605 return i2s_priv->low_jitter_en; 606 607 return 0; 608 } 609 610 static int mtk_afe_i2s_apll_connect(struct snd_soc_dapm_widget *source, 611 struct snd_soc_dapm_widget *sink) 612 { 613 struct snd_soc_dapm_widget *w = sink; 614 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 615 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 616 struct mtk_afe_i2s_priv *i2s_priv; 617 int cur_apll; 618 int i2s_need_apll; 619 620 i2s_priv = get_i2s_priv_by_name(afe, w->name); 621 622 if (!i2s_priv) { 623 dev_err(afe->dev, "%s(), i2s_priv == NULL", __func__); 624 return 0; 625 } 626 627 /* which apll */ 628 cur_apll = mt8186_get_apll_by_name(afe, source->name); 629 630 /* choose APLL from i2s rate */ 631 i2s_need_apll = mt8186_get_apll_by_rate(afe, i2s_priv->rate); 632 633 return (i2s_need_apll == cur_apll) ? 1 : 0; 634 } 635 636 static int mtk_afe_i2s_mclk_connect(struct snd_soc_dapm_widget *source, 637 struct snd_soc_dapm_widget *sink) 638 { 639 struct snd_soc_dapm_widget *w = sink; 640 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 641 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 642 struct mtk_afe_i2s_priv *i2s_priv; 643 644 i2s_priv = get_i2s_priv_by_name(afe, sink->name); 645 646 if (!i2s_priv) { 647 dev_err(afe->dev, "%s(), i2s_priv == NULL", __func__); 648 return 0; 649 } 650 651 if (get_i2s_id_by_name(afe, sink->name) == 652 get_i2s_id_by_name(afe, source->name)) 653 return (i2s_priv->mclk_rate > 0) ? 1 : 0; 654 655 /* check if share i2s need mclk */ 656 if (i2s_priv->share_i2s_id < 0) 657 return 0; 658 659 if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name)) 660 return (i2s_priv->mclk_rate > 0) ? 1 : 0; 661 662 return 0; 663 } 664 665 static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source, 666 struct snd_soc_dapm_widget *sink) 667 { 668 struct snd_soc_dapm_widget *w = sink; 669 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 670 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 671 struct mtk_afe_i2s_priv *i2s_priv; 672 int cur_apll; 673 674 i2s_priv = get_i2s_priv_by_name(afe, w->name); 675 676 if (!i2s_priv) { 677 dev_err(afe->dev, "%s(), i2s_priv == NULL", __func__); 678 return 0; 679 } 680 681 /* which apll */ 682 cur_apll = mt8186_get_apll_by_name(afe, source->name); 683 684 return (i2s_priv->mclk_apll == cur_apll) ? 1 : 0; 685 } 686 687 static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = { 688 {"Connsys I2S", NULL, "CONNSYS"}, 689 690 /* i2s0 */ 691 {"I2S0", NULL, "I2S0_EN"}, 692 {"I2S0", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, 693 {"I2S0", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, 694 {"I2S0", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, 695 696 {"I2S0", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 697 {"I2S0", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 698 {"I2S0", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 699 {"I2S0", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 700 {I2S0_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 701 {I2S0_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 702 703 {"I2S0", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 704 {"I2S0", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 705 {"I2S0", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 706 {"I2S0", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 707 {I2S0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 708 {I2S0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 709 710 /* i2s1 */ 711 {"I2S1_CH1", "DL1_CH1 Switch", "DL1"}, 712 {"I2S1_CH2", "DL1_CH2 Switch", "DL1"}, 713 714 {"I2S1_CH1", "DL2_CH1 Switch", "DL2"}, 715 {"I2S1_CH2", "DL2_CH2 Switch", "DL2"}, 716 717 {"I2S1_CH1", "DL3_CH1 Switch", "DL3"}, 718 {"I2S1_CH2", "DL3_CH2 Switch", "DL3"}, 719 720 {"I2S1_CH1", "DL12_CH1 Switch", "DL12"}, 721 {"I2S1_CH2", "DL12_CH2 Switch", "DL12"}, 722 723 {"I2S1_CH1", "DL12_CH3 Switch", "DL12"}, 724 {"I2S1_CH2", "DL12_CH4 Switch", "DL12"}, 725 726 {"I2S1_CH1", "DL6_CH1 Switch", "DL6"}, 727 {"I2S1_CH2", "DL6_CH2 Switch", "DL6"}, 728 729 {"I2S1_CH1", "DL4_CH1 Switch", "DL4"}, 730 {"I2S1_CH2", "DL4_CH2 Switch", "DL4"}, 731 732 {"I2S1_CH1", "DL5_CH1 Switch", "DL5"}, 733 {"I2S1_CH2", "DL5_CH2 Switch", "DL5"}, 734 735 {"I2S1_CH1", "DL8_CH1 Switch", "DL8"}, 736 {"I2S1_CH2", "DL8_CH2 Switch", "DL8"}, 737 738 {"I2S1", NULL, "I2S1_CH1"}, 739 {"I2S1", NULL, "I2S1_CH2"}, 740 741 {"I2S1", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, 742 {"I2S1", NULL, "I2S1_EN"}, 743 {"I2S1", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, 744 {"I2S1", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, 745 746 {"I2S1", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 747 {"I2S1", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 748 {"I2S1", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 749 {"I2S1", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 750 {I2S1_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 751 {I2S1_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 752 753 {"I2S1", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 754 {"I2S1", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 755 {"I2S1", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 756 {"I2S1", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 757 {I2S1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 758 {I2S1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 759 760 /* i2s2 */ 761 {"I2S2", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, 762 {"I2S2", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, 763 {"I2S2", NULL, "I2S2_EN"}, 764 {"I2S2", NULL, "I2S3_EN", mtk_afe_i2s_share_connect}, 765 766 {"I2S2", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 767 {"I2S2", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 768 {"I2S2", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 769 {"I2S2", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 770 {I2S2_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 771 {I2S2_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 772 773 {"I2S2", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 774 {"I2S2", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 775 {"I2S2", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 776 {"I2S2", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 777 {I2S2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 778 {I2S2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 779 780 /* i2s3 */ 781 {"I2S3_CH1", "DL1_CH1 Switch", "DL1"}, 782 {"I2S3_CH2", "DL1_CH2 Switch", "DL1"}, 783 784 {"I2S3_CH1", "DL2_CH1 Switch", "DL2"}, 785 {"I2S3_CH2", "DL2_CH2 Switch", "DL2"}, 786 787 {"I2S3_CH1", "DL3_CH1 Switch", "DL3"}, 788 {"I2S3_CH2", "DL3_CH2 Switch", "DL3"}, 789 790 {"I2S3_CH1", "DL12_CH1 Switch", "DL12"}, 791 {"I2S3_CH2", "DL12_CH2 Switch", "DL12"}, 792 793 {"I2S3_CH1", "DL12_CH3 Switch", "DL12"}, 794 {"I2S3_CH2", "DL12_CH4 Switch", "DL12"}, 795 796 {"I2S3_CH1", "DL6_CH1 Switch", "DL6"}, 797 {"I2S3_CH2", "DL6_CH2 Switch", "DL6"}, 798 799 {"I2S3_CH1", "DL4_CH1 Switch", "DL4"}, 800 {"I2S3_CH2", "DL4_CH2 Switch", "DL4"}, 801 802 {"I2S3_CH1", "DL5_CH1 Switch", "DL5"}, 803 {"I2S3_CH2", "DL5_CH2 Switch", "DL5"}, 804 805 {"I2S3_CH1", "DL8_CH1 Switch", "DL8"}, 806 {"I2S3_CH2", "DL8_CH2 Switch", "DL8"}, 807 808 {"I2S3", NULL, "I2S3_CH1"}, 809 {"I2S3", NULL, "I2S3_CH2"}, 810 811 {"I2S3", NULL, "I2S0_EN", mtk_afe_i2s_share_connect}, 812 {"I2S3", NULL, "I2S1_EN", mtk_afe_i2s_share_connect}, 813 {"I2S3", NULL, "I2S2_EN", mtk_afe_i2s_share_connect}, 814 {"I2S3", NULL, "I2S3_EN"}, 815 816 {"I2S3", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 817 {"I2S3", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 818 {"I2S3", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 819 {"I2S3", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect}, 820 {I2S3_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect}, 821 {I2S3_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect}, 822 823 {"I2S3", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 824 {"I2S3", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 825 {"I2S3", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 826 {"I2S3", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect}, 827 {I2S3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect}, 828 {I2S3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect}, 829 830 /* allow i2s on without codec on */ 831 {"I2S0", NULL, "I2S0_In_Mux"}, 832 {"I2S0_In_Mux", "Dummy_Widget", "I2S_DUMMY_IN"}, 833 834 {"I2S1_Out_Mux", "Dummy_Widget", "I2S1"}, 835 {"I2S_DUMMY_OUT", NULL, "I2S1_Out_Mux"}, 836 837 {"I2S2", NULL, "I2S2_In_Mux"}, 838 {"I2S2_In_Mux", "Dummy_Widget", "I2S_DUMMY_IN"}, 839 840 {"I2S3_Out_Mux", "Dummy_Widget", "I2S3"}, 841 {"I2S_DUMMY_OUT", NULL, "I2S3_Out_Mux"}, 842 843 /* i2s in lpbk */ 844 {"I2S0_Lpbk_Mux", "Lpbk", "I2S3"}, 845 {"I2S2_Lpbk_Mux", "Lpbk", "I2S1"}, 846 {"I2S0", NULL, "I2S0_Lpbk_Mux"}, 847 {"I2S2", NULL, "I2S2_Lpbk_Mux"}, 848 }; 849 850 /* dai ops */ 851 static int mtk_dai_connsys_i2s_hw_params(struct snd_pcm_substream *substream, 852 struct snd_pcm_hw_params *params, 853 struct snd_soc_dai *dai) 854 { 855 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 856 unsigned int rate = params_rate(params); 857 unsigned int rate_reg = mt8186_rate_transform(afe->dev, 858 rate, dai->id); 859 unsigned int i2s_con = 0; 860 861 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n", 862 __func__, dai->id, substream->stream, rate); 863 864 /* non-inverse, i2s mode, slave, 16bits, from connsys */ 865 i2s_con |= 0 << INV_PAD_CTRL_SFT; 866 i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT; 867 i2s_con |= 1 << I2S_SRC_SFT; 868 i2s_con |= get_i2s_wlen(SNDRV_PCM_FORMAT_S16_LE) << I2S_WLEN_SFT; 869 i2s_con |= 0 << I2SIN_PAD_SEL_SFT; 870 regmap_write(afe->regmap, AFE_CONNSYS_I2S_CON, i2s_con); 871 872 /* use asrc */ 873 regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON, 874 I2S_BYPSRC_MASK_SFT, 0); 875 876 /* slave mode, set i2s for asrc */ 877 regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON, 878 I2S_MODE_MASK_SFT, rate_reg << I2S_MODE_SFT); 879 880 if (rate == 44100) 881 regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x1b9000); 882 else if (rate == 32000) 883 regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x140000); 884 else 885 regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x1e0000); 886 887 /* Calibration setting */ 888 regmap_write(afe->regmap, AFE_ASRC_2CH_CON4, 0x140000); 889 regmap_write(afe->regmap, AFE_ASRC_2CH_CON9, 0x36000); 890 regmap_write(afe->regmap, AFE_ASRC_2CH_CON10, 0x2fc00); 891 regmap_write(afe->regmap, AFE_ASRC_2CH_CON6, 0x7ef4); 892 regmap_write(afe->regmap, AFE_ASRC_2CH_CON5, 0xff5986); 893 894 /* 0:Stereo 1:Mono */ 895 regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON2, 896 CHSET_IS_MONO_MASK_SFT, 0); 897 898 return 0; 899 } 900 901 static int mtk_dai_connsys_i2s_trigger(struct snd_pcm_substream *substream, 902 int cmd, struct snd_soc_dai *dai) 903 { 904 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 905 struct mt8186_afe_private *afe_priv = afe->platform_priv; 906 907 dev_dbg(afe->dev, "%s(), cmd %d, stream %d\n", 908 __func__, cmd, substream->stream); 909 910 switch (cmd) { 911 case SNDRV_PCM_TRIGGER_START: 912 case SNDRV_PCM_TRIGGER_RESUME: 913 /* i2s enable */ 914 regmap_update_bits(afe->regmap, 915 AFE_CONNSYS_I2S_CON, 916 I2S_EN_MASK_SFT, 917 BIT(I2S_EN_SFT)); 918 919 /* calibrator enable */ 920 regmap_update_bits(afe->regmap, 921 AFE_ASRC_2CH_CON5, 922 CALI_EN_MASK_SFT, 923 BIT(CALI_EN_SFT)); 924 925 /* asrc enable */ 926 regmap_update_bits(afe->regmap, 927 AFE_ASRC_2CH_CON0, 928 CON0_CHSET_STR_CLR_MASK_SFT, 929 BIT(CON0_CHSET_STR_CLR_SFT)); 930 regmap_update_bits(afe->regmap, 931 AFE_ASRC_2CH_CON0, 932 CON0_ASM_ON_MASK_SFT, 933 BIT(CON0_ASM_ON_SFT)); 934 935 afe_priv->dai_on[dai->id] = true; 936 return 0; 937 case SNDRV_PCM_TRIGGER_STOP: 938 case SNDRV_PCM_TRIGGER_SUSPEND: 939 regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0, 940 CON0_ASM_ON_MASK_SFT, 0); 941 regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON5, 942 CALI_EN_MASK_SFT, 0); 943 944 /* i2s disable */ 945 regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON, 946 I2S_EN_MASK_SFT, 0); 947 948 /* bypass asrc */ 949 regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON, 950 I2S_BYPSRC_MASK_SFT, BIT(I2S_BYPSRC_SFT)); 951 952 afe_priv->dai_on[dai->id] = false; 953 return 0; 954 default: 955 return -EINVAL; 956 } 957 return 0; 958 } 959 960 static const struct snd_soc_dai_ops mtk_dai_connsys_i2s_ops = { 961 .hw_params = mtk_dai_connsys_i2s_hw_params, 962 .trigger = mtk_dai_connsys_i2s_trigger, 963 }; 964 965 /* i2s */ 966 static int mtk_dai_i2s_config(struct mtk_base_afe *afe, 967 struct snd_pcm_hw_params *params, 968 int i2s_id) 969 { 970 struct mt8186_afe_private *afe_priv = afe->platform_priv; 971 struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[i2s_id]; 972 973 unsigned int rate = params_rate(params); 974 unsigned int rate_reg = mt8186_rate_transform(afe->dev, 975 rate, i2s_id); 976 snd_pcm_format_t format = params_format(params); 977 unsigned int i2s_con = 0; 978 int ret; 979 980 dev_dbg(afe->dev, "%s(), id %d, rate %d, format %d\n", 981 __func__, i2s_id, rate, format); 982 983 if (!i2s_priv) { 984 dev_err(afe->dev, "%s(), i2s_priv == NULL", __func__); 985 return -EINVAL; 986 } 987 988 i2s_priv->rate = rate; 989 990 switch (i2s_id) { 991 case MT8186_DAI_I2S_0: 992 i2s_con = I2S_IN_PAD_IO_MUX << I2SIN_PAD_SEL_SFT; 993 i2s_con |= rate_reg << I2S_OUT_MODE_SFT; 994 i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT; 995 i2s_con |= get_i2s_wlen(format) << I2S_WLEN_SFT; 996 regmap_update_bits(afe->regmap, AFE_I2S_CON, 997 0xffffeffa, i2s_con); 998 break; 999 case MT8186_DAI_I2S_1: 1000 i2s_con = I2S1_SEL_O28_O29 << I2S2_SEL_O03_O04_SFT; 1001 i2s_con |= rate_reg << I2S2_OUT_MODE_SFT; 1002 i2s_con |= I2S_FMT_I2S << I2S2_FMT_SFT; 1003 i2s_con |= get_i2s_wlen(format) << I2S2_WLEN_SFT; 1004 regmap_update_bits(afe->regmap, AFE_I2S_CON1, 1005 0xffffeffa, i2s_con); 1006 break; 1007 case MT8186_DAI_I2S_2: 1008 i2s_con = 8 << I2S3_UPDATE_WORD_SFT; 1009 i2s_con |= rate_reg << I2S3_OUT_MODE_SFT; 1010 i2s_con |= I2S_FMT_I2S << I2S3_FMT_SFT; 1011 i2s_con |= get_i2s_wlen(format) << I2S3_WLEN_SFT; 1012 regmap_update_bits(afe->regmap, AFE_I2S_CON2, 1013 0xffffeffa, i2s_con); 1014 break; 1015 case MT8186_DAI_I2S_3: 1016 i2s_con = rate_reg << I2S4_OUT_MODE_SFT; 1017 i2s_con |= I2S_FMT_I2S << I2S4_FMT_SFT; 1018 i2s_con |= get_i2s_wlen(format) << I2S4_WLEN_SFT; 1019 regmap_update_bits(afe->regmap, AFE_I2S_CON3, 1020 0xffffeffa, i2s_con); 1021 break; 1022 default: 1023 dev_err(afe->dev, "%s(), id %d not support\n", 1024 __func__, i2s_id); 1025 return -EINVAL; 1026 } 1027 1028 /* set share i2s */ 1029 if (i2s_priv && i2s_priv->share_i2s_id >= 0) { 1030 ret = mtk_dai_i2s_config(afe, params, i2s_priv->share_i2s_id); 1031 if (ret) 1032 return ret; 1033 } 1034 1035 return 0; 1036 } 1037 1038 static int mtk_dai_i2s_hw_params(struct snd_pcm_substream *substream, 1039 struct snd_pcm_hw_params *params, 1040 struct snd_soc_dai *dai) 1041 { 1042 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1043 1044 return mtk_dai_i2s_config(afe, params, dai->id); 1045 } 1046 1047 static int mtk_dai_i2s_set_sysclk(struct snd_soc_dai *dai, 1048 int clk_id, unsigned int freq, int dir) 1049 { 1050 struct mtk_base_afe *afe = dev_get_drvdata(dai->dev); 1051 struct mt8186_afe_private *afe_priv = afe->platform_priv; 1052 struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[dai->id]; 1053 int apll; 1054 int apll_rate; 1055 1056 if (!i2s_priv) { 1057 dev_err(afe->dev, "%s(), i2s_priv == NULL", __func__); 1058 return -EINVAL; 1059 } 1060 1061 if (dir != SND_SOC_CLOCK_OUT) { 1062 dev_err(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__); 1063 return -EINVAL; 1064 } 1065 1066 dev_dbg(afe->dev, "%s(), freq %d\n", __func__, freq); 1067 1068 apll = mt8186_get_apll_by_rate(afe, freq); 1069 apll_rate = mt8186_get_apll_rate(afe, apll); 1070 1071 if (freq > apll_rate) { 1072 dev_err(afe->dev, "%s(), freq > apll rate", __func__); 1073 return -EINVAL; 1074 } 1075 1076 if (apll_rate % freq != 0) { 1077 dev_err(afe->dev, "%s(), APLL cannot generate freq Hz", __func__); 1078 return -EINVAL; 1079 } 1080 1081 i2s_priv->mclk_rate = freq; 1082 i2s_priv->mclk_apll = apll; 1083 1084 if (i2s_priv->share_i2s_id > 0) { 1085 struct mtk_afe_i2s_priv *share_i2s_priv; 1086 1087 share_i2s_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id]; 1088 if (!share_i2s_priv) { 1089 dev_err(afe->dev, "%s(), share_i2s_priv == NULL", __func__); 1090 return -EINVAL; 1091 } 1092 1093 share_i2s_priv->mclk_rate = i2s_priv->mclk_rate; 1094 share_i2s_priv->mclk_apll = i2s_priv->mclk_apll; 1095 } 1096 1097 return 0; 1098 } 1099 1100 static const struct snd_soc_dai_ops mtk_dai_i2s_ops = { 1101 .hw_params = mtk_dai_i2s_hw_params, 1102 .set_sysclk = mtk_dai_i2s_set_sysclk, 1103 }; 1104 1105 /* dai driver */ 1106 #define MTK_CONNSYS_I2S_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 1107 1108 #define MTK_I2S_RATES (SNDRV_PCM_RATE_8000_48000 |\ 1109 SNDRV_PCM_RATE_88200 |\ 1110 SNDRV_PCM_RATE_96000 |\ 1111 SNDRV_PCM_RATE_176400 |\ 1112 SNDRV_PCM_RATE_192000) 1113 1114 #define MTK_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1115 SNDRV_PCM_FMTBIT_S24_LE |\ 1116 SNDRV_PCM_FMTBIT_S32_LE) 1117 1118 static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = { 1119 { 1120 .name = "CONNSYS_I2S", 1121 .id = MT8186_DAI_CONNSYS_I2S, 1122 .capture = { 1123 .stream_name = "Connsys I2S", 1124 .channels_min = 1, 1125 .channels_max = 2, 1126 .rates = MTK_CONNSYS_I2S_RATES, 1127 .formats = MTK_I2S_FORMATS, 1128 }, 1129 .ops = &mtk_dai_connsys_i2s_ops, 1130 }, 1131 { 1132 .name = "I2S0", 1133 .id = MT8186_DAI_I2S_0, 1134 .capture = { 1135 .stream_name = "I2S0", 1136 .channels_min = 1, 1137 .channels_max = 2, 1138 .rates = MTK_I2S_RATES, 1139 .formats = MTK_I2S_FORMATS, 1140 }, 1141 .ops = &mtk_dai_i2s_ops, 1142 }, 1143 { 1144 .name = "I2S1", 1145 .id = MT8186_DAI_I2S_1, 1146 .playback = { 1147 .stream_name = "I2S1", 1148 .channels_min = 1, 1149 .channels_max = 2, 1150 .rates = MTK_I2S_RATES, 1151 .formats = MTK_I2S_FORMATS, 1152 }, 1153 .ops = &mtk_dai_i2s_ops, 1154 }, 1155 { 1156 .name = "I2S2", 1157 .id = MT8186_DAI_I2S_2, 1158 .capture = { 1159 .stream_name = "I2S2", 1160 .channels_min = 1, 1161 .channels_max = 2, 1162 .rates = MTK_I2S_RATES, 1163 .formats = MTK_I2S_FORMATS, 1164 }, 1165 .ops = &mtk_dai_i2s_ops, 1166 }, 1167 { 1168 .name = "I2S3", 1169 .id = MT8186_DAI_I2S_3, 1170 .playback = { 1171 .stream_name = "I2S3", 1172 .channels_min = 1, 1173 .channels_max = 2, 1174 .rates = MTK_I2S_RATES, 1175 .formats = MTK_I2S_FORMATS, 1176 }, 1177 .ops = &mtk_dai_i2s_ops, 1178 } 1179 }; 1180 1181 /* this enum is merely for mtk_afe_i2s_priv declare */ 1182 enum { 1183 DAI_I2S0 = 0, 1184 DAI_I2S1, 1185 DAI_I2S2, 1186 DAI_I2S3, 1187 DAI_I2S_NUM, 1188 }; 1189 1190 static const struct mtk_afe_i2s_priv mt8186_i2s_priv[DAI_I2S_NUM] = { 1191 [DAI_I2S0] = { 1192 .id = MT8186_DAI_I2S_0, 1193 .mclk_id = MT8186_I2S0_MCK, 1194 .share_property_name = "i2s0-share", 1195 .share_i2s_id = -1, 1196 }, 1197 [DAI_I2S1] = { 1198 .id = MT8186_DAI_I2S_1, 1199 .mclk_id = MT8186_I2S1_MCK, 1200 .share_property_name = "i2s1-share", 1201 .share_i2s_id = -1, 1202 }, 1203 [DAI_I2S2] = { 1204 .id = MT8186_DAI_I2S_2, 1205 .mclk_id = MT8186_I2S2_MCK, 1206 .share_property_name = "i2s2-share", 1207 .share_i2s_id = -1, 1208 }, 1209 [DAI_I2S3] = { 1210 .id = MT8186_DAI_I2S_3, 1211 /* clock gate naming is hf_faud_i2s4_m_ck*/ 1212 .mclk_id = MT8186_I2S4_MCK, 1213 .share_property_name = "i2s3-share", 1214 .share_i2s_id = -1, 1215 } 1216 }; 1217 1218 static int mt8186_dai_i2s_get_share(struct mtk_base_afe *afe) 1219 { 1220 struct mt8186_afe_private *afe_priv = afe->platform_priv; 1221 const struct device_node *of_node = afe->dev->of_node; 1222 const char *of_str; 1223 const char *property_name; 1224 struct mtk_afe_i2s_priv *i2s_priv; 1225 int i; 1226 1227 for (i = 0; i < DAI_I2S_NUM; i++) { 1228 i2s_priv = afe_priv->dai_priv[mt8186_i2s_priv[i].id]; 1229 property_name = mt8186_i2s_priv[i].share_property_name; 1230 if (of_property_read_string(of_node, property_name, &of_str)) 1231 continue; 1232 i2s_priv->share_i2s_id = get_i2s_id_by_name(afe, of_str); 1233 } 1234 1235 return 0; 1236 } 1237 1238 static int mt8186_dai_i2s_set_priv(struct mtk_base_afe *afe) 1239 { 1240 int i; 1241 int ret; 1242 1243 for (i = 0; i < DAI_I2S_NUM; i++) { 1244 ret = mt8186_dai_set_priv(afe, mt8186_i2s_priv[i].id, 1245 sizeof(struct mtk_afe_i2s_priv), 1246 &mt8186_i2s_priv[i]); 1247 if (ret) 1248 return ret; 1249 } 1250 1251 return 0; 1252 } 1253 1254 int mt8186_dai_i2s_register(struct mtk_base_afe *afe) 1255 { 1256 struct mtk_base_afe_dai *dai; 1257 int ret; 1258 1259 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 1260 if (!dai) 1261 return -ENOMEM; 1262 1263 list_add(&dai->list, &afe->sub_dais); 1264 1265 dai->dai_drivers = mtk_dai_i2s_driver; 1266 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver); 1267 1268 dai->controls = mtk_dai_i2s_controls; 1269 dai->num_controls = ARRAY_SIZE(mtk_dai_i2s_controls); 1270 dai->dapm_widgets = mtk_dai_i2s_widgets; 1271 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets); 1272 dai->dapm_routes = mtk_dai_i2s_routes; 1273 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes); 1274 1275 /* set all dai i2s private data */ 1276 ret = mt8186_dai_i2s_set_priv(afe); 1277 if (ret) 1278 return ret; 1279 1280 /* parse share i2s */ 1281 ret = mt8186_dai_i2s_get_share(afe); 1282 if (ret) 1283 return ret; 1284 1285 return 0; 1286 } 1287