1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // MediaTek ALSA SoC Audio DAI ADDA Control 4 // 5 // Copyright (c) 2022 MediaTek Inc. 6 // Author: Jiaxin Yu <jiaxin.yu@mediatek.com> 7 8 #include <linux/regmap.h> 9 #include <linux/delay.h> 10 #include "mt8186-afe-clk.h" 11 #include "mt8186-afe-common.h" 12 #include "mt8186-afe-gpio.h" 13 #include "mt8186-interconnection.h" 14 15 enum { 16 UL_IIR_SW = 0, 17 UL_IIR_5HZ, 18 UL_IIR_10HZ, 19 UL_IIR_25HZ, 20 UL_IIR_50HZ, 21 UL_IIR_75HZ, 22 }; 23 24 enum { 25 AUDIO_SDM_LEVEL_MUTE = 0, 26 AUDIO_SDM_LEVEL_NORMAL = 0x1d, 27 /* if you change level normal */ 28 /* you need to change formula of hp impedance and dc trim too */ 29 }; 30 31 enum { 32 AUDIO_SDM_2ND = 0, 33 AUDIO_SDM_3RD, 34 }; 35 36 enum { 37 DELAY_DATA_MISO1 = 0, 38 DELAY_DATA_MISO2, 39 }; 40 41 enum { 42 MTK_AFE_ADDA_DL_RATE_8K = 0, 43 MTK_AFE_ADDA_DL_RATE_11K = 1, 44 MTK_AFE_ADDA_DL_RATE_12K = 2, 45 MTK_AFE_ADDA_DL_RATE_16K = 3, 46 MTK_AFE_ADDA_DL_RATE_22K = 4, 47 MTK_AFE_ADDA_DL_RATE_24K = 5, 48 MTK_AFE_ADDA_DL_RATE_32K = 6, 49 MTK_AFE_ADDA_DL_RATE_44K = 7, 50 MTK_AFE_ADDA_DL_RATE_48K = 8, 51 MTK_AFE_ADDA_DL_RATE_96K = 9, 52 MTK_AFE_ADDA_DL_RATE_192K = 10, 53 }; 54 55 enum { 56 MTK_AFE_ADDA_UL_RATE_8K = 0, 57 MTK_AFE_ADDA_UL_RATE_16K = 1, 58 MTK_AFE_ADDA_UL_RATE_32K = 2, 59 MTK_AFE_ADDA_UL_RATE_48K = 3, 60 MTK_AFE_ADDA_UL_RATE_96K = 4, 61 MTK_AFE_ADDA_UL_RATE_192K = 5, 62 MTK_AFE_ADDA_UL_RATE_48K_HD = 6, 63 }; 64 65 #define SDM_AUTO_RESET_THRESHOLD 0x190000 66 67 struct mtk_afe_adda_priv { 68 int dl_rate; 69 int ul_rate; 70 }; 71 72 static struct mtk_afe_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe, 73 const char *name) 74 { 75 struct mt8186_afe_private *afe_priv = afe->platform_priv; 76 int dai_id; 77 78 if (strncmp(name, "aud_dac_hires_clk", 7) == 0 || 79 strncmp(name, "aud_adc_hires_clk", 7) == 0) 80 dai_id = MT8186_DAI_ADDA; 81 else 82 return NULL; 83 84 return afe_priv->dai_priv[dai_id]; 85 } 86 87 static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe, 88 unsigned int rate) 89 { 90 switch (rate) { 91 case 8000: 92 return MTK_AFE_ADDA_DL_RATE_8K; 93 case 11025: 94 return MTK_AFE_ADDA_DL_RATE_11K; 95 case 12000: 96 return MTK_AFE_ADDA_DL_RATE_12K; 97 case 16000: 98 return MTK_AFE_ADDA_DL_RATE_16K; 99 case 22050: 100 return MTK_AFE_ADDA_DL_RATE_22K; 101 case 24000: 102 return MTK_AFE_ADDA_DL_RATE_24K; 103 case 32000: 104 return MTK_AFE_ADDA_DL_RATE_32K; 105 case 44100: 106 return MTK_AFE_ADDA_DL_RATE_44K; 107 case 48000: 108 return MTK_AFE_ADDA_DL_RATE_48K; 109 case 96000: 110 return MTK_AFE_ADDA_DL_RATE_96K; 111 case 192000: 112 return MTK_AFE_ADDA_DL_RATE_192K; 113 default: 114 dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", 115 __func__, rate); 116 } 117 118 return MTK_AFE_ADDA_DL_RATE_48K; 119 } 120 121 static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe, 122 unsigned int rate) 123 { 124 switch (rate) { 125 case 8000: 126 return MTK_AFE_ADDA_UL_RATE_8K; 127 case 16000: 128 return MTK_AFE_ADDA_UL_RATE_16K; 129 case 32000: 130 return MTK_AFE_ADDA_UL_RATE_32K; 131 case 48000: 132 return MTK_AFE_ADDA_UL_RATE_48K; 133 case 96000: 134 return MTK_AFE_ADDA_UL_RATE_96K; 135 case 192000: 136 return MTK_AFE_ADDA_UL_RATE_192K; 137 default: 138 dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", 139 __func__, rate); 140 } 141 142 return MTK_AFE_ADDA_UL_RATE_48K; 143 } 144 145 /* dai component */ 146 static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = { 147 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN3, I_DL1_CH1, 1, 0), 148 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN3, I_DL12_CH1, 1, 0), 149 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN3, I_DL2_CH1, 1, 0), 150 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN3, I_DL3_CH1, 1, 0), 151 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN3_1, I_DL4_CH1, 1, 0), 152 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN3_1, I_DL5_CH1, 1, 0), 153 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN3_1, I_DL6_CH1, 1, 0), 154 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN3_1, I_DL8_CH1, 1, 0), 155 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN3, 156 I_ADDA_UL_CH2, 1, 0), 157 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN3, 158 I_ADDA_UL_CH1, 1, 0), 159 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN3, 160 I_GAIN1_OUT_CH1, 1, 0), 161 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN3, 162 I_PCM_1_CAP_CH1, 1, 0), 163 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1 Switch", AFE_CONN3, 164 I_PCM_2_CAP_CH1, 1, 0), 165 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN3_1, 166 I_SRC_1_OUT_CH1, 1, 0), 167 SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1 Switch", AFE_CONN3_1, 168 I_SRC_2_OUT_CH1, 1, 0), 169 }; 170 171 static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = { 172 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN4, I_DL1_CH1, 1, 0), 173 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN4, I_DL1_CH2, 1, 0), 174 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN4, I_DL12_CH2, 1, 0), 175 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN4, I_DL2_CH1, 1, 0), 176 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN4, I_DL2_CH2, 1, 0), 177 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN4, I_DL3_CH1, 1, 0), 178 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN4, I_DL3_CH2, 1, 0), 179 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN4_1, I_DL4_CH2, 1, 0), 180 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN4_1, I_DL5_CH2, 1, 0), 181 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN4_1, I_DL6_CH2, 1, 0), 182 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN4_1, I_DL8_CH2, 1, 0), 183 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN4, 184 I_ADDA_UL_CH2, 1, 0), 185 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN4, 186 I_ADDA_UL_CH1, 1, 0), 187 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN4, 188 I_GAIN1_OUT_CH2, 1, 0), 189 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN4, 190 I_PCM_1_CAP_CH2, 1, 0), 191 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN4, 192 I_PCM_2_CAP_CH2, 1, 0), 193 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN4_1, 194 I_SRC_1_OUT_CH2, 1, 0), 195 SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2 Switch", AFE_CONN4_1, 196 I_SRC_2_OUT_CH2, 1, 0), 197 }; 198 199 enum { 200 SUPPLY_SEQ_ADDA_AFE_ON, 201 SUPPLY_SEQ_ADDA_DL_ON, 202 SUPPLY_SEQ_ADDA_AUD_PAD_TOP, 203 SUPPLY_SEQ_ADDA_MTKAIF_CFG, 204 SUPPLY_SEQ_ADDA_FIFO, 205 SUPPLY_SEQ_ADDA_AP_DMIC, 206 SUPPLY_SEQ_ADDA_UL_ON, 207 }; 208 209 static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id) 210 { 211 unsigned int reg; 212 213 switch (id) { 214 case MT8186_DAI_ADDA: 215 case MT8186_DAI_AP_DMIC: 216 reg = AFE_ADDA_UL_SRC_CON0; 217 break; 218 default: 219 return -EINVAL; 220 } 221 222 /* dmic mode, 3.25M*/ 223 regmap_update_bits(afe->regmap, reg, 224 DIGMIC_3P25M_1P625M_SEL_MASK_SFT, 0); 225 regmap_update_bits(afe->regmap, reg, 226 DMIC_LOW_POWER_CTL_MASK_SFT, 0); 227 228 /* turn on dmic, ch1, ch2 */ 229 regmap_update_bits(afe->regmap, reg, 230 UL_SDM_3_LEVEL_MASK_SFT, 231 BIT(UL_SDM_3_LEVEL_SFT)); 232 regmap_update_bits(afe->regmap, reg, 233 UL_MODE_3P25M_CH1_CTL_MASK_SFT, 234 BIT(UL_MODE_3P25M_CH1_CTL_SFT)); 235 regmap_update_bits(afe->regmap, reg, 236 UL_MODE_3P25M_CH2_CTL_MASK_SFT, 237 BIT(UL_MODE_3P25M_CH2_CTL_SFT)); 238 239 return 0; 240 } 241 242 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w, 243 struct snd_kcontrol *kcontrol, 244 int event) 245 { 246 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 247 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 248 struct mt8186_afe_private *afe_priv = afe->platform_priv; 249 int mtkaif_dmic = afe_priv->mtkaif_dmic; 250 251 dev_dbg(afe->dev, "%s(), name %s, event 0x%x, mtkaif_dmic %d\n", 252 __func__, w->name, event, mtkaif_dmic); 253 254 switch (event) { 255 case SND_SOC_DAPM_PRE_PMU: 256 mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_ADDA, 1); 257 258 /* update setting to dmic */ 259 if (mtkaif_dmic) { 260 /* mtkaif_rxif_data_mode = 1, dmic */ 261 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, 262 0x1, 0x1); 263 264 /* dmic mode, 3.25M*/ 265 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, 266 MTKAIF_RXIF_VOICE_MODE_MASK_SFT, 267 0x0); 268 mtk_adda_ul_src_dmic(afe, MT8186_DAI_ADDA); 269 } 270 break; 271 case SND_SOC_DAPM_POST_PMD: 272 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 273 usleep_range(125, 135); 274 mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_ADDA, 1); 275 276 /* reset dmic */ 277 afe_priv->mtkaif_dmic = 0; 278 break; 279 default: 280 break; 281 } 282 283 return 0; 284 } 285 286 static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w, 287 struct snd_kcontrol *kcontrol, 288 int event) 289 { 290 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 291 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 292 struct mt8186_afe_private *afe_priv = afe->platform_priv; 293 294 switch (event) { 295 case SND_SOC_DAPM_PRE_PMU: 296 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) 297 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39); 298 else 299 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31); 300 break; 301 default: 302 break; 303 } 304 305 return 0; 306 } 307 308 static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w, 309 struct snd_kcontrol *kcontrol, 310 int event) 311 { 312 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 313 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 314 struct mt8186_afe_private *afe_priv = afe->platform_priv; 315 int delay_data; 316 int delay_cycle; 317 318 switch (event) { 319 case SND_SOC_DAPM_PRE_PMU: 320 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) { 321 /* set protocol 2 */ 322 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x10000); 323 /* mtkaif_rxif_clkinv_adc inverse */ 324 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 325 MTKAIF_RXIF_CLKINV_ADC_MASK_SFT, 326 BIT(MTKAIF_RXIF_CLKINV_ADC_SFT)); 327 328 if (strcmp(w->name, "ADDA_MTKAIF_CFG") == 0) { 329 if (afe_priv->mtkaif_chosen_phase[0] < 0 && 330 afe_priv->mtkaif_chosen_phase[1] < 0) { 331 dev_err(afe->dev, 332 "%s(), calib fail mtkaif_chosen_phase[0/1]:%d/%d\n", 333 __func__, 334 afe_priv->mtkaif_chosen_phase[0], 335 afe_priv->mtkaif_chosen_phase[1]); 336 break; 337 } 338 339 if (afe_priv->mtkaif_chosen_phase[0] < 0 || 340 afe_priv->mtkaif_chosen_phase[1] < 0) { 341 dev_err(afe->dev, 342 "%s(), skip delay setting mtkaif_chosen_phase[0/1]:%d/%d\n", 343 __func__, 344 afe_priv->mtkaif_chosen_phase[0], 345 afe_priv->mtkaif_chosen_phase[1]); 346 break; 347 } 348 } 349 350 /* set delay for ch12 */ 351 if (afe_priv->mtkaif_phase_cycle[0] >= 352 afe_priv->mtkaif_phase_cycle[1]) { 353 delay_data = DELAY_DATA_MISO1; 354 delay_cycle = afe_priv->mtkaif_phase_cycle[0] - 355 afe_priv->mtkaif_phase_cycle[1]; 356 } else { 357 delay_data = DELAY_DATA_MISO2; 358 delay_cycle = afe_priv->mtkaif_phase_cycle[1] - 359 afe_priv->mtkaif_phase_cycle[0]; 360 } 361 362 regmap_update_bits(afe->regmap, 363 AFE_ADDA_MTKAIF_RX_CFG2, 364 MTKAIF_RXIF_DELAY_DATA_MASK_SFT, 365 delay_data << 366 MTKAIF_RXIF_DELAY_DATA_SFT); 367 368 regmap_update_bits(afe->regmap, 369 AFE_ADDA_MTKAIF_RX_CFG2, 370 MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT, 371 delay_cycle << 372 MTKAIF_RXIF_DELAY_CYCLE_SFT); 373 374 } else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) { 375 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x10000); 376 } else { 377 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0); 378 } 379 380 break; 381 default: 382 break; 383 } 384 385 return 0; 386 } 387 388 static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w, 389 struct snd_kcontrol *kcontrol, 390 int event) 391 { 392 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 393 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 394 395 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 396 __func__, w->name, event); 397 398 switch (event) { 399 case SND_SOC_DAPM_PRE_PMU: 400 mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_ADDA, 0); 401 break; 402 case SND_SOC_DAPM_POST_PMD: 403 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 404 usleep_range(125, 135); 405 mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_ADDA, 0); 406 break; 407 default: 408 break; 409 } 410 411 return 0; 412 } 413 414 static int mt8186_adda_dmic_get(struct snd_kcontrol *kcontrol, 415 struct snd_ctl_elem_value *ucontrol) 416 { 417 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 418 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 419 struct mt8186_afe_private *afe_priv = afe->platform_priv; 420 421 ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic; 422 423 return 0; 424 } 425 426 static int mt8186_adda_dmic_set(struct snd_kcontrol *kcontrol, 427 struct snd_ctl_elem_value *ucontrol) 428 { 429 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 430 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 431 struct mt8186_afe_private *afe_priv = afe->platform_priv; 432 int dmic_on; 433 434 dmic_on = ucontrol->value.integer.value[0]; 435 436 dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n", 437 __func__, kcontrol->id.name, dmic_on); 438 439 if (afe_priv->mtkaif_dmic == dmic_on) 440 return 0; 441 442 afe_priv->mtkaif_dmic = dmic_on; 443 444 return 1; 445 } 446 447 static const struct snd_kcontrol_new mtk_adda_controls[] = { 448 SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1, 449 DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0), 450 SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0, 451 mt8186_adda_dmic_get, mt8186_adda_dmic_set), 452 }; 453 454 /* ADDA UL MUX */ 455 enum { 456 ADDA_UL_MUX_MTKAIF = 0, 457 ADDA_UL_MUX_AP_DMIC, 458 ADDA_UL_MUX_MASK = 0x1, 459 }; 460 461 static const char * const adda_ul_mux_map[] = { 462 "MTKAIF", "AP_DMIC" 463 }; 464 465 static int adda_ul_map_value[] = { 466 ADDA_UL_MUX_MTKAIF, 467 ADDA_UL_MUX_AP_DMIC, 468 }; 469 470 static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum, 471 SND_SOC_NOPM, 472 0, 473 ADDA_UL_MUX_MASK, 474 adda_ul_mux_map, 475 adda_ul_map_value); 476 477 static const struct snd_kcontrol_new adda_ul_mux_control = 478 SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum); 479 480 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = { 481 /* inter-connections */ 482 SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0, 483 mtk_adda_dl_ch1_mix, 484 ARRAY_SIZE(mtk_adda_dl_ch1_mix)), 485 SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0, 486 mtk_adda_dl_ch2_mix, 487 ARRAY_SIZE(mtk_adda_dl_ch2_mix)), 488 489 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON, 490 AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0, 491 NULL, 0), 492 493 SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON, 494 AFE_ADDA_DL_SRC2_CON0, 495 DL_2_SRC_ON_CTL_PRE_SFT, 0, 496 mtk_adda_dl_event, 497 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 498 499 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 500 AFE_ADDA_UL_SRC_CON0, 501 UL_SRC_ON_CTL_SFT, 0, 502 mtk_adda_ul_event, 503 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 504 505 SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP, 506 0, 0, 0, 507 mtk_adda_pad_top_event, 508 SND_SOC_DAPM_PRE_PMU), 509 SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG, 510 SND_SOC_NOPM, 0, 0, 511 mtk_adda_mtkaif_cfg_event, 512 SND_SOC_DAPM_PRE_PMU), 513 514 SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC, 515 AFE_ADDA_UL_SRC_CON0, 516 UL_AP_DMIC_ON_SFT, 0, 517 NULL, 0), 518 519 SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO, 520 AFE_ADDA_UL_DL_CON0, 521 AFE_ADDA_FIFO_AUTO_RST_SFT, 1, 522 NULL, 0), 523 524 SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0, 525 &adda_ul_mux_control), 526 527 SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"), 528 529 /* clock */ 530 SND_SOC_DAPM_CLOCK_SUPPLY("top_mux_audio_h"), 531 532 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"), 533 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires_clk"), 534 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"), 535 536 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"), 537 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires_clk"), 538 }; 539 540 #define HIRES_THRESHOLD 48000 541 static int mtk_afe_dac_hires_connect(struct snd_soc_dapm_widget *source, 542 struct snd_soc_dapm_widget *sink) 543 { 544 struct snd_soc_dapm_widget *w = source; 545 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 546 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 547 struct mtk_afe_adda_priv *adda_priv; 548 549 adda_priv = get_adda_priv_by_name(afe, w->name); 550 551 if (!adda_priv) { 552 dev_err(afe->dev, "%s(), adda_priv == NULL", __func__); 553 return 0; 554 } 555 556 return (adda_priv->dl_rate > HIRES_THRESHOLD) ? 1 : 0; 557 } 558 559 static int mtk_afe_adc_hires_connect(struct snd_soc_dapm_widget *source, 560 struct snd_soc_dapm_widget *sink) 561 { 562 struct snd_soc_dapm_widget *w = source; 563 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 564 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 565 struct mtk_afe_adda_priv *adda_priv; 566 567 adda_priv = get_adda_priv_by_name(afe, w->name); 568 569 if (!adda_priv) { 570 dev_err(afe->dev, "%s(), adda_priv == NULL", __func__); 571 return 0; 572 } 573 574 return (adda_priv->ul_rate > HIRES_THRESHOLD) ? 1 : 0; 575 } 576 577 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = { 578 /* playback */ 579 {"ADDA_DL_CH1", "DL1_CH1 Switch", "DL1"}, 580 {"ADDA_DL_CH2", "DL1_CH1 Switch", "DL1"}, 581 {"ADDA_DL_CH2", "DL1_CH2 Switch", "DL1"}, 582 583 {"ADDA_DL_CH1", "DL12_CH1 Switch", "DL12"}, 584 {"ADDA_DL_CH2", "DL12_CH2 Switch", "DL12"}, 585 586 {"ADDA_DL_CH1", "DL6_CH1 Switch", "DL6"}, 587 {"ADDA_DL_CH2", "DL6_CH2 Switch", "DL6"}, 588 589 {"ADDA_DL_CH1", "DL8_CH1 Switch", "DL8"}, 590 {"ADDA_DL_CH2", "DL8_CH2 Switch", "DL8"}, 591 592 {"ADDA_DL_CH1", "DL2_CH1 Switch", "DL2"}, 593 {"ADDA_DL_CH2", "DL2_CH1 Switch", "DL2"}, 594 {"ADDA_DL_CH2", "DL2_CH2 Switch", "DL2"}, 595 596 {"ADDA_DL_CH1", "DL3_CH1 Switch", "DL3"}, 597 {"ADDA_DL_CH2", "DL3_CH1 Switch", "DL3"}, 598 {"ADDA_DL_CH2", "DL3_CH2 Switch", "DL3"}, 599 600 {"ADDA_DL_CH1", "DL4_CH1 Switch", "DL4"}, 601 {"ADDA_DL_CH2", "DL4_CH2 Switch", "DL4"}, 602 603 {"ADDA_DL_CH1", "DL5_CH1 Switch", "DL5"}, 604 {"ADDA_DL_CH2", "DL5_CH2 Switch", "DL5"}, 605 606 {"ADDA Playback", NULL, "ADDA_DL_CH1"}, 607 {"ADDA Playback", NULL, "ADDA_DL_CH2"}, 608 609 {"ADDA Playback", NULL, "ADDA Enable"}, 610 {"ADDA Playback", NULL, "ADDA Playback Enable"}, 611 612 /* capture */ 613 {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"}, 614 {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"}, 615 616 {"ADDA Capture", NULL, "ADDA Enable"}, 617 {"ADDA Capture", NULL, "ADDA Capture Enable"}, 618 {"ADDA Capture", NULL, "AUD_PAD_TOP"}, 619 {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"}, 620 621 {"AP DMIC Capture", NULL, "ADDA Enable"}, 622 {"AP DMIC Capture", NULL, "ADDA Capture Enable"}, 623 {"AP DMIC Capture", NULL, "ADDA_FIFO"}, 624 {"AP DMIC Capture", NULL, "AP_DMIC_EN"}, 625 626 {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"}, 627 628 /* clk */ 629 {"ADDA Playback", NULL, "aud_dac_clk"}, 630 {"ADDA Playback", NULL, "aud_dac_predis_clk"}, 631 {"ADDA Playback", NULL, "aud_dac_hires_clk", mtk_afe_dac_hires_connect}, 632 633 {"ADDA Capture Enable", NULL, "aud_adc_clk"}, 634 {"ADDA Capture Enable", NULL, "aud_adc_hires_clk", 635 mtk_afe_adc_hires_connect}, 636 637 /* hires source from apll1 */ 638 {"top_mux_audio_h", NULL, APLL2_W_NAME}, 639 640 {"aud_dac_hires_clk", NULL, "top_mux_audio_h"}, 641 {"aud_adc_hires_clk", NULL, "top_mux_audio_h"}, 642 }; 643 644 /* dai ops */ 645 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream, 646 struct snd_pcm_hw_params *params, 647 struct snd_soc_dai *dai) 648 { 649 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 650 struct mt8186_afe_private *afe_priv = afe->platform_priv; 651 unsigned int rate = params_rate(params); 652 int id = dai->id; 653 struct mtk_afe_adda_priv *adda_priv = afe_priv->dai_priv[id]; 654 655 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n", 656 __func__, id, substream->stream, rate); 657 658 if (!adda_priv) { 659 dev_err(afe->dev, "%s(), adda_priv == NULL", __func__); 660 return -EINVAL; 661 } 662 663 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 664 unsigned int dl_src2_con0; 665 unsigned int dl_src2_con1; 666 667 adda_priv->dl_rate = rate; 668 669 /* set sampling rate */ 670 dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 671 DL_2_INPUT_MODE_CTL_SFT; 672 673 /* set output mode, UP_SAMPLING_RATE_X8 */ 674 dl_src2_con0 |= (0x3 << DL_2_OUTPUT_SEL_CTL_SFT); 675 676 /* turn off mute function */ 677 dl_src2_con0 |= BIT(DL_2_MUTE_CH2_OFF_CTL_PRE_SFT); 678 dl_src2_con0 |= BIT(DL_2_MUTE_CH1_OFF_CTL_PRE_SFT); 679 680 /* set voice input data if input sample rate is 8k or 16k */ 681 if (rate == 8000 || rate == 16000) 682 dl_src2_con0 |= BIT(DL_2_VOICE_MODE_CTL_PRE_SFT); 683 684 /* SA suggest apply -0.3db to audio/speech path */ 685 dl_src2_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL << 686 DL_2_GAIN_CTL_PRE_SFT; 687 688 /* turn on down-link gain */ 689 dl_src2_con0 |= BIT(DL_2_GAIN_ON_CTL_PRE_SFT); 690 691 if (id == MT8186_DAI_ADDA) { 692 /* clean predistortion */ 693 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0); 694 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0); 695 696 regmap_write(afe->regmap, 697 AFE_ADDA_DL_SRC2_CON0, dl_src2_con0); 698 regmap_write(afe->regmap, 699 AFE_ADDA_DL_SRC2_CON1, dl_src2_con1); 700 701 /* set sdm gain */ 702 regmap_update_bits(afe->regmap, 703 AFE_ADDA_DL_SDM_DCCOMP_CON, 704 ATTGAIN_CTL_MASK_SFT, 705 AUDIO_SDM_LEVEL_NORMAL << 706 ATTGAIN_CTL_SFT); 707 708 /* Use new 2nd sdm */ 709 regmap_update_bits(afe->regmap, 710 AFE_ADDA_DL_SDM_DITHER_CON, 711 AFE_DL_SDM_DITHER_64TAP_EN_MASK_SFT, 712 BIT(AFE_DL_SDM_DITHER_64TAP_EN_SFT)); 713 regmap_update_bits(afe->regmap, 714 AFE_ADDA_DL_SDM_AUTO_RESET_CON, 715 AFE_DL_USE_NEW_2ND_SDM_MASK_SFT, 716 BIT(AFE_DL_USE_NEW_2ND_SDM_SFT)); 717 regmap_update_bits(afe->regmap, 718 AFE_ADDA_DL_SDM_DCCOMP_CON, 719 USE_3RD_SDM_MASK_SFT, 720 AUDIO_SDM_2ND << USE_3RD_SDM_SFT); 721 722 /* sdm auto reset */ 723 regmap_write(afe->regmap, 724 AFE_ADDA_DL_SDM_AUTO_RESET_CON, 725 SDM_AUTO_RESET_THRESHOLD); 726 regmap_update_bits(afe->regmap, 727 AFE_ADDA_DL_SDM_AUTO_RESET_CON, 728 SDM_AUTO_RESET_TEST_ON_MASK_SFT, 729 BIT(SDM_AUTO_RESET_TEST_ON_SFT)); 730 } 731 } else { 732 unsigned int ul_src_con0 = 0; 733 unsigned int voice_mode = adda_ul_rate_transform(afe, rate); 734 735 adda_priv->ul_rate = rate; 736 ul_src_con0 |= (voice_mode << 17) & (0x7 << 17); 737 738 /* enable iir */ 739 ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) & 740 UL_IIR_ON_TMP_CTL_MASK_SFT; 741 ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) & 742 UL_IIRMODE_CTL_MASK_SFT; 743 switch (id) { 744 case MT8186_DAI_ADDA: 745 case MT8186_DAI_AP_DMIC: 746 /* 35Hz @ 48k */ 747 regmap_write(afe->regmap, 748 AFE_ADDA_IIR_COEF_02_01, 0); 749 regmap_write(afe->regmap, 750 AFE_ADDA_IIR_COEF_04_03, 0x3fb8); 751 regmap_write(afe->regmap, 752 AFE_ADDA_IIR_COEF_06_05, 0x3fb80000); 753 regmap_write(afe->regmap, 754 AFE_ADDA_IIR_COEF_08_07, 0x3fb80000); 755 regmap_write(afe->regmap, 756 AFE_ADDA_IIR_COEF_10_09, 0xc048); 757 758 regmap_write(afe->regmap, 759 AFE_ADDA_UL_SRC_CON0, ul_src_con0); 760 761 /* Using Internal ADC */ 762 regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, BIT(0), 0); 763 764 /* mtkaif_rxif_data_mode = 0, amic */ 765 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, BIT(0), 0); 766 break; 767 default: 768 break; 769 } 770 771 /* ap dmic */ 772 switch (id) { 773 case MT8186_DAI_AP_DMIC: 774 mtk_adda_ul_src_dmic(afe, id); 775 break; 776 default: 777 break; 778 } 779 } 780 781 return 0; 782 } 783 784 static const struct snd_soc_dai_ops mtk_dai_adda_ops = { 785 .hw_params = mtk_dai_adda_hw_params, 786 }; 787 788 /* dai driver */ 789 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\ 790 SNDRV_PCM_RATE_96000 |\ 791 SNDRV_PCM_RATE_192000) 792 793 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 794 SNDRV_PCM_RATE_16000 |\ 795 SNDRV_PCM_RATE_32000 |\ 796 SNDRV_PCM_RATE_48000 |\ 797 SNDRV_PCM_RATE_96000 |\ 798 SNDRV_PCM_RATE_192000) 799 800 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 801 SNDRV_PCM_FMTBIT_S24_LE |\ 802 SNDRV_PCM_FMTBIT_S32_LE) 803 804 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = { 805 { 806 .name = "ADDA", 807 .id = MT8186_DAI_ADDA, 808 .playback = { 809 .stream_name = "ADDA Playback", 810 .channels_min = 1, 811 .channels_max = 2, 812 .rates = MTK_ADDA_PLAYBACK_RATES, 813 .formats = MTK_ADDA_FORMATS, 814 }, 815 .capture = { 816 .stream_name = "ADDA Capture", 817 .channels_min = 1, 818 .channels_max = 2, 819 .rates = MTK_ADDA_CAPTURE_RATES, 820 .formats = MTK_ADDA_FORMATS, 821 }, 822 .ops = &mtk_dai_adda_ops, 823 }, 824 { 825 .name = "AP_DMIC", 826 .id = MT8186_DAI_AP_DMIC, 827 .capture = { 828 .stream_name = "AP DMIC Capture", 829 .channels_min = 1, 830 .channels_max = 2, 831 .rates = MTK_ADDA_CAPTURE_RATES, 832 .formats = MTK_ADDA_FORMATS, 833 }, 834 .ops = &mtk_dai_adda_ops, 835 }, 836 }; 837 838 int mt8186_dai_adda_register(struct mtk_base_afe *afe) 839 { 840 struct mtk_base_afe_dai *dai; 841 struct mt8186_afe_private *afe_priv = afe->platform_priv; 842 int ret; 843 844 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 845 if (!dai) 846 return -ENOMEM; 847 848 list_add(&dai->list, &afe->sub_dais); 849 850 dai->dai_drivers = mtk_dai_adda_driver; 851 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver); 852 853 dai->controls = mtk_adda_controls; 854 dai->num_controls = ARRAY_SIZE(mtk_adda_controls); 855 dai->dapm_widgets = mtk_dai_adda_widgets; 856 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets); 857 dai->dapm_routes = mtk_dai_adda_routes; 858 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes); 859 860 /* set dai priv */ 861 ret = mt8186_dai_set_priv(afe, MT8186_DAI_ADDA, 862 sizeof(struct mtk_afe_adda_priv), NULL); 863 if (ret) 864 return ret; 865 866 /* ap dmic priv share with adda */ 867 afe_priv->dai_priv[MT8186_DAI_AP_DMIC] = 868 afe_priv->dai_priv[MT8186_DAI_ADDA]; 869 870 return 0; 871 } 872