1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // MediaTek ALSA SoC Audio DAI ADDA Control 4 // 5 // Copyright (c) 2022 MediaTek Inc. 6 // Author: Jiaxin Yu <jiaxin.yu@mediatek.com> 7 8 #include <linux/regmap.h> 9 #include <linux/delay.h> 10 #include "mt8186-afe-clk.h" 11 #include "mt8186-afe-common.h" 12 #include "mt8186-afe-gpio.h" 13 #include "mt8186-interconnection.h" 14 15 enum { 16 UL_IIR_SW = 0, 17 UL_IIR_5HZ, 18 UL_IIR_10HZ, 19 UL_IIR_25HZ, 20 UL_IIR_50HZ, 21 UL_IIR_75HZ, 22 }; 23 24 enum { 25 AUDIO_SDM_LEVEL_MUTE = 0, 26 AUDIO_SDM_LEVEL_NORMAL = 0x1d, 27 /* if you change level normal */ 28 /* you need to change formula of hp impedance and dc trim too */ 29 }; 30 31 enum { 32 AUDIO_SDM_2ND = 0, 33 AUDIO_SDM_3RD, 34 }; 35 36 enum { 37 DELAY_DATA_MISO1 = 0, 38 DELAY_DATA_MISO2, 39 }; 40 41 enum { 42 MTK_AFE_ADDA_DL_RATE_8K = 0, 43 MTK_AFE_ADDA_DL_RATE_11K = 1, 44 MTK_AFE_ADDA_DL_RATE_12K = 2, 45 MTK_AFE_ADDA_DL_RATE_16K = 3, 46 MTK_AFE_ADDA_DL_RATE_22K = 4, 47 MTK_AFE_ADDA_DL_RATE_24K = 5, 48 MTK_AFE_ADDA_DL_RATE_32K = 6, 49 MTK_AFE_ADDA_DL_RATE_44K = 7, 50 MTK_AFE_ADDA_DL_RATE_48K = 8, 51 MTK_AFE_ADDA_DL_RATE_96K = 9, 52 MTK_AFE_ADDA_DL_RATE_192K = 10, 53 }; 54 55 enum { 56 MTK_AFE_ADDA_UL_RATE_8K = 0, 57 MTK_AFE_ADDA_UL_RATE_16K = 1, 58 MTK_AFE_ADDA_UL_RATE_32K = 2, 59 MTK_AFE_ADDA_UL_RATE_48K = 3, 60 MTK_AFE_ADDA_UL_RATE_96K = 4, 61 MTK_AFE_ADDA_UL_RATE_192K = 5, 62 MTK_AFE_ADDA_UL_RATE_48K_HD = 6, 63 }; 64 65 #define SDM_AUTO_RESET_THRESHOLD 0x190000 66 67 struct mtk_afe_adda_priv { 68 int dl_rate; 69 int ul_rate; 70 }; 71 72 static struct mtk_afe_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe, 73 const char *name) 74 { 75 struct mt8186_afe_private *afe_priv = afe->platform_priv; 76 int dai_id; 77 78 if (strncmp(name, "aud_dac_hires_clk", 7) == 0 || 79 strncmp(name, "aud_adc_hires_clk", 7) == 0) 80 dai_id = MT8186_DAI_ADDA; 81 else 82 return NULL; 83 84 return afe_priv->dai_priv[dai_id]; 85 } 86 87 static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe, 88 unsigned int rate) 89 { 90 switch (rate) { 91 case 8000: 92 return MTK_AFE_ADDA_DL_RATE_8K; 93 case 11025: 94 return MTK_AFE_ADDA_DL_RATE_11K; 95 case 12000: 96 return MTK_AFE_ADDA_DL_RATE_12K; 97 case 16000: 98 return MTK_AFE_ADDA_DL_RATE_16K; 99 case 22050: 100 return MTK_AFE_ADDA_DL_RATE_22K; 101 case 24000: 102 return MTK_AFE_ADDA_DL_RATE_24K; 103 case 32000: 104 return MTK_AFE_ADDA_DL_RATE_32K; 105 case 44100: 106 return MTK_AFE_ADDA_DL_RATE_44K; 107 case 48000: 108 return MTK_AFE_ADDA_DL_RATE_48K; 109 case 96000: 110 return MTK_AFE_ADDA_DL_RATE_96K; 111 case 192000: 112 return MTK_AFE_ADDA_DL_RATE_192K; 113 default: 114 dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", 115 __func__, rate); 116 } 117 118 return MTK_AFE_ADDA_DL_RATE_48K; 119 } 120 121 static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe, 122 unsigned int rate) 123 { 124 switch (rate) { 125 case 8000: 126 return MTK_AFE_ADDA_UL_RATE_8K; 127 case 16000: 128 return MTK_AFE_ADDA_UL_RATE_16K; 129 case 32000: 130 return MTK_AFE_ADDA_UL_RATE_32K; 131 case 48000: 132 return MTK_AFE_ADDA_UL_RATE_48K; 133 case 96000: 134 return MTK_AFE_ADDA_UL_RATE_96K; 135 case 192000: 136 return MTK_AFE_ADDA_UL_RATE_192K; 137 default: 138 dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", 139 __func__, rate); 140 } 141 142 return MTK_AFE_ADDA_UL_RATE_48K; 143 } 144 145 /* dai component */ 146 static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = { 147 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN3, I_DL1_CH1, 1, 0), 148 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN3, I_DL12_CH1, 1, 0), 149 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN3, I_DL2_CH1, 1, 0), 150 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN3, I_DL3_CH1, 1, 0), 151 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN3_1, I_DL4_CH1, 1, 0), 152 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN3_1, I_DL5_CH1, 1, 0), 153 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN3_1, I_DL6_CH1, 1, 0), 154 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN3_1, I_DL8_CH1, 1, 0), 155 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN3, 156 I_ADDA_UL_CH2, 1, 0), 157 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN3, 158 I_ADDA_UL_CH1, 1, 0), 159 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN3, 160 I_GAIN1_OUT_CH1, 1, 0), 161 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN3, 162 I_PCM_1_CAP_CH1, 1, 0), 163 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1 Switch", AFE_CONN3, 164 I_PCM_2_CAP_CH1, 1, 0), 165 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN3_1, 166 I_SRC_1_OUT_CH1, 1, 0), 167 SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1 Switch", AFE_CONN3_1, 168 I_SRC_2_OUT_CH1, 1, 0), 169 }; 170 171 static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = { 172 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN4, I_DL1_CH1, 1, 0), 173 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN4, I_DL1_CH2, 1, 0), 174 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN4, I_DL12_CH2, 1, 0), 175 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN4, I_DL2_CH1, 1, 0), 176 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN4, I_DL2_CH2, 1, 0), 177 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN4, I_DL3_CH1, 1, 0), 178 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN4, I_DL3_CH2, 1, 0), 179 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN4_1, I_DL4_CH2, 1, 0), 180 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN4_1, I_DL5_CH2, 1, 0), 181 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN4_1, I_DL6_CH2, 1, 0), 182 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN4_1, I_DL8_CH2, 1, 0), 183 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN4, 184 I_ADDA_UL_CH2, 1, 0), 185 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN4, 186 I_ADDA_UL_CH1, 1, 0), 187 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN4, 188 I_GAIN1_OUT_CH2, 1, 0), 189 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN4, 190 I_PCM_1_CAP_CH2, 1, 0), 191 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN4, 192 I_PCM_2_CAP_CH2, 1, 0), 193 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN4_1, 194 I_SRC_1_OUT_CH2, 1, 0), 195 SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2 Switch", AFE_CONN4_1, 196 I_SRC_2_OUT_CH2, 1, 0), 197 }; 198 199 enum { 200 SUPPLY_SEQ_ADDA_AFE_ON, 201 SUPPLY_SEQ_ADDA_DL_ON, 202 SUPPLY_SEQ_ADDA_AUD_PAD_TOP, 203 SUPPLY_SEQ_ADDA_MTKAIF_CFG, 204 SUPPLY_SEQ_ADDA_FIFO, 205 SUPPLY_SEQ_ADDA_AP_DMIC, 206 SUPPLY_SEQ_ADDA_UL_ON, 207 }; 208 209 static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id) 210 { 211 unsigned int reg; 212 213 switch (id) { 214 case MT8186_DAI_ADDA: 215 case MT8186_DAI_AP_DMIC: 216 reg = AFE_ADDA_UL_SRC_CON0; 217 break; 218 default: 219 return -EINVAL; 220 } 221 222 /* dmic mode, 3.25M*/ 223 regmap_update_bits(afe->regmap, reg, 224 DIGMIC_3P25M_1P625M_SEL_MASK_SFT, 0); 225 regmap_update_bits(afe->regmap, reg, 226 DMIC_LOW_POWER_CTL_MASK_SFT, 0); 227 228 /* turn on dmic, ch1, ch2 */ 229 regmap_update_bits(afe->regmap, reg, 230 UL_SDM_3_LEVEL_MASK_SFT, 231 BIT(UL_SDM_3_LEVEL_SFT)); 232 regmap_update_bits(afe->regmap, reg, 233 UL_MODE_3P25M_CH1_CTL_MASK_SFT, 234 BIT(UL_MODE_3P25M_CH1_CTL_SFT)); 235 regmap_update_bits(afe->regmap, reg, 236 UL_MODE_3P25M_CH2_CTL_MASK_SFT, 237 BIT(UL_MODE_3P25M_CH2_CTL_SFT)); 238 239 return 0; 240 } 241 242 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w, 243 struct snd_kcontrol *kcontrol, 244 int event) 245 { 246 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 247 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 248 struct mt8186_afe_private *afe_priv = afe->platform_priv; 249 int mtkaif_dmic = afe_priv->mtkaif_dmic; 250 251 dev_dbg(afe->dev, "%s(), name %s, event 0x%x, mtkaif_dmic %d\n", 252 __func__, w->name, event, mtkaif_dmic); 253 254 switch (event) { 255 case SND_SOC_DAPM_PRE_PMU: 256 mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_ADDA, 1); 257 258 /* update setting to dmic */ 259 if (mtkaif_dmic) { 260 /* mtkaif_rxif_data_mode = 1, dmic */ 261 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, 262 0x1, 0x1); 263 264 /* dmic mode, 3.25M*/ 265 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, 266 MTKAIF_RXIF_VOICE_MODE_MASK_SFT, 267 0x0); 268 mtk_adda_ul_src_dmic(afe, MT8186_DAI_ADDA); 269 } 270 break; 271 case SND_SOC_DAPM_POST_PMD: 272 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 273 usleep_range(125, 135); 274 mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_ADDA, 1); 275 276 /* reset dmic */ 277 afe_priv->mtkaif_dmic = 0; 278 break; 279 default: 280 break; 281 } 282 283 return 0; 284 } 285 286 static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w, 287 struct snd_kcontrol *kcontrol, 288 int event) 289 { 290 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 291 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 292 struct mt8186_afe_private *afe_priv = afe->platform_priv; 293 294 switch (event) { 295 case SND_SOC_DAPM_PRE_PMU: 296 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) 297 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39); 298 else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) 299 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31); 300 else 301 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31); 302 break; 303 default: 304 break; 305 } 306 307 return 0; 308 } 309 310 static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w, 311 struct snd_kcontrol *kcontrol, 312 int event) 313 { 314 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 315 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 316 struct mt8186_afe_private *afe_priv = afe->platform_priv; 317 int delay_data; 318 int delay_cycle; 319 320 switch (event) { 321 case SND_SOC_DAPM_PRE_PMU: 322 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) { 323 /* set protocol 2 */ 324 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x10000); 325 /* mtkaif_rxif_clkinv_adc inverse */ 326 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 327 MTKAIF_RXIF_CLKINV_ADC_MASK_SFT, 328 BIT(MTKAIF_RXIF_CLKINV_ADC_SFT)); 329 330 if (strcmp(w->name, "ADDA_MTKAIF_CFG") == 0) { 331 if (afe_priv->mtkaif_chosen_phase[0] < 0 && 332 afe_priv->mtkaif_chosen_phase[1] < 0) { 333 dev_err(afe->dev, 334 "%s(), calib fail mtkaif_chosen_phase[0/1]:%d/%d\n", 335 __func__, 336 afe_priv->mtkaif_chosen_phase[0], 337 afe_priv->mtkaif_chosen_phase[1]); 338 break; 339 } 340 341 if (afe_priv->mtkaif_chosen_phase[0] < 0 || 342 afe_priv->mtkaif_chosen_phase[1] < 0) { 343 dev_err(afe->dev, 344 "%s(), skip delay setting mtkaif_chosen_phase[0/1]:%d/%d\n", 345 __func__, 346 afe_priv->mtkaif_chosen_phase[0], 347 afe_priv->mtkaif_chosen_phase[1]); 348 break; 349 } 350 } 351 352 /* set delay for ch12 */ 353 if (afe_priv->mtkaif_phase_cycle[0] >= 354 afe_priv->mtkaif_phase_cycle[1]) { 355 delay_data = DELAY_DATA_MISO1; 356 delay_cycle = afe_priv->mtkaif_phase_cycle[0] - 357 afe_priv->mtkaif_phase_cycle[1]; 358 } else { 359 delay_data = DELAY_DATA_MISO2; 360 delay_cycle = afe_priv->mtkaif_phase_cycle[1] - 361 afe_priv->mtkaif_phase_cycle[0]; 362 } 363 364 regmap_update_bits(afe->regmap, 365 AFE_ADDA_MTKAIF_RX_CFG2, 366 MTKAIF_RXIF_DELAY_DATA_MASK_SFT, 367 delay_data << 368 MTKAIF_RXIF_DELAY_DATA_SFT); 369 370 regmap_update_bits(afe->regmap, 371 AFE_ADDA_MTKAIF_RX_CFG2, 372 MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT, 373 delay_cycle << 374 MTKAIF_RXIF_DELAY_CYCLE_SFT); 375 376 } else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) { 377 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x10000); 378 } else { 379 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0); 380 } 381 382 break; 383 default: 384 break; 385 } 386 387 return 0; 388 } 389 390 static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w, 391 struct snd_kcontrol *kcontrol, 392 int event) 393 { 394 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 395 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 396 397 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 398 __func__, w->name, event); 399 400 switch (event) { 401 case SND_SOC_DAPM_PRE_PMU: 402 mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_ADDA, 0); 403 break; 404 case SND_SOC_DAPM_POST_PMD: 405 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 406 usleep_range(125, 135); 407 mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_ADDA, 0); 408 break; 409 default: 410 break; 411 } 412 413 return 0; 414 } 415 416 static int mt8186_adda_dmic_get(struct snd_kcontrol *kcontrol, 417 struct snd_ctl_elem_value *ucontrol) 418 { 419 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 420 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 421 struct mt8186_afe_private *afe_priv = afe->platform_priv; 422 423 ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic; 424 425 return 0; 426 } 427 428 static int mt8186_adda_dmic_set(struct snd_kcontrol *kcontrol, 429 struct snd_ctl_elem_value *ucontrol) 430 { 431 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 432 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 433 struct mt8186_afe_private *afe_priv = afe->platform_priv; 434 int dmic_on; 435 436 dmic_on = ucontrol->value.integer.value[0]; 437 438 dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n", 439 __func__, kcontrol->id.name, dmic_on); 440 441 if (afe_priv->mtkaif_dmic == dmic_on) 442 return 0; 443 444 afe_priv->mtkaif_dmic = dmic_on; 445 446 return 1; 447 } 448 449 static const struct snd_kcontrol_new mtk_adda_controls[] = { 450 SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1, 451 DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0), 452 SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0, 453 mt8186_adda_dmic_get, mt8186_adda_dmic_set), 454 }; 455 456 /* ADDA UL MUX */ 457 enum { 458 ADDA_UL_MUX_MTKAIF = 0, 459 ADDA_UL_MUX_AP_DMIC, 460 ADDA_UL_MUX_MASK = 0x1, 461 }; 462 463 static const char * const adda_ul_mux_map[] = { 464 "MTKAIF", "AP_DMIC" 465 }; 466 467 static int adda_ul_map_value[] = { 468 ADDA_UL_MUX_MTKAIF, 469 ADDA_UL_MUX_AP_DMIC, 470 }; 471 472 static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum, 473 SND_SOC_NOPM, 474 0, 475 ADDA_UL_MUX_MASK, 476 adda_ul_mux_map, 477 adda_ul_map_value); 478 479 static const struct snd_kcontrol_new adda_ul_mux_control = 480 SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum); 481 482 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = { 483 /* inter-connections */ 484 SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0, 485 mtk_adda_dl_ch1_mix, 486 ARRAY_SIZE(mtk_adda_dl_ch1_mix)), 487 SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0, 488 mtk_adda_dl_ch2_mix, 489 ARRAY_SIZE(mtk_adda_dl_ch2_mix)), 490 491 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON, 492 AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0, 493 NULL, 0), 494 495 SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON, 496 AFE_ADDA_DL_SRC2_CON0, 497 DL_2_SRC_ON_CTL_PRE_SFT, 0, 498 mtk_adda_dl_event, 499 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 500 501 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 502 AFE_ADDA_UL_SRC_CON0, 503 UL_SRC_ON_CTL_SFT, 0, 504 mtk_adda_ul_event, 505 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 506 507 SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP, 508 0, 0, 0, 509 mtk_adda_pad_top_event, 510 SND_SOC_DAPM_PRE_PMU), 511 SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG, 512 SND_SOC_NOPM, 0, 0, 513 mtk_adda_mtkaif_cfg_event, 514 SND_SOC_DAPM_PRE_PMU), 515 516 SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC, 517 AFE_ADDA_UL_SRC_CON0, 518 UL_AP_DMIC_ON_SFT, 0, 519 NULL, 0), 520 521 SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO, 522 AFE_ADDA_UL_DL_CON0, 523 AFE_ADDA_FIFO_AUTO_RST_SFT, 1, 524 NULL, 0), 525 526 SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0, 527 &adda_ul_mux_control), 528 529 SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"), 530 531 /* clock */ 532 SND_SOC_DAPM_CLOCK_SUPPLY("top_mux_audio_h"), 533 534 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"), 535 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires_clk"), 536 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"), 537 538 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"), 539 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires_clk"), 540 }; 541 542 #define HIRES_THRESHOLD 48000 543 static int mtk_afe_dac_hires_connect(struct snd_soc_dapm_widget *source, 544 struct snd_soc_dapm_widget *sink) 545 { 546 struct snd_soc_dapm_widget *w = source; 547 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 548 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 549 struct mtk_afe_adda_priv *adda_priv; 550 551 adda_priv = get_adda_priv_by_name(afe, w->name); 552 553 if (!adda_priv) { 554 dev_err(afe->dev, "%s(), adda_priv == NULL", __func__); 555 return 0; 556 } 557 558 return (adda_priv->dl_rate > HIRES_THRESHOLD) ? 1 : 0; 559 } 560 561 static int mtk_afe_adc_hires_connect(struct snd_soc_dapm_widget *source, 562 struct snd_soc_dapm_widget *sink) 563 { 564 struct snd_soc_dapm_widget *w = source; 565 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 566 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 567 struct mtk_afe_adda_priv *adda_priv; 568 569 adda_priv = get_adda_priv_by_name(afe, w->name); 570 571 if (!adda_priv) { 572 dev_err(afe->dev, "%s(), adda_priv == NULL", __func__); 573 return 0; 574 } 575 576 return (adda_priv->ul_rate > HIRES_THRESHOLD) ? 1 : 0; 577 } 578 579 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = { 580 /* playback */ 581 {"ADDA_DL_CH1", "DL1_CH1 Switch", "DL1"}, 582 {"ADDA_DL_CH2", "DL1_CH1 Switch", "DL1"}, 583 {"ADDA_DL_CH2", "DL1_CH2 Switch", "DL1"}, 584 585 {"ADDA_DL_CH1", "DL12_CH1 Switch", "DL12"}, 586 {"ADDA_DL_CH2", "DL12_CH2 Switch", "DL12"}, 587 588 {"ADDA_DL_CH1", "DL6_CH1 Switch", "DL6"}, 589 {"ADDA_DL_CH2", "DL6_CH2 Switch", "DL6"}, 590 591 {"ADDA_DL_CH1", "DL8_CH1 Switch", "DL8"}, 592 {"ADDA_DL_CH2", "DL8_CH2 Switch", "DL8"}, 593 594 {"ADDA_DL_CH1", "DL2_CH1 Switch", "DL2"}, 595 {"ADDA_DL_CH2", "DL2_CH1 Switch", "DL2"}, 596 {"ADDA_DL_CH2", "DL2_CH2 Switch", "DL2"}, 597 598 {"ADDA_DL_CH1", "DL3_CH1 Switch", "DL3"}, 599 {"ADDA_DL_CH2", "DL3_CH1 Switch", "DL3"}, 600 {"ADDA_DL_CH2", "DL3_CH2 Switch", "DL3"}, 601 602 {"ADDA_DL_CH1", "DL4_CH1 Switch", "DL4"}, 603 {"ADDA_DL_CH2", "DL4_CH2 Switch", "DL4"}, 604 605 {"ADDA_DL_CH1", "DL5_CH1 Switch", "DL5"}, 606 {"ADDA_DL_CH2", "DL5_CH2 Switch", "DL5"}, 607 608 {"ADDA Playback", NULL, "ADDA_DL_CH1"}, 609 {"ADDA Playback", NULL, "ADDA_DL_CH2"}, 610 611 {"ADDA Playback", NULL, "ADDA Enable"}, 612 {"ADDA Playback", NULL, "ADDA Playback Enable"}, 613 614 /* capture */ 615 {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"}, 616 {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"}, 617 618 {"ADDA Capture", NULL, "ADDA Enable"}, 619 {"ADDA Capture", NULL, "ADDA Capture Enable"}, 620 {"ADDA Capture", NULL, "AUD_PAD_TOP"}, 621 {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"}, 622 623 {"AP DMIC Capture", NULL, "ADDA Enable"}, 624 {"AP DMIC Capture", NULL, "ADDA Capture Enable"}, 625 {"AP DMIC Capture", NULL, "ADDA_FIFO"}, 626 {"AP DMIC Capture", NULL, "AP_DMIC_EN"}, 627 628 {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"}, 629 630 /* clk */ 631 {"ADDA Playback", NULL, "aud_dac_clk"}, 632 {"ADDA Playback", NULL, "aud_dac_predis_clk"}, 633 {"ADDA Playback", NULL, "aud_dac_hires_clk", mtk_afe_dac_hires_connect}, 634 635 {"ADDA Capture Enable", NULL, "aud_adc_clk"}, 636 {"ADDA Capture Enable", NULL, "aud_adc_hires_clk", 637 mtk_afe_adc_hires_connect}, 638 639 /* hires source from apll1 */ 640 {"top_mux_audio_h", NULL, APLL2_W_NAME}, 641 642 {"aud_dac_hires_clk", NULL, "top_mux_audio_h"}, 643 {"aud_adc_hires_clk", NULL, "top_mux_audio_h"}, 644 }; 645 646 /* dai ops */ 647 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream, 648 struct snd_pcm_hw_params *params, 649 struct snd_soc_dai *dai) 650 { 651 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 652 struct mt8186_afe_private *afe_priv = afe->platform_priv; 653 unsigned int rate = params_rate(params); 654 int id = dai->id; 655 struct mtk_afe_adda_priv *adda_priv = afe_priv->dai_priv[id]; 656 657 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n", 658 __func__, id, substream->stream, rate); 659 660 if (!adda_priv) { 661 dev_err(afe->dev, "%s(), adda_priv == NULL", __func__); 662 return -EINVAL; 663 } 664 665 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 666 unsigned int dl_src2_con0; 667 unsigned int dl_src2_con1; 668 669 adda_priv->dl_rate = rate; 670 671 /* set sampling rate */ 672 dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 673 DL_2_INPUT_MODE_CTL_SFT; 674 675 /* set output mode, UP_SAMPLING_RATE_X8 */ 676 dl_src2_con0 |= (0x3 << DL_2_OUTPUT_SEL_CTL_SFT); 677 678 /* turn off mute function */ 679 dl_src2_con0 |= BIT(DL_2_MUTE_CH2_OFF_CTL_PRE_SFT); 680 dl_src2_con0 |= BIT(DL_2_MUTE_CH1_OFF_CTL_PRE_SFT); 681 682 /* set voice input data if input sample rate is 8k or 16k */ 683 if (rate == 8000 || rate == 16000) 684 dl_src2_con0 |= BIT(DL_2_VOICE_MODE_CTL_PRE_SFT); 685 686 /* SA suggest apply -0.3db to audio/speech path */ 687 dl_src2_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL << 688 DL_2_GAIN_CTL_PRE_SFT; 689 690 /* turn on down-link gain */ 691 dl_src2_con0 |= BIT(DL_2_GAIN_ON_CTL_PRE_SFT); 692 693 if (id == MT8186_DAI_ADDA) { 694 /* clean predistortion */ 695 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0); 696 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0); 697 698 regmap_write(afe->regmap, 699 AFE_ADDA_DL_SRC2_CON0, dl_src2_con0); 700 regmap_write(afe->regmap, 701 AFE_ADDA_DL_SRC2_CON1, dl_src2_con1); 702 703 /* set sdm gain */ 704 regmap_update_bits(afe->regmap, 705 AFE_ADDA_DL_SDM_DCCOMP_CON, 706 ATTGAIN_CTL_MASK_SFT, 707 AUDIO_SDM_LEVEL_NORMAL << 708 ATTGAIN_CTL_SFT); 709 710 /* Use new 2nd sdm */ 711 regmap_update_bits(afe->regmap, 712 AFE_ADDA_DL_SDM_DITHER_CON, 713 AFE_DL_SDM_DITHER_64TAP_EN_MASK_SFT, 714 BIT(AFE_DL_SDM_DITHER_64TAP_EN_SFT)); 715 regmap_update_bits(afe->regmap, 716 AFE_ADDA_DL_SDM_AUTO_RESET_CON, 717 AFE_DL_USE_NEW_2ND_SDM_MASK_SFT, 718 BIT(AFE_DL_USE_NEW_2ND_SDM_SFT)); 719 regmap_update_bits(afe->regmap, 720 AFE_ADDA_DL_SDM_DCCOMP_CON, 721 USE_3RD_SDM_MASK_SFT, 722 AUDIO_SDM_2ND << USE_3RD_SDM_SFT); 723 724 /* sdm auto reset */ 725 regmap_write(afe->regmap, 726 AFE_ADDA_DL_SDM_AUTO_RESET_CON, 727 SDM_AUTO_RESET_THRESHOLD); 728 regmap_update_bits(afe->regmap, 729 AFE_ADDA_DL_SDM_AUTO_RESET_CON, 730 SDM_AUTO_RESET_TEST_ON_MASK_SFT, 731 BIT(SDM_AUTO_RESET_TEST_ON_SFT)); 732 } 733 } else { 734 unsigned int ul_src_con0 = 0; 735 unsigned int voice_mode = adda_ul_rate_transform(afe, rate); 736 737 adda_priv->ul_rate = rate; 738 ul_src_con0 |= (voice_mode << 17) & (0x7 << 17); 739 740 /* enable iir */ 741 ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) & 742 UL_IIR_ON_TMP_CTL_MASK_SFT; 743 ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) & 744 UL_IIRMODE_CTL_MASK_SFT; 745 switch (id) { 746 case MT8186_DAI_ADDA: 747 case MT8186_DAI_AP_DMIC: 748 /* 35Hz @ 48k */ 749 regmap_write(afe->regmap, 750 AFE_ADDA_IIR_COEF_02_01, 0); 751 regmap_write(afe->regmap, 752 AFE_ADDA_IIR_COEF_04_03, 0x3fb8); 753 regmap_write(afe->regmap, 754 AFE_ADDA_IIR_COEF_06_05, 0x3fb80000); 755 regmap_write(afe->regmap, 756 AFE_ADDA_IIR_COEF_08_07, 0x3fb80000); 757 regmap_write(afe->regmap, 758 AFE_ADDA_IIR_COEF_10_09, 0xc048); 759 760 regmap_write(afe->regmap, 761 AFE_ADDA_UL_SRC_CON0, ul_src_con0); 762 763 /* Using Internal ADC */ 764 regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, BIT(0), 0); 765 766 /* mtkaif_rxif_data_mode = 0, amic */ 767 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, BIT(0), 0); 768 break; 769 default: 770 break; 771 } 772 773 /* ap dmic */ 774 switch (id) { 775 case MT8186_DAI_AP_DMIC: 776 mtk_adda_ul_src_dmic(afe, id); 777 break; 778 default: 779 break; 780 } 781 } 782 783 return 0; 784 } 785 786 static const struct snd_soc_dai_ops mtk_dai_adda_ops = { 787 .hw_params = mtk_dai_adda_hw_params, 788 }; 789 790 /* dai driver */ 791 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\ 792 SNDRV_PCM_RATE_96000 |\ 793 SNDRV_PCM_RATE_192000) 794 795 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 796 SNDRV_PCM_RATE_16000 |\ 797 SNDRV_PCM_RATE_32000 |\ 798 SNDRV_PCM_RATE_48000 |\ 799 SNDRV_PCM_RATE_96000 |\ 800 SNDRV_PCM_RATE_192000) 801 802 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 803 SNDRV_PCM_FMTBIT_S24_LE |\ 804 SNDRV_PCM_FMTBIT_S32_LE) 805 806 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = { 807 { 808 .name = "ADDA", 809 .id = MT8186_DAI_ADDA, 810 .playback = { 811 .stream_name = "ADDA Playback", 812 .channels_min = 1, 813 .channels_max = 2, 814 .rates = MTK_ADDA_PLAYBACK_RATES, 815 .formats = MTK_ADDA_FORMATS, 816 }, 817 .capture = { 818 .stream_name = "ADDA Capture", 819 .channels_min = 1, 820 .channels_max = 2, 821 .rates = MTK_ADDA_CAPTURE_RATES, 822 .formats = MTK_ADDA_FORMATS, 823 }, 824 .ops = &mtk_dai_adda_ops, 825 }, 826 { 827 .name = "AP_DMIC", 828 .id = MT8186_DAI_AP_DMIC, 829 .capture = { 830 .stream_name = "AP DMIC Capture", 831 .channels_min = 1, 832 .channels_max = 2, 833 .rates = MTK_ADDA_CAPTURE_RATES, 834 .formats = MTK_ADDA_FORMATS, 835 }, 836 .ops = &mtk_dai_adda_ops, 837 }, 838 }; 839 840 int mt8186_dai_adda_register(struct mtk_base_afe *afe) 841 { 842 struct mtk_base_afe_dai *dai; 843 struct mt8186_afe_private *afe_priv = afe->platform_priv; 844 int ret; 845 846 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 847 if (!dai) 848 return -ENOMEM; 849 850 list_add(&dai->list, &afe->sub_dais); 851 852 dai->dai_drivers = mtk_dai_adda_driver; 853 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver); 854 855 dai->controls = mtk_adda_controls; 856 dai->num_controls = ARRAY_SIZE(mtk_adda_controls); 857 dai->dapm_widgets = mtk_dai_adda_widgets; 858 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets); 859 dai->dapm_routes = mtk_dai_adda_routes; 860 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes); 861 862 /* set dai priv */ 863 ret = mt8186_dai_set_priv(afe, MT8186_DAI_ADDA, 864 sizeof(struct mtk_afe_adda_priv), NULL); 865 if (ret) 866 return ret; 867 868 /* ap dmic priv share with adda */ 869 afe_priv->dai_priv[MT8186_DAI_AP_DMIC] = 870 afe_priv->dai_priv[MT8186_DAI_ADDA]; 871 872 return 0; 873 } 874