1*a94aec03SShunli Wang /* SPDX-License-Identifier: GPL-2.0 */ 2*a94aec03SShunli Wang /* 3*a94aec03SShunli Wang * Mediatek MT8183 audio driver interconnection definition 4*a94aec03SShunli Wang * 5*a94aec03SShunli Wang * Copyright (c) 2018 MediaTek Inc. 6*a94aec03SShunli Wang * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7*a94aec03SShunli Wang */ 8*a94aec03SShunli Wang 9*a94aec03SShunli Wang #ifndef _MT8183_INTERCONNECTION_H_ 10*a94aec03SShunli Wang #define _MT8183_INTERCONNECTION_H_ 11*a94aec03SShunli Wang 12*a94aec03SShunli Wang #define I_I2S0_CH1 0 13*a94aec03SShunli Wang #define I_I2S0_CH2 1 14*a94aec03SShunli Wang #define I_ADDA_UL_CH1 3 15*a94aec03SShunli Wang #define I_ADDA_UL_CH2 4 16*a94aec03SShunli Wang #define I_DL1_CH1 5 17*a94aec03SShunli Wang #define I_DL1_CH2 6 18*a94aec03SShunli Wang #define I_DL2_CH1 7 19*a94aec03SShunli Wang #define I_DL2_CH2 8 20*a94aec03SShunli Wang #define I_PCM_1_CAP_CH1 9 21*a94aec03SShunli Wang #define I_GAIN1_OUT_CH1 10 22*a94aec03SShunli Wang #define I_GAIN1_OUT_CH2 11 23*a94aec03SShunli Wang #define I_GAIN2_OUT_CH1 12 24*a94aec03SShunli Wang #define I_GAIN2_OUT_CH2 13 25*a94aec03SShunli Wang #define I_PCM_2_CAP_CH1 14 26*a94aec03SShunli Wang #define I_PCM_2_CAP_CH2 21 27*a94aec03SShunli Wang #define I_PCM_1_CAP_CH2 22 28*a94aec03SShunli Wang #define I_DL3_CH1 23 29*a94aec03SShunli Wang #define I_DL3_CH2 24 30*a94aec03SShunli Wang #define I_I2S2_CH1 25 31*a94aec03SShunli Wang #define I_I2S2_CH2 26 32*a94aec03SShunli Wang 33*a94aec03SShunli Wang #endif 34