1 /* 2 * mt6797-reg.h -- Mediatek 6797 audio driver reg definition 3 * 4 * Copyright (c) 2018 MediaTek Inc. 5 * Author: Garlic Tseng <garlic.tseng@mediatek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 and 9 * only version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #ifndef _MT6797_REG_H_ 18 #define _MT6797_REG_H_ 19 20 #define AUDIO_TOP_CON0 0x0000 21 #define AUDIO_TOP_CON1 0x0004 22 #define AUDIO_TOP_CON3 0x000c 23 #define AFE_DAC_CON0 0x0010 24 #define AFE_DAC_CON1 0x0014 25 #define AFE_I2S_CON 0x0018 26 #define AFE_DAIBT_CON0 0x001c 27 #define AFE_CONN0 0x0020 28 #define AFE_CONN1 0x0024 29 #define AFE_CONN2 0x0028 30 #define AFE_CONN3 0x002c 31 #define AFE_CONN4 0x0030 32 #define AFE_I2S_CON1 0x0034 33 #define AFE_I2S_CON2 0x0038 34 #define AFE_MRGIF_CON 0x003c 35 #define AFE_DL1_BASE 0x0040 36 #define AFE_DL1_CUR 0x0044 37 #define AFE_DL1_END 0x0048 38 #define AFE_I2S_CON3 0x004c 39 #define AFE_DL2_BASE 0x0050 40 #define AFE_DL2_CUR 0x0054 41 #define AFE_DL2_END 0x0058 42 #define AFE_CONN5 0x005c 43 #define AFE_CONN_24BIT 0x006c 44 #define AFE_AWB_BASE 0x0070 45 #define AFE_AWB_END 0x0078 46 #define AFE_AWB_CUR 0x007c 47 #define AFE_VUL_BASE 0x0080 48 #define AFE_VUL_END 0x0088 49 #define AFE_VUL_CUR 0x008c 50 #define AFE_DAI_BASE 0x0090 51 #define AFE_DAI_END 0x0098 52 #define AFE_DAI_CUR 0x009c 53 #define AFE_CONN6 0x00bc 54 #define AFE_MEMIF_MSB 0x00cc 55 #define AFE_MEMIF_MON0 0x00d0 56 #define AFE_MEMIF_MON1 0x00d4 57 #define AFE_MEMIF_MON2 0x00d8 58 #define AFE_MEMIF_MON4 0x00e0 59 #define AFE_ADDA_DL_SRC2_CON0 0x0108 60 #define AFE_ADDA_DL_SRC2_CON1 0x010c 61 #define AFE_ADDA_UL_SRC_CON0 0x0114 62 #define AFE_ADDA_UL_SRC_CON1 0x0118 63 #define AFE_ADDA_TOP_CON0 0x0120 64 #define AFE_ADDA_UL_DL_CON0 0x0124 65 #define AFE_ADDA_SRC_DEBUG 0x012c 66 #define AFE_ADDA_SRC_DEBUG_MON0 0x0130 67 #define AFE_ADDA_SRC_DEBUG_MON1 0x0134 68 #define AFE_ADDA_NEWIF_CFG0 0x0138 69 #define AFE_ADDA_NEWIF_CFG1 0x013c 70 #define AFE_ADDA_NEWIF_CFG2 0x0140 71 #define AFE_DMA_CTL 0x0150 72 #define AFE_DMA_MON0 0x0154 73 #define AFE_DMA_MON1 0x0158 74 #define AFE_SIDETONE_DEBUG 0x01d0 75 #define AFE_SIDETONE_MON 0x01d4 76 #define AFE_SIDETONE_CON0 0x01e0 77 #define AFE_SIDETONE_COEFF 0x01e4 78 #define AFE_SIDETONE_CON1 0x01e8 79 #define AFE_SIDETONE_GAIN 0x01ec 80 #define AFE_SGEN_CON0 0x01f0 81 #define AFE_SINEGEN_CON_TDM 0x01fc 82 #define AFE_TOP_CON0 0x0200 83 #define AFE_ADDA_PREDIS_CON0 0x0260 84 #define AFE_ADDA_PREDIS_CON1 0x0264 85 #define AFE_MRGIF_MON0 0x0270 86 #define AFE_MRGIF_MON1 0x0274 87 #define AFE_MRGIF_MON2 0x0278 88 #define AFE_I2S_MON 0x027c 89 #define AFE_MOD_DAI_BASE 0x0330 90 #define AFE_MOD_DAI_END 0x0338 91 #define AFE_MOD_DAI_CUR 0x033c 92 #define AFE_VUL_D2_BASE 0x0350 93 #define AFE_VUL_D2_END 0x0358 94 #define AFE_VUL_D2_CUR 0x035c 95 #define AFE_DL3_BASE 0x0360 96 #define AFE_DL3_CUR 0x0364 97 #define AFE_DL3_END 0x0368 98 #define AFE_HDMI_OUT_CON0 0x0370 99 #define AFE_HDMI_BASE 0x0374 100 #define AFE_HDMI_CUR 0x0378 101 #define AFE_HDMI_END 0x037c 102 #define AFE_HDMI_CONN0 0x0390 103 #define AFE_IRQ3_MCU_CNT_MON 0x0398 104 #define AFE_IRQ4_MCU_CNT_MON 0x039c 105 #define AFE_IRQ_MCU_CON 0x03a0 106 #define AFE_IRQ_MCU_STATUS 0x03a4 107 #define AFE_IRQ_MCU_CLR 0x03a8 108 #define AFE_IRQ_MCU_CNT1 0x03ac 109 #define AFE_IRQ_MCU_CNT2 0x03b0 110 #define AFE_IRQ_MCU_EN 0x03b4 111 #define AFE_IRQ_MCU_MON2 0x03b8 112 #define AFE_IRQ_MCU_CNT5 0x03bc 113 #define AFE_IRQ1_MCU_CNT_MON 0x03c0 114 #define AFE_IRQ2_MCU_CNT_MON 0x03c4 115 #define AFE_IRQ1_MCU_EN_CNT_MON 0x03c8 116 #define AFE_IRQ5_MCU_CNT_MON 0x03cc 117 #define AFE_MEMIF_MINLEN 0x03d0 118 #define AFE_MEMIF_MAXLEN 0x03d4 119 #define AFE_MEMIF_PBUF_SIZE 0x03d8 120 #define AFE_IRQ_MCU_CNT7 0x03dc 121 #define AFE_IRQ7_MCU_CNT_MON 0x03e0 122 #define AFE_IRQ_MCU_CNT3 0x03e4 123 #define AFE_IRQ_MCU_CNT4 0x03e8 124 #define AFE_APLL1_TUNER_CFG 0x03f0 125 #define AFE_APLL2_TUNER_CFG 0x03f4 126 #define AFE_MEMIF_HD_MODE 0x03f8 127 #define AFE_MEMIF_HDALIGN 0x03fc 128 #define AFE_GAIN1_CON0 0x0410 129 #define AFE_GAIN1_CON1 0x0414 130 #define AFE_GAIN1_CON2 0x0418 131 #define AFE_GAIN1_CON3 0x041c 132 #define AFE_CONN7 0x0420 133 #define AFE_GAIN1_CUR 0x0424 134 #define AFE_GAIN2_CON0 0x0428 135 #define AFE_GAIN2_CON1 0x042c 136 #define AFE_GAIN2_CON2 0x0430 137 #define AFE_GAIN2_CON3 0x0434 138 #define AFE_CONN8 0x0438 139 #define AFE_GAIN2_CUR 0x043c 140 #define AFE_CONN9 0x0440 141 #define AFE_CONN10 0x0444 142 #define AFE_CONN11 0x0448 143 #define AFE_CONN12 0x044c 144 #define AFE_CONN13 0x0450 145 #define AFE_CONN14 0x0454 146 #define AFE_CONN15 0x0458 147 #define AFE_CONN16 0x045c 148 #define AFE_CONN17 0x0460 149 #define AFE_CONN18 0x0464 150 #define AFE_CONN19 0x0468 151 #define AFE_CONN20 0x046c 152 #define AFE_CONN21 0x0470 153 #define AFE_CONN22 0x0474 154 #define AFE_CONN23 0x0478 155 #define AFE_CONN24 0x047c 156 #define AFE_CONN_RS 0x0494 157 #define AFE_CONN_DI 0x0498 158 #define AFE_CONN25 0x04b0 159 #define AFE_CONN26 0x04b4 160 #define AFE_CONN27 0x04b8 161 #define AFE_CONN28 0x04bc 162 #define AFE_CONN29 0x04c0 163 #define AFE_SRAM_DELSEL_CON0 0x04f0 164 #define AFE_SRAM_DELSEL_CON1 0x04f4 165 #define AFE_ASRC_CON0 0x0500 166 #define AFE_ASRC_CON1 0x0504 167 #define AFE_ASRC_CON2 0x0508 168 #define AFE_ASRC_CON3 0x050c 169 #define AFE_ASRC_CON4 0x0510 170 #define AFE_ASRC_CON5 0x0514 171 #define AFE_ASRC_CON6 0x0518 172 #define AFE_ASRC_CON7 0x051c 173 #define AFE_ASRC_CON8 0x0520 174 #define AFE_ASRC_CON9 0x0524 175 #define AFE_ASRC_CON10 0x0528 176 #define AFE_ASRC_CON11 0x052c 177 #define PCM_INTF_CON1 0x0530 178 #define PCM_INTF_CON2 0x0538 179 #define PCM2_INTF_CON 0x053c 180 #define AFE_TDM_CON1 0x0548 181 #define AFE_TDM_CON2 0x054c 182 #define AFE_ASRC_CON13 0x0550 183 #define AFE_ASRC_CON14 0x0554 184 #define AFE_ASRC_CON15 0x0558 185 #define AFE_ASRC_CON16 0x055c 186 #define AFE_ASRC_CON17 0x0560 187 #define AFE_ASRC_CON18 0x0564 188 #define AFE_ASRC_CON19 0x0568 189 #define AFE_ASRC_CON20 0x056c 190 #define AFE_ASRC_CON21 0x0570 191 #define CLK_AUDDIV_0 0x05a0 192 #define CLK_AUDDIV_1 0x05a4 193 #define CLK_AUDDIV_2 0x05a8 194 #define CLK_AUDDIV_3 0x05ac 195 #define AUDIO_TOP_DBG_CON 0x05c8 196 #define AUDIO_TOP_DBG_MON0 0x05cc 197 #define AUDIO_TOP_DBG_MON1 0x05d0 198 #define AUDIO_TOP_DBG_MON2 0x05d4 199 #define AFE_ADDA2_TOP_CON0 0x0600 200 #define AFE_ASRC4_CON0 0x06c0 201 #define AFE_ASRC4_CON1 0x06c4 202 #define AFE_ASRC4_CON2 0x06c8 203 #define AFE_ASRC4_CON3 0x06cc 204 #define AFE_ASRC4_CON4 0x06d0 205 #define AFE_ASRC4_CON5 0x06d4 206 #define AFE_ASRC4_CON6 0x06d8 207 #define AFE_ASRC4_CON7 0x06dc 208 #define AFE_ASRC4_CON8 0x06e0 209 #define AFE_ASRC4_CON9 0x06e4 210 #define AFE_ASRC4_CON10 0x06e8 211 #define AFE_ASRC4_CON11 0x06ec 212 #define AFE_ASRC4_CON12 0x06f0 213 #define AFE_ASRC4_CON13 0x06f4 214 #define AFE_ASRC4_CON14 0x06f8 215 #define AFE_ASRC2_CON0 0x0700 216 #define AFE_ASRC2_CON1 0x0704 217 #define AFE_ASRC2_CON2 0x0708 218 #define AFE_ASRC2_CON3 0x070c 219 #define AFE_ASRC2_CON4 0x0710 220 #define AFE_ASRC2_CON5 0x0714 221 #define AFE_ASRC2_CON6 0x0718 222 #define AFE_ASRC2_CON7 0x071c 223 #define AFE_ASRC2_CON8 0x0720 224 #define AFE_ASRC2_CON9 0x0724 225 #define AFE_ASRC2_CON10 0x0728 226 #define AFE_ASRC2_CON11 0x072c 227 #define AFE_ASRC2_CON12 0x0730 228 #define AFE_ASRC2_CON13 0x0734 229 #define AFE_ASRC2_CON14 0x0738 230 #define AFE_ASRC3_CON0 0x0740 231 #define AFE_ASRC3_CON1 0x0744 232 #define AFE_ASRC3_CON2 0x0748 233 #define AFE_ASRC3_CON3 0x074c 234 #define AFE_ASRC3_CON4 0x0750 235 #define AFE_ASRC3_CON5 0x0754 236 #define AFE_ASRC3_CON6 0x0758 237 #define AFE_ASRC3_CON7 0x075c 238 #define AFE_ASRC3_CON8 0x0760 239 #define AFE_ASRC3_CON9 0x0764 240 #define AFE_ASRC3_CON10 0x0768 241 #define AFE_ASRC3_CON11 0x076c 242 #define AFE_ASRC3_CON12 0x0770 243 #define AFE_ASRC3_CON13 0x0774 244 #define AFE_ASRC3_CON14 0x0778 245 #define AFE_GENERAL_REG0 0x0800 246 #define AFE_GENERAL_REG1 0x0804 247 #define AFE_GENERAL_REG2 0x0808 248 #define AFE_GENERAL_REG3 0x080c 249 #define AFE_GENERAL_REG4 0x0810 250 #define AFE_GENERAL_REG5 0x0814 251 #define AFE_GENERAL_REG6 0x0818 252 #define AFE_GENERAL_REG7 0x081c 253 #define AFE_GENERAL_REG8 0x0820 254 #define AFE_GENERAL_REG9 0x0824 255 #define AFE_GENERAL_REG10 0x0828 256 #define AFE_GENERAL_REG11 0x082c 257 #define AFE_GENERAL_REG12 0x0830 258 #define AFE_GENERAL_REG13 0x0834 259 #define AFE_GENERAL_REG14 0x0838 260 #define AFE_GENERAL_REG15 0x083c 261 #define AFE_CBIP_CFG0 0x0840 262 #define AFE_CBIP_MON0 0x0844 263 #define AFE_CBIP_SLV_MUX_MON0 0x0848 264 #define AFE_CBIP_SLV_DECODER_MON0 0x084c 265 266 #define AFE_MAX_REGISTER AFE_CBIP_SLV_DECODER_MON0 267 #define AFE_IRQ_STATUS_BITS 0x5f 268 269 /* AUDIO_TOP_CON0 */ 270 #define AHB_IDLE_EN_INT_SFT 30 271 #define AHB_IDLE_EN_INT_MASK 0x1 272 #define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 30) 273 #define AHB_IDLE_EN_EXT_SFT 29 274 #define AHB_IDLE_EN_EXT_MASK 0x1 275 #define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 29) 276 #define PDN_TML_SFT 27 277 #define PDN_TML_MASK 0x1 278 #define PDN_TML_MASK_SFT (0x1 << 27) 279 #define PDN_DAC_PREDIS_SFT 26 280 #define PDN_DAC_PREDIS_MASK 0x1 281 #define PDN_DAC_PREDIS_MASK_SFT (0x1 << 26) 282 #define PDN_DAC_SFT 25 283 #define PDN_DAC_MASK 0x1 284 #define PDN_DAC_MASK_SFT (0x1 << 25) 285 #define PDN_ADC_SFT 24 286 #define PDN_ADC_MASK 0x1 287 #define PDN_ADC_MASK_SFT (0x1 << 24) 288 #define PDN_TDM_CK_SFT 20 289 #define PDN_TDM_CK_MASK 0x1 290 #define PDN_TDM_CK_MASK_SFT (0x1 << 20) 291 #define PDN_APLL_TUNER_SFT 19 292 #define PDN_APLL_TUNER_MASK 0x1 293 #define PDN_APLL_TUNER_MASK_SFT (0x1 << 19) 294 #define PDN_APLL2_TUNER_SFT 18 295 #define PDN_APLL2_TUNER_MASK 0x1 296 #define PDN_APLL2_TUNER_MASK_SFT (0x1 << 18) 297 #define APB3_SEL_SFT 14 298 #define APB3_SEL_MASK 0x1 299 #define APB3_SEL_MASK_SFT (0x1 << 14) 300 #define APB_R2T_SFT 13 301 #define APB_R2T_MASK 0x1 302 #define APB_R2T_MASK_SFT (0x1 << 13) 303 #define APB_W2T_SFT 12 304 #define APB_W2T_MASK 0x1 305 #define APB_W2T_MASK_SFT (0x1 << 12) 306 #define PDN_24M_SFT 9 307 #define PDN_24M_MASK 0x1 308 #define PDN_24M_MASK_SFT (0x1 << 9) 309 #define PDN_22M_SFT 8 310 #define PDN_22M_MASK 0x1 311 #define PDN_22M_MASK_SFT (0x1 << 8) 312 #define PDN_ADDA4_ADC_SFT 7 313 #define PDN_ADDA4_ADC_MASK 0x1 314 #define PDN_ADDA4_ADC_MASK_SFT (0x1 << 7) 315 #define PDN_I2S_SFT 6 316 #define PDN_I2S_MASK 0x1 317 #define PDN_I2S_MASK_SFT (0x1 << 6) 318 #define PDN_AFE_SFT 2 319 #define PDN_AFE_MASK 0x1 320 #define PDN_AFE_MASK_SFT (0x1 << 2) 321 322 /* AUDIO_TOP_CON1 */ 323 #define PDN_ADC_HIRES_TML_SFT 17 324 #define PDN_ADC_HIRES_TML_MASK 0x1 325 #define PDN_ADC_HIRES_TML_MASK_SFT (0x1 << 17) 326 #define PDN_ADC_HIRES_SFT 16 327 #define PDN_ADC_HIRES_MASK 0x1 328 #define PDN_ADC_HIRES_MASK_SFT (0x1 << 16) 329 #define I2S4_BCLK_SW_CG_SFT 7 330 #define I2S4_BCLK_SW_CG_MASK 0x1 331 #define I2S4_BCLK_SW_CG_MASK_SFT (0x1 << 7) 332 #define I2S3_BCLK_SW_CG_SFT 6 333 #define I2S3_BCLK_SW_CG_MASK 0x1 334 #define I2S3_BCLK_SW_CG_MASK_SFT (0x1 << 6) 335 #define I2S2_BCLK_SW_CG_SFT 5 336 #define I2S2_BCLK_SW_CG_MASK 0x1 337 #define I2S2_BCLK_SW_CG_MASK_SFT (0x1 << 5) 338 #define I2S1_BCLK_SW_CG_SFT 4 339 #define I2S1_BCLK_SW_CG_MASK 0x1 340 #define I2S1_BCLK_SW_CG_MASK_SFT (0x1 << 4) 341 #define I2S_SOFT_RST2_SFT 2 342 #define I2S_SOFT_RST2_MASK 0x1 343 #define I2S_SOFT_RST2_MASK_SFT (0x1 << 2) 344 #define I2S_SOFT_RST_SFT 1 345 #define I2S_SOFT_RST_MASK 0x1 346 #define I2S_SOFT_RST_MASK_SFT (0x1 << 1) 347 348 /* AFE_DAC_CON0 */ 349 #define AFE_AWB_RETM_SFT 31 350 #define AFE_AWB_RETM_MASK 0x1 351 #define AFE_AWB_RETM_MASK_SFT (0x1 << 31) 352 #define AFE_DL1_DATA2_RETM_SFT 30 353 #define AFE_DL1_DATA2_RETM_MASK 0x1 354 #define AFE_DL1_DATA2_RETM_MASK_SFT (0x1 << 30) 355 #define AFE_DL2_RETM_SFT 29 356 #define AFE_DL2_RETM_MASK 0x1 357 #define AFE_DL2_RETM_MASK_SFT (0x1 << 29) 358 #define AFE_DL1_RETM_SFT 28 359 #define AFE_DL1_RETM_MASK 0x1 360 #define AFE_DL1_RETM_MASK_SFT (0x1 << 28) 361 #define AFE_ON_RETM_SFT 27 362 #define AFE_ON_RETM_MASK 0x1 363 #define AFE_ON_RETM_MASK_SFT (0x1 << 27) 364 #define MOD_DAI_DUP_WR_SFT 26 365 #define MOD_DAI_DUP_WR_MASK 0x1 366 #define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26) 367 #define DAI_MODE_SFT 24 368 #define DAI_MODE_MASK 0x3 369 #define DAI_MODE_MASK_SFT (0x3 << 24) 370 #define VUL_DATA2_MODE_SFT 20 371 #define VUL_DATA2_MODE_MASK 0xf 372 #define VUL_DATA2_MODE_MASK_SFT (0xf << 20) 373 #define DL1_DATA2_MODE_SFT 16 374 #define DL1_DATA2_MODE_MASK 0xf 375 #define DL1_DATA2_MODE_MASK_SFT (0xf << 16) 376 #define DL3_MODE_SFT 12 377 #define DL3_MODE_MASK 0xf 378 #define DL3_MODE_MASK_SFT (0xf << 12) 379 #define VUL_DATA2_R_MONO_SFT 11 380 #define VUL_DATA2_R_MONO_MASK 0x1 381 #define VUL_DATA2_R_MONO_MASK_SFT (0x1 << 11) 382 #define VUL_DATA2_DATA_SFT 10 383 #define VUL_DATA2_DATA_MASK 0x1 384 #define VUL_DATA2_DATA_MASK_SFT (0x1 << 10) 385 #define VUL_DATA2_ON_SFT 9 386 #define VUL_DATA2_ON_MASK 0x1 387 #define VUL_DATA2_ON_MASK_SFT (0x1 << 9) 388 #define DL1_DATA2_ON_SFT 8 389 #define DL1_DATA2_ON_MASK 0x1 390 #define DL1_DATA2_ON_MASK_SFT (0x1 << 8) 391 #define MOD_DAI_ON_SFT 7 392 #define MOD_DAI_ON_MASK 0x1 393 #define MOD_DAI_ON_MASK_SFT (0x1 << 7) 394 #define AWB_ON_SFT 6 395 #define AWB_ON_MASK 0x1 396 #define AWB_ON_MASK_SFT (0x1 << 6) 397 #define DL3_ON_SFT 5 398 #define DL3_ON_MASK 0x1 399 #define DL3_ON_MASK_SFT (0x1 << 5) 400 #define DAI_ON_SFT 4 401 #define DAI_ON_MASK 0x1 402 #define DAI_ON_MASK_SFT (0x1 << 4) 403 #define VUL_ON_SFT 3 404 #define VUL_ON_MASK 0x1 405 #define VUL_ON_MASK_SFT (0x1 << 3) 406 #define DL2_ON_SFT 2 407 #define DL2_ON_MASK 0x1 408 #define DL2_ON_MASK_SFT (0x1 << 2) 409 #define DL1_ON_SFT 1 410 #define DL1_ON_MASK 0x1 411 #define DL1_ON_MASK_SFT (0x1 << 1) 412 #define AFE_ON_SFT 0 413 #define AFE_ON_MASK 0x1 414 #define AFE_ON_MASK_SFT (0x1 << 0) 415 416 /* AFE_DAC_CON1 */ 417 #define MOD_DAI_MODE_SFT 30 418 #define MOD_DAI_MODE_MASK 0x3 419 #define MOD_DAI_MODE_MASK_SFT (0x3 << 30) 420 #define DAI_DUP_WR_SFT 29 421 #define DAI_DUP_WR_MASK 0x1 422 #define DAI_DUP_WR_MASK_SFT (0x1 << 29) 423 #define VUL_R_MONO_SFT 28 424 #define VUL_R_MONO_MASK 0x1 425 #define VUL_R_MONO_MASK_SFT (0x1 << 28) 426 #define VUL_DATA_SFT 27 427 #define VUL_DATA_MASK 0x1 428 #define VUL_DATA_MASK_SFT (0x1 << 27) 429 #define AXI_2X1_CG_DISABLE_SFT 26 430 #define AXI_2X1_CG_DISABLE_MASK 0x1 431 #define AXI_2X1_CG_DISABLE_MASK_SFT (0x1 << 26) 432 #define AWB_R_MONO_SFT 25 433 #define AWB_R_MONO_MASK 0x1 434 #define AWB_R_MONO_MASK_SFT (0x1 << 25) 435 #define AWB_DATA_SFT 24 436 #define AWB_DATA_MASK 0x1 437 #define AWB_DATA_MASK_SFT (0x1 << 24) 438 #define DL3_DATA_SFT 23 439 #define DL3_DATA_MASK 0x1 440 #define DL3_DATA_MASK_SFT (0x1 << 23) 441 #define DL2_DATA_SFT 22 442 #define DL2_DATA_MASK 0x1 443 #define DL2_DATA_MASK_SFT (0x1 << 22) 444 #define DL1_DATA_SFT 21 445 #define DL1_DATA_MASK 0x1 446 #define DL1_DATA_MASK_SFT (0x1 << 21) 447 #define DL1_DATA2_DATA_SFT 20 448 #define DL1_DATA2_DATA_MASK 0x1 449 #define DL1_DATA2_DATA_MASK_SFT (0x1 << 20) 450 #define VUL_MODE_SFT 16 451 #define VUL_MODE_MASK 0xf 452 #define VUL_MODE_MASK_SFT (0xf << 16) 453 #define AWB_MODE_SFT 12 454 #define AWB_MODE_MASK 0xf 455 #define AWB_MODE_MASK_SFT (0xf << 12) 456 #define I2S_MODE_SFT 8 457 #define I2S_MODE_MASK 0xf 458 #define I2S_MODE_MASK_SFT (0xf << 8) 459 #define DL2_MODE_SFT 4 460 #define DL2_MODE_MASK 0xf 461 #define DL2_MODE_MASK_SFT (0xf << 4) 462 #define DL1_MODE_SFT 0 463 #define DL1_MODE_MASK 0xf 464 #define DL1_MODE_MASK_SFT (0xf << 0) 465 466 /* AFE_ADDA_DL_SRC2_CON0 */ 467 #define DL_2_INPUT_MODE_CTL_SFT 28 468 #define DL_2_INPUT_MODE_CTL_MASK 0xf 469 #define DL_2_INPUT_MODE_CTL_MASK_SFT (0xf << 28) 470 #define DL_2_CH1_SATURATION_EN_CTL_SFT 27 471 #define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1 472 #define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27) 473 #define DL_2_CH2_SATURATION_EN_CTL_SFT 26 474 #define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1 475 #define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26) 476 #define DL_2_OUTPUT_SEL_CTL_SFT 24 477 #define DL_2_OUTPUT_SEL_CTL_MASK 0x3 478 #define DL_2_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 24) 479 #define DL_2_FADEIN_0START_EN_SFT 16 480 #define DL_2_FADEIN_0START_EN_MASK 0x3 481 #define DL_2_FADEIN_0START_EN_MASK_SFT (0x3 << 16) 482 #define DL_DISABLE_HW_CG_CTL_SFT 15 483 #define DL_DISABLE_HW_CG_CTL_MASK 0x1 484 #define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15) 485 #define C_DATA_EN_SEL_CTL_PRE_SFT 14 486 #define C_DATA_EN_SEL_CTL_PRE_MASK 0x1 487 #define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14) 488 #define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 13 489 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1 490 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13) 491 #define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 12 492 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1 493 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12) 494 #define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 11 495 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1 496 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11) 497 #define DL2_ARAMPSP_CTL_PRE_SFT 9 498 #define DL2_ARAMPSP_CTL_PRE_MASK 0x3 499 #define DL2_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9) 500 #define DL_2_IIRMODE_CTL_PRE_SFT 6 501 #define DL_2_IIRMODE_CTL_PRE_MASK 0x7 502 #define DL_2_IIRMODE_CTL_PRE_MASK_SFT (0x7 << 6) 503 #define DL_2_VOICE_MODE_CTL_PRE_SFT 5 504 #define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1 505 #define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5) 506 #define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 4 507 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1 508 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4) 509 #define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 3 510 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1 511 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3) 512 #define DL_2_IIR_ON_CTL_PRE_SFT 2 513 #define DL_2_IIR_ON_CTL_PRE_MASK 0x1 514 #define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2) 515 #define DL_2_GAIN_ON_CTL_PRE_SFT 1 516 #define DL_2_GAIN_ON_CTL_PRE_MASK 0x1 517 #define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1) 518 #define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0 519 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1 520 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0) 521 522 /* AFE_ADDA_DL_SRC2_CON1 */ 523 #define DL_2_GAIN_CTL_PRE_SFT 16 524 #define DL_2_GAIN_CTL_PRE_MASK 0xffff 525 #define DL_2_GAIN_CTL_PRE_MASK_SFT (0xffff << 16) 526 #define DL_2_GAIN_MODE_CTL_SFT 0 527 #define DL_2_GAIN_MODE_CTL_MASK 0x1 528 #define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0) 529 530 /* AFE_ADDA_UL_SRC_CON0 */ 531 #define C_COMB_OUT_SIN_GEN_CTL_SFT 31 532 #define C_COMB_OUT_SIN_GEN_CTL_MASK 0x1 533 #define C_COMB_OUT_SIN_GEN_CTL_MASK_SFT (0x1 << 31) 534 #define C_BASEBAND_SIN_GEN_CTL_SFT 30 535 #define C_BASEBAND_SIN_GEN_CTL_MASK 0x1 536 #define C_BASEBAND_SIN_GEN_CTL_MASK_SFT (0x1 << 30) 537 #define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 27 538 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7 539 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 27) 540 #define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 24 541 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7 542 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 24) 543 #define C_TWO_DIGITAL_MIC_CTL_SFT 23 544 #define C_TWO_DIGITAL_MIC_CTL_MASK 0x1 545 #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 23) 546 #define UL_MODE_3P25M_CH2_CTL_SFT 22 547 #define UL_MODE_3P25M_CH2_CTL_MASK 0x1 548 #define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22) 549 #define UL_MODE_3P25M_CH1_CTL_SFT 21 550 #define UL_MODE_3P25M_CH1_CTL_MASK 0x1 551 #define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21) 552 #define UL_SRC_USE_CIC_OUT_CTL_SFT 20 553 #define UL_SRC_USE_CIC_OUT_CTL_MASK 0x1 554 #define UL_SRC_USE_CIC_OUT_CTL_MASK_SFT (0x1 << 20) 555 #define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17 556 #define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7 557 #define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17) 558 #define DMIC_LOW_POWER_MODE_CTL_SFT 14 559 #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3 560 #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14) 561 #define DMIC_48K_SEL_CTL_SFT 13 562 #define DMIC_48K_SEL_CTL_MASK 0x1 563 #define DMIC_48K_SEL_CTL_MASK_SFT (0x1 << 13) 564 #define UL_DISABLE_HW_CG_CTL_SFT 12 565 #define UL_DISABLE_HW_CG_CTL_MASK 0x1 566 #define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12) 567 #define UL_IIR_ON_TMP_CTL_SFT 10 568 #define UL_IIR_ON_TMP_CTL_MASK 0x1 569 #define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10) 570 #define UL_IIRMODE_CTL_SFT 7 571 #define UL_IIRMODE_CTL_MASK 0x7 572 #define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7) 573 #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5 574 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1 575 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5) 576 #define AGC_260K_SEL_CH2_CTL_SFT 4 577 #define AGC_260K_SEL_CH2_CTL_MASK 0x1 578 #define AGC_260K_SEL_CH2_CTL_MASK_SFT (0x1 << 4) 579 #define AGC_260K_SEL_CH1_CTL_SFT 3 580 #define AGC_260K_SEL_CH1_CTL_MASK 0x1 581 #define AGC_260K_SEL_CH1_CTL_MASK_SFT (0x1 << 3) 582 #define UL_LOOP_BACK_MODE_CTL_SFT 2 583 #define UL_LOOP_BACK_MODE_CTL_MASK 0x1 584 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2) 585 #define UL_SDM_3_LEVEL_CTL_SFT 1 586 #define UL_SDM_3_LEVEL_CTL_MASK 0x1 587 #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1) 588 #define UL_SRC_ON_TMP_CTL_SFT 0 589 #define UL_SRC_ON_TMP_CTL_MASK 0x1 590 #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0) 591 592 /* AFE_ADDA_UL_SRC_CON1 */ 593 #define C_SDM_RESET_CTL_SFT 31 594 #define C_SDM_RESET_CTL_MASK 0x1 595 #define C_SDM_RESET_CTL_MASK_SFT (0x1 << 31) 596 #define ADITHON_CTL_SFT 30 597 #define ADITHON_CTL_MASK 0x1 598 #define ADITHON_CTL_MASK_SFT (0x1 << 30) 599 #define ADITHVAL_CTL_SFT 28 600 #define ADITHVAL_CTL_MASK 0x3 601 #define ADITHVAL_CTL_MASK_SFT (0x3 << 28) 602 #define C_DAC_EN_CTL_SFT 27 603 #define C_DAC_EN_CTL_MASK 0x1 604 #define C_DAC_EN_CTL_MASK_SFT (0x1 << 27) 605 #define C_MUTE_SW_CTL_SFT 26 606 #define C_MUTE_SW_CTL_MASK 0x1 607 #define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26) 608 #define ASDM_SRC_SEL_CTL_SFT 25 609 #define ASDM_SRC_SEL_CTL_MASK 0x1 610 #define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25) 611 #define C_AMP_DIV_CH2_CTL_SFT 21 612 #define C_AMP_DIV_CH2_CTL_MASK 0x7 613 #define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21) 614 #define C_FREQ_DIV_CH2_CTL_SFT 16 615 #define C_FREQ_DIV_CH2_CTL_MASK 0x1f 616 #define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16) 617 #define C_SINE_MODE_CH2_CTL_SFT 12 618 #define C_SINE_MODE_CH2_CTL_MASK 0xf 619 #define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12) 620 #define C_AMP_DIV_CH1_CTL_SFT 9 621 #define C_AMP_DIV_CH1_CTL_MASK 0x7 622 #define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9) 623 #define C_FREQ_DIV_CH1_CTL_SFT 4 624 #define C_FREQ_DIV_CH1_CTL_MASK 0x1f 625 #define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4) 626 #define C_SINE_MODE_CH1_CTL_SFT 0 627 #define C_SINE_MODE_CH1_CTL_MASK 0xf 628 #define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0) 629 630 /* AFE_ADDA_TOP_CON0 */ 631 #define C_LOOP_BACK_MODE_CTL_SFT 12 632 #define C_LOOP_BACK_MODE_CTL_MASK 0xf 633 #define C_LOOP_BACK_MODE_CTL_MASK_SFT (0xf << 12) 634 #define C_EXT_ADC_CTL_SFT 0 635 #define C_EXT_ADC_CTL_MASK 0x1 636 #define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0) 637 638 /* AFE_ADDA_UL_DL_CON0 */ 639 #define AFE_UL_DL_CON0_RESERVED_SFT 1 640 #define AFE_UL_DL_CON0_RESERVED_MASK 0x3fff 641 #define AFE_UL_DL_CON0_RESERVED_MASK_SFT (0x3fff << 1) 642 #define ADDA_AFE_ON_SFT 0 643 #define ADDA_AFE_ON_MASK 0x1 644 #define ADDA_AFE_ON_MASK_SFT (0x1 << 0) 645 646 /* AFE_IRQ_MCU_CON */ 647 #define IRQ7_MCU_MODE_SFT 24 648 #define IRQ7_MCU_MODE_MASK 0xf 649 #define IRQ7_MCU_MODE_MASK_SFT (0xf << 24) 650 #define IRQ4_MCU_MODE_SFT 20 651 #define IRQ4_MCU_MODE_MASK 0xf 652 #define IRQ4_MCU_MODE_MASK_SFT (0xf << 20) 653 #define IRQ3_MCU_MODE_SFT 16 654 #define IRQ3_MCU_MODE_MASK 0xf 655 #define IRQ3_MCU_MODE_MASK_SFT (0xf << 16) 656 #define IRQ7_MCU_ON_SFT 14 657 #define IRQ7_MCU_ON_MASK 0x1 658 #define IRQ7_MCU_ON_MASK_SFT (0x1 << 14) 659 #define IRQ5_MCU_ON_SFT 12 660 #define IRQ5_MCU_ON_MASK 0x1 661 #define IRQ5_MCU_ON_MASK_SFT (0x1 << 12) 662 #define IRQ2_MCU_MODE_SFT 8 663 #define IRQ2_MCU_MODE_MASK 0xf 664 #define IRQ2_MCU_MODE_MASK_SFT (0xf << 8) 665 #define IRQ1_MCU_MODE_SFT 4 666 #define IRQ1_MCU_MODE_MASK 0xf 667 #define IRQ1_MCU_MODE_MASK_SFT (0xf << 4) 668 #define IRQ4_MCU_ON_SFT 3 669 #define IRQ4_MCU_ON_MASK 0x1 670 #define IRQ4_MCU_ON_MASK_SFT (0x1 << 3) 671 #define IRQ3_MCU_ON_SFT 2 672 #define IRQ3_MCU_ON_MASK 0x1 673 #define IRQ3_MCU_ON_MASK_SFT (0x1 << 2) 674 #define IRQ2_MCU_ON_SFT 1 675 #define IRQ2_MCU_ON_MASK 0x1 676 #define IRQ2_MCU_ON_MASK_SFT (0x1 << 1) 677 #define IRQ1_MCU_ON_SFT 0 678 #define IRQ1_MCU_ON_MASK 0x1 679 #define IRQ1_MCU_ON_MASK_SFT (0x1 << 0) 680 681 /* AFE_IRQ_MCU_EN */ 682 #define AFE_IRQ_CM4_EN_SFT 16 683 #define AFE_IRQ_CM4_EN_MASK 0x7f 684 #define AFE_IRQ_CM4_EN_MASK_SFT (0x7f << 16) 685 #define AFE_IRQ_MD32_EN_SFT 8 686 #define AFE_IRQ_MD32_EN_MASK 0x7f 687 #define AFE_IRQ_MD32_EN_MASK_SFT (0x7f << 8) 688 #define AFE_IRQ_MCU_EN_SFT 0 689 #define AFE_IRQ_MCU_EN_MASK 0x7f 690 #define AFE_IRQ_MCU_EN_MASK_SFT (0x7f << 0) 691 692 /* AFE_IRQ_MCU_CLR */ 693 #define IRQ7_MCU_CLR_SFT 6 694 #define IRQ7_MCU_CLR_MASK 0x1 695 #define IRQ7_MCU_CLR_MASK_SFT (0x1 << 6) 696 #define IRQ5_MCU_CLR_SFT 4 697 #define IRQ5_MCU_CLR_MASK 0x1 698 #define IRQ5_MCU_CLR_MASK_SFT (0x1 << 4) 699 #define IRQ4_MCU_CLR_SFT 3 700 #define IRQ4_MCU_CLR_MASK 0x1 701 #define IRQ4_MCU_CLR_MASK_SFT (0x1 << 3) 702 #define IRQ3_MCU_CLR_SFT 2 703 #define IRQ3_MCU_CLR_MASK 0x1 704 #define IRQ3_MCU_CLR_MASK_SFT (0x1 << 2) 705 #define IRQ2_MCU_CLR_SFT 1 706 #define IRQ2_MCU_CLR_MASK 0x1 707 #define IRQ2_MCU_CLR_MASK_SFT (0x1 << 1) 708 #define IRQ1_MCU_CLR_SFT 0 709 #define IRQ1_MCU_CLR_MASK 0x1 710 #define IRQ1_MCU_CLR_MASK_SFT (0x1 << 0) 711 712 /* AFE_IRQ_MCU_CNT1 */ 713 #define AFE_IRQ_MCU_CNT1_SFT 0 714 #define AFE_IRQ_MCU_CNT1_MASK 0x3ffff 715 #define AFE_IRQ_MCU_CNT1_MASK_SFT (0x3ffff << 0) 716 717 /* AFE_IRQ_MCU_CNT2 */ 718 #define AFE_IRQ_MCU_CNT2_SFT 0 719 #define AFE_IRQ_MCU_CNT2_MASK 0x3ffff 720 #define AFE_IRQ_MCU_CNT2_MASK_SFT (0x3ffff << 0) 721 722 /* AFE_IRQ_MCU_CNT3 */ 723 #define AFE_IRQ_MCU_CNT3_SFT 0 724 #define AFE_IRQ_MCU_CNT3_MASK 0x3ffff 725 #define AFE_IRQ_MCU_CNT3_MASK_SFT (0x3ffff << 0) 726 727 /* AFE_IRQ_MCU_CNT4 */ 728 #define AFE_IRQ_MCU_CNT4_SFT 0 729 #define AFE_IRQ_MCU_CNT4_MASK 0x3ffff 730 #define AFE_IRQ_MCU_CNT4_MASK_SFT (0x3ffff << 0) 731 732 /* AFE_IRQ_MCU_CNT5 */ 733 #define AFE_IRQ_MCU_CNT5_SFT 0 734 #define AFE_IRQ_MCU_CNT5_MASK 0x3ffff 735 #define AFE_IRQ_MCU_CNT5_MASK_SFT (0x3ffff << 0) 736 737 /* AFE_IRQ_MCU_CNT7 */ 738 #define AFE_IRQ_MCU_CNT7_SFT 0 739 #define AFE_IRQ_MCU_CNT7_MASK 0x3ffff 740 #define AFE_IRQ_MCU_CNT7_MASK_SFT (0x3ffff << 0) 741 742 /* AFE_MEMIF_MSB */ 743 #define CPU_COMPACT_MODE_SFT 23 744 #define CPU_COMPACT_MODE_MASK 0x1 745 #define CPU_COMPACT_MODE_MASK_SFT (0x1 << 23) 746 #define CPU_HD_ALIGN_SFT 22 747 #define CPU_HD_ALIGN_MASK 0x1 748 #define CPU_HD_ALIGN_MASK_SFT (0x1 << 22) 749 750 /* AFE_MEMIF_HD_MODE */ 751 #define HDMI_HD_SFT 20 752 #define HDMI_HD_MASK 0x3 753 #define HDMI_HD_MASK_SFT (0x3 << 20) 754 #define MOD_DAI_HD_SFT 18 755 #define MOD_DAI_HD_MASK 0x3 756 #define MOD_DAI_HD_MASK_SFT (0x3 << 18) 757 #define DAI_HD_SFT 16 758 #define DAI_HD_MASK 0x3 759 #define DAI_HD_MASK_SFT (0x3 << 16) 760 #define VUL_DATA2_HD_SFT 12 761 #define VUL_DATA2_HD_MASK 0x3 762 #define VUL_DATA2_HD_MASK_SFT (0x3 << 12) 763 #define VUL_HD_SFT 10 764 #define VUL_HD_MASK 0x3 765 #define VUL_HD_MASK_SFT (0x3 << 10) 766 #define AWB_HD_SFT 8 767 #define AWB_HD_MASK 0x3 768 #define AWB_HD_MASK_SFT (0x3 << 8) 769 #define DL3_HD_SFT 6 770 #define DL3_HD_MASK 0x3 771 #define DL3_HD_MASK_SFT (0x3 << 6) 772 #define DL2_HD_SFT 4 773 #define DL2_HD_MASK 0x3 774 #define DL2_HD_MASK_SFT (0x3 << 4) 775 #define DL1_DATA2_HD_SFT 2 776 #define DL1_DATA2_HD_MASK 0x3 777 #define DL1_DATA2_HD_MASK_SFT (0x3 << 2) 778 #define DL1_HD_SFT 0 779 #define DL1_HD_MASK 0x3 780 #define DL1_HD_MASK_SFT (0x3 << 0) 781 782 /* AFE_MEMIF_HDALIGN */ 783 #define HDMI_NORMAL_MODE_SFT 26 784 #define HDMI_NORMAL_MODE_MASK 0x1 785 #define HDMI_NORMAL_MODE_MASK_SFT (0x1 << 26) 786 #define MOD_DAI_NORMAL_MODE_SFT 25 787 #define MOD_DAI_NORMAL_MODE_MASK 0x1 788 #define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 25) 789 #define DAI_NORMAL_MODE_SFT 24 790 #define DAI_NORMAL_MODE_MASK 0x1 791 #define DAI_NORMAL_MODE_MASK_SFT (0x1 << 24) 792 #define VUL_DATA2_NORMAL_MODE_SFT 22 793 #define VUL_DATA2_NORMAL_MODE_MASK 0x1 794 #define VUL_DATA2_NORMAL_MODE_MASK_SFT (0x1 << 22) 795 #define VUL_NORMAL_MODE_SFT 21 796 #define VUL_NORMAL_MODE_MASK 0x1 797 #define VUL_NORMAL_MODE_MASK_SFT (0x1 << 21) 798 #define AWB_NORMAL_MODE_SFT 20 799 #define AWB_NORMAL_MODE_MASK 0x1 800 #define AWB_NORMAL_MODE_MASK_SFT (0x1 << 20) 801 #define DL3_NORMAL_MODE_SFT 19 802 #define DL3_NORMAL_MODE_MASK 0x1 803 #define DL3_NORMAL_MODE_MASK_SFT (0x1 << 19) 804 #define DL2_NORMAL_MODE_SFT 18 805 #define DL2_NORMAL_MODE_MASK 0x1 806 #define DL2_NORMAL_MODE_MASK_SFT (0x1 << 18) 807 #define DL1_DATA2_NORMAL_MODE_SFT 17 808 #define DL1_DATA2_NORMAL_MODE_MASK 0x1 809 #define DL1_DATA2_NORMAL_MODE_MASK_SFT (0x1 << 17) 810 #define DL1_NORMAL_MODE_SFT 16 811 #define DL1_NORMAL_MODE_MASK 0x1 812 #define DL1_NORMAL_MODE_MASK_SFT (0x1 << 16) 813 #define HDMI_HD_ALIGN_SFT 10 814 #define HDMI_HD_ALIGN_MASK 0x1 815 #define HDMI_HD_ALIGN_MASK_SFT (0x1 << 10) 816 #define MOD_DAI_HD_ALIGN_SFT 9 817 #define MOD_DAI_HD_ALIGN_MASK 0x1 818 #define MOD_DAI_HD_ALIGN_MASK_SFT (0x1 << 9) 819 #define DAI_ALIGN_SFT 8 820 #define DAI_ALIGN_MASK 0x1 821 #define DAI_ALIGN_MASK_SFT (0x1 << 8) 822 #define VUL2_HD_ALIGN_SFT 7 823 #define VUL2_HD_ALIGN_MASK 0x1 824 #define VUL2_HD_ALIGN_MASK_SFT (0x1 << 7) 825 #define VUL_DATA2_HD_ALIGN_SFT 6 826 #define VUL_DATA2_HD_ALIGN_MASK 0x1 827 #define VUL_DATA2_HD_ALIGN_MASK_SFT (0x1 << 6) 828 #define VUL_HD_ALIGN_SFT 5 829 #define VUL_HD_ALIGN_MASK 0x1 830 #define VUL_HD_ALIGN_MASK_SFT (0x1 << 5) 831 #define AWB_HD_ALIGN_SFT 4 832 #define AWB_HD_ALIGN_MASK 0x1 833 #define AWB_HD_ALIGN_MASK_SFT (0x1 << 4) 834 #define DL3_HD_ALIGN_SFT 3 835 #define DL3_HD_ALIGN_MASK 0x1 836 #define DL3_HD_ALIGN_MASK_SFT (0x1 << 3) 837 #define DL2_HD_ALIGN_SFT 2 838 #define DL2_HD_ALIGN_MASK 0x1 839 #define DL2_HD_ALIGN_MASK_SFT (0x1 << 2) 840 #define DL1_DATA2_HD_ALIGN_SFT 1 841 #define DL1_DATA2_HD_ALIGN_MASK 0x1 842 #define DL1_DATA2_HD_ALIGN_MASK_SFT (0x1 << 1) 843 #define DL1_HD_ALIGN_SFT 0 844 #define DL1_HD_ALIGN_MASK 0x1 845 #define DL1_HD_ALIGN_MASK_SFT (0x1 << 0) 846 #endif 847