1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/slab.h> 15 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 19 #include <linux/dma-mapping.h> 20 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/initval.h> 26 #include <sound/dmaengine_pcm.h> 27 28 #include "jz4740-i2s.h" 29 30 #define JZ_REG_AIC_CONF 0x00 31 #define JZ_REG_AIC_CTRL 0x04 32 #define JZ_REG_AIC_I2S_FMT 0x10 33 #define JZ_REG_AIC_FIFO_STATUS 0x14 34 #define JZ_REG_AIC_I2S_STATUS 0x1c 35 #define JZ_REG_AIC_CLK_DIV 0x30 36 #define JZ_REG_AIC_FIFO 0x34 37 38 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) 39 #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) 40 #define JZ_AIC_CONF_I2S BIT(4) 41 #define JZ_AIC_CONF_RESET BIT(3) 42 #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) 43 #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) 44 #define JZ_AIC_CONF_ENABLE BIT(0) 45 46 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) 47 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) 48 #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) 49 #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) 50 #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) 51 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) 52 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) 53 #define JZ_AIC_CTRL_TFLUSH BIT(8) 54 #define JZ_AIC_CTRL_RFLUSH BIT(7) 55 #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) 56 #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) 57 #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) 58 #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) 59 #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) 60 #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) 61 #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) 62 63 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) 64 #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) 65 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) 66 #define JZ_AIC_I2S_FMT_MSB BIT(0) 67 68 #define JZ_AIC_I2S_STATUS_BUSY BIT(2) 69 70 struct i2s_soc_info { 71 struct snd_soc_dai_driver *dai; 72 73 struct reg_field field_rx_fifo_thresh; 74 struct reg_field field_tx_fifo_thresh; 75 struct reg_field field_i2sdiv_capture; 76 struct reg_field field_i2sdiv_playback; 77 78 bool shared_fifo_flush; 79 }; 80 81 struct jz4740_i2s { 82 struct regmap *regmap; 83 84 struct regmap_field *field_rx_fifo_thresh; 85 struct regmap_field *field_tx_fifo_thresh; 86 struct regmap_field *field_i2sdiv_capture; 87 struct regmap_field *field_i2sdiv_playback; 88 89 struct clk *clk_aic; 90 struct clk *clk_i2s; 91 92 struct snd_dmaengine_dai_dma_data playback_dma_data; 93 struct snd_dmaengine_dai_dma_data capture_dma_data; 94 95 const struct i2s_soc_info *soc_info; 96 }; 97 98 static int jz4740_i2s_startup(struct snd_pcm_substream *substream, 99 struct snd_soc_dai *dai) 100 { 101 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 102 int ret; 103 104 /* 105 * When we can flush FIFOs independently, only flush the FIFO 106 * that is starting up. We can do this when the DAI is active 107 * because it does not disturb other active substreams. 108 */ 109 if (!i2s->soc_info->shared_fifo_flush) { 110 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 111 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); 112 else 113 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_RFLUSH); 114 } 115 116 if (snd_soc_dai_active(dai)) 117 return 0; 118 119 /* 120 * When there is a shared flush bit for both FIFOs, the TFLUSH 121 * bit flushes both FIFOs. Flushing while the DAI is active would 122 * cause FIFO underruns in other active substreams so we have to 123 * guard this behind the snd_soc_dai_active() check. 124 */ 125 if (i2s->soc_info->shared_fifo_flush) 126 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); 127 128 ret = clk_prepare_enable(i2s->clk_i2s); 129 if (ret) 130 return ret; 131 132 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); 133 return 0; 134 } 135 136 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, 137 struct snd_soc_dai *dai) 138 { 139 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 140 141 if (snd_soc_dai_active(dai)) 142 return; 143 144 regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); 145 146 clk_disable_unprepare(i2s->clk_i2s); 147 } 148 149 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 150 struct snd_soc_dai *dai) 151 { 152 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 153 uint32_t mask; 154 155 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 156 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA; 157 else 158 mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA; 159 160 switch (cmd) { 161 case SNDRV_PCM_TRIGGER_START: 162 case SNDRV_PCM_TRIGGER_RESUME: 163 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 164 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask); 165 break; 166 case SNDRV_PCM_TRIGGER_STOP: 167 case SNDRV_PCM_TRIGGER_SUSPEND: 168 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 169 regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask); 170 break; 171 default: 172 return -EINVAL; 173 } 174 175 return 0; 176 } 177 178 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 179 { 180 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 181 const unsigned int conf_mask = JZ_AIC_CONF_BIT_CLK_MASTER | 182 JZ_AIC_CONF_SYNC_CLK_MASTER; 183 unsigned int conf = 0, format = 0; 184 185 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 186 case SND_SOC_DAIFMT_BP_FP: 187 conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER; 188 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK; 189 break; 190 case SND_SOC_DAIFMT_BC_FP: 191 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER; 192 break; 193 case SND_SOC_DAIFMT_BP_FC: 194 conf |= JZ_AIC_CONF_BIT_CLK_MASTER; 195 break; 196 case SND_SOC_DAIFMT_BC_FC: 197 break; 198 default: 199 return -EINVAL; 200 } 201 202 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 203 case SND_SOC_DAIFMT_MSB: 204 format |= JZ_AIC_I2S_FMT_MSB; 205 break; 206 case SND_SOC_DAIFMT_I2S: 207 break; 208 default: 209 return -EINVAL; 210 } 211 212 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 213 case SND_SOC_DAIFMT_NB_NF: 214 break; 215 default: 216 return -EINVAL; 217 } 218 219 regmap_update_bits(i2s->regmap, JZ_REG_AIC_CONF, conf_mask, conf); 220 regmap_write(i2s->regmap, JZ_REG_AIC_I2S_FMT, format); 221 222 return 0; 223 } 224 225 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, 226 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 227 { 228 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 229 struct regmap_field *div_field; 230 unsigned int sample_size; 231 uint32_t ctrl; 232 int div; 233 234 regmap_read(i2s->regmap, JZ_REG_AIC_CTRL, &ctrl); 235 236 div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params)); 237 238 switch (params_format(params)) { 239 case SNDRV_PCM_FORMAT_S8: 240 sample_size = 0; 241 break; 242 case SNDRV_PCM_FORMAT_S16: 243 sample_size = 1; 244 break; 245 default: 246 return -EINVAL; 247 } 248 249 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 250 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE; 251 ctrl |= FIELD_PREP(JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE, sample_size); 252 253 if (params_channels(params) == 1) 254 ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO; 255 else 256 ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO; 257 258 div_field = i2s->field_i2sdiv_playback; 259 } else { 260 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE; 261 ctrl |= FIELD_PREP(JZ_AIC_CTRL_INPUT_SAMPLE_SIZE, sample_size); 262 263 div_field = i2s->field_i2sdiv_capture; 264 } 265 266 regmap_write(i2s->regmap, JZ_REG_AIC_CTRL, ctrl); 267 regmap_field_write(div_field, div - 1); 268 269 return 0; 270 } 271 272 static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, 273 unsigned int freq, int dir) 274 { 275 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 276 struct clk *parent; 277 int ret = 0; 278 279 switch (clk_id) { 280 case JZ4740_I2S_CLKSRC_EXT: 281 parent = clk_get(NULL, "ext"); 282 if (IS_ERR(parent)) 283 return PTR_ERR(parent); 284 clk_set_parent(i2s->clk_i2s, parent); 285 break; 286 case JZ4740_I2S_CLKSRC_PLL: 287 parent = clk_get(NULL, "pll half"); 288 if (IS_ERR(parent)) 289 return PTR_ERR(parent); 290 clk_set_parent(i2s->clk_i2s, parent); 291 ret = clk_set_rate(i2s->clk_i2s, freq); 292 break; 293 default: 294 return -EINVAL; 295 } 296 clk_put(parent); 297 298 return ret; 299 } 300 301 static int jz4740_i2s_suspend(struct snd_soc_component *component) 302 { 303 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); 304 305 if (snd_soc_component_active(component)) { 306 regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); 307 clk_disable_unprepare(i2s->clk_i2s); 308 } 309 310 clk_disable_unprepare(i2s->clk_aic); 311 312 return 0; 313 } 314 315 static int jz4740_i2s_resume(struct snd_soc_component *component) 316 { 317 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); 318 int ret; 319 320 ret = clk_prepare_enable(i2s->clk_aic); 321 if (ret) 322 return ret; 323 324 if (snd_soc_component_active(component)) { 325 ret = clk_prepare_enable(i2s->clk_i2s); 326 if (ret) { 327 clk_disable_unprepare(i2s->clk_aic); 328 return ret; 329 } 330 331 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); 332 } 333 334 return 0; 335 } 336 337 static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) 338 { 339 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 340 int ret; 341 342 ret = clk_prepare_enable(i2s->clk_aic); 343 if (ret) 344 return ret; 345 346 snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, 347 &i2s->capture_dma_data); 348 349 regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); 350 351 regmap_write(i2s->regmap, JZ_REG_AIC_CONF, 352 JZ_AIC_CONF_OVERFLOW_PLAY_LAST | 353 JZ_AIC_CONF_I2S | JZ_AIC_CONF_INTERNAL_CODEC); 354 355 regmap_field_write(i2s->field_rx_fifo_thresh, 7); 356 regmap_field_write(i2s->field_tx_fifo_thresh, 8); 357 358 return 0; 359 } 360 361 static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai) 362 { 363 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 364 365 clk_disable_unprepare(i2s->clk_aic); 366 return 0; 367 } 368 369 static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = { 370 .startup = jz4740_i2s_startup, 371 .shutdown = jz4740_i2s_shutdown, 372 .trigger = jz4740_i2s_trigger, 373 .hw_params = jz4740_i2s_hw_params, 374 .set_fmt = jz4740_i2s_set_fmt, 375 .set_sysclk = jz4740_i2s_set_sysclk, 376 }; 377 378 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 379 SNDRV_PCM_FMTBIT_S16_LE) 380 381 static struct snd_soc_dai_driver jz4740_i2s_dai = { 382 .probe = jz4740_i2s_dai_probe, 383 .remove = jz4740_i2s_dai_remove, 384 .playback = { 385 .channels_min = 1, 386 .channels_max = 2, 387 .rates = SNDRV_PCM_RATE_8000_48000, 388 .formats = JZ4740_I2S_FMTS, 389 }, 390 .capture = { 391 .channels_min = 2, 392 .channels_max = 2, 393 .rates = SNDRV_PCM_RATE_8000_48000, 394 .formats = JZ4740_I2S_FMTS, 395 }, 396 .symmetric_rate = 1, 397 .ops = &jz4740_i2s_dai_ops, 398 }; 399 400 static const struct i2s_soc_info jz4740_i2s_soc_info = { 401 .dai = &jz4740_i2s_dai, 402 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 12, 15), 403 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), 404 .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 405 .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 406 .shared_fifo_flush = true, 407 }; 408 409 static const struct i2s_soc_info jz4760_i2s_soc_info = { 410 .dai = &jz4740_i2s_dai, 411 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), 412 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), 413 .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 414 .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 415 }; 416 417 static struct snd_soc_dai_driver jz4770_i2s_dai = { 418 .probe = jz4740_i2s_dai_probe, 419 .remove = jz4740_i2s_dai_remove, 420 .playback = { 421 .channels_min = 1, 422 .channels_max = 2, 423 .rates = SNDRV_PCM_RATE_8000_48000, 424 .formats = JZ4740_I2S_FMTS, 425 }, 426 .capture = { 427 .channels_min = 2, 428 .channels_max = 2, 429 .rates = SNDRV_PCM_RATE_8000_48000, 430 .formats = JZ4740_I2S_FMTS, 431 }, 432 .ops = &jz4740_i2s_dai_ops, 433 }; 434 435 static const struct i2s_soc_info jz4770_i2s_soc_info = { 436 .dai = &jz4770_i2s_dai, 437 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), 438 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), 439 .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), 440 .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 441 }; 442 443 static const struct i2s_soc_info jz4780_i2s_soc_info = { 444 .dai = &jz4770_i2s_dai, 445 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), 446 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), 447 .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), 448 .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 449 }; 450 451 static const struct snd_soc_component_driver jz4740_i2s_component = { 452 .name = "jz4740-i2s", 453 .suspend = jz4740_i2s_suspend, 454 .resume = jz4740_i2s_resume, 455 .legacy_dai_naming = 1, 456 }; 457 458 static const struct of_device_id jz4740_of_matches[] = { 459 { .compatible = "ingenic,jz4740-i2s", .data = &jz4740_i2s_soc_info }, 460 { .compatible = "ingenic,jz4760-i2s", .data = &jz4760_i2s_soc_info }, 461 { .compatible = "ingenic,jz4770-i2s", .data = &jz4770_i2s_soc_info }, 462 { .compatible = "ingenic,jz4780-i2s", .data = &jz4780_i2s_soc_info }, 463 { /* sentinel */ } 464 }; 465 MODULE_DEVICE_TABLE(of, jz4740_of_matches); 466 467 static int jz4740_i2s_init_regmap_fields(struct device *dev, 468 struct jz4740_i2s *i2s) 469 { 470 i2s->field_rx_fifo_thresh = 471 devm_regmap_field_alloc(dev, i2s->regmap, 472 i2s->soc_info->field_rx_fifo_thresh); 473 if (IS_ERR(i2s->field_rx_fifo_thresh)) 474 return PTR_ERR(i2s->field_rx_fifo_thresh); 475 476 i2s->field_tx_fifo_thresh = 477 devm_regmap_field_alloc(dev, i2s->regmap, 478 i2s->soc_info->field_tx_fifo_thresh); 479 if (IS_ERR(i2s->field_tx_fifo_thresh)) 480 return PTR_ERR(i2s->field_tx_fifo_thresh); 481 482 i2s->field_i2sdiv_capture = 483 devm_regmap_field_alloc(dev, i2s->regmap, 484 i2s->soc_info->field_i2sdiv_capture); 485 if (IS_ERR(i2s->field_i2sdiv_capture)) 486 return PTR_ERR(i2s->field_i2sdiv_capture); 487 488 i2s->field_i2sdiv_playback = 489 devm_regmap_field_alloc(dev, i2s->regmap, 490 i2s->soc_info->field_i2sdiv_playback); 491 if (IS_ERR(i2s->field_i2sdiv_playback)) 492 return PTR_ERR(i2s->field_i2sdiv_playback); 493 494 return 0; 495 } 496 497 static const struct regmap_config jz4740_i2s_regmap_config = { 498 .reg_bits = 32, 499 .reg_stride = 4, 500 .val_bits = 32, 501 .max_register = JZ_REG_AIC_FIFO, 502 }; 503 504 static int jz4740_i2s_dev_probe(struct platform_device *pdev) 505 { 506 struct device *dev = &pdev->dev; 507 struct jz4740_i2s *i2s; 508 struct resource *mem; 509 void __iomem *regs; 510 int ret; 511 512 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL); 513 if (!i2s) 514 return -ENOMEM; 515 516 i2s->soc_info = device_get_match_data(dev); 517 518 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 519 if (IS_ERR(regs)) 520 return PTR_ERR(regs); 521 522 i2s->playback_dma_data.maxburst = 16; 523 i2s->playback_dma_data.addr = mem->start + JZ_REG_AIC_FIFO; 524 525 i2s->capture_dma_data.maxburst = 16; 526 i2s->capture_dma_data.addr = mem->start + JZ_REG_AIC_FIFO; 527 528 i2s->clk_aic = devm_clk_get(dev, "aic"); 529 if (IS_ERR(i2s->clk_aic)) 530 return PTR_ERR(i2s->clk_aic); 531 532 i2s->clk_i2s = devm_clk_get(dev, "i2s"); 533 if (IS_ERR(i2s->clk_i2s)) 534 return PTR_ERR(i2s->clk_i2s); 535 536 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 537 &jz4740_i2s_regmap_config); 538 if (IS_ERR(i2s->regmap)) 539 return PTR_ERR(i2s->regmap); 540 541 ret = jz4740_i2s_init_regmap_fields(dev, i2s); 542 if (ret) 543 return ret; 544 545 platform_set_drvdata(pdev, i2s); 546 547 ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component, 548 i2s->soc_info->dai, 1); 549 if (ret) 550 return ret; 551 552 return devm_snd_dmaengine_pcm_register(dev, NULL, 553 SND_DMAENGINE_PCM_FLAG_COMPAT); 554 } 555 556 static struct platform_driver jz4740_i2s_driver = { 557 .probe = jz4740_i2s_dev_probe, 558 .driver = { 559 .name = "jz4740-i2s", 560 .of_match_table = jz4740_of_matches, 561 }, 562 }; 563 564 module_platform_driver(jz4740_i2s_driver); 565 566 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>"); 567 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver"); 568 MODULE_LICENSE("GPL"); 569 MODULE_ALIAS("platform:jz4740-i2s"); 570