1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 19 #include <sound/core.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/initval.h> 24 #include <sound/dmaengine_pcm.h> 25 26 #include "jz4740-i2s.h" 27 28 #define JZ_REG_AIC_CONF 0x00 29 #define JZ_REG_AIC_CTRL 0x04 30 #define JZ_REG_AIC_I2S_FMT 0x10 31 #define JZ_REG_AIC_FIFO_STATUS 0x14 32 #define JZ_REG_AIC_I2S_STATUS 0x1c 33 #define JZ_REG_AIC_CLK_DIV 0x30 34 #define JZ_REG_AIC_FIFO 0x34 35 36 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) 37 #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) 38 #define JZ_AIC_CONF_I2S BIT(4) 39 #define JZ_AIC_CONF_RESET BIT(3) 40 #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) 41 #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) 42 #define JZ_AIC_CONF_ENABLE BIT(0) 43 44 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) 45 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) 46 #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) 47 #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) 48 #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) 49 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) 50 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) 51 #define JZ_AIC_CTRL_TFLUSH BIT(8) 52 #define JZ_AIC_CTRL_RFLUSH BIT(7) 53 #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) 54 #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) 55 #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) 56 #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) 57 #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) 58 #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) 59 #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) 60 61 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) 62 #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) 63 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) 64 #define JZ_AIC_I2S_FMT_MSB BIT(0) 65 66 #define JZ_AIC_I2S_STATUS_BUSY BIT(2) 67 68 struct i2s_soc_info { 69 struct snd_soc_dai_driver *dai; 70 71 struct reg_field field_rx_fifo_thresh; 72 struct reg_field field_tx_fifo_thresh; 73 struct reg_field field_i2sdiv_capture; 74 struct reg_field field_i2sdiv_playback; 75 76 bool shared_fifo_flush; 77 }; 78 79 struct jz4740_i2s { 80 struct regmap *regmap; 81 82 struct regmap_field *field_rx_fifo_thresh; 83 struct regmap_field *field_tx_fifo_thresh; 84 struct regmap_field *field_i2sdiv_capture; 85 struct regmap_field *field_i2sdiv_playback; 86 87 struct clk *clk_aic; 88 struct clk *clk_i2s; 89 90 struct snd_dmaengine_dai_dma_data playback_dma_data; 91 struct snd_dmaengine_dai_dma_data capture_dma_data; 92 93 const struct i2s_soc_info *soc_info; 94 }; 95 96 static int jz4740_i2s_startup(struct snd_pcm_substream *substream, 97 struct snd_soc_dai *dai) 98 { 99 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 100 int ret; 101 102 /* 103 * When we can flush FIFOs independently, only flush the FIFO 104 * that is starting up. We can do this when the DAI is active 105 * because it does not disturb other active substreams. 106 */ 107 if (!i2s->soc_info->shared_fifo_flush) { 108 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 109 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); 110 else 111 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_RFLUSH); 112 } 113 114 if (snd_soc_dai_active(dai)) 115 return 0; 116 117 /* 118 * When there is a shared flush bit for both FIFOs, the TFLUSH 119 * bit flushes both FIFOs. Flushing while the DAI is active would 120 * cause FIFO underruns in other active substreams so we have to 121 * guard this behind the snd_soc_dai_active() check. 122 */ 123 if (i2s->soc_info->shared_fifo_flush) 124 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); 125 126 ret = clk_prepare_enable(i2s->clk_i2s); 127 if (ret) 128 return ret; 129 130 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); 131 return 0; 132 } 133 134 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, 135 struct snd_soc_dai *dai) 136 { 137 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 138 139 if (snd_soc_dai_active(dai)) 140 return; 141 142 regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); 143 144 clk_disable_unprepare(i2s->clk_i2s); 145 } 146 147 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 148 struct snd_soc_dai *dai) 149 { 150 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 151 uint32_t mask; 152 153 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 154 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA; 155 else 156 mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA; 157 158 switch (cmd) { 159 case SNDRV_PCM_TRIGGER_START: 160 case SNDRV_PCM_TRIGGER_RESUME: 161 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 162 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask); 163 break; 164 case SNDRV_PCM_TRIGGER_STOP: 165 case SNDRV_PCM_TRIGGER_SUSPEND: 166 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 167 regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask); 168 break; 169 default: 170 return -EINVAL; 171 } 172 173 return 0; 174 } 175 176 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 177 { 178 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 179 const unsigned int conf_mask = JZ_AIC_CONF_BIT_CLK_MASTER | 180 JZ_AIC_CONF_SYNC_CLK_MASTER; 181 unsigned int conf = 0, format = 0; 182 183 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 184 case SND_SOC_DAIFMT_BP_FP: 185 conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER; 186 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK; 187 break; 188 case SND_SOC_DAIFMT_BC_FP: 189 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER; 190 break; 191 case SND_SOC_DAIFMT_BP_FC: 192 conf |= JZ_AIC_CONF_BIT_CLK_MASTER; 193 break; 194 case SND_SOC_DAIFMT_BC_FC: 195 break; 196 default: 197 return -EINVAL; 198 } 199 200 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 201 case SND_SOC_DAIFMT_MSB: 202 format |= JZ_AIC_I2S_FMT_MSB; 203 break; 204 case SND_SOC_DAIFMT_I2S: 205 break; 206 default: 207 return -EINVAL; 208 } 209 210 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 211 case SND_SOC_DAIFMT_NB_NF: 212 break; 213 default: 214 return -EINVAL; 215 } 216 217 regmap_update_bits(i2s->regmap, JZ_REG_AIC_CONF, conf_mask, conf); 218 regmap_write(i2s->regmap, JZ_REG_AIC_I2S_FMT, format); 219 220 return 0; 221 } 222 223 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, 224 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 225 { 226 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 227 struct regmap_field *div_field; 228 unsigned int sample_size; 229 uint32_t ctrl; 230 int div; 231 232 regmap_read(i2s->regmap, JZ_REG_AIC_CTRL, &ctrl); 233 234 div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params)); 235 236 switch (params_format(params)) { 237 case SNDRV_PCM_FORMAT_S8: 238 sample_size = 0; 239 break; 240 case SNDRV_PCM_FORMAT_S16_LE: 241 sample_size = 1; 242 break; 243 case SNDRV_PCM_FORMAT_S20_LE: 244 sample_size = 3; 245 break; 246 case SNDRV_PCM_FORMAT_S24_LE: 247 sample_size = 4; 248 break; 249 default: 250 return -EINVAL; 251 } 252 253 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 254 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE; 255 ctrl |= FIELD_PREP(JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE, sample_size); 256 257 if (params_channels(params) == 1) 258 ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO; 259 else 260 ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO; 261 262 div_field = i2s->field_i2sdiv_playback; 263 } else { 264 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE; 265 ctrl |= FIELD_PREP(JZ_AIC_CTRL_INPUT_SAMPLE_SIZE, sample_size); 266 267 div_field = i2s->field_i2sdiv_capture; 268 } 269 270 regmap_write(i2s->regmap, JZ_REG_AIC_CTRL, ctrl); 271 regmap_field_write(div_field, div - 1); 272 273 return 0; 274 } 275 276 static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, 277 unsigned int freq, int dir) 278 { 279 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 280 struct clk *parent; 281 int ret = 0; 282 283 switch (clk_id) { 284 case JZ4740_I2S_CLKSRC_EXT: 285 parent = clk_get(NULL, "ext"); 286 if (IS_ERR(parent)) 287 return PTR_ERR(parent); 288 clk_set_parent(i2s->clk_i2s, parent); 289 break; 290 case JZ4740_I2S_CLKSRC_PLL: 291 parent = clk_get(NULL, "pll half"); 292 if (IS_ERR(parent)) 293 return PTR_ERR(parent); 294 clk_set_parent(i2s->clk_i2s, parent); 295 ret = clk_set_rate(i2s->clk_i2s, freq); 296 break; 297 default: 298 return -EINVAL; 299 } 300 clk_put(parent); 301 302 return ret; 303 } 304 305 static int jz4740_i2s_suspend(struct snd_soc_component *component) 306 { 307 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); 308 309 if (snd_soc_component_active(component)) { 310 regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); 311 clk_disable_unprepare(i2s->clk_i2s); 312 } 313 314 clk_disable_unprepare(i2s->clk_aic); 315 316 return 0; 317 } 318 319 static int jz4740_i2s_resume(struct snd_soc_component *component) 320 { 321 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); 322 int ret; 323 324 ret = clk_prepare_enable(i2s->clk_aic); 325 if (ret) 326 return ret; 327 328 if (snd_soc_component_active(component)) { 329 ret = clk_prepare_enable(i2s->clk_i2s); 330 if (ret) { 331 clk_disable_unprepare(i2s->clk_aic); 332 return ret; 333 } 334 335 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); 336 } 337 338 return 0; 339 } 340 341 static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) 342 { 343 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 344 int ret; 345 346 ret = clk_prepare_enable(i2s->clk_aic); 347 if (ret) 348 return ret; 349 350 snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, 351 &i2s->capture_dma_data); 352 353 regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); 354 355 regmap_write(i2s->regmap, JZ_REG_AIC_CONF, 356 JZ_AIC_CONF_OVERFLOW_PLAY_LAST | 357 JZ_AIC_CONF_I2S | JZ_AIC_CONF_INTERNAL_CODEC); 358 359 regmap_field_write(i2s->field_rx_fifo_thresh, 7); 360 regmap_field_write(i2s->field_tx_fifo_thresh, 8); 361 362 return 0; 363 } 364 365 static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai) 366 { 367 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 368 369 clk_disable_unprepare(i2s->clk_aic); 370 return 0; 371 } 372 373 static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = { 374 .startup = jz4740_i2s_startup, 375 .shutdown = jz4740_i2s_shutdown, 376 .trigger = jz4740_i2s_trigger, 377 .hw_params = jz4740_i2s_hw_params, 378 .set_fmt = jz4740_i2s_set_fmt, 379 .set_sysclk = jz4740_i2s_set_sysclk, 380 }; 381 382 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 383 SNDRV_PCM_FMTBIT_S16_LE | \ 384 SNDRV_PCM_FMTBIT_S20_LE | \ 385 SNDRV_PCM_FMTBIT_S24_LE) 386 387 static struct snd_soc_dai_driver jz4740_i2s_dai = { 388 .probe = jz4740_i2s_dai_probe, 389 .remove = jz4740_i2s_dai_remove, 390 .playback = { 391 .channels_min = 1, 392 .channels_max = 2, 393 .rates = SNDRV_PCM_RATE_CONTINUOUS, 394 .formats = JZ4740_I2S_FMTS, 395 }, 396 .capture = { 397 .channels_min = 2, 398 .channels_max = 2, 399 .rates = SNDRV_PCM_RATE_CONTINUOUS, 400 .formats = JZ4740_I2S_FMTS, 401 }, 402 .symmetric_rate = 1, 403 .ops = &jz4740_i2s_dai_ops, 404 }; 405 406 static const struct i2s_soc_info jz4740_i2s_soc_info = { 407 .dai = &jz4740_i2s_dai, 408 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 12, 15), 409 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), 410 .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 411 .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 412 .shared_fifo_flush = true, 413 }; 414 415 static const struct i2s_soc_info jz4760_i2s_soc_info = { 416 .dai = &jz4740_i2s_dai, 417 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), 418 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), 419 .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 420 .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 421 }; 422 423 static struct snd_soc_dai_driver jz4770_i2s_dai = { 424 .probe = jz4740_i2s_dai_probe, 425 .remove = jz4740_i2s_dai_remove, 426 .playback = { 427 .channels_min = 1, 428 .channels_max = 2, 429 .rates = SNDRV_PCM_RATE_CONTINUOUS, 430 .formats = JZ4740_I2S_FMTS, 431 }, 432 .capture = { 433 .channels_min = 2, 434 .channels_max = 2, 435 .rates = SNDRV_PCM_RATE_CONTINUOUS, 436 .formats = JZ4740_I2S_FMTS, 437 }, 438 .ops = &jz4740_i2s_dai_ops, 439 }; 440 441 static const struct i2s_soc_info jz4770_i2s_soc_info = { 442 .dai = &jz4770_i2s_dai, 443 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), 444 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), 445 .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), 446 .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 447 }; 448 449 static const struct i2s_soc_info jz4780_i2s_soc_info = { 450 .dai = &jz4770_i2s_dai, 451 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), 452 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), 453 .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), 454 .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 455 }; 456 457 static const struct snd_soc_component_driver jz4740_i2s_component = { 458 .name = "jz4740-i2s", 459 .suspend = jz4740_i2s_suspend, 460 .resume = jz4740_i2s_resume, 461 .legacy_dai_naming = 1, 462 }; 463 464 static const struct of_device_id jz4740_of_matches[] = { 465 { .compatible = "ingenic,jz4740-i2s", .data = &jz4740_i2s_soc_info }, 466 { .compatible = "ingenic,jz4760-i2s", .data = &jz4760_i2s_soc_info }, 467 { .compatible = "ingenic,jz4770-i2s", .data = &jz4770_i2s_soc_info }, 468 { .compatible = "ingenic,jz4780-i2s", .data = &jz4780_i2s_soc_info }, 469 { /* sentinel */ } 470 }; 471 MODULE_DEVICE_TABLE(of, jz4740_of_matches); 472 473 static int jz4740_i2s_init_regmap_fields(struct device *dev, 474 struct jz4740_i2s *i2s) 475 { 476 i2s->field_rx_fifo_thresh = 477 devm_regmap_field_alloc(dev, i2s->regmap, 478 i2s->soc_info->field_rx_fifo_thresh); 479 if (IS_ERR(i2s->field_rx_fifo_thresh)) 480 return PTR_ERR(i2s->field_rx_fifo_thresh); 481 482 i2s->field_tx_fifo_thresh = 483 devm_regmap_field_alloc(dev, i2s->regmap, 484 i2s->soc_info->field_tx_fifo_thresh); 485 if (IS_ERR(i2s->field_tx_fifo_thresh)) 486 return PTR_ERR(i2s->field_tx_fifo_thresh); 487 488 i2s->field_i2sdiv_capture = 489 devm_regmap_field_alloc(dev, i2s->regmap, 490 i2s->soc_info->field_i2sdiv_capture); 491 if (IS_ERR(i2s->field_i2sdiv_capture)) 492 return PTR_ERR(i2s->field_i2sdiv_capture); 493 494 i2s->field_i2sdiv_playback = 495 devm_regmap_field_alloc(dev, i2s->regmap, 496 i2s->soc_info->field_i2sdiv_playback); 497 if (IS_ERR(i2s->field_i2sdiv_playback)) 498 return PTR_ERR(i2s->field_i2sdiv_playback); 499 500 return 0; 501 } 502 503 static const struct regmap_config jz4740_i2s_regmap_config = { 504 .reg_bits = 32, 505 .reg_stride = 4, 506 .val_bits = 32, 507 .max_register = JZ_REG_AIC_FIFO, 508 }; 509 510 static int jz4740_i2s_dev_probe(struct platform_device *pdev) 511 { 512 struct device *dev = &pdev->dev; 513 struct jz4740_i2s *i2s; 514 struct resource *mem; 515 void __iomem *regs; 516 int ret; 517 518 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL); 519 if (!i2s) 520 return -ENOMEM; 521 522 i2s->soc_info = device_get_match_data(dev); 523 524 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 525 if (IS_ERR(regs)) 526 return PTR_ERR(regs); 527 528 i2s->playback_dma_data.maxburst = 16; 529 i2s->playback_dma_data.addr = mem->start + JZ_REG_AIC_FIFO; 530 531 i2s->capture_dma_data.maxburst = 16; 532 i2s->capture_dma_data.addr = mem->start + JZ_REG_AIC_FIFO; 533 534 i2s->clk_aic = devm_clk_get(dev, "aic"); 535 if (IS_ERR(i2s->clk_aic)) 536 return PTR_ERR(i2s->clk_aic); 537 538 i2s->clk_i2s = devm_clk_get(dev, "i2s"); 539 if (IS_ERR(i2s->clk_i2s)) 540 return PTR_ERR(i2s->clk_i2s); 541 542 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 543 &jz4740_i2s_regmap_config); 544 if (IS_ERR(i2s->regmap)) 545 return PTR_ERR(i2s->regmap); 546 547 ret = jz4740_i2s_init_regmap_fields(dev, i2s); 548 if (ret) 549 return ret; 550 551 platform_set_drvdata(pdev, i2s); 552 553 ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component, 554 i2s->soc_info->dai, 1); 555 if (ret) 556 return ret; 557 558 return devm_snd_dmaengine_pcm_register(dev, NULL, 559 SND_DMAENGINE_PCM_FLAG_COMPAT); 560 } 561 562 static struct platform_driver jz4740_i2s_driver = { 563 .probe = jz4740_i2s_dev_probe, 564 .driver = { 565 .name = "jz4740-i2s", 566 .of_match_table = jz4740_of_matches, 567 }, 568 }; 569 570 module_platform_driver(jz4740_i2s_driver); 571 572 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>"); 573 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver"); 574 MODULE_LICENSE("GPL"); 575 MODULE_ALIAS("platform:jz4740-i2s"); 576