1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 19 #include <sound/core.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/initval.h> 24 #include <sound/dmaengine_pcm.h> 25 26 #include "jz4740-i2s.h" 27 28 #define JZ_REG_AIC_CONF 0x00 29 #define JZ_REG_AIC_CTRL 0x04 30 #define JZ_REG_AIC_I2S_FMT 0x10 31 #define JZ_REG_AIC_FIFO_STATUS 0x14 32 #define JZ_REG_AIC_I2S_STATUS 0x1c 33 #define JZ_REG_AIC_CLK_DIV 0x30 34 #define JZ_REG_AIC_FIFO 0x34 35 36 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) 37 #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) 38 #define JZ_AIC_CONF_I2S BIT(4) 39 #define JZ_AIC_CONF_RESET BIT(3) 40 #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) 41 #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) 42 #define JZ_AIC_CONF_ENABLE BIT(0) 43 44 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) 45 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) 46 #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) 47 #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) 48 #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) 49 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) 50 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) 51 #define JZ_AIC_CTRL_TFLUSH BIT(8) 52 #define JZ_AIC_CTRL_RFLUSH BIT(7) 53 #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) 54 #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) 55 #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) 56 #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) 57 #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) 58 #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) 59 #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) 60 61 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) 62 #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) 63 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) 64 #define JZ_AIC_I2S_FMT_MSB BIT(0) 65 66 #define JZ_AIC_I2S_STATUS_BUSY BIT(2) 67 68 struct i2s_soc_info { 69 struct snd_soc_dai_driver *dai; 70 71 struct reg_field field_rx_fifo_thresh; 72 struct reg_field field_tx_fifo_thresh; 73 struct reg_field field_i2sdiv_capture; 74 struct reg_field field_i2sdiv_playback; 75 76 bool shared_fifo_flush; 77 }; 78 79 struct jz4740_i2s { 80 struct regmap *regmap; 81 82 struct regmap_field *field_rx_fifo_thresh; 83 struct regmap_field *field_tx_fifo_thresh; 84 struct regmap_field *field_i2sdiv_capture; 85 struct regmap_field *field_i2sdiv_playback; 86 87 struct clk *clk_aic; 88 struct clk *clk_i2s; 89 90 struct snd_dmaengine_dai_dma_data playback_dma_data; 91 struct snd_dmaengine_dai_dma_data capture_dma_data; 92 93 const struct i2s_soc_info *soc_info; 94 }; 95 96 static int jz4740_i2s_startup(struct snd_pcm_substream *substream, 97 struct snd_soc_dai *dai) 98 { 99 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 100 int ret; 101 102 /* 103 * When we can flush FIFOs independently, only flush the FIFO 104 * that is starting up. We can do this when the DAI is active 105 * because it does not disturb other active substreams. 106 */ 107 if (!i2s->soc_info->shared_fifo_flush) { 108 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 109 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); 110 else 111 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_RFLUSH); 112 } 113 114 if (snd_soc_dai_active(dai)) 115 return 0; 116 117 /* 118 * When there is a shared flush bit for both FIFOs, the TFLUSH 119 * bit flushes both FIFOs. Flushing while the DAI is active would 120 * cause FIFO underruns in other active substreams so we have to 121 * guard this behind the snd_soc_dai_active() check. 122 */ 123 if (i2s->soc_info->shared_fifo_flush) 124 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); 125 126 ret = clk_prepare_enable(i2s->clk_i2s); 127 if (ret) 128 return ret; 129 130 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); 131 return 0; 132 } 133 134 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, 135 struct snd_soc_dai *dai) 136 { 137 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 138 139 if (snd_soc_dai_active(dai)) 140 return; 141 142 regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); 143 144 clk_disable_unprepare(i2s->clk_i2s); 145 } 146 147 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 148 struct snd_soc_dai *dai) 149 { 150 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 151 uint32_t mask; 152 153 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 154 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA; 155 else 156 mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA; 157 158 switch (cmd) { 159 case SNDRV_PCM_TRIGGER_START: 160 case SNDRV_PCM_TRIGGER_RESUME: 161 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 162 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask); 163 break; 164 case SNDRV_PCM_TRIGGER_STOP: 165 case SNDRV_PCM_TRIGGER_SUSPEND: 166 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 167 regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask); 168 break; 169 default: 170 return -EINVAL; 171 } 172 173 return 0; 174 } 175 176 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 177 { 178 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 179 const unsigned int conf_mask = JZ_AIC_CONF_BIT_CLK_MASTER | 180 JZ_AIC_CONF_SYNC_CLK_MASTER; 181 unsigned int conf = 0, format = 0; 182 183 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 184 case SND_SOC_DAIFMT_BP_FP: 185 conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER; 186 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK; 187 break; 188 case SND_SOC_DAIFMT_BC_FP: 189 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER; 190 break; 191 case SND_SOC_DAIFMT_BP_FC: 192 conf |= JZ_AIC_CONF_BIT_CLK_MASTER; 193 break; 194 case SND_SOC_DAIFMT_BC_FC: 195 break; 196 default: 197 return -EINVAL; 198 } 199 200 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 201 case SND_SOC_DAIFMT_MSB: 202 format |= JZ_AIC_I2S_FMT_MSB; 203 break; 204 case SND_SOC_DAIFMT_I2S: 205 break; 206 default: 207 return -EINVAL; 208 } 209 210 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 211 case SND_SOC_DAIFMT_NB_NF: 212 break; 213 default: 214 return -EINVAL; 215 } 216 217 regmap_update_bits(i2s->regmap, JZ_REG_AIC_CONF, conf_mask, conf); 218 regmap_write(i2s->regmap, JZ_REG_AIC_I2S_FMT, format); 219 220 return 0; 221 } 222 223 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, 224 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 225 { 226 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 227 struct regmap_field *div_field; 228 unsigned int sample_size; 229 uint32_t ctrl; 230 int div; 231 232 regmap_read(i2s->regmap, JZ_REG_AIC_CTRL, &ctrl); 233 234 div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params)); 235 236 switch (params_format(params)) { 237 case SNDRV_PCM_FORMAT_S8: 238 sample_size = 0; 239 break; 240 case SNDRV_PCM_FORMAT_S16_LE: 241 sample_size = 1; 242 break; 243 case SNDRV_PCM_FORMAT_S20_LE: 244 sample_size = 3; 245 break; 246 case SNDRV_PCM_FORMAT_S24_LE: 247 sample_size = 4; 248 break; 249 default: 250 return -EINVAL; 251 } 252 253 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 254 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE; 255 ctrl |= FIELD_PREP(JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE, sample_size); 256 257 if (params_channels(params) == 1) 258 ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO; 259 else 260 ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO; 261 262 div_field = i2s->field_i2sdiv_playback; 263 } else { 264 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE; 265 ctrl |= FIELD_PREP(JZ_AIC_CTRL_INPUT_SAMPLE_SIZE, sample_size); 266 267 div_field = i2s->field_i2sdiv_capture; 268 } 269 270 regmap_write(i2s->regmap, JZ_REG_AIC_CTRL, ctrl); 271 regmap_field_write(div_field, div - 1); 272 273 return 0; 274 } 275 276 static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, 277 unsigned int freq, int dir) 278 { 279 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 280 struct clk *parent; 281 int ret = 0; 282 283 switch (clk_id) { 284 case JZ4740_I2S_CLKSRC_EXT: 285 parent = clk_get(NULL, "ext"); 286 if (IS_ERR(parent)) 287 return PTR_ERR(parent); 288 clk_set_parent(i2s->clk_i2s, parent); 289 break; 290 case JZ4740_I2S_CLKSRC_PLL: 291 parent = clk_get(NULL, "pll half"); 292 if (IS_ERR(parent)) 293 return PTR_ERR(parent); 294 clk_set_parent(i2s->clk_i2s, parent); 295 ret = clk_set_rate(i2s->clk_i2s, freq); 296 break; 297 default: 298 return -EINVAL; 299 } 300 clk_put(parent); 301 302 return ret; 303 } 304 305 static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) 306 { 307 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 308 309 snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, 310 &i2s->capture_dma_data); 311 312 return 0; 313 } 314 315 static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = { 316 .startup = jz4740_i2s_startup, 317 .shutdown = jz4740_i2s_shutdown, 318 .trigger = jz4740_i2s_trigger, 319 .hw_params = jz4740_i2s_hw_params, 320 .set_fmt = jz4740_i2s_set_fmt, 321 .set_sysclk = jz4740_i2s_set_sysclk, 322 }; 323 324 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 325 SNDRV_PCM_FMTBIT_S16_LE | \ 326 SNDRV_PCM_FMTBIT_S20_LE | \ 327 SNDRV_PCM_FMTBIT_S24_LE) 328 329 static struct snd_soc_dai_driver jz4740_i2s_dai = { 330 .probe = jz4740_i2s_dai_probe, 331 .playback = { 332 .channels_min = 1, 333 .channels_max = 2, 334 .rates = SNDRV_PCM_RATE_CONTINUOUS, 335 .formats = JZ4740_I2S_FMTS, 336 }, 337 .capture = { 338 .channels_min = 2, 339 .channels_max = 2, 340 .rates = SNDRV_PCM_RATE_CONTINUOUS, 341 .formats = JZ4740_I2S_FMTS, 342 }, 343 .symmetric_rate = 1, 344 .ops = &jz4740_i2s_dai_ops, 345 }; 346 347 static const struct i2s_soc_info jz4740_i2s_soc_info = { 348 .dai = &jz4740_i2s_dai, 349 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 12, 15), 350 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), 351 .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 352 .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 353 .shared_fifo_flush = true, 354 }; 355 356 static const struct i2s_soc_info jz4760_i2s_soc_info = { 357 .dai = &jz4740_i2s_dai, 358 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), 359 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), 360 .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 361 .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 362 }; 363 364 static struct snd_soc_dai_driver jz4770_i2s_dai = { 365 .probe = jz4740_i2s_dai_probe, 366 .playback = { 367 .channels_min = 1, 368 .channels_max = 2, 369 .rates = SNDRV_PCM_RATE_CONTINUOUS, 370 .formats = JZ4740_I2S_FMTS, 371 }, 372 .capture = { 373 .channels_min = 2, 374 .channels_max = 2, 375 .rates = SNDRV_PCM_RATE_CONTINUOUS, 376 .formats = JZ4740_I2S_FMTS, 377 }, 378 .ops = &jz4740_i2s_dai_ops, 379 }; 380 381 static const struct i2s_soc_info jz4770_i2s_soc_info = { 382 .dai = &jz4770_i2s_dai, 383 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), 384 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), 385 .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), 386 .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 387 }; 388 389 static const struct i2s_soc_info jz4780_i2s_soc_info = { 390 .dai = &jz4770_i2s_dai, 391 .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), 392 .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), 393 .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), 394 .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), 395 }; 396 397 static int jz4740_i2s_suspend(struct snd_soc_component *component) 398 { 399 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); 400 401 if (snd_soc_component_active(component)) { 402 regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); 403 clk_disable_unprepare(i2s->clk_i2s); 404 } 405 406 clk_disable_unprepare(i2s->clk_aic); 407 408 return 0; 409 } 410 411 static int jz4740_i2s_resume(struct snd_soc_component *component) 412 { 413 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); 414 int ret; 415 416 ret = clk_prepare_enable(i2s->clk_aic); 417 if (ret) 418 return ret; 419 420 if (snd_soc_component_active(component)) { 421 ret = clk_prepare_enable(i2s->clk_i2s); 422 if (ret) { 423 clk_disable_unprepare(i2s->clk_aic); 424 return ret; 425 } 426 427 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); 428 } 429 430 return 0; 431 } 432 433 static int jz4740_i2s_probe(struct snd_soc_component *component) 434 { 435 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); 436 int ret; 437 438 ret = clk_prepare_enable(i2s->clk_aic); 439 if (ret) 440 return ret; 441 442 regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); 443 444 regmap_write(i2s->regmap, JZ_REG_AIC_CONF, 445 JZ_AIC_CONF_OVERFLOW_PLAY_LAST | 446 JZ_AIC_CONF_I2S | JZ_AIC_CONF_INTERNAL_CODEC); 447 448 regmap_field_write(i2s->field_rx_fifo_thresh, 7); 449 regmap_field_write(i2s->field_tx_fifo_thresh, 8); 450 451 return 0; 452 } 453 454 static void jz4740_i2s_remove(struct snd_soc_component *component) 455 { 456 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); 457 458 clk_disable_unprepare(i2s->clk_aic); 459 } 460 461 static const struct snd_soc_component_driver jz4740_i2s_component = { 462 .name = "jz4740-i2s", 463 .probe = jz4740_i2s_probe, 464 .remove = jz4740_i2s_remove, 465 .suspend = jz4740_i2s_suspend, 466 .resume = jz4740_i2s_resume, 467 .legacy_dai_naming = 1, 468 }; 469 470 static const struct of_device_id jz4740_of_matches[] = { 471 { .compatible = "ingenic,jz4740-i2s", .data = &jz4740_i2s_soc_info }, 472 { .compatible = "ingenic,jz4760-i2s", .data = &jz4760_i2s_soc_info }, 473 { .compatible = "ingenic,jz4770-i2s", .data = &jz4770_i2s_soc_info }, 474 { .compatible = "ingenic,jz4780-i2s", .data = &jz4780_i2s_soc_info }, 475 { /* sentinel */ } 476 }; 477 MODULE_DEVICE_TABLE(of, jz4740_of_matches); 478 479 static int jz4740_i2s_init_regmap_fields(struct device *dev, 480 struct jz4740_i2s *i2s) 481 { 482 i2s->field_rx_fifo_thresh = 483 devm_regmap_field_alloc(dev, i2s->regmap, 484 i2s->soc_info->field_rx_fifo_thresh); 485 if (IS_ERR(i2s->field_rx_fifo_thresh)) 486 return PTR_ERR(i2s->field_rx_fifo_thresh); 487 488 i2s->field_tx_fifo_thresh = 489 devm_regmap_field_alloc(dev, i2s->regmap, 490 i2s->soc_info->field_tx_fifo_thresh); 491 if (IS_ERR(i2s->field_tx_fifo_thresh)) 492 return PTR_ERR(i2s->field_tx_fifo_thresh); 493 494 i2s->field_i2sdiv_capture = 495 devm_regmap_field_alloc(dev, i2s->regmap, 496 i2s->soc_info->field_i2sdiv_capture); 497 if (IS_ERR(i2s->field_i2sdiv_capture)) 498 return PTR_ERR(i2s->field_i2sdiv_capture); 499 500 i2s->field_i2sdiv_playback = 501 devm_regmap_field_alloc(dev, i2s->regmap, 502 i2s->soc_info->field_i2sdiv_playback); 503 if (IS_ERR(i2s->field_i2sdiv_playback)) 504 return PTR_ERR(i2s->field_i2sdiv_playback); 505 506 return 0; 507 } 508 509 static const struct regmap_config jz4740_i2s_regmap_config = { 510 .reg_bits = 32, 511 .reg_stride = 4, 512 .val_bits = 32, 513 .max_register = JZ_REG_AIC_FIFO, 514 }; 515 516 static int jz4740_i2s_dev_probe(struct platform_device *pdev) 517 { 518 struct device *dev = &pdev->dev; 519 struct jz4740_i2s *i2s; 520 struct resource *mem; 521 void __iomem *regs; 522 int ret; 523 524 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL); 525 if (!i2s) 526 return -ENOMEM; 527 528 i2s->soc_info = device_get_match_data(dev); 529 530 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 531 if (IS_ERR(regs)) 532 return PTR_ERR(regs); 533 534 i2s->playback_dma_data.maxburst = 16; 535 i2s->playback_dma_data.addr = mem->start + JZ_REG_AIC_FIFO; 536 537 i2s->capture_dma_data.maxburst = 16; 538 i2s->capture_dma_data.addr = mem->start + JZ_REG_AIC_FIFO; 539 540 i2s->clk_aic = devm_clk_get(dev, "aic"); 541 if (IS_ERR(i2s->clk_aic)) 542 return PTR_ERR(i2s->clk_aic); 543 544 i2s->clk_i2s = devm_clk_get(dev, "i2s"); 545 if (IS_ERR(i2s->clk_i2s)) 546 return PTR_ERR(i2s->clk_i2s); 547 548 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 549 &jz4740_i2s_regmap_config); 550 if (IS_ERR(i2s->regmap)) 551 return PTR_ERR(i2s->regmap); 552 553 ret = jz4740_i2s_init_regmap_fields(dev, i2s); 554 if (ret) 555 return ret; 556 557 platform_set_drvdata(pdev, i2s); 558 559 ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component, 560 i2s->soc_info->dai, 1); 561 if (ret) 562 return ret; 563 564 return devm_snd_dmaengine_pcm_register(dev, NULL, 565 SND_DMAENGINE_PCM_FLAG_COMPAT); 566 } 567 568 static struct platform_driver jz4740_i2s_driver = { 569 .probe = jz4740_i2s_dev_probe, 570 .driver = { 571 .name = "jz4740-i2s", 572 .of_match_table = jz4740_of_matches, 573 }, 574 }; 575 576 module_platform_driver(jz4740_i2s_driver); 577 578 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>"); 579 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver"); 580 MODULE_LICENSE("GPL"); 581 MODULE_ALIAS("platform:jz4740-i2s"); 582