xref: /openbmc/linux/sound/soc/intel/keembay/kmb_platform.h (revision d0034a7a4ac7fae708146ac0059b9c47a1543f0d)
1c5477e96SSia Jee Heng /* SPDX-License-Identifier: GPL-2.0-only */
2c5477e96SSia Jee Heng /*
3c5477e96SSia Jee Heng  *  Intel KeemBay Platform driver
4c5477e96SSia Jee Heng  *
5c5477e96SSia Jee Heng  *  Copyright (C) 2020 Intel Corporation.
6c5477e96SSia Jee Heng  *
7c5477e96SSia Jee Heng  */
8c5477e96SSia Jee Heng 
9c5477e96SSia Jee Heng #ifndef KMB_PLATFORM_H_
109a7794bdSNathan Chancellor #define KMB_PLATFORM_H_
11c5477e96SSia Jee Heng 
12c5477e96SSia Jee Heng #include <linux/bits.h>
13c5477e96SSia Jee Heng #include <linux/bitfield.h>
14c5477e96SSia Jee Heng #include <linux/types.h>
1511b943c0SMichael Sit Wei Hong #include <sound/dmaengine_pcm.h>
16c5477e96SSia Jee Heng 
17c5477e96SSia Jee Heng /* Register values with reference to KMB databook v1.1 */
18c5477e96SSia Jee Heng /* common register for all channel */
19c5477e96SSia Jee Heng #define IER		0x000
20c5477e96SSia Jee Heng #define IRER		0x004
21c5477e96SSia Jee Heng #define ITER		0x008
22c5477e96SSia Jee Heng #define CER		0x00C
23c5477e96SSia Jee Heng #define CCR		0x010
24c5477e96SSia Jee Heng #define RXFFR		0x014
25c5477e96SSia Jee Heng #define TXFFR		0x018
26c5477e96SSia Jee Heng 
27c5477e96SSia Jee Heng /* Interrupt status register fields */
28c5477e96SSia Jee Heng #define ISR_TXFO	BIT(5)
29c5477e96SSia Jee Heng #define ISR_TXFE	BIT(4)
30c5477e96SSia Jee Heng #define ISR_RXFO	BIT(1)
31c5477e96SSia Jee Heng #define ISR_RXDA	BIT(0)
32c5477e96SSia Jee Heng 
33c5477e96SSia Jee Heng /* I2S Tx Rx Registers for all channels */
34c5477e96SSia Jee Heng #define LRBR_LTHR(x)	(0x40 * (x) + 0x020)
35c5477e96SSia Jee Heng #define RRBR_RTHR(x)	(0x40 * (x) + 0x024)
36c5477e96SSia Jee Heng #define RER(x)		(0x40 * (x) + 0x028)
37c5477e96SSia Jee Heng #define TER(x)		(0x40 * (x) + 0x02C)
38c5477e96SSia Jee Heng #define RCR(x)		(0x40 * (x) + 0x030)
39c5477e96SSia Jee Heng #define TCR(x)		(0x40 * (x) + 0x034)
40c5477e96SSia Jee Heng #define ISR(x)		(0x40 * (x) + 0x038)
41c5477e96SSia Jee Heng #define IMR(x)		(0x40 * (x) + 0x03C)
42c5477e96SSia Jee Heng #define ROR(x)		(0x40 * (x) + 0x040)
43c5477e96SSia Jee Heng #define TOR(x)		(0x40 * (x) + 0x044)
44c5477e96SSia Jee Heng #define RFCR(x)		(0x40 * (x) + 0x048)
45c5477e96SSia Jee Heng #define TFCR(x)		(0x40 * (x) + 0x04C)
46c5477e96SSia Jee Heng #define RFF(x)		(0x40 * (x) + 0x050)
47c5477e96SSia Jee Heng #define TFF(x)		(0x40 * (x) + 0x054)
48c5477e96SSia Jee Heng 
49c5477e96SSia Jee Heng /* I2S COMP Registers */
50c5477e96SSia Jee Heng #define I2S_COMP_PARAM_2	0x01F0
51c5477e96SSia Jee Heng #define I2S_COMP_PARAM_1	0x01F4
52c5477e96SSia Jee Heng #define I2S_COMP_VERSION	0x01F8
53c5477e96SSia Jee Heng #define I2S_COMP_TYPE		0x01FC
54c5477e96SSia Jee Heng 
55c5477e96SSia Jee Heng /* PSS_GEN_CTRL_I2S_GEN_CFG_0 Registers */
56c5477e96SSia Jee Heng #define I2S_GEN_CFG_0		0x000
57c5477e96SSia Jee Heng #define PSS_CPR_RST_EN		0x010
58c5477e96SSia Jee Heng #define PSS_CPR_RST_SET		0x014
59c5477e96SSia Jee Heng #define PSS_CPR_CLK_CLR		0x000
60c5477e96SSia Jee Heng #define PSS_CPR_AUX_RST_EN	0x070
61c5477e96SSia Jee Heng 
62a6e9717aSPierre-Louis Bossart #define CLOCK_PROVIDER_MODE	BIT(13)
63c5477e96SSia Jee Heng 
64c5477e96SSia Jee Heng /* Interrupt Flag */
65c5477e96SSia Jee Heng #define TX_INT_FLAG		GENMASK(5, 4)
66c5477e96SSia Jee Heng #define RX_INT_FLAG		GENMASK(1, 0)
67c5477e96SSia Jee Heng /*
68c5477e96SSia Jee Heng  * Component parameter register fields - define the I2S block's
69c5477e96SSia Jee Heng  * configuration.
70c5477e96SSia Jee Heng  */
71c5477e96SSia Jee Heng #define	COMP1_TX_WORDSIZE_3(r)		FIELD_GET(GENMASK(27, 25), (r))
72c5477e96SSia Jee Heng #define	COMP1_TX_WORDSIZE_2(r)		FIELD_GET(GENMASK(24, 22), (r))
73c5477e96SSia Jee Heng #define	COMP1_TX_WORDSIZE_1(r)		FIELD_GET(GENMASK(21, 19), (r))
74c5477e96SSia Jee Heng #define	COMP1_TX_WORDSIZE_0(r)		FIELD_GET(GENMASK(18, 16), (r))
75c5477e96SSia Jee Heng #define	COMP1_RX_ENABLED(r)		FIELD_GET(BIT(6), (r))
76c5477e96SSia Jee Heng #define	COMP1_TX_ENABLED(r)		FIELD_GET(BIT(5), (r))
77c5477e96SSia Jee Heng #define	COMP1_MODE_EN(r)		FIELD_GET(BIT(4), (r))
78c5477e96SSia Jee Heng #define	COMP1_APB_DATA_WIDTH(r)		FIELD_GET(GENMASK(1, 0), (r))
79c5477e96SSia Jee Heng #define	COMP2_RX_WORDSIZE_3(r)		FIELD_GET(GENMASK(12, 10), (r))
80c5477e96SSia Jee Heng #define	COMP2_RX_WORDSIZE_2(r)		FIELD_GET(GENMASK(9, 7), (r))
81c5477e96SSia Jee Heng #define	COMP2_RX_WORDSIZE_1(r)		FIELD_GET(GENMASK(5, 3), (r))
82c5477e96SSia Jee Heng #define	COMP2_RX_WORDSIZE_0(r)		FIELD_GET(GENMASK(2, 0), (r))
83c5477e96SSia Jee Heng 
84c5477e96SSia Jee Heng /* Add 1 to the below registers to indicate the actual size */
85c5477e96SSia Jee Heng #define	COMP1_TX_CHANNELS(r)	(FIELD_GET(GENMASK(10, 9), (r)) + 1)
86c5477e96SSia Jee Heng #define	COMP1_RX_CHANNELS(r)	(FIELD_GET(GENMASK(8, 7), (r)) + 1)
87c5477e96SSia Jee Heng #define	COMP1_FIFO_DEPTH(r)	(FIELD_GET(GENMASK(3, 2), (r)) + 1)
88c5477e96SSia Jee Heng 
89c5477e96SSia Jee Heng /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
90c5477e96SSia Jee Heng #define	COMP_MAX_WORDSIZE	8	/* 3 bits register width */
91c5477e96SSia Jee Heng 
92c5477e96SSia Jee Heng #define MAX_CHANNEL_NUM		8
93c5477e96SSia Jee Heng #define MIN_CHANNEL_NUM		2
94d1338984SMichael Sit Wei Hong #define MAX_ISR			4
95c5477e96SSia Jee Heng 
96c5477e96SSia Jee Heng #define TWO_CHANNEL_SUPPORT	2	/* up to 2.0 */
97c5477e96SSia Jee Heng #define FOUR_CHANNEL_SUPPORT	4	/* up to 3.1 */
98c5477e96SSia Jee Heng #define SIX_CHANNEL_SUPPORT	6	/* up to 5.1 */
99c5477e96SSia Jee Heng #define EIGHT_CHANNEL_SUPPORT	8	/* up to 7.1 */
100c5477e96SSia Jee Heng 
101c5477e96SSia Jee Heng #define DWC_I2S_PLAY	BIT(0)
102c5477e96SSia Jee Heng #define DWC_I2S_RECORD	BIT(1)
103a6e9717aSPierre-Louis Bossart #define DW_I2S_CONSUMER	BIT(2)
104a6e9717aSPierre-Louis Bossart #define DW_I2S_PROVIDER	BIT(3)
105c5477e96SSia Jee Heng 
106c5477e96SSia Jee Heng #define I2S_RXDMA	0x01C0
10711b943c0SMichael Sit Wei Hong #define I2S_RRXDMA	0x01C4
108c5477e96SSia Jee Heng #define I2S_TXDMA	0x01C8
10911b943c0SMichael Sit Wei Hong #define I2S_RTXDMA	0x01CC
11011b943c0SMichael Sit Wei Hong #define I2S_DMACR	0x0200
11111b943c0SMichael Sit Wei Hong #define I2S_DMAEN_RXBLOCK	(1 << 16)
11211b943c0SMichael Sit Wei Hong #define I2S_DMAEN_TXBLOCK	(1 << 17)
113c5477e96SSia Jee Heng 
114c5477e96SSia Jee Heng /*
115c5477e96SSia Jee Heng  * struct i2s_clk_config_data - represent i2s clk configuration data
116c5477e96SSia Jee Heng  * @chan_nr: number of channel
117c5477e96SSia Jee Heng  * @data_width: number of bits per sample (8/16/24/32 bit)
118c5477e96SSia Jee Heng  * @sample_rate: sampling frequency (8Khz, 16Khz, 48Khz)
119c5477e96SSia Jee Heng  */
120c5477e96SSia Jee Heng struct i2s_clk_config_data {
121c5477e96SSia Jee Heng 	int chan_nr;
122c5477e96SSia Jee Heng 	u32 data_width;
123c5477e96SSia Jee Heng 	u32 sample_rate;
124c5477e96SSia Jee Heng };
125c5477e96SSia Jee Heng 
126c5477e96SSia Jee Heng struct kmb_i2s_info {
127c5477e96SSia Jee Heng 	void __iomem *i2s_base;
128c5477e96SSia Jee Heng 	void __iomem *pss_base;
129c5477e96SSia Jee Heng 	struct clk *clk_i2s;
130c5477e96SSia Jee Heng 	struct clk *clk_apb;
131c5477e96SSia Jee Heng 	int active;
132c5477e96SSia Jee Heng 	unsigned int capability;
133c5477e96SSia Jee Heng 	unsigned int i2s_reg_comp1;
134c5477e96SSia Jee Heng 	unsigned int i2s_reg_comp2;
135c5477e96SSia Jee Heng 	struct device *dev;
136c5477e96SSia Jee Heng 	u32 ccr;
137c5477e96SSia Jee Heng 	u32 xfer_resolution;
138c5477e96SSia Jee Heng 	u32 fifo_th;
139a6e9717aSPierre-Louis Bossart 	bool clock_provider;
14011b943c0SMichael Sit Wei Hong 	/* data related to DMA transfers b/w i2s and DMAC */
14111b943c0SMichael Sit Wei Hong 	struct snd_dmaengine_dai_dma_data play_dma_data;
14211b943c0SMichael Sit Wei Hong 	struct snd_dmaengine_dai_dma_data capture_dma_data;
143c5477e96SSia Jee Heng 
144c5477e96SSia Jee Heng 	struct i2s_clk_config_data config;
145c5477e96SSia Jee Heng 	int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
146c5477e96SSia Jee Heng 
147c5477e96SSia Jee Heng 	/* data related to PIO transfers */
148c5477e96SSia Jee Heng 	bool use_pio;
149c5477e96SSia Jee Heng 	struct snd_pcm_substream *tx_substream;
150c5477e96SSia Jee Heng 	struct snd_pcm_substream *rx_substream;
151c5477e96SSia Jee Heng 	unsigned int tx_ptr;
152c5477e96SSia Jee Heng 	unsigned int rx_ptr;
153*1c5f6e07SSia Jee Heng 	bool iec958_fmt;
154c5477e96SSia Jee Heng };
155c5477e96SSia Jee Heng 
156c5477e96SSia Jee Heng #endif /* KMB_PLATFORM_H_ */
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