1*4fac9b31SCezary Rojewski /* SPDX-License-Identifier: GPL-2.0-only */ 2*4fac9b31SCezary Rojewski /* 3*4fac9b31SCezary Rojewski * Copyright(c) 2020 Intel Corporation. All rights reserved. 4*4fac9b31SCezary Rojewski * 5*4fac9b31SCezary Rojewski * Author: Cezary Rojewski <cezary.rojewski@intel.com> 6*4fac9b31SCezary Rojewski */ 7*4fac9b31SCezary Rojewski 8*4fac9b31SCezary Rojewski #ifndef __SND_SOC_INTEL_CATPT_REGS_H 9*4fac9b31SCezary Rojewski #define __SND_SOC_INTEL_CATPT_REGS_H 10*4fac9b31SCezary Rojewski 11*4fac9b31SCezary Rojewski #include <linux/bitops.h> 12*4fac9b31SCezary Rojewski #include <linux/iopoll.h> 13*4fac9b31SCezary Rojewski #include <uapi/linux/pci_regs.h> 14*4fac9b31SCezary Rojewski 15*4fac9b31SCezary Rojewski #define CATPT_SHIM_REGS_SIZE 4096 16*4fac9b31SCezary Rojewski #define CATPT_DMA_REGS_SIZE 1024 17*4fac9b31SCezary Rojewski #define CATPT_DMA_COUNT 2 18*4fac9b31SCezary Rojewski #define CATPT_SSP_REGS_SIZE 512 19*4fac9b31SCezary Rojewski 20*4fac9b31SCezary Rojewski /* DSP Shim registers */ 21*4fac9b31SCezary Rojewski 22*4fac9b31SCezary Rojewski #define CATPT_SHIM_CS1 0x00 23*4fac9b31SCezary Rojewski #define CATPT_SHIM_ISC 0x18 24*4fac9b31SCezary Rojewski #define CATPT_SHIM_ISD 0x20 25*4fac9b31SCezary Rojewski #define CATPT_SHIM_IMC 0x28 26*4fac9b31SCezary Rojewski #define CATPT_SHIM_IMD 0x30 27*4fac9b31SCezary Rojewski #define CATPT_SHIM_IPCC 0x38 28*4fac9b31SCezary Rojewski #define CATPT_SHIM_IPCD 0x40 29*4fac9b31SCezary Rojewski #define CATPT_SHIM_CLKCTL 0x78 30*4fac9b31SCezary Rojewski #define CATPT_SHIM_CS2 0x80 31*4fac9b31SCezary Rojewski #define CATPT_SHIM_LTRC 0xE0 32*4fac9b31SCezary Rojewski #define CATPT_SHIM_HMDC 0xE8 33*4fac9b31SCezary Rojewski 34*4fac9b31SCezary Rojewski #define CATPT_CS_LPCS BIT(31) 35*4fac9b31SCezary Rojewski #define CATPT_CS_SFCR(ssp) BIT(27 + (ssp)) 36*4fac9b31SCezary Rojewski #define CATPT_CS_S1IOCS BIT(23) 37*4fac9b31SCezary Rojewski #define CATPT_CS_S0IOCS BIT(21) 38*4fac9b31SCezary Rojewski #define CATPT_CS_PCE BIT(15) 39*4fac9b31SCezary Rojewski #define CATPT_CS_SDPM(ssp) BIT(11 + (ssp)) 40*4fac9b31SCezary Rojewski #define CATPT_CS_STALL BIT(10) 41*4fac9b31SCezary Rojewski #define CATPT_CS_DCS GENMASK(6, 4) 42*4fac9b31SCezary Rojewski /* b100 DSP core & audio fabric high clock */ 43*4fac9b31SCezary Rojewski #define CATPT_CS_DCS_HIGH (0x4 << 4) 44*4fac9b31SCezary Rojewski #define CATPT_CS_SBCS(ssp) BIT(2 + (ssp)) 45*4fac9b31SCezary Rojewski #define CATPT_CS_RST BIT(1) 46*4fac9b31SCezary Rojewski 47*4fac9b31SCezary Rojewski #define CATPT_ISC_IPCDB BIT(1) 48*4fac9b31SCezary Rojewski #define CATPT_ISC_IPCCD BIT(0) 49*4fac9b31SCezary Rojewski #define CATPT_ISD_DCPWM BIT(31) 50*4fac9b31SCezary Rojewski #define CATPT_ISD_IPCCB BIT(1) 51*4fac9b31SCezary Rojewski #define CATPT_ISD_IPCDD BIT(0) 52*4fac9b31SCezary Rojewski 53*4fac9b31SCezary Rojewski #define CATPT_IMC_IPCDB BIT(1) 54*4fac9b31SCezary Rojewski #define CATPT_IMC_IPCCD BIT(0) 55*4fac9b31SCezary Rojewski #define CATPT_IMD_IPCCB BIT(1) 56*4fac9b31SCezary Rojewski #define CATPT_IMD_IPCDD BIT(0) 57*4fac9b31SCezary Rojewski 58*4fac9b31SCezary Rojewski #define CATPT_IPCC_BUSY BIT(31) 59*4fac9b31SCezary Rojewski #define CATPT_IPCC_DONE BIT(30) 60*4fac9b31SCezary Rojewski #define CATPT_IPCD_BUSY BIT(31) 61*4fac9b31SCezary Rojewski #define CATPT_IPCD_DONE BIT(30) 62*4fac9b31SCezary Rojewski 63*4fac9b31SCezary Rojewski #define CATPT_CLKCTL_CFCIP BIT(31) 64*4fac9b31SCezary Rojewski #define CATPT_CLKCTL_SMOS GENMASK(25, 24) 65*4fac9b31SCezary Rojewski 66*4fac9b31SCezary Rojewski #define CATPT_HMDC_HDDA(e, ch) BIT(8 * (e) + (ch)) 67*4fac9b31SCezary Rojewski 68*4fac9b31SCezary Rojewski /* defaults to reset SHIM registers to after each power cycle */ 69*4fac9b31SCezary Rojewski #define CATPT_CS_DEFAULT 0x8480040E 70*4fac9b31SCezary Rojewski #define CATPT_ISC_DEFAULT 0x0 71*4fac9b31SCezary Rojewski #define CATPT_ISD_DEFAULT 0x0 72*4fac9b31SCezary Rojewski #define CATPT_IMC_DEFAULT 0x7FFF0003 73*4fac9b31SCezary Rojewski #define CATPT_IMD_DEFAULT 0x7FFF0003 74*4fac9b31SCezary Rojewski #define CATPT_IPCC_DEFAULT 0x0 75*4fac9b31SCezary Rojewski #define CATPT_IPCD_DEFAULT 0x0 76*4fac9b31SCezary Rojewski #define CATPT_CLKCTL_DEFAULT 0x7FF 77*4fac9b31SCezary Rojewski #define CATPT_CS2_DEFAULT 0x0 78*4fac9b31SCezary Rojewski #define CATPT_LTRC_DEFAULT 0x0 79*4fac9b31SCezary Rojewski #define CATPT_HMDC_DEFAULT 0x0 80*4fac9b31SCezary Rojewski 81*4fac9b31SCezary Rojewski /* PCI Configuration registers */ 82*4fac9b31SCezary Rojewski 83*4fac9b31SCezary Rojewski #define CATPT_PCI_PMCAPID 0x80 84*4fac9b31SCezary Rojewski #define CATPT_PCI_PMCS (CATPT_PCI_PMCAPID + PCI_PM_CTRL) 85*4fac9b31SCezary Rojewski #define CATPT_PCI_VDRTCTL0 0xA0 86*4fac9b31SCezary Rojewski #define CATPT_PCI_VDRTCTL2 0xA8 87*4fac9b31SCezary Rojewski 88*4fac9b31SCezary Rojewski #define CATPT_VDRTCTL2_DTCGE BIT(10) 89*4fac9b31SCezary Rojewski #define CATPT_VDRTCTL2_DCLCGE BIT(1) 90*4fac9b31SCezary Rojewski #define CATPT_VDRTCTL2_CGEALL 0xF7F 91*4fac9b31SCezary Rojewski 92*4fac9b31SCezary Rojewski /* LPT PCI Configuration bits */ 93*4fac9b31SCezary Rojewski 94*4fac9b31SCezary Rojewski #define LPT_VDRTCTL0_DSRAMPGE(b) BIT(16 + (b)) 95*4fac9b31SCezary Rojewski #define LPT_VDRTCTL0_DSRAMPGE_MASK GENMASK(31, 16) 96*4fac9b31SCezary Rojewski #define LPT_VDRTCTL0_ISRAMPGE(b) BIT(6 + (b)) 97*4fac9b31SCezary Rojewski #define LPT_VDRTCTL0_ISRAMPGE_MASK GENMASK(15, 6) 98*4fac9b31SCezary Rojewski #define LPT_VDRTCTL0_D3SRAMPGD BIT(2) 99*4fac9b31SCezary Rojewski #define LPT_VDRTCTL0_D3PGD BIT(1) 100*4fac9b31SCezary Rojewski #define LPT_VDRTCTL0_APLLSE BIT(0) 101*4fac9b31SCezary Rojewski 102*4fac9b31SCezary Rojewski /* WPT PCI Configuration bits */ 103*4fac9b31SCezary Rojewski 104*4fac9b31SCezary Rojewski #define WPT_VDRTCTL0_DSRAMPGE(b) BIT(12 + (b)) 105*4fac9b31SCezary Rojewski #define WPT_VDRTCTL0_DSRAMPGE_MASK GENMASK(31, 12) 106*4fac9b31SCezary Rojewski #define WPT_VDRTCTL0_ISRAMPGE(b) BIT(2 + (b)) 107*4fac9b31SCezary Rojewski #define WPT_VDRTCTL0_ISRAMPGE_MASK GENMASK(11, 2) 108*4fac9b31SCezary Rojewski #define WPT_VDRTCTL0_D3SRAMPGD BIT(1) 109*4fac9b31SCezary Rojewski #define WPT_VDRTCTL0_D3PGD BIT(0) 110*4fac9b31SCezary Rojewski 111*4fac9b31SCezary Rojewski #define WPT_VDRTCTL2_APLLSE BIT(31) 112*4fac9b31SCezary Rojewski 113*4fac9b31SCezary Rojewski /* defaults to reset SSP registers to after each power cycle */ 114*4fac9b31SCezary Rojewski #define CATPT_SSC0_DEFAULT 0x0 115*4fac9b31SCezary Rojewski #define CATPT_SSC1_DEFAULT 0x0 116*4fac9b31SCezary Rojewski #define CATPT_SSS_DEFAULT 0xF004 117*4fac9b31SCezary Rojewski #define CATPT_SSIT_DEFAULT 0x0 118*4fac9b31SCezary Rojewski #define CATPT_SSD_DEFAULT 0xC43893A3 119*4fac9b31SCezary Rojewski #define CATPT_SSTO_DEFAULT 0x0 120*4fac9b31SCezary Rojewski #define CATPT_SSPSP_DEFAULT 0x0 121*4fac9b31SCezary Rojewski #define CATPT_SSTSA_DEFAULT 0x0 122*4fac9b31SCezary Rojewski #define CATPT_SSRSA_DEFAULT 0x0 123*4fac9b31SCezary Rojewski #define CATPT_SSTSS_DEFAULT 0x0 124*4fac9b31SCezary Rojewski #define CATPT_SSCR2_DEFAULT 0x0 125*4fac9b31SCezary Rojewski #define CATPT_SSPSP2_DEFAULT 0x0 126*4fac9b31SCezary Rojewski 127*4fac9b31SCezary Rojewski /* Physically the same block, access address differs between host and dsp */ 128*4fac9b31SCezary Rojewski #define CATPT_DSP_DRAM_OFFSET 0x400000 129*4fac9b31SCezary Rojewski #define catpt_to_host_offset(offset) ((offset) & ~(CATPT_DSP_DRAM_OFFSET)) 130*4fac9b31SCezary Rojewski #define catpt_to_dsp_offset(offset) ((offset) | CATPT_DSP_DRAM_OFFSET) 131*4fac9b31SCezary Rojewski 132*4fac9b31SCezary Rojewski #define CATPT_MEMBLOCK_SIZE 0x8000 133*4fac9b31SCezary Rojewski #define catpt_num_dram(cdev) (hweight_long((cdev)->spec->dram_mask)) 134*4fac9b31SCezary Rojewski #define catpt_num_iram(cdev) (hweight_long((cdev)->spec->iram_mask)) 135*4fac9b31SCezary Rojewski #define catpt_dram_size(cdev) (catpt_num_dram(cdev) * CATPT_MEMBLOCK_SIZE) 136*4fac9b31SCezary Rojewski #define catpt_iram_size(cdev) (catpt_num_iram(cdev) * CATPT_MEMBLOCK_SIZE) 137*4fac9b31SCezary Rojewski 138*4fac9b31SCezary Rojewski /* registry I/O helpers */ 139*4fac9b31SCezary Rojewski 140*4fac9b31SCezary Rojewski #define catpt_shim_addr(cdev) \ 141*4fac9b31SCezary Rojewski ((cdev)->lpe_ba + (cdev)->spec->host_shim_offset) 142*4fac9b31SCezary Rojewski #define catpt_dma_addr(cdev, dma) \ 143*4fac9b31SCezary Rojewski ((cdev)->lpe_ba + (cdev)->spec->host_dma_offset[dma]) 144*4fac9b31SCezary Rojewski #define catpt_ssp_addr(cdev, ssp) \ 145*4fac9b31SCezary Rojewski ((cdev)->lpe_ba + (cdev)->spec->host_ssp_offset[ssp]) 146*4fac9b31SCezary Rojewski #define catpt_inbox_addr(cdev) \ 147*4fac9b31SCezary Rojewski ((cdev)->lpe_ba + (cdev)->ipc.config.inbox_offset) 148*4fac9b31SCezary Rojewski #define catpt_outbox_addr(cdev) \ 149*4fac9b31SCezary Rojewski ((cdev)->lpe_ba + (cdev)->ipc.config.outbox_offset) 150*4fac9b31SCezary Rojewski 151*4fac9b31SCezary Rojewski #define catpt_writel_ssp(cdev, ssp, reg, val) \ 152*4fac9b31SCezary Rojewski writel(val, catpt_ssp_addr(cdev, ssp) + (reg)) 153*4fac9b31SCezary Rojewski 154*4fac9b31SCezary Rojewski #define catpt_readl_shim(cdev, reg) \ 155*4fac9b31SCezary Rojewski readl(catpt_shim_addr(cdev) + CATPT_SHIM_##reg) 156*4fac9b31SCezary Rojewski #define catpt_writel_shim(cdev, reg, val) \ 157*4fac9b31SCezary Rojewski writel(val, catpt_shim_addr(cdev) + CATPT_SHIM_##reg) 158*4fac9b31SCezary Rojewski #define catpt_updatel_shim(cdev, reg, mask, val) \ 159*4fac9b31SCezary Rojewski catpt_writel_shim(cdev, reg, \ 160*4fac9b31SCezary Rojewski (catpt_readl_shim(cdev, reg) & ~(mask)) | (val)) 161*4fac9b31SCezary Rojewski 162*4fac9b31SCezary Rojewski #define catpt_readl_poll_shim(cdev, reg, val, cond, delay_us, timeout_us) \ 163*4fac9b31SCezary Rojewski readl_poll_timeout(catpt_shim_addr(cdev) + CATPT_SHIM_##reg, \ 164*4fac9b31SCezary Rojewski val, cond, delay_us, timeout_us) 165*4fac9b31SCezary Rojewski 166*4fac9b31SCezary Rojewski #define catpt_readl_pci(cdev, reg) \ 167*4fac9b31SCezary Rojewski readl(cdev->pci_ba + CATPT_PCI_##reg) 168*4fac9b31SCezary Rojewski #define catpt_writel_pci(cdev, reg, val) \ 169*4fac9b31SCezary Rojewski writel(val, cdev->pci_ba + CATPT_PCI_##reg) 170*4fac9b31SCezary Rojewski #define catpt_updatel_pci(cdev, reg, mask, val) \ 171*4fac9b31SCezary Rojewski catpt_writel_pci(cdev, reg, \ 172*4fac9b31SCezary Rojewski (catpt_readl_pci(cdev, reg) & ~(mask)) | (val)) 173*4fac9b31SCezary Rojewski 174*4fac9b31SCezary Rojewski #define catpt_readl_poll_pci(cdev, reg, val, cond, delay_us, timeout_us) \ 175*4fac9b31SCezary Rojewski readl_poll_timeout((cdev)->pci_ba + CATPT_PCI_##reg, \ 176*4fac9b31SCezary Rojewski val, cond, delay_us, timeout_us) 177*4fac9b31SCezary Rojewski 178*4fac9b31SCezary Rojewski #endif 179