1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/pm_qos.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 #include <linux/time.h> 18 #include <sound/core.h> 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 23 24 #include "fsl_sai.h" 25 #include "imx-pcm.h" 26 27 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 28 FSL_SAI_CSR_FEIE) 29 30 static const unsigned int fsl_sai_rates[] = { 31 8000, 11025, 12000, 16000, 22050, 32 24000, 32000, 44100, 48000, 64000, 33 88200, 96000, 176400, 192000 34 }; 35 36 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 37 .count = ARRAY_SIZE(fsl_sai_rates), 38 .list = fsl_sai_rates, 39 }; 40 41 /** 42 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 43 * 44 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 45 * or Receiver's for both streams. This function is used to check if clocks of 46 * the stream's are synced by the opposite stream. 47 * 48 * @sai: SAI context 49 * @dir: stream direction 50 */ 51 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 52 { 53 int adir = (dir == TX) ? RX : TX; 54 55 /* current dir in async mode while opposite dir in sync mode */ 56 return !sai->synchronous[dir] && sai->synchronous[adir]; 57 } 58 59 static irqreturn_t fsl_sai_isr(int irq, void *devid) 60 { 61 struct fsl_sai *sai = (struct fsl_sai *)devid; 62 unsigned int ofs = sai->soc_data->reg_offset; 63 struct device *dev = &sai->pdev->dev; 64 u32 flags, xcsr, mask; 65 irqreturn_t iret = IRQ_NONE; 66 67 /* 68 * Both IRQ status bits and IRQ mask bits are in the xCSR but 69 * different shifts. And we here create a mask only for those 70 * IRQs that we activated. 71 */ 72 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 73 74 /* Tx IRQ */ 75 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 76 flags = xcsr & mask; 77 78 if (flags) 79 iret = IRQ_HANDLED; 80 else 81 goto irq_rx; 82 83 if (flags & FSL_SAI_CSR_WSF) 84 dev_dbg(dev, "isr: Start of Tx word detected\n"); 85 86 if (flags & FSL_SAI_CSR_SEF) 87 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 88 89 if (flags & FSL_SAI_CSR_FEF) { 90 dev_dbg(dev, "isr: Transmit underrun detected\n"); 91 /* FIFO reset for safety */ 92 xcsr |= FSL_SAI_CSR_FR; 93 } 94 95 if (flags & FSL_SAI_CSR_FWF) 96 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 97 98 if (flags & FSL_SAI_CSR_FRF) 99 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 100 101 flags &= FSL_SAI_CSR_xF_W_MASK; 102 xcsr &= ~FSL_SAI_CSR_xF_MASK; 103 104 if (flags) 105 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 106 107 irq_rx: 108 /* Rx IRQ */ 109 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 110 flags = xcsr & mask; 111 112 if (flags) 113 iret = IRQ_HANDLED; 114 else 115 goto out; 116 117 if (flags & FSL_SAI_CSR_WSF) 118 dev_dbg(dev, "isr: Start of Rx word detected\n"); 119 120 if (flags & FSL_SAI_CSR_SEF) 121 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 122 123 if (flags & FSL_SAI_CSR_FEF) { 124 dev_dbg(dev, "isr: Receive overflow detected\n"); 125 /* FIFO reset for safety */ 126 xcsr |= FSL_SAI_CSR_FR; 127 } 128 129 if (flags & FSL_SAI_CSR_FWF) 130 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 131 132 if (flags & FSL_SAI_CSR_FRF) 133 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 134 135 flags &= FSL_SAI_CSR_xF_W_MASK; 136 xcsr &= ~FSL_SAI_CSR_xF_MASK; 137 138 if (flags) 139 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 140 141 out: 142 return iret; 143 } 144 145 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 146 u32 rx_mask, int slots, int slot_width) 147 { 148 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 149 150 sai->slots = slots; 151 sai->slot_width = slot_width; 152 153 return 0; 154 } 155 156 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 157 unsigned int ratio) 158 { 159 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 160 161 sai->bclk_ratio = ratio; 162 163 return 0; 164 } 165 166 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 167 int clk_id, unsigned int freq, bool tx) 168 { 169 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 170 unsigned int ofs = sai->soc_data->reg_offset; 171 u32 val_cr2 = 0; 172 173 switch (clk_id) { 174 case FSL_SAI_CLK_BUS: 175 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 176 break; 177 case FSL_SAI_CLK_MAST1: 178 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 179 break; 180 case FSL_SAI_CLK_MAST2: 181 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 182 break; 183 case FSL_SAI_CLK_MAST3: 184 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 185 break; 186 default: 187 return -EINVAL; 188 } 189 190 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 191 FSL_SAI_CR2_MSEL_MASK, val_cr2); 192 193 return 0; 194 } 195 196 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 197 int clk_id, unsigned int freq, int dir) 198 { 199 int ret; 200 201 if (dir == SND_SOC_CLOCK_IN) 202 return 0; 203 204 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); 205 if (ret) { 206 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 207 return ret; 208 } 209 210 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false); 211 if (ret) 212 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 213 214 return ret; 215 } 216 217 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 218 unsigned int fmt, bool tx) 219 { 220 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 221 unsigned int ofs = sai->soc_data->reg_offset; 222 u32 val_cr2 = 0, val_cr4 = 0; 223 224 if (!sai->is_lsb_first) 225 val_cr4 |= FSL_SAI_CR4_MF; 226 227 /* DAI mode */ 228 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 229 case SND_SOC_DAIFMT_I2S: 230 /* 231 * Frame low, 1clk before data, one word length for frame sync, 232 * frame sync starts one serial clock cycle earlier, 233 * that is, together with the last bit of the previous 234 * data word. 235 */ 236 val_cr2 |= FSL_SAI_CR2_BCP; 237 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 238 break; 239 case SND_SOC_DAIFMT_LEFT_J: 240 /* 241 * Frame high, one word length for frame sync, 242 * frame sync asserts with the first bit of the frame. 243 */ 244 val_cr2 |= FSL_SAI_CR2_BCP; 245 break; 246 case SND_SOC_DAIFMT_DSP_A: 247 /* 248 * Frame high, 1clk before data, one bit for frame sync, 249 * frame sync starts one serial clock cycle earlier, 250 * that is, together with the last bit of the previous 251 * data word. 252 */ 253 val_cr2 |= FSL_SAI_CR2_BCP; 254 val_cr4 |= FSL_SAI_CR4_FSE; 255 sai->is_dsp_mode = true; 256 break; 257 case SND_SOC_DAIFMT_DSP_B: 258 /* 259 * Frame high, one bit for frame sync, 260 * frame sync asserts with the first bit of the frame. 261 */ 262 val_cr2 |= FSL_SAI_CR2_BCP; 263 sai->is_dsp_mode = true; 264 break; 265 case SND_SOC_DAIFMT_RIGHT_J: 266 /* To be done */ 267 default: 268 return -EINVAL; 269 } 270 271 /* DAI clock inversion */ 272 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 273 case SND_SOC_DAIFMT_IB_IF: 274 /* Invert both clocks */ 275 val_cr2 ^= FSL_SAI_CR2_BCP; 276 val_cr4 ^= FSL_SAI_CR4_FSP; 277 break; 278 case SND_SOC_DAIFMT_IB_NF: 279 /* Invert bit clock */ 280 val_cr2 ^= FSL_SAI_CR2_BCP; 281 break; 282 case SND_SOC_DAIFMT_NB_IF: 283 /* Invert frame clock */ 284 val_cr4 ^= FSL_SAI_CR4_FSP; 285 break; 286 case SND_SOC_DAIFMT_NB_NF: 287 /* Nothing to do for both normal cases */ 288 break; 289 default: 290 return -EINVAL; 291 } 292 293 /* DAI clock provider masks */ 294 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 295 case SND_SOC_DAIFMT_BP_FP: 296 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 297 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 298 sai->is_consumer_mode = false; 299 break; 300 case SND_SOC_DAIFMT_BC_FC: 301 sai->is_consumer_mode = true; 302 break; 303 case SND_SOC_DAIFMT_BP_FC: 304 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 305 sai->is_consumer_mode = false; 306 break; 307 case SND_SOC_DAIFMT_BC_FP: 308 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 309 sai->is_consumer_mode = true; 310 break; 311 default: 312 return -EINVAL; 313 } 314 315 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 316 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 317 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 318 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 319 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 320 321 return 0; 322 } 323 324 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 325 { 326 int ret; 327 328 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 329 if (ret) { 330 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 331 return ret; 332 } 333 334 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 335 if (ret) 336 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 337 338 return ret; 339 } 340 341 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 342 { 343 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 344 unsigned int reg, ofs = sai->soc_data->reg_offset; 345 unsigned long clk_rate; 346 u32 savediv = 0, ratio, bestdiff = freq; 347 int adir = tx ? RX : TX; 348 int dir = tx ? TX : RX; 349 u32 id; 350 bool support_1_1_ratio = sai->verid.version >= 0x0301; 351 352 /* Don't apply to consumer mode */ 353 if (sai->is_consumer_mode) 354 return 0; 355 356 /* 357 * There is no point in polling MCLK0 if it is identical to MCLK1. 358 * And given that MQS use case has to use MCLK1 though two clocks 359 * are the same, we simply skip MCLK0 and start to find from MCLK1. 360 */ 361 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 362 363 for (; id < FSL_SAI_MCLK_MAX; id++) { 364 int diff; 365 366 clk_rate = clk_get_rate(sai->mclk_clk[id]); 367 if (!clk_rate) 368 continue; 369 370 ratio = DIV_ROUND_CLOSEST(clk_rate, freq); 371 if (!ratio || ratio > 512) 372 continue; 373 if (ratio == 1 && !support_1_1_ratio) 374 continue; 375 if ((ratio & 1) && ratio > 1) 376 continue; 377 378 diff = abs((long)clk_rate - ratio * freq); 379 380 /* 381 * Drop the source that can not be 382 * divided into the required rate. 383 */ 384 if (diff != 0 && clk_rate / diff < 1000) 385 continue; 386 387 dev_dbg(dai->dev, 388 "ratio %d for freq %dHz based on clock %ldHz\n", 389 ratio, freq, clk_rate); 390 391 392 if (diff < bestdiff) { 393 savediv = ratio; 394 sai->mclk_id[tx] = id; 395 bestdiff = diff; 396 } 397 398 if (diff == 0) 399 break; 400 } 401 402 if (savediv == 0) { 403 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 404 tx ? 'T' : 'R', freq); 405 return -EINVAL; 406 } 407 408 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 409 sai->mclk_id[tx], savediv, bestdiff); 410 411 /* 412 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 413 * set TCR2 register for playback. 414 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 415 * and capture. 416 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 417 * and capture. 418 * 4) For Tx and Rx are both Synchronous with another SAI, we just 419 * ignore it. 420 */ 421 if (fsl_sai_dir_is_synced(sai, adir)) 422 reg = FSL_SAI_xCR2(!tx, ofs); 423 else if (!sai->synchronous[dir]) 424 reg = FSL_SAI_xCR2(tx, ofs); 425 else 426 return 0; 427 428 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, 429 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 430 431 if (savediv == 1) 432 regmap_update_bits(sai->regmap, reg, 433 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 434 FSL_SAI_CR2_BYP); 435 else 436 regmap_update_bits(sai->regmap, reg, 437 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 438 savediv / 2 - 1); 439 440 if (sai->soc_data->max_register >= FSL_SAI_MCTL) { 441 /* SAI is in master mode at this point, so enable MCLK */ 442 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 443 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 444 } 445 446 return 0; 447 } 448 449 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 450 struct snd_pcm_hw_params *params, 451 struct snd_soc_dai *cpu_dai) 452 { 453 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 454 unsigned int ofs = sai->soc_data->reg_offset; 455 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 456 unsigned int channels = params_channels(params); 457 u32 word_width = params_width(params); 458 u32 val_cr4 = 0, val_cr5 = 0; 459 u32 slots = (channels == 1) ? 2 : channels; 460 u32 slot_width = word_width; 461 int adir = tx ? RX : TX; 462 u32 pins; 463 int ret; 464 465 if (sai->slots) 466 slots = sai->slots; 467 468 if (sai->slot_width) 469 slot_width = sai->slot_width; 470 471 pins = DIV_ROUND_UP(channels, slots); 472 473 if (!sai->is_consumer_mode) { 474 if (sai->bclk_ratio) 475 ret = fsl_sai_set_bclk(cpu_dai, tx, 476 sai->bclk_ratio * 477 params_rate(params)); 478 else 479 ret = fsl_sai_set_bclk(cpu_dai, tx, 480 slots * slot_width * 481 params_rate(params)); 482 if (ret) 483 return ret; 484 485 /* Do not enable the clock if it is already enabled */ 486 if (!(sai->mclk_streams & BIT(substream->stream))) { 487 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 488 if (ret) 489 return ret; 490 491 sai->mclk_streams |= BIT(substream->stream); 492 } 493 } 494 495 if (!sai->is_dsp_mode) 496 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 497 498 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 499 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 500 501 if (sai->is_lsb_first) 502 val_cr5 |= FSL_SAI_CR5_FBT(0); 503 else 504 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 505 506 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 507 508 /* Set to output mode to avoid tri-stated data pins */ 509 if (tx) 510 val_cr4 |= FSL_SAI_CR4_CHMOD; 511 512 /* 513 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 514 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 515 * RCR5(TCR5) for playback(capture), or there will be sync error. 516 */ 517 518 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) { 519 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 520 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 521 FSL_SAI_CR4_CHMOD_MASK, 522 val_cr4); 523 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 524 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 525 FSL_SAI_CR5_FBT_MASK, val_cr5); 526 } 527 528 if (sai->soc_data->pins > 1) 529 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 530 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); 531 532 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 533 FSL_SAI_CR3_TRCE_MASK, 534 FSL_SAI_CR3_TRCE((1 << pins) - 1)); 535 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 536 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 537 FSL_SAI_CR4_CHMOD_MASK, 538 val_cr4); 539 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 540 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 541 FSL_SAI_CR5_FBT_MASK, val_cr5); 542 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 543 ~0UL - ((1 << min(channels, slots)) - 1)); 544 545 return 0; 546 } 547 548 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 549 struct snd_soc_dai *cpu_dai) 550 { 551 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 552 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 553 unsigned int ofs = sai->soc_data->reg_offset; 554 555 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 556 FSL_SAI_CR3_TRCE_MASK, 0); 557 558 if (!sai->is_consumer_mode && 559 sai->mclk_streams & BIT(substream->stream)) { 560 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 561 sai->mclk_streams &= ~BIT(substream->stream); 562 } 563 564 return 0; 565 } 566 567 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 568 { 569 unsigned int ofs = sai->soc_data->reg_offset; 570 bool tx = dir == TX; 571 u32 xcsr, count = 100; 572 573 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 574 FSL_SAI_CSR_TERE, 0); 575 576 /* TERE will remain set till the end of current frame */ 577 do { 578 udelay(10); 579 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 580 } while (--count && xcsr & FSL_SAI_CSR_TERE); 581 582 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 583 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 584 585 /* 586 * For sai master mode, after several open/close sai, 587 * there will be no frame clock, and can't recover 588 * anymore. Add software reset to fix this issue. 589 * This is a hardware bug, and will be fix in the 590 * next sai version. 591 */ 592 if (!sai->is_consumer_mode) { 593 /* Software Reset */ 594 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); 595 /* Clear SR bit to finish the reset */ 596 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); 597 } 598 } 599 600 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 601 struct snd_soc_dai *cpu_dai) 602 { 603 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 604 unsigned int ofs = sai->soc_data->reg_offset; 605 606 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 607 int adir = tx ? RX : TX; 608 int dir = tx ? TX : RX; 609 u32 xcsr; 610 611 /* 612 * Asynchronous mode: Clear SYNC for both Tx and Rx. 613 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 614 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 615 */ 616 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 617 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 618 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 619 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 620 621 /* 622 * It is recommended that the transmitter is the last enabled 623 * and the first disabled. 624 */ 625 switch (cmd) { 626 case SNDRV_PCM_TRIGGER_START: 627 case SNDRV_PCM_TRIGGER_RESUME: 628 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 629 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 630 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 631 632 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 633 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 634 /* 635 * Enable the opposite direction for synchronous mode 636 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 637 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 638 * 639 * RM recommends to enable RE after TE for case 1 and to enable 640 * TE after RE for case 2, but we here may not always guarantee 641 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 642 * TE after RE, which is against what RM recommends but should 643 * be safe to do, judging by years of testing results. 644 */ 645 if (fsl_sai_dir_is_synced(sai, adir)) 646 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 647 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 648 649 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 650 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 651 break; 652 case SNDRV_PCM_TRIGGER_STOP: 653 case SNDRV_PCM_TRIGGER_SUSPEND: 654 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 655 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 656 FSL_SAI_CSR_FRDE, 0); 657 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 658 FSL_SAI_CSR_xIE_MASK, 0); 659 660 /* Check if the opposite FRDE is also disabled */ 661 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 662 663 /* 664 * If opposite stream provides clocks for synchronous mode and 665 * it is inactive, disable it before disabling the current one 666 */ 667 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 668 fsl_sai_config_disable(sai, adir); 669 670 /* 671 * Disable current stream if either of: 672 * 1. current stream doesn't provide clocks for synchronous mode 673 * 2. current stream provides clocks for synchronous mode but no 674 * more stream is active. 675 */ 676 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 677 fsl_sai_config_disable(sai, dir); 678 679 break; 680 default: 681 return -EINVAL; 682 } 683 684 return 0; 685 } 686 687 static int fsl_sai_startup(struct snd_pcm_substream *substream, 688 struct snd_soc_dai *cpu_dai) 689 { 690 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 691 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 692 int ret; 693 694 /* 695 * EDMA controller needs period size to be a multiple of 696 * tx/rx maxburst 697 */ 698 if (sai->soc_data->use_edma) 699 snd_pcm_hw_constraint_step(substream->runtime, 0, 700 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 701 tx ? sai->dma_params_tx.maxburst : 702 sai->dma_params_rx.maxburst); 703 704 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 705 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); 706 707 return ret; 708 } 709 710 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 711 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 712 .set_sysclk = fsl_sai_set_dai_sysclk, 713 .set_fmt = fsl_sai_set_dai_fmt, 714 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 715 .hw_params = fsl_sai_hw_params, 716 .hw_free = fsl_sai_hw_free, 717 .trigger = fsl_sai_trigger, 718 .startup = fsl_sai_startup, 719 }; 720 721 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 722 { 723 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 724 unsigned int ofs = sai->soc_data->reg_offset; 725 726 /* Software Reset for both Tx and Rx */ 727 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 728 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 729 /* Clear SR bit to finish the reset */ 730 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 731 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 732 733 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 734 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 735 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX); 736 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 737 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 738 FSL_SAI_MAXBURST_RX - 1); 739 740 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 741 &sai->dma_params_rx); 742 743 return 0; 744 } 745 746 static struct snd_soc_dai_driver fsl_sai_dai_template = { 747 .probe = fsl_sai_dai_probe, 748 .playback = { 749 .stream_name = "CPU-Playback", 750 .channels_min = 1, 751 .channels_max = 32, 752 .rate_min = 8000, 753 .rate_max = 192000, 754 .rates = SNDRV_PCM_RATE_KNOT, 755 .formats = FSL_SAI_FORMATS, 756 }, 757 .capture = { 758 .stream_name = "CPU-Capture", 759 .channels_min = 1, 760 .channels_max = 32, 761 .rate_min = 8000, 762 .rate_max = 192000, 763 .rates = SNDRV_PCM_RATE_KNOT, 764 .formats = FSL_SAI_FORMATS, 765 }, 766 .ops = &fsl_sai_pcm_dai_ops, 767 }; 768 769 static const struct snd_soc_component_driver fsl_component = { 770 .name = "fsl-sai", 771 }; 772 773 static struct reg_default fsl_sai_reg_defaults_ofs0[] = { 774 {FSL_SAI_TCR1(0), 0}, 775 {FSL_SAI_TCR2(0), 0}, 776 {FSL_SAI_TCR3(0), 0}, 777 {FSL_SAI_TCR4(0), 0}, 778 {FSL_SAI_TCR5(0), 0}, 779 {FSL_SAI_TDR0, 0}, 780 {FSL_SAI_TDR1, 0}, 781 {FSL_SAI_TDR2, 0}, 782 {FSL_SAI_TDR3, 0}, 783 {FSL_SAI_TDR4, 0}, 784 {FSL_SAI_TDR5, 0}, 785 {FSL_SAI_TDR6, 0}, 786 {FSL_SAI_TDR7, 0}, 787 {FSL_SAI_TMR, 0}, 788 {FSL_SAI_RCR1(0), 0}, 789 {FSL_SAI_RCR2(0), 0}, 790 {FSL_SAI_RCR3(0), 0}, 791 {FSL_SAI_RCR4(0), 0}, 792 {FSL_SAI_RCR5(0), 0}, 793 {FSL_SAI_RMR, 0}, 794 }; 795 796 static struct reg_default fsl_sai_reg_defaults_ofs8[] = { 797 {FSL_SAI_TCR1(8), 0}, 798 {FSL_SAI_TCR2(8), 0}, 799 {FSL_SAI_TCR3(8), 0}, 800 {FSL_SAI_TCR4(8), 0}, 801 {FSL_SAI_TCR5(8), 0}, 802 {FSL_SAI_TDR0, 0}, 803 {FSL_SAI_TDR1, 0}, 804 {FSL_SAI_TDR2, 0}, 805 {FSL_SAI_TDR3, 0}, 806 {FSL_SAI_TDR4, 0}, 807 {FSL_SAI_TDR5, 0}, 808 {FSL_SAI_TDR6, 0}, 809 {FSL_SAI_TDR7, 0}, 810 {FSL_SAI_TMR, 0}, 811 {FSL_SAI_RCR1(8), 0}, 812 {FSL_SAI_RCR2(8), 0}, 813 {FSL_SAI_RCR3(8), 0}, 814 {FSL_SAI_RCR4(8), 0}, 815 {FSL_SAI_RCR5(8), 0}, 816 {FSL_SAI_RMR, 0}, 817 {FSL_SAI_MCTL, 0}, 818 {FSL_SAI_MDIV, 0}, 819 }; 820 821 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 822 { 823 struct fsl_sai *sai = dev_get_drvdata(dev); 824 unsigned int ofs = sai->soc_data->reg_offset; 825 826 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 827 return true; 828 829 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 830 return true; 831 832 switch (reg) { 833 case FSL_SAI_TFR0: 834 case FSL_SAI_TFR1: 835 case FSL_SAI_TFR2: 836 case FSL_SAI_TFR3: 837 case FSL_SAI_TFR4: 838 case FSL_SAI_TFR5: 839 case FSL_SAI_TFR6: 840 case FSL_SAI_TFR7: 841 case FSL_SAI_TMR: 842 case FSL_SAI_RDR0: 843 case FSL_SAI_RDR1: 844 case FSL_SAI_RDR2: 845 case FSL_SAI_RDR3: 846 case FSL_SAI_RDR4: 847 case FSL_SAI_RDR5: 848 case FSL_SAI_RDR6: 849 case FSL_SAI_RDR7: 850 case FSL_SAI_RFR0: 851 case FSL_SAI_RFR1: 852 case FSL_SAI_RFR2: 853 case FSL_SAI_RFR3: 854 case FSL_SAI_RFR4: 855 case FSL_SAI_RFR5: 856 case FSL_SAI_RFR6: 857 case FSL_SAI_RFR7: 858 case FSL_SAI_RMR: 859 case FSL_SAI_MCTL: 860 case FSL_SAI_MDIV: 861 case FSL_SAI_VERID: 862 case FSL_SAI_PARAM: 863 case FSL_SAI_TTCTN: 864 case FSL_SAI_RTCTN: 865 case FSL_SAI_TTCTL: 866 case FSL_SAI_TBCTN: 867 case FSL_SAI_TTCAP: 868 case FSL_SAI_RTCTL: 869 case FSL_SAI_RBCTN: 870 case FSL_SAI_RTCAP: 871 return true; 872 default: 873 return false; 874 } 875 } 876 877 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 878 { 879 struct fsl_sai *sai = dev_get_drvdata(dev); 880 unsigned int ofs = sai->soc_data->reg_offset; 881 882 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 883 return true; 884 885 /* Set VERID and PARAM be volatile for reading value in probe */ 886 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 887 return true; 888 889 switch (reg) { 890 case FSL_SAI_TFR0: 891 case FSL_SAI_TFR1: 892 case FSL_SAI_TFR2: 893 case FSL_SAI_TFR3: 894 case FSL_SAI_TFR4: 895 case FSL_SAI_TFR5: 896 case FSL_SAI_TFR6: 897 case FSL_SAI_TFR7: 898 case FSL_SAI_RFR0: 899 case FSL_SAI_RFR1: 900 case FSL_SAI_RFR2: 901 case FSL_SAI_RFR3: 902 case FSL_SAI_RFR4: 903 case FSL_SAI_RFR5: 904 case FSL_SAI_RFR6: 905 case FSL_SAI_RFR7: 906 case FSL_SAI_RDR0: 907 case FSL_SAI_RDR1: 908 case FSL_SAI_RDR2: 909 case FSL_SAI_RDR3: 910 case FSL_SAI_RDR4: 911 case FSL_SAI_RDR5: 912 case FSL_SAI_RDR6: 913 case FSL_SAI_RDR7: 914 return true; 915 default: 916 return false; 917 } 918 } 919 920 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 921 { 922 struct fsl_sai *sai = dev_get_drvdata(dev); 923 unsigned int ofs = sai->soc_data->reg_offset; 924 925 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 926 return true; 927 928 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 929 return true; 930 931 switch (reg) { 932 case FSL_SAI_TDR0: 933 case FSL_SAI_TDR1: 934 case FSL_SAI_TDR2: 935 case FSL_SAI_TDR3: 936 case FSL_SAI_TDR4: 937 case FSL_SAI_TDR5: 938 case FSL_SAI_TDR6: 939 case FSL_SAI_TDR7: 940 case FSL_SAI_TMR: 941 case FSL_SAI_RMR: 942 case FSL_SAI_MCTL: 943 case FSL_SAI_MDIV: 944 case FSL_SAI_TTCTL: 945 case FSL_SAI_RTCTL: 946 return true; 947 default: 948 return false; 949 } 950 } 951 952 static struct regmap_config fsl_sai_regmap_config = { 953 .reg_bits = 32, 954 .reg_stride = 4, 955 .val_bits = 32, 956 .fast_io = true, 957 958 .max_register = FSL_SAI_RMR, 959 .reg_defaults = fsl_sai_reg_defaults_ofs0, 960 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 961 .readable_reg = fsl_sai_readable_reg, 962 .volatile_reg = fsl_sai_volatile_reg, 963 .writeable_reg = fsl_sai_writeable_reg, 964 .cache_type = REGCACHE_FLAT, 965 }; 966 967 static int fsl_sai_check_version(struct device *dev) 968 { 969 struct fsl_sai *sai = dev_get_drvdata(dev); 970 unsigned char ofs = sai->soc_data->reg_offset; 971 unsigned int val; 972 int ret; 973 974 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 975 return 0; 976 977 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 978 if (ret < 0) 979 return ret; 980 981 dev_dbg(dev, "VERID: 0x%016X\n", val); 982 983 sai->verid.version = val & 984 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK); 985 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 986 987 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 988 if (ret < 0) 989 return ret; 990 991 dev_dbg(dev, "PARAM: 0x%016X\n", val); 992 993 /* Max slots per frame, power of 2 */ 994 sai->param.slot_num = 1 << 995 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 996 997 /* Words per fifo, power of 2 */ 998 sai->param.fifo_depth = 1 << 999 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 1000 1001 /* Number of datalines implemented */ 1002 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 1003 1004 return 0; 1005 } 1006 1007 static int fsl_sai_runtime_suspend(struct device *dev); 1008 static int fsl_sai_runtime_resume(struct device *dev); 1009 1010 static int fsl_sai_probe(struct platform_device *pdev) 1011 { 1012 struct device_node *np = pdev->dev.of_node; 1013 struct device *dev = &pdev->dev; 1014 struct fsl_sai *sai; 1015 struct regmap *gpr; 1016 struct resource *res; 1017 void __iomem *base; 1018 char tmp[8]; 1019 int irq, ret, i; 1020 int index; 1021 1022 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); 1023 if (!sai) 1024 return -ENOMEM; 1025 1026 sai->pdev = pdev; 1027 sai->soc_data = of_device_get_match_data(dev); 1028 1029 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1030 1031 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1032 if (IS_ERR(base)) 1033 return PTR_ERR(base); 1034 1035 if (sai->soc_data->reg_offset == 8) { 1036 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1037 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1038 fsl_sai_regmap_config.num_reg_defaults = 1039 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1040 } 1041 1042 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); 1043 if (IS_ERR(sai->regmap)) { 1044 dev_err(dev, "regmap init failed\n"); 1045 return PTR_ERR(sai->regmap); 1046 } 1047 1048 sai->bus_clk = devm_clk_get(dev, "bus"); 1049 /* Compatible with old DTB cases */ 1050 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1051 sai->bus_clk = devm_clk_get(dev, "sai"); 1052 if (IS_ERR(sai->bus_clk)) { 1053 dev_err(dev, "failed to get bus clock: %ld\n", 1054 PTR_ERR(sai->bus_clk)); 1055 /* -EPROBE_DEFER */ 1056 return PTR_ERR(sai->bus_clk); 1057 } 1058 1059 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1060 sprintf(tmp, "mclk%d", i); 1061 sai->mclk_clk[i] = devm_clk_get(dev, tmp); 1062 if (IS_ERR(sai->mclk_clk[i])) { 1063 dev_err(dev, "failed to get mclk%d clock: %ld\n", 1064 i + 1, PTR_ERR(sai->mclk_clk[i])); 1065 sai->mclk_clk[i] = NULL; 1066 } 1067 } 1068 1069 if (sai->soc_data->mclk0_is_mclk1) 1070 sai->mclk_clk[0] = sai->mclk_clk[1]; 1071 else 1072 sai->mclk_clk[0] = sai->bus_clk; 1073 1074 irq = platform_get_irq(pdev, 0); 1075 if (irq < 0) 1076 return irq; 1077 1078 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED, 1079 np->name, sai); 1080 if (ret) { 1081 dev_err(dev, "failed to claim irq %u\n", irq); 1082 return ret; 1083 } 1084 1085 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, 1086 sizeof(fsl_sai_dai_template)); 1087 1088 /* Sync Tx with Rx as default by following old DT binding */ 1089 sai->synchronous[RX] = true; 1090 sai->synchronous[TX] = false; 1091 sai->cpu_dai_drv.symmetric_rate = 1; 1092 sai->cpu_dai_drv.symmetric_channels = 1; 1093 sai->cpu_dai_drv.symmetric_sample_bits = 1; 1094 1095 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && 1096 of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1097 /* error out if both synchronous and asynchronous are present */ 1098 dev_err(dev, "invalid binding for synchronous mode\n"); 1099 return -EINVAL; 1100 } 1101 1102 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { 1103 /* Sync Rx with Tx */ 1104 sai->synchronous[RX] = false; 1105 sai->synchronous[TX] = true; 1106 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1107 /* Discard all settings for asynchronous mode */ 1108 sai->synchronous[RX] = false; 1109 sai->synchronous[TX] = false; 1110 sai->cpu_dai_drv.symmetric_rate = 0; 1111 sai->cpu_dai_drv.symmetric_channels = 0; 1112 sai->cpu_dai_drv.symmetric_sample_bits = 0; 1113 } 1114 1115 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1116 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1117 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1118 if (IS_ERR(gpr)) { 1119 dev_err(dev, "cannot find iomuxc registers\n"); 1120 return PTR_ERR(gpr); 1121 } 1122 1123 index = of_alias_get_id(np, "sai"); 1124 if (index < 0) 1125 return index; 1126 1127 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1128 MCLK_DIR(index)); 1129 } 1130 1131 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0; 1132 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0; 1133 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; 1134 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; 1135 1136 platform_set_drvdata(pdev, sai); 1137 pm_runtime_enable(dev); 1138 if (!pm_runtime_enabled(dev)) { 1139 ret = fsl_sai_runtime_resume(dev); 1140 if (ret) 1141 goto err_pm_disable; 1142 } 1143 1144 ret = pm_runtime_get_sync(dev); 1145 if (ret < 0) { 1146 pm_runtime_put_noidle(dev); 1147 goto err_pm_get_sync; 1148 } 1149 1150 /* Get sai version */ 1151 ret = fsl_sai_check_version(dev); 1152 if (ret < 0) 1153 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1154 1155 /* Select MCLK direction */ 1156 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1157 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1158 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1159 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1160 } 1161 1162 ret = pm_runtime_put_sync(dev); 1163 if (ret < 0) 1164 goto err_pm_get_sync; 1165 1166 /* 1167 * Register platform component before registering cpu dai for there 1168 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1169 */ 1170 if (sai->soc_data->use_imx_pcm) { 1171 ret = imx_pcm_dma_init(pdev); 1172 if (ret) { 1173 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)) 1174 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); 1175 goto err_pm_get_sync; 1176 } 1177 } else { 1178 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1179 if (ret) 1180 goto err_pm_get_sync; 1181 } 1182 1183 ret = devm_snd_soc_register_component(dev, &fsl_component, 1184 &sai->cpu_dai_drv, 1); 1185 if (ret) 1186 goto err_pm_get_sync; 1187 1188 return ret; 1189 1190 err_pm_get_sync: 1191 if (!pm_runtime_status_suspended(dev)) 1192 fsl_sai_runtime_suspend(dev); 1193 err_pm_disable: 1194 pm_runtime_disable(dev); 1195 1196 return ret; 1197 } 1198 1199 static int fsl_sai_remove(struct platform_device *pdev) 1200 { 1201 pm_runtime_disable(&pdev->dev); 1202 if (!pm_runtime_status_suspended(&pdev->dev)) 1203 fsl_sai_runtime_suspend(&pdev->dev); 1204 1205 return 0; 1206 } 1207 1208 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1209 .use_imx_pcm = false, 1210 .use_edma = false, 1211 .fifo_depth = 32, 1212 .pins = 1, 1213 .reg_offset = 0, 1214 .mclk0_is_mclk1 = false, 1215 .flags = 0, 1216 .max_register = FSL_SAI_RMR, 1217 }; 1218 1219 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1220 .use_imx_pcm = true, 1221 .use_edma = false, 1222 .fifo_depth = 32, 1223 .pins = 1, 1224 .reg_offset = 0, 1225 .mclk0_is_mclk1 = true, 1226 .flags = 0, 1227 .max_register = FSL_SAI_RMR, 1228 }; 1229 1230 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1231 .use_imx_pcm = true, 1232 .use_edma = false, 1233 .fifo_depth = 16, 1234 .pins = 2, 1235 .reg_offset = 8, 1236 .mclk0_is_mclk1 = false, 1237 .flags = PMQOS_CPU_LATENCY, 1238 .max_register = FSL_SAI_RMR, 1239 }; 1240 1241 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1242 .use_imx_pcm = true, 1243 .use_edma = false, 1244 .fifo_depth = 128, 1245 .pins = 8, 1246 .reg_offset = 8, 1247 .mclk0_is_mclk1 = false, 1248 .flags = 0, 1249 .max_register = FSL_SAI_RMR, 1250 }; 1251 1252 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1253 .use_imx_pcm = true, 1254 .use_edma = true, 1255 .fifo_depth = 64, 1256 .pins = 1, 1257 .reg_offset = 0, 1258 .mclk0_is_mclk1 = false, 1259 .flags = 0, 1260 .max_register = FSL_SAI_RMR, 1261 }; 1262 1263 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = { 1264 .use_imx_pcm = true, 1265 .use_edma = false, 1266 .fifo_depth = 128, 1267 .reg_offset = 8, 1268 .mclk0_is_mclk1 = false, 1269 .pins = 8, 1270 .flags = 0, 1271 .max_register = FSL_SAI_MCTL, 1272 }; 1273 1274 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1275 .use_imx_pcm = true, 1276 .use_edma = false, 1277 .fifo_depth = 128, 1278 .reg_offset = 8, 1279 .mclk0_is_mclk1 = false, 1280 .pins = 8, 1281 .flags = 0, 1282 .max_register = FSL_SAI_MDIV, 1283 }; 1284 1285 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { 1286 .use_imx_pcm = true, 1287 .use_edma = true, 1288 .fifo_depth = 16, 1289 .reg_offset = 8, 1290 .mclk0_is_mclk1 = false, 1291 .pins = 4, 1292 .flags = PMQOS_CPU_LATENCY, 1293 .max_register = FSL_SAI_RTCAP, 1294 }; 1295 1296 static const struct of_device_id fsl_sai_ids[] = { 1297 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1298 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1299 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1300 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1301 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1302 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1303 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1304 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1305 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1306 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mp_data }, 1307 { /* sentinel */ } 1308 }; 1309 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1310 1311 static int fsl_sai_runtime_suspend(struct device *dev) 1312 { 1313 struct fsl_sai *sai = dev_get_drvdata(dev); 1314 1315 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1316 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1317 1318 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1319 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1320 1321 clk_disable_unprepare(sai->bus_clk); 1322 1323 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1324 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1325 1326 regcache_cache_only(sai->regmap, true); 1327 1328 return 0; 1329 } 1330 1331 static int fsl_sai_runtime_resume(struct device *dev) 1332 { 1333 struct fsl_sai *sai = dev_get_drvdata(dev); 1334 unsigned int ofs = sai->soc_data->reg_offset; 1335 int ret; 1336 1337 ret = clk_prepare_enable(sai->bus_clk); 1338 if (ret) { 1339 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1340 return ret; 1341 } 1342 1343 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1344 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1345 if (ret) 1346 goto disable_bus_clk; 1347 } 1348 1349 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1350 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1351 if (ret) 1352 goto disable_tx_clk; 1353 } 1354 1355 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1356 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1357 1358 regcache_cache_only(sai->regmap, false); 1359 regcache_mark_dirty(sai->regmap); 1360 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 1361 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 1362 usleep_range(1000, 2000); 1363 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1364 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1365 1366 ret = regcache_sync(sai->regmap); 1367 if (ret) 1368 goto disable_rx_clk; 1369 1370 return 0; 1371 1372 disable_rx_clk: 1373 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1374 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1375 disable_tx_clk: 1376 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1377 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1378 disable_bus_clk: 1379 clk_disable_unprepare(sai->bus_clk); 1380 1381 return ret; 1382 } 1383 1384 static const struct dev_pm_ops fsl_sai_pm_ops = { 1385 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, 1386 fsl_sai_runtime_resume, NULL) 1387 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1388 pm_runtime_force_resume) 1389 }; 1390 1391 static struct platform_driver fsl_sai_driver = { 1392 .probe = fsl_sai_probe, 1393 .remove = fsl_sai_remove, 1394 .driver = { 1395 .name = "fsl-sai", 1396 .pm = &fsl_sai_pm_ops, 1397 .of_match_table = fsl_sai_ids, 1398 }, 1399 }; 1400 module_platform_driver(fsl_sai_driver); 1401 1402 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1403 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1404 MODULE_ALIAS("platform:fsl-sai"); 1405 MODULE_LICENSE("GPL"); 1406