1b73d9e62SShengjiu Wang /* SPDX-License-Identifier: GPL-2.0 */ 2b73d9e62SShengjiu Wang /* 3b73d9e62SShengjiu Wang * Copyright 2017-2021 NXP 4b73d9e62SShengjiu Wang */ 5b73d9e62SShengjiu Wang 6b73d9e62SShengjiu Wang #ifndef __FSL_RPMSG_H 7b73d9e62SShengjiu Wang #define __FSL_RPMSG_H 8b73d9e62SShengjiu Wang 9b73d9e62SShengjiu Wang /* 10*b7bbbf01SShengjiu Wang * struct fsl_rpmsg_soc_data 11*b7bbbf01SShengjiu Wang * @rates: supported rates 12*b7bbbf01SShengjiu Wang * @formats: supported formats 13*b7bbbf01SShengjiu Wang */ 14*b7bbbf01SShengjiu Wang struct fsl_rpmsg_soc_data { 15*b7bbbf01SShengjiu Wang int rates; 16*b7bbbf01SShengjiu Wang u64 formats; 17*b7bbbf01SShengjiu Wang }; 18*b7bbbf01SShengjiu Wang 19*b7bbbf01SShengjiu Wang /* 20b73d9e62SShengjiu Wang * struct fsl_rpmsg - rpmsg private data 21b73d9e62SShengjiu Wang * 22b73d9e62SShengjiu Wang * @ipg: ipg clock for cpu dai (SAI) 23b73d9e62SShengjiu Wang * @mclk: master clock for cpu dai (SAI) 24b73d9e62SShengjiu Wang * @dma: clock for dma device 25b73d9e62SShengjiu Wang * @pll8k: parent clock for multiple of 8kHz frequency 26b73d9e62SShengjiu Wang * @pll11k: parent clock for multiple of 11kHz frequency 27b73d9e62SShengjiu Wang * @card_pdev: Platform_device pointer to register a sound card 28*b7bbbf01SShengjiu Wang * @soc_data: soc specific data 29b73d9e62SShengjiu Wang * @mclk_streams: Active streams that are using baudclk 30b73d9e62SShengjiu Wang * @force_lpa: force enable low power audio routine if condition satisfy 31b73d9e62SShengjiu Wang * @enable_lpa: enable low power audio routine according to dts setting 32b73d9e62SShengjiu Wang * @buffer_size: pre allocated dma buffer size 33b73d9e62SShengjiu Wang */ 34b73d9e62SShengjiu Wang struct fsl_rpmsg { 35b73d9e62SShengjiu Wang struct clk *ipg; 36b73d9e62SShengjiu Wang struct clk *mclk; 37b73d9e62SShengjiu Wang struct clk *dma; 38b73d9e62SShengjiu Wang struct clk *pll8k; 39b73d9e62SShengjiu Wang struct clk *pll11k; 40b73d9e62SShengjiu Wang struct platform_device *card_pdev; 41*b7bbbf01SShengjiu Wang const struct fsl_rpmsg_soc_data *soc_data; 42b73d9e62SShengjiu Wang unsigned int mclk_streams; 43b73d9e62SShengjiu Wang int force_lpa; 44b73d9e62SShengjiu Wang int enable_lpa; 45b73d9e62SShengjiu Wang int buffer_size; 46b73d9e62SShengjiu Wang }; 47b73d9e62SShengjiu Wang #endif /* __FSL_RPMSG_H */ 48