1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright 2018 NXP 3 4 #include <linux/bitfield.h> 5 #include <linux/clk.h> 6 #include <linux/device.h> 7 #include <linux/interrupt.h> 8 #include <linux/kobject.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_platform.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/sysfs.h> 18 #include <linux/types.h> 19 #include <linux/dma/imx-dma.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm.h> 22 #include <sound/soc.h> 23 #include <sound/tlv.h> 24 #include <sound/core.h> 25 26 #include "fsl_micfil.h" 27 #include "fsl_utils.h" 28 29 #define MICFIL_OSR_DEFAULT 16 30 31 enum quality { 32 QUALITY_HIGH, 33 QUALITY_MEDIUM, 34 QUALITY_LOW, 35 QUALITY_VLOW0, 36 QUALITY_VLOW1, 37 QUALITY_VLOW2, 38 }; 39 40 struct fsl_micfil { 41 struct platform_device *pdev; 42 struct regmap *regmap; 43 const struct fsl_micfil_soc_data *soc; 44 struct clk *busclk; 45 struct clk *mclk; 46 struct clk *pll8k_clk; 47 struct clk *pll11k_clk; 48 struct snd_dmaengine_dai_dma_data dma_params_rx; 49 struct sdma_peripheral_config sdmacfg; 50 struct snd_soc_card *card; 51 unsigned int dataline; 52 char name[32]; 53 int irq[MICFIL_IRQ_LINES]; 54 enum quality quality; 55 int dc_remover; 56 int vad_init_mode; 57 int vad_enabled; 58 int vad_detected; 59 }; 60 61 struct fsl_micfil_soc_data { 62 unsigned int fifos; 63 unsigned int fifo_depth; 64 unsigned int dataline; 65 bool imx; 66 u64 formats; 67 }; 68 69 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = { 70 .imx = true, 71 .fifos = 8, 72 .fifo_depth = 8, 73 .dataline = 0xf, 74 .formats = SNDRV_PCM_FMTBIT_S16_LE, 75 }; 76 77 static struct fsl_micfil_soc_data fsl_micfil_imx8mp = { 78 .imx = true, 79 .fifos = 8, 80 .fifo_depth = 32, 81 .dataline = 0xf, 82 .formats = SNDRV_PCM_FMTBIT_S32_LE, 83 }; 84 85 static const struct of_device_id fsl_micfil_dt_ids[] = { 86 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm }, 87 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp }, 88 {} 89 }; 90 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids); 91 92 static const char * const micfil_quality_select_texts[] = { 93 [QUALITY_HIGH] = "High", 94 [QUALITY_MEDIUM] = "Medium", 95 [QUALITY_LOW] = "Low", 96 [QUALITY_VLOW0] = "VLow0", 97 [QUALITY_VLOW1] = "Vlow1", 98 [QUALITY_VLOW2] = "Vlow2", 99 }; 100 101 static const struct soc_enum fsl_micfil_quality_enum = 102 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts), 103 micfil_quality_select_texts); 104 105 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0); 106 107 static int micfil_set_quality(struct fsl_micfil *micfil) 108 { 109 u32 qsel; 110 111 switch (micfil->quality) { 112 case QUALITY_HIGH: 113 qsel = MICFIL_QSEL_HIGH_QUALITY; 114 break; 115 case QUALITY_MEDIUM: 116 qsel = MICFIL_QSEL_MEDIUM_QUALITY; 117 break; 118 case QUALITY_LOW: 119 qsel = MICFIL_QSEL_LOW_QUALITY; 120 break; 121 case QUALITY_VLOW0: 122 qsel = MICFIL_QSEL_VLOW0_QUALITY; 123 break; 124 case QUALITY_VLOW1: 125 qsel = MICFIL_QSEL_VLOW1_QUALITY; 126 break; 127 case QUALITY_VLOW2: 128 qsel = MICFIL_QSEL_VLOW2_QUALITY; 129 break; 130 } 131 132 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 133 MICFIL_CTRL2_QSEL, 134 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel)); 135 } 136 137 static int micfil_quality_get(struct snd_kcontrol *kcontrol, 138 struct snd_ctl_elem_value *ucontrol) 139 { 140 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 141 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 142 143 ucontrol->value.integer.value[0] = micfil->quality; 144 145 return 0; 146 } 147 148 static int micfil_quality_set(struct snd_kcontrol *kcontrol, 149 struct snd_ctl_elem_value *ucontrol) 150 { 151 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 152 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 153 154 micfil->quality = ucontrol->value.integer.value[0]; 155 156 return micfil_set_quality(micfil); 157 } 158 159 static const char * const micfil_hwvad_enable[] = { 160 "Disable (Record only)", 161 "Enable (Record with Vad)", 162 }; 163 164 static const char * const micfil_hwvad_init_mode[] = { 165 "Envelope mode", "Energy mode", 166 }; 167 168 static const char * const micfil_hwvad_hpf_texts[] = { 169 "Filter bypass", 170 "Cut-off @1750Hz", 171 "Cut-off @215Hz", 172 "Cut-off @102Hz", 173 }; 174 175 /* 176 * DC Remover Control 177 * Filter Bypassed 1 1 178 * Cut-off @21Hz 0 0 179 * Cut-off @83Hz 0 1 180 * Cut-off @152HZ 1 0 181 */ 182 static const char * const micfil_dc_remover_texts[] = { 183 "Cut-off @21Hz", "Cut-off @83Hz", 184 "Cut-off @152Hz", "Bypass", 185 }; 186 187 static const struct soc_enum hwvad_enable_enum = 188 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable), 189 micfil_hwvad_enable); 190 static const struct soc_enum hwvad_init_mode_enum = 191 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode), 192 micfil_hwvad_init_mode); 193 static const struct soc_enum hwvad_hpf_enum = 194 SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0, 195 ARRAY_SIZE(micfil_hwvad_hpf_texts), 196 micfil_hwvad_hpf_texts); 197 static const struct soc_enum fsl_micfil_dc_remover_enum = 198 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts), 199 micfil_dc_remover_texts); 200 201 static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol, 202 struct snd_ctl_elem_value *ucontrol) 203 { 204 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 205 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 206 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 207 unsigned int *item = ucontrol->value.enumerated.item; 208 int val = snd_soc_enum_item_to_val(e, item[0]); 209 int i = 0, ret = 0; 210 u32 reg_val = 0; 211 212 if (val < 0 || val > 3) 213 return -EINVAL; 214 215 micfil->dc_remover = val; 216 217 /* Calculate total value for all channels */ 218 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) 219 reg_val |= val << MICFIL_DC_CHX_SHIFT(i); 220 221 /* Update DC Remover mode for all channels */ 222 ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL, 223 MICFIL_DC_CTRL_CONFIG, reg_val); 224 if (ret < 0) 225 return ret; 226 227 return 0; 228 } 229 230 static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol, 231 struct snd_ctl_elem_value *ucontrol) 232 { 233 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 234 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 235 236 ucontrol->value.enumerated.item[0] = micfil->dc_remover; 237 238 return 0; 239 } 240 241 static int hwvad_put_enable(struct snd_kcontrol *kcontrol, 242 struct snd_ctl_elem_value *ucontrol) 243 { 244 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 245 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 246 unsigned int *item = ucontrol->value.enumerated.item; 247 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 248 int val = snd_soc_enum_item_to_val(e, item[0]); 249 250 micfil->vad_enabled = val; 251 252 return 0; 253 } 254 255 static int hwvad_get_enable(struct snd_kcontrol *kcontrol, 256 struct snd_ctl_elem_value *ucontrol) 257 { 258 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 259 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 260 261 ucontrol->value.enumerated.item[0] = micfil->vad_enabled; 262 263 return 0; 264 } 265 266 static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol, 267 struct snd_ctl_elem_value *ucontrol) 268 { 269 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 270 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 271 unsigned int *item = ucontrol->value.enumerated.item; 272 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 273 int val = snd_soc_enum_item_to_val(e, item[0]); 274 275 /* 0 - Envelope-based Mode 276 * 1 - Energy-based Mode 277 */ 278 micfil->vad_init_mode = val; 279 280 return 0; 281 } 282 283 static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol, 284 struct snd_ctl_elem_value *ucontrol) 285 { 286 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 287 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 288 289 ucontrol->value.enumerated.item[0] = micfil->vad_init_mode; 290 291 return 0; 292 } 293 294 static int hwvad_detected(struct snd_kcontrol *kcontrol, 295 struct snd_ctl_elem_value *ucontrol) 296 { 297 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 298 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 299 300 ucontrol->value.enumerated.item[0] = micfil->vad_detected; 301 302 return 0; 303 } 304 305 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = { 306 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL, 307 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv), 308 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL, 309 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0x7, gain_tlv), 310 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL, 311 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0x7, gain_tlv), 312 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL, 313 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0x7, gain_tlv), 314 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL, 315 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0x7, gain_tlv), 316 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL, 317 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0x7, gain_tlv), 318 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL, 319 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0x7, gain_tlv), 320 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL, 321 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv), 322 SOC_ENUM_EXT("MICFIL Quality Select", 323 fsl_micfil_quality_enum, 324 micfil_quality_get, micfil_quality_set), 325 SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum, 326 hwvad_get_enable, hwvad_put_enable), 327 SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum, 328 hwvad_get_init_mode, hwvad_put_init_mode), 329 SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum), 330 SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0), 331 SOC_SINGLE("HWVAD ZCD Auto Threshold Switch", 332 REG_MICFIL_VAD0_ZCD, 2, 1, 0), 333 SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum, 334 micfil_get_dc_remover_state, micfil_put_dc_remover_state), 335 SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0), 336 SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0), 337 SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0), 338 SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0), 339 SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0), 340 SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0), 341 SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0), 342 SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0), 343 SOC_SINGLE("HWVAD ZCD And Behavior Switch", 344 REG_MICFIL_VAD0_ZCD, 4, 1, 0), 345 SOC_SINGLE_BOOL_EXT("VAD Detected", 0, hwvad_detected, NULL), 346 }; 347 348 /* The SRES is a self-negated bit which provides the CPU with the 349 * capability to initialize the PDM Interface module through the 350 * slave-bus interface. This bit always reads as zero, and this 351 * bit is only effective when MDIS is cleared 352 */ 353 static int fsl_micfil_reset(struct device *dev) 354 { 355 struct fsl_micfil *micfil = dev_get_drvdata(dev); 356 int ret; 357 358 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 359 MICFIL_CTRL1_MDIS); 360 if (ret) 361 return ret; 362 363 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, 364 MICFIL_CTRL1_SRES); 365 if (ret) 366 return ret; 367 368 return 0; 369 } 370 371 static int fsl_micfil_startup(struct snd_pcm_substream *substream, 372 struct snd_soc_dai *dai) 373 { 374 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 375 376 if (!micfil) { 377 dev_err(dai->dev, "micfil dai priv_data not set\n"); 378 return -EINVAL; 379 } 380 381 return 0; 382 } 383 384 /* Enable/disable hwvad interrupts */ 385 static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable) 386 { 387 u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0; 388 u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0; 389 390 /* Voice Activity Detector Error Interruption */ 391 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 392 MICFIL_VAD0_CTRL1_ERIE, vaderie_reg); 393 394 /* Voice Activity Detector Interruption */ 395 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 396 MICFIL_VAD0_CTRL1_IE, vadie_reg); 397 398 return 0; 399 } 400 401 /* Configuration done only in energy-based initialization mode */ 402 static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil) 403 { 404 /* Keep the VADFRENDIS bitfield cleared. */ 405 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 406 MICFIL_VAD0_CTRL2_FRENDIS); 407 408 /* Keep the VADPREFEN bitfield cleared. */ 409 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 410 MICFIL_VAD0_CTRL2_PREFEN); 411 412 /* Keep the VADSFILEN bitfield cleared. */ 413 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 414 MICFIL_VAD0_SCONFIG_SFILEN); 415 416 /* Keep the VADSMAXEN bitfield cleared. */ 417 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 418 MICFIL_VAD0_SCONFIG_SMAXEN); 419 420 /* Keep the VADNFILAUTO bitfield asserted. */ 421 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 422 MICFIL_VAD0_NCONFIG_NFILAUT); 423 424 /* Keep the VADNMINEN bitfield cleared. */ 425 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 426 MICFIL_VAD0_NCONFIG_NMINEN); 427 428 /* Keep the VADNDECEN bitfield cleared. */ 429 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 430 MICFIL_VAD0_NCONFIG_NDECEN); 431 432 /* Keep the VADNOREN bitfield cleared. */ 433 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 434 MICFIL_VAD0_NCONFIG_NOREN); 435 436 return 0; 437 } 438 439 /* Configuration done only in envelope-based initialization mode */ 440 static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil) 441 { 442 /* Assert the VADFRENDIS bitfield */ 443 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 444 MICFIL_VAD0_CTRL2_FRENDIS); 445 446 /* Assert the VADPREFEN bitfield. */ 447 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 448 MICFIL_VAD0_CTRL2_PREFEN); 449 450 /* Assert the VADSFILEN bitfield. */ 451 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 452 MICFIL_VAD0_SCONFIG_SFILEN); 453 454 /* Assert the VADSMAXEN bitfield. */ 455 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 456 MICFIL_VAD0_SCONFIG_SMAXEN); 457 458 /* Clear the VADNFILAUTO bitfield */ 459 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 460 MICFIL_VAD0_NCONFIG_NFILAUT); 461 462 /* Assert the VADNMINEN bitfield. */ 463 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 464 MICFIL_VAD0_NCONFIG_NMINEN); 465 466 /* Assert the VADNDECEN bitfield. */ 467 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 468 MICFIL_VAD0_NCONFIG_NDECEN); 469 470 /* Assert VADNOREN bitfield. */ 471 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 472 MICFIL_VAD0_NCONFIG_NOREN); 473 474 return 0; 475 } 476 477 /* 478 * Hardware Voice Active Detection: The HWVAD takes data from the input 479 * of a selected PDM microphone to detect if there is any 480 * voice activity. When a voice activity is detected, an interrupt could 481 * be delivered to the system. Initialization in section 8.4: 482 * Can work in two modes: 483 * -> Eneveope-based mode (section 8.4.1) 484 * -> Energy-based mode (section 8.4.2) 485 * 486 * It is important to remark that the HWVAD detector could be enabled 487 * or reset only when the MICFIL isn't running i.e. when the BSY_FIL 488 * bit in STAT register is cleared 489 */ 490 static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil) 491 { 492 int ret; 493 494 micfil->vad_detected = 0; 495 496 /* envelope-based specific initialization */ 497 if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE) 498 ret = fsl_micfil_init_hwvad_envelope_mode(micfil); 499 else 500 ret = fsl_micfil_init_hwvad_energy_mode(micfil); 501 if (ret) 502 return ret; 503 504 /* Voice Activity Detector Internal Filters Initialization*/ 505 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 506 MICFIL_VAD0_CTRL1_ST10); 507 508 /* Voice Activity Detector Internal Filter */ 509 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 510 MICFIL_VAD0_CTRL1_ST10); 511 512 /* Enable Interrupts */ 513 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1); 514 if (ret) 515 return ret; 516 517 /* Voice Activity Detector Reset */ 518 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 519 MICFIL_VAD0_CTRL1_RST); 520 521 /* Voice Activity Detector Enabled */ 522 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 523 MICFIL_VAD0_CTRL1_EN); 524 525 return 0; 526 } 527 528 static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil) 529 { 530 struct device *dev = &micfil->pdev->dev; 531 int ret = 0; 532 533 /* Disable HWVAD */ 534 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 535 MICFIL_VAD0_CTRL1_EN); 536 537 /* Disable hwvad interrupts */ 538 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0); 539 if (ret) 540 dev_err(dev, "Failed to disable interrupts\n"); 541 542 return ret; 543 } 544 545 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd, 546 struct snd_soc_dai *dai) 547 { 548 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 549 struct device *dev = &micfil->pdev->dev; 550 int ret; 551 552 switch (cmd) { 553 case SNDRV_PCM_TRIGGER_START: 554 case SNDRV_PCM_TRIGGER_RESUME: 555 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 556 ret = fsl_micfil_reset(dev); 557 if (ret) { 558 dev_err(dev, "failed to soft reset\n"); 559 return ret; 560 } 561 562 /* DMA Interrupt Selection - DISEL bits 563 * 00 - DMA and IRQ disabled 564 * 01 - DMA req enabled 565 * 10 - IRQ enabled 566 * 11 - reserved 567 */ 568 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 569 MICFIL_CTRL1_DISEL, 570 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA)); 571 if (ret) 572 return ret; 573 574 /* Enable the module */ 575 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, 576 MICFIL_CTRL1_PDMIEN); 577 if (ret) 578 return ret; 579 580 if (micfil->vad_enabled) 581 fsl_micfil_hwvad_enable(micfil); 582 583 break; 584 case SNDRV_PCM_TRIGGER_STOP: 585 case SNDRV_PCM_TRIGGER_SUSPEND: 586 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 587 if (micfil->vad_enabled) 588 fsl_micfil_hwvad_disable(micfil); 589 590 /* Disable the module */ 591 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 592 MICFIL_CTRL1_PDMIEN); 593 if (ret) 594 return ret; 595 596 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 597 MICFIL_CTRL1_DISEL, 598 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE)); 599 if (ret) 600 return ret; 601 break; 602 default: 603 return -EINVAL; 604 } 605 return 0; 606 } 607 608 static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate) 609 { 610 struct device *dev = &micfil->pdev->dev; 611 u64 ratio = sample_rate; 612 struct clk *clk; 613 int ret; 614 615 /* Get root clock */ 616 clk = micfil->mclk; 617 618 /* Disable clock first, for it was enabled by pm_runtime */ 619 clk_disable_unprepare(clk); 620 fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk, 621 micfil->pll11k_clk, ratio); 622 ret = clk_prepare_enable(clk); 623 if (ret) 624 return ret; 625 626 return 0; 627 } 628 629 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream, 630 struct snd_pcm_hw_params *params, 631 struct snd_soc_dai *dai) 632 { 633 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 634 unsigned int channels = params_channels(params); 635 unsigned int rate = params_rate(params); 636 int clk_div = 8; 637 int osr = MICFIL_OSR_DEFAULT; 638 int ret; 639 640 /* 1. Disable the module */ 641 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 642 MICFIL_CTRL1_PDMIEN); 643 if (ret) 644 return ret; 645 646 /* enable channels */ 647 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 648 0xFF, ((1 << channels) - 1)); 649 if (ret) 650 return ret; 651 652 ret = fsl_micfil_reparent_rootclk(micfil, rate); 653 if (ret) 654 return ret; 655 656 ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8); 657 if (ret) 658 return ret; 659 660 ret = micfil_set_quality(micfil); 661 if (ret) 662 return ret; 663 664 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 665 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR, 666 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) | 667 FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr)); 668 669 /* Configure CIC OSR in VADCICOSR */ 670 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 671 MICFIL_VAD0_CTRL1_CICOSR, 672 FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr)); 673 674 /* Configure source channel in VADCHSEL */ 675 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 676 MICFIL_VAD0_CTRL1_CHSEL, 677 FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1))); 678 679 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg; 680 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg); 681 micfil->sdmacfg.n_fifos_src = channels; 682 micfil->sdmacfg.sw_done = true; 683 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX; 684 685 return 0; 686 } 687 688 static const struct snd_soc_dai_ops fsl_micfil_dai_ops = { 689 .startup = fsl_micfil_startup, 690 .trigger = fsl_micfil_trigger, 691 .hw_params = fsl_micfil_hw_params, 692 }; 693 694 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai) 695 { 696 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev); 697 struct device *dev = cpu_dai->dev; 698 unsigned int val = 0; 699 int ret, i; 700 701 micfil->quality = QUALITY_VLOW0; 702 micfil->card = cpu_dai->component->card; 703 704 /* set default gain to 2 */ 705 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222); 706 707 /* set DC Remover in bypass mode*/ 708 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) 709 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i); 710 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL, 711 MICFIL_DC_CTRL_CONFIG, val); 712 if (ret) { 713 dev_err(dev, "failed to set DC Remover mode bits\n"); 714 return ret; 715 } 716 micfil->dc_remover = MICFIL_DC_BYPASS; 717 718 snd_soc_dai_init_dma_data(cpu_dai, NULL, 719 &micfil->dma_params_rx); 720 721 /* FIFO Watermark Control - FIFOWMK*/ 722 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL, 723 MICFIL_FIFO_CTRL_FIFOWMK, 724 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1)); 725 if (ret) 726 return ret; 727 728 return 0; 729 } 730 731 static struct snd_soc_dai_driver fsl_micfil_dai = { 732 .probe = fsl_micfil_dai_probe, 733 .capture = { 734 .stream_name = "CPU-Capture", 735 .channels_min = 1, 736 .channels_max = 8, 737 .rates = SNDRV_PCM_RATE_8000_48000, 738 .formats = SNDRV_PCM_FMTBIT_S16_LE, 739 }, 740 .ops = &fsl_micfil_dai_ops, 741 }; 742 743 static const struct snd_soc_component_driver fsl_micfil_component = { 744 .name = "fsl-micfil-dai", 745 .controls = fsl_micfil_snd_controls, 746 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls), 747 .legacy_dai_naming = 1, 748 }; 749 750 /* REGMAP */ 751 static const struct reg_default fsl_micfil_reg_defaults[] = { 752 {REG_MICFIL_CTRL1, 0x00000000}, 753 {REG_MICFIL_CTRL2, 0x00000000}, 754 {REG_MICFIL_STAT, 0x00000000}, 755 {REG_MICFIL_FIFO_CTRL, 0x00000007}, 756 {REG_MICFIL_FIFO_STAT, 0x00000000}, 757 {REG_MICFIL_DATACH0, 0x00000000}, 758 {REG_MICFIL_DATACH1, 0x00000000}, 759 {REG_MICFIL_DATACH2, 0x00000000}, 760 {REG_MICFIL_DATACH3, 0x00000000}, 761 {REG_MICFIL_DATACH4, 0x00000000}, 762 {REG_MICFIL_DATACH5, 0x00000000}, 763 {REG_MICFIL_DATACH6, 0x00000000}, 764 {REG_MICFIL_DATACH7, 0x00000000}, 765 {REG_MICFIL_DC_CTRL, 0x00000000}, 766 {REG_MICFIL_OUT_CTRL, 0x00000000}, 767 {REG_MICFIL_OUT_STAT, 0x00000000}, 768 {REG_MICFIL_VAD0_CTRL1, 0x00000000}, 769 {REG_MICFIL_VAD0_CTRL2, 0x000A0000}, 770 {REG_MICFIL_VAD0_STAT, 0x00000000}, 771 {REG_MICFIL_VAD0_SCONFIG, 0x00000000}, 772 {REG_MICFIL_VAD0_NCONFIG, 0x80000000}, 773 {REG_MICFIL_VAD0_NDATA, 0x00000000}, 774 {REG_MICFIL_VAD0_ZCD, 0x00000004}, 775 }; 776 777 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg) 778 { 779 switch (reg) { 780 case REG_MICFIL_CTRL1: 781 case REG_MICFIL_CTRL2: 782 case REG_MICFIL_STAT: 783 case REG_MICFIL_FIFO_CTRL: 784 case REG_MICFIL_FIFO_STAT: 785 case REG_MICFIL_DATACH0: 786 case REG_MICFIL_DATACH1: 787 case REG_MICFIL_DATACH2: 788 case REG_MICFIL_DATACH3: 789 case REG_MICFIL_DATACH4: 790 case REG_MICFIL_DATACH5: 791 case REG_MICFIL_DATACH6: 792 case REG_MICFIL_DATACH7: 793 case REG_MICFIL_DC_CTRL: 794 case REG_MICFIL_OUT_CTRL: 795 case REG_MICFIL_OUT_STAT: 796 case REG_MICFIL_VAD0_CTRL1: 797 case REG_MICFIL_VAD0_CTRL2: 798 case REG_MICFIL_VAD0_STAT: 799 case REG_MICFIL_VAD0_SCONFIG: 800 case REG_MICFIL_VAD0_NCONFIG: 801 case REG_MICFIL_VAD0_NDATA: 802 case REG_MICFIL_VAD0_ZCD: 803 return true; 804 default: 805 return false; 806 } 807 } 808 809 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg) 810 { 811 switch (reg) { 812 case REG_MICFIL_CTRL1: 813 case REG_MICFIL_CTRL2: 814 case REG_MICFIL_STAT: /* Write 1 to Clear */ 815 case REG_MICFIL_FIFO_CTRL: 816 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */ 817 case REG_MICFIL_DC_CTRL: 818 case REG_MICFIL_OUT_CTRL: 819 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */ 820 case REG_MICFIL_VAD0_CTRL1: 821 case REG_MICFIL_VAD0_CTRL2: 822 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */ 823 case REG_MICFIL_VAD0_SCONFIG: 824 case REG_MICFIL_VAD0_NCONFIG: 825 case REG_MICFIL_VAD0_ZCD: 826 return true; 827 default: 828 return false; 829 } 830 } 831 832 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg) 833 { 834 switch (reg) { 835 case REG_MICFIL_STAT: 836 case REG_MICFIL_DATACH0: 837 case REG_MICFIL_DATACH1: 838 case REG_MICFIL_DATACH2: 839 case REG_MICFIL_DATACH3: 840 case REG_MICFIL_DATACH4: 841 case REG_MICFIL_DATACH5: 842 case REG_MICFIL_DATACH6: 843 case REG_MICFIL_DATACH7: 844 case REG_MICFIL_VAD0_STAT: 845 case REG_MICFIL_VAD0_NDATA: 846 return true; 847 default: 848 return false; 849 } 850 } 851 852 static const struct regmap_config fsl_micfil_regmap_config = { 853 .reg_bits = 32, 854 .reg_stride = 4, 855 .val_bits = 32, 856 857 .max_register = REG_MICFIL_VAD0_ZCD, 858 .reg_defaults = fsl_micfil_reg_defaults, 859 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults), 860 .readable_reg = fsl_micfil_readable_reg, 861 .volatile_reg = fsl_micfil_volatile_reg, 862 .writeable_reg = fsl_micfil_writeable_reg, 863 .cache_type = REGCACHE_RBTREE, 864 }; 865 866 /* END OF REGMAP */ 867 868 static irqreturn_t micfil_isr(int irq, void *devid) 869 { 870 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 871 struct platform_device *pdev = micfil->pdev; 872 u32 stat_reg; 873 u32 fifo_stat_reg; 874 u32 ctrl1_reg; 875 bool dma_enabled; 876 int i; 877 878 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); 879 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg); 880 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg); 881 882 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA; 883 884 /* Channel 0-7 Output Data Flags */ 885 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) { 886 if (stat_reg & MICFIL_STAT_CHXF(i)) 887 dev_dbg(&pdev->dev, 888 "Data available in Data Channel %d\n", i); 889 /* if DMA is not enabled, field must be written with 1 890 * to clear 891 */ 892 if (!dma_enabled) 893 regmap_write_bits(micfil->regmap, 894 REG_MICFIL_STAT, 895 MICFIL_STAT_CHXF(i), 896 1); 897 } 898 899 for (i = 0; i < MICFIL_FIFO_NUM; i++) { 900 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i)) 901 dev_dbg(&pdev->dev, 902 "FIFO Overflow Exception flag for channel %d\n", 903 i); 904 905 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i)) 906 dev_dbg(&pdev->dev, 907 "FIFO Underflow Exception flag for channel %d\n", 908 i); 909 } 910 911 return IRQ_HANDLED; 912 } 913 914 static irqreturn_t micfil_err_isr(int irq, void *devid) 915 { 916 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 917 struct platform_device *pdev = micfil->pdev; 918 u32 stat_reg; 919 920 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); 921 922 if (stat_reg & MICFIL_STAT_BSY_FIL) 923 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n"); 924 925 if (stat_reg & MICFIL_STAT_FIR_RDY) 926 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n"); 927 928 if (stat_reg & MICFIL_STAT_LOWFREQF) { 929 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n"); 930 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 931 MICFIL_STAT_LOWFREQF, 1); 932 } 933 934 return IRQ_HANDLED; 935 } 936 937 static irqreturn_t voice_detected_fn(int irq, void *devid) 938 { 939 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 940 struct snd_kcontrol *kctl; 941 942 if (!micfil->card) 943 return IRQ_HANDLED; 944 945 kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected"); 946 if (!kctl) 947 return IRQ_HANDLED; 948 949 if (micfil->vad_detected) 950 snd_ctl_notify(micfil->card->snd_card, 951 SNDRV_CTL_EVENT_MASK_VALUE, 952 &kctl->id); 953 954 return IRQ_HANDLED; 955 } 956 957 static irqreturn_t hwvad_isr(int irq, void *devid) 958 { 959 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 960 struct device *dev = &micfil->pdev->dev; 961 u32 vad0_reg; 962 int ret; 963 964 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg); 965 966 /* 967 * The only difference between MICFIL_VAD0_STAT_EF and 968 * MICFIL_VAD0_STAT_IF is that the former requires Write 969 * 1 to Clear. Since both flags are set, it is enough 970 * to only read one of them 971 */ 972 if (vad0_reg & MICFIL_VAD0_STAT_IF) { 973 /* Write 1 to clear */ 974 regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT, 975 MICFIL_VAD0_STAT_IF, 976 MICFIL_VAD0_STAT_IF); 977 978 micfil->vad_detected = 1; 979 } 980 981 ret = fsl_micfil_hwvad_disable(micfil); 982 if (ret) 983 dev_err(dev, "Failed to disable hwvad\n"); 984 985 return IRQ_WAKE_THREAD; 986 } 987 988 static irqreturn_t hwvad_err_isr(int irq, void *devid) 989 { 990 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 991 struct device *dev = &micfil->pdev->dev; 992 u32 vad0_reg; 993 994 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg); 995 996 if (vad0_reg & MICFIL_VAD0_STAT_INSATF) 997 dev_dbg(dev, "voice activity input overflow/underflow detected\n"); 998 999 return IRQ_HANDLED; 1000 } 1001 1002 static int fsl_micfil_probe(struct platform_device *pdev) 1003 { 1004 struct device_node *np = pdev->dev.of_node; 1005 struct fsl_micfil *micfil; 1006 struct resource *res; 1007 void __iomem *regs; 1008 int ret, i; 1009 1010 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL); 1011 if (!micfil) 1012 return -ENOMEM; 1013 1014 micfil->pdev = pdev; 1015 strncpy(micfil->name, np->name, sizeof(micfil->name) - 1); 1016 1017 micfil->soc = of_device_get_match_data(&pdev->dev); 1018 1019 /* ipg_clk is used to control the registers 1020 * ipg_clk_app is used to operate the filter 1021 */ 1022 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app"); 1023 if (IS_ERR(micfil->mclk)) { 1024 dev_err(&pdev->dev, "failed to get core clock: %ld\n", 1025 PTR_ERR(micfil->mclk)); 1026 return PTR_ERR(micfil->mclk); 1027 } 1028 1029 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk"); 1030 if (IS_ERR(micfil->busclk)) { 1031 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n", 1032 PTR_ERR(micfil->busclk)); 1033 return PTR_ERR(micfil->busclk); 1034 } 1035 1036 fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk, 1037 &micfil->pll11k_clk); 1038 1039 /* init regmap */ 1040 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1041 if (IS_ERR(regs)) 1042 return PTR_ERR(regs); 1043 1044 micfil->regmap = devm_regmap_init_mmio(&pdev->dev, 1045 regs, 1046 &fsl_micfil_regmap_config); 1047 if (IS_ERR(micfil->regmap)) { 1048 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n", 1049 PTR_ERR(micfil->regmap)); 1050 return PTR_ERR(micfil->regmap); 1051 } 1052 1053 /* dataline mask for RX */ 1054 ret = of_property_read_u32_index(np, 1055 "fsl,dataline", 1056 0, 1057 &micfil->dataline); 1058 if (ret) 1059 micfil->dataline = 1; 1060 1061 if (micfil->dataline & ~micfil->soc->dataline) { 1062 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n", 1063 micfil->soc->dataline); 1064 return -EINVAL; 1065 } 1066 1067 /* get IRQs */ 1068 for (i = 0; i < MICFIL_IRQ_LINES; i++) { 1069 micfil->irq[i] = platform_get_irq(pdev, i); 1070 if (micfil->irq[i] < 0) 1071 return micfil->irq[i]; 1072 } 1073 1074 /* Digital Microphone interface interrupt */ 1075 ret = devm_request_irq(&pdev->dev, micfil->irq[0], 1076 micfil_isr, IRQF_SHARED, 1077 micfil->name, micfil); 1078 if (ret) { 1079 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n", 1080 micfil->irq[0]); 1081 return ret; 1082 } 1083 1084 /* Digital Microphone interface error interrupt */ 1085 ret = devm_request_irq(&pdev->dev, micfil->irq[1], 1086 micfil_err_isr, IRQF_SHARED, 1087 micfil->name, micfil); 1088 if (ret) { 1089 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n", 1090 micfil->irq[1]); 1091 return ret; 1092 } 1093 1094 /* Digital Microphone interface voice activity detector event */ 1095 ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2], 1096 hwvad_isr, voice_detected_fn, 1097 IRQF_SHARED, micfil->name, micfil); 1098 if (ret) { 1099 dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n", 1100 micfil->irq[0]); 1101 return ret; 1102 } 1103 1104 /* Digital Microphone interface voice activity detector error */ 1105 ret = devm_request_irq(&pdev->dev, micfil->irq[3], 1106 hwvad_err_isr, IRQF_SHARED, 1107 micfil->name, micfil); 1108 if (ret) { 1109 dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n", 1110 micfil->irq[1]); 1111 return ret; 1112 } 1113 1114 micfil->dma_params_rx.chan_name = "rx"; 1115 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0; 1116 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX; 1117 1118 platform_set_drvdata(pdev, micfil); 1119 1120 pm_runtime_enable(&pdev->dev); 1121 regcache_cache_only(micfil->regmap, true); 1122 1123 /* 1124 * Register platform component before registering cpu dai for there 1125 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1126 */ 1127 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1128 if (ret) { 1129 dev_err(&pdev->dev, "failed to pcm register\n"); 1130 return ret; 1131 } 1132 1133 fsl_micfil_dai.capture.formats = micfil->soc->formats; 1134 1135 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component, 1136 &fsl_micfil_dai, 1); 1137 if (ret) { 1138 dev_err(&pdev->dev, "failed to register component %s\n", 1139 fsl_micfil_component.name); 1140 } 1141 1142 return ret; 1143 } 1144 1145 static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev) 1146 { 1147 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1148 1149 regcache_cache_only(micfil->regmap, true); 1150 1151 clk_disable_unprepare(micfil->mclk); 1152 clk_disable_unprepare(micfil->busclk); 1153 1154 return 0; 1155 } 1156 1157 static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev) 1158 { 1159 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1160 int ret; 1161 1162 ret = clk_prepare_enable(micfil->busclk); 1163 if (ret < 0) 1164 return ret; 1165 1166 ret = clk_prepare_enable(micfil->mclk); 1167 if (ret < 0) { 1168 clk_disable_unprepare(micfil->busclk); 1169 return ret; 1170 } 1171 1172 regcache_cache_only(micfil->regmap, false); 1173 regcache_mark_dirty(micfil->regmap); 1174 regcache_sync(micfil->regmap); 1175 1176 return 0; 1177 } 1178 1179 static int __maybe_unused fsl_micfil_suspend(struct device *dev) 1180 { 1181 pm_runtime_force_suspend(dev); 1182 1183 return 0; 1184 } 1185 1186 static int __maybe_unused fsl_micfil_resume(struct device *dev) 1187 { 1188 pm_runtime_force_resume(dev); 1189 1190 return 0; 1191 } 1192 1193 static const struct dev_pm_ops fsl_micfil_pm_ops = { 1194 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend, 1195 fsl_micfil_runtime_resume, 1196 NULL) 1197 SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend, 1198 fsl_micfil_resume) 1199 }; 1200 1201 static struct platform_driver fsl_micfil_driver = { 1202 .probe = fsl_micfil_probe, 1203 .driver = { 1204 .name = "fsl-micfil-dai", 1205 .pm = &fsl_micfil_pm_ops, 1206 .of_match_table = fsl_micfil_dt_ids, 1207 }, 1208 }; 1209 module_platform_driver(fsl_micfil_driver); 1210 1211 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>"); 1212 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver"); 1213 MODULE_LICENSE("GPL v2"); 1214