1 /* 2 * wm8990.c -- WM8990 ALSA Soc Audio driver 3 * 4 * Copyright 2008 Wolfson Microelectronics PLC. 5 * Author: Liam Girdwood <lrg@slimlogic.co.uk> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/platform_device.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/soc-dapm.h> 26 #include <sound/initval.h> 27 #include <sound/tlv.h> 28 #include <asm/div64.h> 29 30 #include "wm8990.h" 31 32 #define WM8990_VERSION "0.2" 33 34 /* codec private data */ 35 struct wm8990_priv { 36 unsigned int sysclk; 37 unsigned int pcmclk; 38 }; 39 40 /* 41 * wm8990 register cache. Note that register 0 is not included in the 42 * cache. 43 */ 44 static const u16 wm8990_reg[] = { 45 0x8990, /* R0 - Reset */ 46 0x0000, /* R1 - Power Management (1) */ 47 0x6000, /* R2 - Power Management (2) */ 48 0x0000, /* R3 - Power Management (3) */ 49 0x4050, /* R4 - Audio Interface (1) */ 50 0x4000, /* R5 - Audio Interface (2) */ 51 0x01C8, /* R6 - Clocking (1) */ 52 0x0000, /* R7 - Clocking (2) */ 53 0x0040, /* R8 - Audio Interface (3) */ 54 0x0040, /* R9 - Audio Interface (4) */ 55 0x0004, /* R10 - DAC CTRL */ 56 0x00C0, /* R11 - Left DAC Digital Volume */ 57 0x00C0, /* R12 - Right DAC Digital Volume */ 58 0x0000, /* R13 - Digital Side Tone */ 59 0x0100, /* R14 - ADC CTRL */ 60 0x00C0, /* R15 - Left ADC Digital Volume */ 61 0x00C0, /* R16 - Right ADC Digital Volume */ 62 0x0000, /* R17 */ 63 0x0000, /* R18 - GPIO CTRL 1 */ 64 0x1000, /* R19 - GPIO1 & GPIO2 */ 65 0x1010, /* R20 - GPIO3 & GPIO4 */ 66 0x1010, /* R21 - GPIO5 & GPIO6 */ 67 0x8000, /* R22 - GPIOCTRL 2 */ 68 0x0800, /* R23 - GPIO_POL */ 69 0x008B, /* R24 - Left Line Input 1&2 Volume */ 70 0x008B, /* R25 - Left Line Input 3&4 Volume */ 71 0x008B, /* R26 - Right Line Input 1&2 Volume */ 72 0x008B, /* R27 - Right Line Input 3&4 Volume */ 73 0x0000, /* R28 - Left Output Volume */ 74 0x0000, /* R29 - Right Output Volume */ 75 0x0066, /* R30 - Line Outputs Volume */ 76 0x0022, /* R31 - Out3/4 Volume */ 77 0x0079, /* R32 - Left OPGA Volume */ 78 0x0079, /* R33 - Right OPGA Volume */ 79 0x0003, /* R34 - Speaker Volume */ 80 0x0003, /* R35 - ClassD1 */ 81 0x0000, /* R36 */ 82 0x0100, /* R37 - ClassD3 */ 83 0x0079, /* R38 - ClassD4 */ 84 0x0000, /* R39 - Input Mixer1 */ 85 0x0000, /* R40 - Input Mixer2 */ 86 0x0000, /* R41 - Input Mixer3 */ 87 0x0000, /* R42 - Input Mixer4 */ 88 0x0000, /* R43 - Input Mixer5 */ 89 0x0000, /* R44 - Input Mixer6 */ 90 0x0000, /* R45 - Output Mixer1 */ 91 0x0000, /* R46 - Output Mixer2 */ 92 0x0000, /* R47 - Output Mixer3 */ 93 0x0000, /* R48 - Output Mixer4 */ 94 0x0000, /* R49 - Output Mixer5 */ 95 0x0000, /* R50 - Output Mixer6 */ 96 0x0180, /* R51 - Out3/4 Mixer */ 97 0x0000, /* R52 - Line Mixer1 */ 98 0x0000, /* R53 - Line Mixer2 */ 99 0x0000, /* R54 - Speaker Mixer */ 100 0x0000, /* R55 - Additional Control */ 101 0x0000, /* R56 - AntiPOP1 */ 102 0x0000, /* R57 - AntiPOP2 */ 103 0x0000, /* R58 - MICBIAS */ 104 0x0000, /* R59 */ 105 0x0008, /* R60 - PLL1 */ 106 0x0031, /* R61 - PLL2 */ 107 0x0026, /* R62 - PLL3 */ 108 0x0000, /* R63 - Driver internal */ 109 }; 110 111 /* 112 * read wm8990 register cache 113 */ 114 static inline unsigned int wm8990_read_reg_cache(struct snd_soc_codec *codec, 115 unsigned int reg) 116 { 117 u16 *cache = codec->reg_cache; 118 BUG_ON(reg > (ARRAY_SIZE(wm8990_reg)) - 1); 119 return cache[reg]; 120 } 121 122 /* 123 * write wm8990 register cache 124 */ 125 static inline void wm8990_write_reg_cache(struct snd_soc_codec *codec, 126 unsigned int reg, unsigned int value) 127 { 128 u16 *cache = codec->reg_cache; 129 130 /* Reset register and reserved registers are uncached */ 131 if (reg == 0 || reg > ARRAY_SIZE(wm8990_reg) - 1) 132 return; 133 134 cache[reg] = value; 135 } 136 137 /* 138 * write to the wm8990 register space 139 */ 140 static int wm8990_write(struct snd_soc_codec *codec, unsigned int reg, 141 unsigned int value) 142 { 143 u8 data[3]; 144 145 data[0] = reg & 0xFF; 146 data[1] = (value >> 8) & 0xFF; 147 data[2] = value & 0xFF; 148 149 wm8990_write_reg_cache(codec, reg, value); 150 151 if (codec->hw_write(codec->control_data, data, 3) == 2) 152 return 0; 153 else 154 return -EIO; 155 } 156 157 #define wm8990_reset(c) wm8990_write(c, WM8990_RESET, 0) 158 159 static const DECLARE_TLV_DB_LINEAR(rec_mix_tlv, -1500, 600); 160 161 static const DECLARE_TLV_DB_LINEAR(in_pga_tlv, -1650, 3000); 162 163 static const DECLARE_TLV_DB_LINEAR(out_mix_tlv, 0, -2100); 164 165 static const DECLARE_TLV_DB_LINEAR(out_pga_tlv, -7300, 600); 166 167 static const DECLARE_TLV_DB_LINEAR(out_omix_tlv, -600, 0); 168 169 static const DECLARE_TLV_DB_LINEAR(out_dac_tlv, -7163, 0); 170 171 static const DECLARE_TLV_DB_LINEAR(in_adc_tlv, -7163, 1763); 172 173 static const DECLARE_TLV_DB_LINEAR(out_sidetone_tlv, -3600, 0); 174 175 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 176 struct snd_ctl_elem_value *ucontrol) 177 { 178 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 179 struct soc_mixer_control *mc = 180 (struct soc_mixer_control *)kcontrol->private_value; 181 int reg = mc->reg; 182 int ret; 183 u16 val; 184 185 ret = snd_soc_put_volsw(kcontrol, ucontrol); 186 if (ret < 0) 187 return ret; 188 189 /* now hit the volume update bits (always bit 8) */ 190 val = wm8990_read_reg_cache(codec, reg); 191 return wm8990_write(codec, reg, val | 0x0100); 192 } 193 194 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ 195 tlv_array) {\ 196 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 197 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 198 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 199 .tlv.p = (tlv_array), \ 200 .info = snd_soc_info_volsw, \ 201 .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \ 202 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 203 204 205 static const char *wm8990_digital_sidetone[] = 206 {"None", "Left ADC", "Right ADC", "Reserved"}; 207 208 static const struct soc_enum wm8990_left_digital_sidetone_enum = 209 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 210 WM8990_ADC_TO_DACL_SHIFT, 211 WM8990_ADC_TO_DACL_MASK, 212 wm8990_digital_sidetone); 213 214 static const struct soc_enum wm8990_right_digital_sidetone_enum = 215 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 216 WM8990_ADC_TO_DACR_SHIFT, 217 WM8990_ADC_TO_DACR_MASK, 218 wm8990_digital_sidetone); 219 220 static const char *wm8990_adcmode[] = 221 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; 222 223 static const struct soc_enum wm8990_right_adcmode_enum = 224 SOC_ENUM_SINGLE(WM8990_ADC_CTRL, 225 WM8990_ADC_HPF_CUT_SHIFT, 226 WM8990_ADC_HPF_CUT_MASK, 227 wm8990_adcmode); 228 229 static const struct snd_kcontrol_new wm8990_snd_controls[] = { 230 /* INMIXL */ 231 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0), 232 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0), 233 /* INMIXR */ 234 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0), 235 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0), 236 237 /* LOMIX */ 238 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3, 239 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv), 240 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 241 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv), 242 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 243 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv), 244 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5, 245 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv), 246 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 247 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 248 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 249 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 250 251 /* ROMIX */ 252 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4, 253 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv), 254 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 255 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv), 256 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 257 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv), 258 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6, 259 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv), 260 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 261 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv), 262 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 263 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv), 264 265 /* LOUT */ 266 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME, 267 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv), 268 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0), 269 270 /* ROUT */ 271 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME, 272 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv), 273 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0), 274 275 /* LOPGA */ 276 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME, 277 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv), 278 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME, 279 WM8990_LOPGAZC_BIT, 1, 0), 280 281 /* ROPGA */ 282 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME, 283 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv), 284 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME, 285 WM8990_ROPGAZC_BIT, 1, 0), 286 287 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 288 WM8990_LONMUTE_BIT, 1, 0), 289 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 290 WM8990_LOPMUTE_BIT, 1, 0), 291 SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 292 WM8990_LOATTN_BIT, 1, 0), 293 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 294 WM8990_RONMUTE_BIT, 1, 0), 295 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 296 WM8990_ROPMUTE_BIT, 1, 0), 297 SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 298 WM8990_ROATTN_BIT, 1, 0), 299 300 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME, 301 WM8990_OUT3MUTE_BIT, 1, 0), 302 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME, 303 WM8990_OUT3ATTN_BIT, 1, 0), 304 305 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME, 306 WM8990_OUT4MUTE_BIT, 1, 0), 307 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME, 308 WM8990_OUT4ATTN_BIT, 1, 0), 309 310 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1, 311 WM8990_CDMODE_BIT, 1, 0), 312 313 SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME, 314 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0), 315 SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3, 316 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0), 317 SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3, 318 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0), 319 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4, 320 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv), 321 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4, 322 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0), 323 324 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", 325 WM8990_LEFT_DAC_DIGITAL_VOLUME, 326 WM8990_DACL_VOL_SHIFT, 327 WM8990_DACL_VOL_MASK, 328 0, 329 out_dac_tlv), 330 331 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", 332 WM8990_RIGHT_DAC_DIGITAL_VOLUME, 333 WM8990_DACR_VOL_SHIFT, 334 WM8990_DACR_VOL_MASK, 335 0, 336 out_dac_tlv), 337 338 SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum), 339 SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum), 340 341 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 342 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0, 343 out_sidetone_tlv), 344 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 345 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0, 346 out_sidetone_tlv), 347 348 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL, 349 WM8990_ADC_HPF_ENA_BIT, 1, 0), 350 351 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum), 352 353 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", 354 WM8990_LEFT_ADC_DIGITAL_VOLUME, 355 WM8990_ADCL_VOL_SHIFT, 356 WM8990_ADCL_VOL_MASK, 357 0, 358 in_adc_tlv), 359 360 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", 361 WM8990_RIGHT_ADC_DIGITAL_VOLUME, 362 WM8990_ADCR_VOL_SHIFT, 363 WM8990_ADCR_VOL_MASK, 364 0, 365 in_adc_tlv), 366 367 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 368 WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 369 WM8990_LIN12VOL_SHIFT, 370 WM8990_LIN12VOL_MASK, 371 0, 372 in_pga_tlv), 373 374 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 375 WM8990_LI12ZC_BIT, 1, 0), 376 377 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 378 WM8990_LI12MUTE_BIT, 1, 0), 379 380 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 381 WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 382 WM8990_LIN34VOL_SHIFT, 383 WM8990_LIN34VOL_MASK, 384 0, 385 in_pga_tlv), 386 387 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 388 WM8990_LI34ZC_BIT, 1, 0), 389 390 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 391 WM8990_LI34MUTE_BIT, 1, 0), 392 393 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 394 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 395 WM8990_RIN12VOL_SHIFT, 396 WM8990_RIN12VOL_MASK, 397 0, 398 in_pga_tlv), 399 400 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 401 WM8990_RI12ZC_BIT, 1, 0), 402 403 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 404 WM8990_RI12MUTE_BIT, 1, 0), 405 406 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 407 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 408 WM8990_RIN34VOL_SHIFT, 409 WM8990_RIN34VOL_MASK, 410 0, 411 in_pga_tlv), 412 413 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 414 WM8990_RI34ZC_BIT, 1, 0), 415 416 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 417 WM8990_RI34MUTE_BIT, 1, 0), 418 419 }; 420 421 /* add non dapm controls */ 422 static int wm8990_add_controls(struct snd_soc_codec *codec) 423 { 424 int err, i; 425 426 for (i = 0; i < ARRAY_SIZE(wm8990_snd_controls); i++) { 427 err = snd_ctl_add(codec->card, 428 snd_soc_cnew(&wm8990_snd_controls[i], codec, 429 NULL)); 430 if (err < 0) 431 return err; 432 } 433 return 0; 434 } 435 436 /* 437 * _DAPM_ Controls 438 */ 439 440 static int inmixer_event(struct snd_soc_dapm_widget *w, 441 struct snd_kcontrol *kcontrol, int event) 442 { 443 u16 reg, fakepower; 444 445 reg = wm8990_read_reg_cache(w->codec, WM8990_POWER_MANAGEMENT_2); 446 fakepower = wm8990_read_reg_cache(w->codec, WM8990_INTDRIVBITS); 447 448 if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) | 449 (1 << WM8990_AINLMUX_PWR_BIT))) { 450 reg |= WM8990_AINL_ENA; 451 } else { 452 reg &= ~WM8990_AINL_ENA; 453 } 454 455 if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) | 456 (1 << WM8990_AINRMUX_PWR_BIT))) { 457 reg |= WM8990_AINR_ENA; 458 } else { 459 reg &= ~WM8990_AINL_ENA; 460 } 461 wm8990_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg); 462 463 return 0; 464 } 465 466 static int outmixer_event(struct snd_soc_dapm_widget *w, 467 struct snd_kcontrol *kcontrol, int event) 468 { 469 u32 reg_shift = kcontrol->private_value & 0xfff; 470 int ret = 0; 471 u16 reg; 472 473 switch (reg_shift) { 474 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) : 475 reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER1); 476 if (reg & WM8990_LDLO) { 477 printk(KERN_WARNING 478 "Cannot set as Output Mixer 1 LDLO Set\n"); 479 ret = -1; 480 } 481 break; 482 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8): 483 reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER2); 484 if (reg & WM8990_RDRO) { 485 printk(KERN_WARNING 486 "Cannot set as Output Mixer 2 RDRO Set\n"); 487 ret = -1; 488 } 489 break; 490 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8): 491 reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER); 492 if (reg & WM8990_LDSPK) { 493 printk(KERN_WARNING 494 "Cannot set as Speaker Mixer LDSPK Set\n"); 495 ret = -1; 496 } 497 break; 498 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8): 499 reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER); 500 if (reg & WM8990_RDSPK) { 501 printk(KERN_WARNING 502 "Cannot set as Speaker Mixer RDSPK Set\n"); 503 ret = -1; 504 } 505 break; 506 } 507 508 return ret; 509 } 510 511 /* INMIX dB values */ 512 static const unsigned int in_mix_tlv[] = { 513 TLV_DB_RANGE_HEAD(1), 514 0, 7, TLV_DB_LINEAR_ITEM(-1200, 600), 515 }; 516 517 /* Left In PGA Connections */ 518 static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = { 519 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0), 520 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0), 521 }; 522 523 static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = { 524 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0), 525 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0), 526 }; 527 528 /* Right In PGA Connections */ 529 static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = { 530 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0), 531 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0), 532 }; 533 534 static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = { 535 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0), 536 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0), 537 }; 538 539 /* INMIXL */ 540 static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = { 541 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3, 542 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv), 543 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT, 544 7, 0, in_mix_tlv), 545 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 546 1, 0), 547 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 548 1, 0), 549 }; 550 551 /* INMIXR */ 552 static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = { 553 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4, 554 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv), 555 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT, 556 7, 0, in_mix_tlv), 557 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 558 1, 0), 559 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 560 1, 0), 561 }; 562 563 /* AINLMUX */ 564 static const char *wm8990_ainlmux[] = 565 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; 566 567 static const struct soc_enum wm8990_ainlmux_enum = 568 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT, 569 ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux); 570 571 static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls = 572 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum); 573 574 /* DIFFINL */ 575 576 /* AINRMUX */ 577 static const char *wm8990_ainrmux[] = 578 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; 579 580 static const struct soc_enum wm8990_ainrmux_enum = 581 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT, 582 ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux); 583 584 static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls = 585 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum); 586 587 /* RXVOICE */ 588 static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = { 589 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT, 590 WM8990_LR4BVOL_MASK, 0, in_mix_tlv), 591 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT, 592 WM8990_RL4BVOL_MASK, 0, in_mix_tlv), 593 }; 594 595 /* LOMIX */ 596 static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = { 597 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 598 WM8990_LRBLO_BIT, 1, 0), 599 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 600 WM8990_LLBLO_BIT, 1, 0), 601 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 602 WM8990_LRI3LO_BIT, 1, 0), 603 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 604 WM8990_LLI3LO_BIT, 1, 0), 605 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 606 WM8990_LR12LO_BIT, 1, 0), 607 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 608 WM8990_LL12LO_BIT, 1, 0), 609 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1, 610 WM8990_LDLO_BIT, 1, 0), 611 }; 612 613 /* ROMIX */ 614 static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = { 615 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 616 WM8990_RLBRO_BIT, 1, 0), 617 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 618 WM8990_RRBRO_BIT, 1, 0), 619 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 620 WM8990_RLI3RO_BIT, 1, 0), 621 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 622 WM8990_RRI3RO_BIT, 1, 0), 623 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 624 WM8990_RL12RO_BIT, 1, 0), 625 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 626 WM8990_RR12RO_BIT, 1, 0), 627 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2, 628 WM8990_RDRO_BIT, 1, 0), 629 }; 630 631 /* LONMIX */ 632 static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = { 633 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 634 WM8990_LLOPGALON_BIT, 1, 0), 635 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1, 636 WM8990_LROPGALON_BIT, 1, 0), 637 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1, 638 WM8990_LOPLON_BIT, 1, 0), 639 }; 640 641 /* LOPMIX */ 642 static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = { 643 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1, 644 WM8990_LR12LOP_BIT, 1, 0), 645 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1, 646 WM8990_LL12LOP_BIT, 1, 0), 647 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 648 WM8990_LLOPGALOP_BIT, 1, 0), 649 }; 650 651 /* RONMIX */ 652 static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = { 653 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 654 WM8990_RROPGARON_BIT, 1, 0), 655 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2, 656 WM8990_RLOPGARON_BIT, 1, 0), 657 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2, 658 WM8990_ROPRON_BIT, 1, 0), 659 }; 660 661 /* ROPMIX */ 662 static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = { 663 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2, 664 WM8990_RL12ROP_BIT, 1, 0), 665 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2, 666 WM8990_RR12ROP_BIT, 1, 0), 667 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 668 WM8990_RROPGAROP_BIT, 1, 0), 669 }; 670 671 /* OUT3MIX */ 672 static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = { 673 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 674 WM8990_LI4O3_BIT, 1, 0), 675 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER, 676 WM8990_LPGAO3_BIT, 1, 0), 677 }; 678 679 /* OUT4MIX */ 680 static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = { 681 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER, 682 WM8990_RPGAO4_BIT, 1, 0), 683 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 684 WM8990_RI4O4_BIT, 1, 0), 685 }; 686 687 /* SPKMIX */ 688 static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = { 689 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 690 WM8990_LI2SPK_BIT, 1, 0), 691 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER, 692 WM8990_LB2SPK_BIT, 1, 0), 693 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER, 694 WM8990_LOPGASPK_BIT, 1, 0), 695 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER, 696 WM8990_LDSPK_BIT, 1, 0), 697 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER, 698 WM8990_RDSPK_BIT, 1, 0), 699 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER, 700 WM8990_ROPGASPK_BIT, 1, 0), 701 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER, 702 WM8990_RL12ROP_BIT, 1, 0), 703 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 704 WM8990_RI2SPK_BIT, 1, 0), 705 }; 706 707 static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = { 708 /* Input Side */ 709 /* Input Lines */ 710 SND_SOC_DAPM_INPUT("LIN1"), 711 SND_SOC_DAPM_INPUT("LIN2"), 712 SND_SOC_DAPM_INPUT("LIN3"), 713 SND_SOC_DAPM_INPUT("LIN4/RXN"), 714 SND_SOC_DAPM_INPUT("RIN3"), 715 SND_SOC_DAPM_INPUT("RIN4/RXP"), 716 SND_SOC_DAPM_INPUT("RIN1"), 717 SND_SOC_DAPM_INPUT("RIN2"), 718 SND_SOC_DAPM_INPUT("Internal ADC Source"), 719 720 /* DACs */ 721 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2, 722 WM8990_ADCL_ENA_BIT, 0), 723 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2, 724 WM8990_ADCR_ENA_BIT, 0), 725 726 /* Input PGAs */ 727 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT, 728 0, &wm8990_dapm_lin12_pga_controls[0], 729 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)), 730 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT, 731 0, &wm8990_dapm_lin34_pga_controls[0], 732 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)), 733 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT, 734 0, &wm8990_dapm_rin12_pga_controls[0], 735 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)), 736 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT, 737 0, &wm8990_dapm_rin34_pga_controls[0], 738 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)), 739 740 /* INMIXL */ 741 SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0, 742 &wm8990_dapm_inmixl_controls[0], 743 ARRAY_SIZE(wm8990_dapm_inmixl_controls), 744 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 745 746 /* AINLMUX */ 747 SND_SOC_DAPM_MUX_E("AILNMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0, 748 &wm8990_dapm_ainlmux_controls, inmixer_event, 749 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 750 751 /* INMIXR */ 752 SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0, 753 &wm8990_dapm_inmixr_controls[0], 754 ARRAY_SIZE(wm8990_dapm_inmixr_controls), 755 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 756 757 /* AINRMUX */ 758 SND_SOC_DAPM_MUX_E("AIRNMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0, 759 &wm8990_dapm_ainrmux_controls, inmixer_event, 760 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 761 762 /* Output Side */ 763 /* DACs */ 764 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3, 765 WM8990_DACL_ENA_BIT, 0), 766 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3, 767 WM8990_DACR_ENA_BIT, 0), 768 769 /* LOMIX */ 770 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT, 771 0, &wm8990_dapm_lomix_controls[0], 772 ARRAY_SIZE(wm8990_dapm_lomix_controls), 773 outmixer_event, SND_SOC_DAPM_PRE_REG), 774 775 /* LONMIX */ 776 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0, 777 &wm8990_dapm_lonmix_controls[0], 778 ARRAY_SIZE(wm8990_dapm_lonmix_controls)), 779 780 /* LOPMIX */ 781 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0, 782 &wm8990_dapm_lopmix_controls[0], 783 ARRAY_SIZE(wm8990_dapm_lopmix_controls)), 784 785 /* OUT3MIX */ 786 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0, 787 &wm8990_dapm_out3mix_controls[0], 788 ARRAY_SIZE(wm8990_dapm_out3mix_controls)), 789 790 /* SPKMIX */ 791 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0, 792 &wm8990_dapm_spkmix_controls[0], 793 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event, 794 SND_SOC_DAPM_PRE_REG), 795 796 /* OUT4MIX */ 797 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0, 798 &wm8990_dapm_out4mix_controls[0], 799 ARRAY_SIZE(wm8990_dapm_out4mix_controls)), 800 801 /* ROPMIX */ 802 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0, 803 &wm8990_dapm_ropmix_controls[0], 804 ARRAY_SIZE(wm8990_dapm_ropmix_controls)), 805 806 /* RONMIX */ 807 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0, 808 &wm8990_dapm_ronmix_controls[0], 809 ARRAY_SIZE(wm8990_dapm_ronmix_controls)), 810 811 /* ROMIX */ 812 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT, 813 0, &wm8990_dapm_romix_controls[0], 814 ARRAY_SIZE(wm8990_dapm_romix_controls), 815 outmixer_event, SND_SOC_DAPM_PRE_REG), 816 817 /* LOUT PGA */ 818 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0, 819 NULL, 0), 820 821 /* ROUT PGA */ 822 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0, 823 NULL, 0), 824 825 /* LOPGA */ 826 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0, 827 NULL, 0), 828 829 /* ROPGA */ 830 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0, 831 NULL, 0), 832 833 /* MICBIAS */ 834 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8990_POWER_MANAGEMENT_1, 835 WM8990_MICBIAS_ENA_BIT, 0), 836 837 SND_SOC_DAPM_OUTPUT("LON"), 838 SND_SOC_DAPM_OUTPUT("LOP"), 839 SND_SOC_DAPM_OUTPUT("OUT3"), 840 SND_SOC_DAPM_OUTPUT("LOUT"), 841 SND_SOC_DAPM_OUTPUT("SPKN"), 842 SND_SOC_DAPM_OUTPUT("SPKP"), 843 SND_SOC_DAPM_OUTPUT("ROUT"), 844 SND_SOC_DAPM_OUTPUT("OUT4"), 845 SND_SOC_DAPM_OUTPUT("ROP"), 846 SND_SOC_DAPM_OUTPUT("RON"), 847 848 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 849 }; 850 851 static const struct snd_soc_dapm_route audio_map[] = { 852 /* Make DACs turn on when playing even if not mixed into any outputs */ 853 {"Internal DAC Sink", NULL, "Left DAC"}, 854 {"Internal DAC Sink", NULL, "Right DAC"}, 855 856 /* Make ADCs turn on when recording even if not mixed from any inputs */ 857 {"Left ADC", NULL, "Internal ADC Source"}, 858 {"Right ADC", NULL, "Internal ADC Source"}, 859 860 /* Input Side */ 861 /* LIN12 PGA */ 862 {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 863 {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 864 /* LIN34 PGA */ 865 {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 866 {"LIN34 PGA", "LIN4 Switch", "LIN4"}, 867 /* INMIXL */ 868 {"INMIXL", "Record Left Volume", "LOMIX"}, 869 {"INMIXL", "LIN2 Volume", "LIN2"}, 870 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, 871 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, 872 /* AILNMUX */ 873 {"AILNMUX", "INMIXL Mix", "INMIXL"}, 874 {"AILNMUX", "DIFFINL Mix", "LIN12PGA"}, 875 {"AILNMUX", "DIFFINL Mix", "LIN34PGA"}, 876 {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"}, 877 {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"}, 878 /* ADC */ 879 {"Left ADC", NULL, "AILNMUX"}, 880 881 /* RIN12 PGA */ 882 {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 883 {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 884 /* RIN34 PGA */ 885 {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 886 {"RIN34 PGA", "RIN4 Switch", "RIN4"}, 887 /* INMIXL */ 888 {"INMIXR", "Record Right Volume", "ROMIX"}, 889 {"INMIXR", "RIN2 Volume", "RIN2"}, 890 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, 891 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, 892 /* AIRNMUX */ 893 {"AIRNMUX", "INMIXR Mix", "INMIXR"}, 894 {"AIRNMUX", "DIFFINR Mix", "RIN12PGA"}, 895 {"AIRNMUX", "DIFFINR Mix", "RIN34PGA"}, 896 {"AIRNMUX", "RXVOICE Mix", "RIN4/RXN"}, 897 {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"}, 898 /* ADC */ 899 {"Right ADC", NULL, "AIRNMUX"}, 900 901 /* LOMIX */ 902 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, 903 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, 904 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 905 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 906 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"}, 907 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"}, 908 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, 909 910 /* ROMIX */ 911 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, 912 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, 913 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 914 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 915 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"}, 916 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"}, 917 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, 918 919 /* SPKMIX */ 920 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, 921 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, 922 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"}, 923 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"}, 924 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, 925 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, 926 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, 927 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"}, 928 929 /* LONMIX */ 930 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, 931 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, 932 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, 933 934 /* LOPMIX */ 935 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 936 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 937 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, 938 939 /* OUT3MIX */ 940 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXP"}, 941 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, 942 943 /* OUT4MIX */ 944 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, 945 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"}, 946 947 /* RONMIX */ 948 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, 949 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, 950 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, 951 952 /* ROPMIX */ 953 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 954 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 955 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, 956 957 /* Out Mixer PGAs */ 958 {"LOPGA", NULL, "LOMIX"}, 959 {"ROPGA", NULL, "ROMIX"}, 960 961 {"LOUT PGA", NULL, "LOMIX"}, 962 {"ROUT PGA", NULL, "ROMIX"}, 963 964 /* Output Pins */ 965 {"LON", NULL, "LONMIX"}, 966 {"LOP", NULL, "LOPMIX"}, 967 {"OUT", NULL, "OUT3MIX"}, 968 {"LOUT", NULL, "LOUT PGA"}, 969 {"SPKN", NULL, "SPKMIX"}, 970 {"ROUT", NULL, "ROUT PGA"}, 971 {"OUT4", NULL, "OUT4MIX"}, 972 {"ROP", NULL, "ROPMIX"}, 973 {"RON", NULL, "RONMIX"}, 974 }; 975 976 static int wm8990_add_widgets(struct snd_soc_codec *codec) 977 { 978 snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets, 979 ARRAY_SIZE(wm8990_dapm_widgets)); 980 981 /* set up the WM8990 audio map */ 982 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 983 984 snd_soc_dapm_new_widgets(codec); 985 return 0; 986 } 987 988 /* PLL divisors */ 989 struct _pll_div { 990 u32 div2; 991 u32 n; 992 u32 k; 993 }; 994 995 /* The size in bits of the pll divide multiplied by 10 996 * to allow rounding later */ 997 #define FIXED_PLL_SIZE ((1 << 16) * 10) 998 999 static void pll_factors(struct _pll_div *pll_div, unsigned int target, 1000 unsigned int source) 1001 { 1002 u64 Kpart; 1003 unsigned int K, Ndiv, Nmod; 1004 1005 1006 Ndiv = target / source; 1007 if (Ndiv < 6) { 1008 source >>= 1; 1009 pll_div->div2 = 1; 1010 Ndiv = target / source; 1011 } else 1012 pll_div->div2 = 0; 1013 1014 if ((Ndiv < 6) || (Ndiv > 12)) 1015 printk(KERN_WARNING 1016 "WM8990 N value outwith recommended range! N = %d\n", Ndiv); 1017 1018 pll_div->n = Ndiv; 1019 Nmod = target % source; 1020 Kpart = FIXED_PLL_SIZE * (long long)Nmod; 1021 1022 do_div(Kpart, source); 1023 1024 K = Kpart & 0xFFFFFFFF; 1025 1026 /* Check if we need to round */ 1027 if ((K % 10) >= 5) 1028 K += 5; 1029 1030 /* Move down to proper range now rounding is done */ 1031 K /= 10; 1032 1033 pll_div->k = K; 1034 } 1035 1036 static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, 1037 int pll_id, unsigned int freq_in, unsigned int freq_out) 1038 { 1039 u16 reg; 1040 struct snd_soc_codec *codec = codec_dai->codec; 1041 struct _pll_div pll_div; 1042 1043 if (freq_in && freq_out) { 1044 pll_factors(&pll_div, freq_out * 4, freq_in); 1045 1046 /* Turn on PLL */ 1047 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 1048 reg |= WM8990_PLL_ENA; 1049 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 1050 1051 /* sysclk comes from PLL */ 1052 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2); 1053 wm8990_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC); 1054 1055 /* set up N , fractional mode and pre-divisor if neccessary */ 1056 wm8990_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM | 1057 (pll_div.div2?WM8990_PRESCALE:0)); 1058 wm8990_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8)); 1059 wm8990_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF)); 1060 } else { 1061 /* Turn on PLL */ 1062 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 1063 reg &= ~WM8990_PLL_ENA; 1064 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 1065 } 1066 return 0; 1067 } 1068 1069 /* 1070 * Clock after PLL and dividers 1071 */ 1072 static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1073 int clk_id, unsigned int freq, int dir) 1074 { 1075 struct snd_soc_codec *codec = codec_dai->codec; 1076 struct wm8990_priv *wm8990 = codec->private_data; 1077 1078 wm8990->sysclk = freq; 1079 return 0; 1080 } 1081 1082 /* 1083 * Set's ADC and Voice DAC format. 1084 */ 1085 static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai, 1086 unsigned int fmt) 1087 { 1088 struct snd_soc_codec *codec = codec_dai->codec; 1089 u16 audio1, audio3; 1090 1091 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1); 1092 audio3 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_3); 1093 1094 /* set master/slave audio interface */ 1095 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1096 case SND_SOC_DAIFMT_CBS_CFS: 1097 audio3 &= ~WM8990_AIF_MSTR1; 1098 break; 1099 case SND_SOC_DAIFMT_CBM_CFM: 1100 audio3 |= WM8990_AIF_MSTR1; 1101 break; 1102 default: 1103 return -EINVAL; 1104 } 1105 1106 audio1 &= ~WM8990_AIF_FMT_MASK; 1107 1108 /* interface format */ 1109 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1110 case SND_SOC_DAIFMT_I2S: 1111 audio1 |= WM8990_AIF_TMF_I2S; 1112 audio1 &= ~WM8990_AIF_LRCLK_INV; 1113 break; 1114 case SND_SOC_DAIFMT_RIGHT_J: 1115 audio1 |= WM8990_AIF_TMF_RIGHTJ; 1116 audio1 &= ~WM8990_AIF_LRCLK_INV; 1117 break; 1118 case SND_SOC_DAIFMT_LEFT_J: 1119 audio1 |= WM8990_AIF_TMF_LEFTJ; 1120 audio1 &= ~WM8990_AIF_LRCLK_INV; 1121 break; 1122 case SND_SOC_DAIFMT_DSP_A: 1123 audio1 |= WM8990_AIF_TMF_DSP; 1124 audio1 &= ~WM8990_AIF_LRCLK_INV; 1125 break; 1126 case SND_SOC_DAIFMT_DSP_B: 1127 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV; 1128 break; 1129 default: 1130 return -EINVAL; 1131 } 1132 1133 wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1134 wm8990_write(codec, WM8990_AUDIO_INTERFACE_3, audio3); 1135 return 0; 1136 } 1137 1138 static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 1139 int div_id, int div) 1140 { 1141 struct snd_soc_codec *codec = codec_dai->codec; 1142 u16 reg; 1143 1144 switch (div_id) { 1145 case WM8990_MCLK_DIV: 1146 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1147 ~WM8990_MCLK_DIV_MASK; 1148 wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1149 break; 1150 case WM8990_DACCLK_DIV: 1151 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1152 ~WM8990_DAC_CLKDIV_MASK; 1153 wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1154 break; 1155 case WM8990_ADCCLK_DIV: 1156 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1157 ~WM8990_ADC_CLKDIV_MASK; 1158 wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1159 break; 1160 case WM8990_BCLK_DIV: 1161 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_1) & 1162 ~WM8990_BCLK_DIV_MASK; 1163 wm8990_write(codec, WM8990_CLOCKING_1, reg | div); 1164 break; 1165 default: 1166 return -EINVAL; 1167 } 1168 1169 return 0; 1170 } 1171 1172 /* 1173 * Set PCM DAI bit size and sample rate. 1174 */ 1175 static int wm8990_hw_params(struct snd_pcm_substream *substream, 1176 struct snd_pcm_hw_params *params, 1177 struct snd_soc_dai *dai) 1178 { 1179 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1180 struct snd_soc_device *socdev = rtd->socdev; 1181 struct snd_soc_codec *codec = socdev->codec; 1182 u16 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1); 1183 1184 audio1 &= ~WM8990_AIF_WL_MASK; 1185 /* bit size */ 1186 switch (params_format(params)) { 1187 case SNDRV_PCM_FORMAT_S16_LE: 1188 break; 1189 case SNDRV_PCM_FORMAT_S20_3LE: 1190 audio1 |= WM8990_AIF_WL_20BITS; 1191 break; 1192 case SNDRV_PCM_FORMAT_S24_LE: 1193 audio1 |= WM8990_AIF_WL_24BITS; 1194 break; 1195 case SNDRV_PCM_FORMAT_S32_LE: 1196 audio1 |= WM8990_AIF_WL_32BITS; 1197 break; 1198 } 1199 1200 wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1201 return 0; 1202 } 1203 1204 static int wm8990_mute(struct snd_soc_dai *dai, int mute) 1205 { 1206 struct snd_soc_codec *codec = dai->codec; 1207 u16 val; 1208 1209 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE; 1210 1211 if (mute) 1212 wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1213 else 1214 wm8990_write(codec, WM8990_DAC_CTRL, val); 1215 1216 return 0; 1217 } 1218 1219 static int wm8990_set_bias_level(struct snd_soc_codec *codec, 1220 enum snd_soc_bias_level level) 1221 { 1222 u16 val; 1223 1224 switch (level) { 1225 case SND_SOC_BIAS_ON: 1226 break; 1227 1228 case SND_SOC_BIAS_PREPARE: 1229 /* VMID=2*50k */ 1230 val = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_1) & 1231 ~WM8990_VMID_MODE_MASK; 1232 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x2); 1233 break; 1234 1235 case SND_SOC_BIAS_STANDBY: 1236 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1237 /* Enable all output discharge bits */ 1238 wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1239 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1240 WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1241 WM8990_DIS_ROUT); 1242 1243 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 1244 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1245 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1246 WM8990_VMIDTOG); 1247 1248 /* Delay to allow output caps to discharge */ 1249 msleep(msecs_to_jiffies(300)); 1250 1251 /* Disable VMIDTOG */ 1252 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1253 WM8990_BUFDCOPEN | WM8990_POBCTRL); 1254 1255 /* disable all output discharge bits */ 1256 wm8990_write(codec, WM8990_ANTIPOP1, 0); 1257 1258 /* Enable outputs */ 1259 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00); 1260 1261 msleep(msecs_to_jiffies(50)); 1262 1263 /* Enable VMID at 2x50k */ 1264 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02); 1265 1266 msleep(msecs_to_jiffies(100)); 1267 1268 /* Enable VREF */ 1269 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1270 1271 msleep(msecs_to_jiffies(600)); 1272 1273 /* Enable BUFIOEN */ 1274 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1275 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1276 WM8990_BUFIOEN); 1277 1278 /* Disable outputs */ 1279 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3); 1280 1281 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1282 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN); 1283 1284 /* Enable workaround for ADC clocking issue. */ 1285 wm8990_write(codec, WM8990_EXT_ACCESS_ENA, 0x2); 1286 wm8990_write(codec, WM8990_EXT_CTL1, 0xa003); 1287 wm8990_write(codec, WM8990_EXT_ACCESS_ENA, 0); 1288 } 1289 1290 /* VMID=2*250k */ 1291 val = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_1) & 1292 ~WM8990_VMID_MODE_MASK; 1293 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x4); 1294 break; 1295 1296 case SND_SOC_BIAS_OFF: 1297 /* Enable POBCTRL and SOFT_ST */ 1298 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1299 WM8990_POBCTRL | WM8990_BUFIOEN); 1300 1301 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 1302 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1303 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1304 WM8990_BUFIOEN); 1305 1306 /* mute DAC */ 1307 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL); 1308 wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1309 1310 /* Enable any disabled outputs */ 1311 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1312 1313 /* Disable VMID */ 1314 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01); 1315 1316 msleep(msecs_to_jiffies(300)); 1317 1318 /* Enable all output discharge bits */ 1319 wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1320 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1321 WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1322 WM8990_DIS_ROUT); 1323 1324 /* Disable VREF */ 1325 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0); 1326 1327 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1328 wm8990_write(codec, WM8990_ANTIPOP2, 0x0); 1329 break; 1330 } 1331 1332 codec->bias_level = level; 1333 return 0; 1334 } 1335 1336 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 1337 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ 1338 SNDRV_PCM_RATE_48000) 1339 1340 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1341 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1342 1343 /* 1344 * The WM8990 supports 2 different and mutually exclusive DAI 1345 * configurations. 1346 * 1347 * 1. ADC/DAC on Primary Interface 1348 * 2. ADC on Primary Interface/DAC on secondary 1349 */ 1350 struct snd_soc_dai wm8990_dai = { 1351 /* ADC/DAC on primary */ 1352 .name = "WM8990 ADC/DAC Primary", 1353 .id = 1, 1354 .playback = { 1355 .stream_name = "Playback", 1356 .channels_min = 1, 1357 .channels_max = 2, 1358 .rates = WM8990_RATES, 1359 .formats = WM8990_FORMATS,}, 1360 .capture = { 1361 .stream_name = "Capture", 1362 .channels_min = 1, 1363 .channels_max = 2, 1364 .rates = WM8990_RATES, 1365 .formats = WM8990_FORMATS,}, 1366 .ops = { 1367 .hw_params = wm8990_hw_params, 1368 .digital_mute = wm8990_mute, 1369 .set_fmt = wm8990_set_dai_fmt, 1370 .set_clkdiv = wm8990_set_dai_clkdiv, 1371 .set_pll = wm8990_set_dai_pll, 1372 .set_sysclk = wm8990_set_dai_sysclk, 1373 }, 1374 }; 1375 EXPORT_SYMBOL_GPL(wm8990_dai); 1376 1377 static int wm8990_suspend(struct platform_device *pdev, pm_message_t state) 1378 { 1379 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1380 struct snd_soc_codec *codec = socdev->codec; 1381 1382 /* we only need to suspend if we are a valid card */ 1383 if (!codec->card) 1384 return 0; 1385 1386 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1387 return 0; 1388 } 1389 1390 static int wm8990_resume(struct platform_device *pdev) 1391 { 1392 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1393 struct snd_soc_codec *codec = socdev->codec; 1394 int i; 1395 u8 data[2]; 1396 u16 *cache = codec->reg_cache; 1397 1398 /* we only need to resume if we are a valid card */ 1399 if (!codec->card) 1400 return 0; 1401 1402 /* Sync reg_cache with the hardware */ 1403 for (i = 0; i < ARRAY_SIZE(wm8990_reg); i++) { 1404 if (i + 1 == WM8990_RESET) 1405 continue; 1406 data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001); 1407 data[1] = cache[i] & 0x00ff; 1408 codec->hw_write(codec->control_data, data, 2); 1409 } 1410 1411 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1412 return 0; 1413 } 1414 1415 /* 1416 * initialise the WM8990 driver 1417 * register the mixer and dsp interfaces with the kernel 1418 */ 1419 static int wm8990_init(struct snd_soc_device *socdev) 1420 { 1421 struct snd_soc_codec *codec = socdev->codec; 1422 u16 reg; 1423 int ret = 0; 1424 1425 codec->name = "WM8990"; 1426 codec->owner = THIS_MODULE; 1427 codec->read = wm8990_read_reg_cache; 1428 codec->write = wm8990_write; 1429 codec->set_bias_level = wm8990_set_bias_level; 1430 codec->dai = &wm8990_dai; 1431 codec->num_dai = 2; 1432 codec->reg_cache_size = ARRAY_SIZE(wm8990_reg); 1433 codec->reg_cache = kmemdup(wm8990_reg, sizeof(wm8990_reg), GFP_KERNEL); 1434 1435 if (codec->reg_cache == NULL) 1436 return -ENOMEM; 1437 1438 wm8990_reset(codec); 1439 1440 /* register pcms */ 1441 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 1442 if (ret < 0) { 1443 printk(KERN_ERR "wm8990: failed to create pcms\n"); 1444 goto pcm_err; 1445 } 1446 1447 /* charge output caps */ 1448 codec->bias_level = SND_SOC_BIAS_OFF; 1449 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1450 1451 reg = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_4); 1452 wm8990_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1); 1453 1454 reg = wm8990_read_reg_cache(codec, WM8990_GPIO1_GPIO2) & 1455 ~WM8990_GPIO1_SEL_MASK; 1456 wm8990_write(codec, WM8990_GPIO1_GPIO2, reg | 1); 1457 1458 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 1459 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA); 1460 1461 wm8990_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1462 wm8990_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1463 1464 wm8990_add_controls(codec); 1465 wm8990_add_widgets(codec); 1466 ret = snd_soc_init_card(socdev); 1467 if (ret < 0) { 1468 printk(KERN_ERR "wm8990: failed to register card\n"); 1469 goto card_err; 1470 } 1471 return ret; 1472 1473 card_err: 1474 snd_soc_free_pcms(socdev); 1475 snd_soc_dapm_free(socdev); 1476 pcm_err: 1477 kfree(codec->reg_cache); 1478 return ret; 1479 } 1480 1481 /* If the i2c layer weren't so broken, we could pass this kind of data 1482 around */ 1483 static struct snd_soc_device *wm8990_socdev; 1484 1485 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1486 1487 /* 1488 * WM891 2 wire address is determined by GPIO5 1489 * state during powerup. 1490 * low = 0x34 1491 * high = 0x36 1492 */ 1493 1494 static int wm8990_i2c_probe(struct i2c_client *i2c, 1495 const struct i2c_device_id *id) 1496 { 1497 struct snd_soc_device *socdev = wm8990_socdev; 1498 struct snd_soc_codec *codec = socdev->codec; 1499 int ret; 1500 1501 i2c_set_clientdata(i2c, codec); 1502 codec->control_data = i2c; 1503 1504 ret = wm8990_init(socdev); 1505 if (ret < 0) 1506 pr_err("failed to initialise WM8990\n"); 1507 1508 return ret; 1509 } 1510 1511 static int wm8990_i2c_remove(struct i2c_client *client) 1512 { 1513 struct snd_soc_codec *codec = i2c_get_clientdata(client); 1514 kfree(codec->reg_cache); 1515 return 0; 1516 } 1517 1518 static const struct i2c_device_id wm8990_i2c_id[] = { 1519 { "wm8990", 0 }, 1520 { } 1521 }; 1522 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id); 1523 1524 static struct i2c_driver wm8990_i2c_driver = { 1525 .driver = { 1526 .name = "WM8990 I2C Codec", 1527 .owner = THIS_MODULE, 1528 }, 1529 .probe = wm8990_i2c_probe, 1530 .remove = wm8990_i2c_remove, 1531 .id_table = wm8990_i2c_id, 1532 }; 1533 1534 static int wm8990_add_i2c_device(struct platform_device *pdev, 1535 const struct wm8990_setup_data *setup) 1536 { 1537 struct i2c_board_info info; 1538 struct i2c_adapter *adapter; 1539 struct i2c_client *client; 1540 int ret; 1541 1542 ret = i2c_add_driver(&wm8990_i2c_driver); 1543 if (ret != 0) { 1544 dev_err(&pdev->dev, "can't add i2c driver\n"); 1545 return ret; 1546 } 1547 1548 memset(&info, 0, sizeof(struct i2c_board_info)); 1549 info.addr = setup->i2c_address; 1550 strlcpy(info.type, "wm8990", I2C_NAME_SIZE); 1551 1552 adapter = i2c_get_adapter(setup->i2c_bus); 1553 if (!adapter) { 1554 dev_err(&pdev->dev, "can't get i2c adapter %d\n", 1555 setup->i2c_bus); 1556 goto err_driver; 1557 } 1558 1559 client = i2c_new_device(adapter, &info); 1560 i2c_put_adapter(adapter); 1561 if (!client) { 1562 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n", 1563 (unsigned int)info.addr); 1564 goto err_driver; 1565 } 1566 1567 return 0; 1568 1569 err_driver: 1570 i2c_del_driver(&wm8990_i2c_driver); 1571 return -ENODEV; 1572 } 1573 #endif 1574 1575 static int wm8990_probe(struct platform_device *pdev) 1576 { 1577 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1578 struct wm8990_setup_data *setup; 1579 struct snd_soc_codec *codec; 1580 struct wm8990_priv *wm8990; 1581 int ret; 1582 1583 pr_info("WM8990 Audio Codec %s\n", WM8990_VERSION); 1584 1585 setup = socdev->codec_data; 1586 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); 1587 if (codec == NULL) 1588 return -ENOMEM; 1589 1590 wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL); 1591 if (wm8990 == NULL) { 1592 kfree(codec); 1593 return -ENOMEM; 1594 } 1595 1596 codec->private_data = wm8990; 1597 socdev->codec = codec; 1598 mutex_init(&codec->mutex); 1599 INIT_LIST_HEAD(&codec->dapm_widgets); 1600 INIT_LIST_HEAD(&codec->dapm_paths); 1601 wm8990_socdev = socdev; 1602 1603 ret = -ENODEV; 1604 1605 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1606 if (setup->i2c_address) { 1607 codec->hw_write = (hw_write_t)i2c_master_send; 1608 ret = wm8990_add_i2c_device(pdev, setup); 1609 } 1610 #endif 1611 1612 if (ret != 0) { 1613 kfree(codec->private_data); 1614 kfree(codec); 1615 } 1616 return ret; 1617 } 1618 1619 /* power down chip */ 1620 static int wm8990_remove(struct platform_device *pdev) 1621 { 1622 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1623 struct snd_soc_codec *codec = socdev->codec; 1624 1625 if (codec->control_data) 1626 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1627 snd_soc_free_pcms(socdev); 1628 snd_soc_dapm_free(socdev); 1629 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1630 i2c_unregister_device(codec->control_data); 1631 i2c_del_driver(&wm8990_i2c_driver); 1632 #endif 1633 kfree(codec->private_data); 1634 kfree(codec); 1635 1636 return 0; 1637 } 1638 1639 struct snd_soc_codec_device soc_codec_dev_wm8990 = { 1640 .probe = wm8990_probe, 1641 .remove = wm8990_remove, 1642 .suspend = wm8990_suspend, 1643 .resume = wm8990_resume, 1644 }; 1645 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8990); 1646 1647 static int __init wm8990_modinit(void) 1648 { 1649 return snd_soc_register_dai(&wm8990_dai); 1650 } 1651 module_init(wm8990_modinit); 1652 1653 static void __exit wm8990_exit(void) 1654 { 1655 snd_soc_unregister_dai(&wm8990_dai); 1656 } 1657 module_exit(wm8990_exit); 1658 1659 MODULE_DESCRIPTION("ASoC WM8990 driver"); 1660 MODULE_AUTHOR("Liam Girdwood"); 1661 MODULE_LICENSE("GPL"); 1662