1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 274dc55edSMark Brown /* 374dc55edSMark Brown * wm8961.h -- WM8961 Soc Audio driver 474dc55edSMark Brown */ 574dc55edSMark Brown 674dc55edSMark Brown #ifndef _WM8961_H 774dc55edSMark Brown #define _WM8961_H 874dc55edSMark Brown 974dc55edSMark Brown #include <sound/soc.h> 1074dc55edSMark Brown 1174dc55edSMark Brown #define WM8961_BCLK 1 1274dc55edSMark Brown #define WM8961_LRCLK 2 1374dc55edSMark Brown 1474dc55edSMark Brown #define WM8961_BCLK_DIV_1 0 1574dc55edSMark Brown #define WM8961_BCLK_DIV_1_5 1 1674dc55edSMark Brown #define WM8961_BCLK_DIV_2 2 1774dc55edSMark Brown #define WM8961_BCLK_DIV_3 3 1874dc55edSMark Brown #define WM8961_BCLK_DIV_4 4 1974dc55edSMark Brown #define WM8961_BCLK_DIV_5_5 5 2074dc55edSMark Brown #define WM8961_BCLK_DIV_6 6 2174dc55edSMark Brown #define WM8961_BCLK_DIV_8 7 2274dc55edSMark Brown #define WM8961_BCLK_DIV_11 8 2374dc55edSMark Brown #define WM8961_BCLK_DIV_12 9 2474dc55edSMark Brown #define WM8961_BCLK_DIV_16 10 2574dc55edSMark Brown #define WM8961_BCLK_DIV_24 11 2674dc55edSMark Brown #define WM8961_BCLK_DIV_32 13 2774dc55edSMark Brown 2874dc55edSMark Brown 2974dc55edSMark Brown /* 3074dc55edSMark Brown * Register values. 3174dc55edSMark Brown */ 3274dc55edSMark Brown #define WM8961_LEFT_INPUT_VOLUME 0x00 3374dc55edSMark Brown #define WM8961_RIGHT_INPUT_VOLUME 0x01 3474dc55edSMark Brown #define WM8961_LOUT1_VOLUME 0x02 3574dc55edSMark Brown #define WM8961_ROUT1_VOLUME 0x03 3674dc55edSMark Brown #define WM8961_CLOCKING1 0x04 3774dc55edSMark Brown #define WM8961_ADC_DAC_CONTROL_1 0x05 3874dc55edSMark Brown #define WM8961_ADC_DAC_CONTROL_2 0x06 3974dc55edSMark Brown #define WM8961_AUDIO_INTERFACE_0 0x07 4074dc55edSMark Brown #define WM8961_CLOCKING2 0x08 4174dc55edSMark Brown #define WM8961_AUDIO_INTERFACE_1 0x09 4274dc55edSMark Brown #define WM8961_LEFT_DAC_VOLUME 0x0A 4374dc55edSMark Brown #define WM8961_RIGHT_DAC_VOLUME 0x0B 4474dc55edSMark Brown #define WM8961_AUDIO_INTERFACE_2 0x0E 4574dc55edSMark Brown #define WM8961_SOFTWARE_RESET 0x0F 4674dc55edSMark Brown #define WM8961_ALC1 0x11 4774dc55edSMark Brown #define WM8961_ALC2 0x12 4874dc55edSMark Brown #define WM8961_ALC3 0x13 4974dc55edSMark Brown #define WM8961_NOISE_GATE 0x14 5074dc55edSMark Brown #define WM8961_LEFT_ADC_VOLUME 0x15 5174dc55edSMark Brown #define WM8961_RIGHT_ADC_VOLUME 0x16 5274dc55edSMark Brown #define WM8961_ADDITIONAL_CONTROL_1 0x17 5374dc55edSMark Brown #define WM8961_ADDITIONAL_CONTROL_2 0x18 5474dc55edSMark Brown #define WM8961_PWR_MGMT_1 0x19 5574dc55edSMark Brown #define WM8961_PWR_MGMT_2 0x1A 5674dc55edSMark Brown #define WM8961_ADDITIONAL_CONTROL_3 0x1B 5774dc55edSMark Brown #define WM8961_ANTI_POP 0x1C 5874dc55edSMark Brown #define WM8961_CLOCKING_3 0x1E 5974dc55edSMark Brown #define WM8961_ADCL_SIGNAL_PATH 0x20 6074dc55edSMark Brown #define WM8961_ADCR_SIGNAL_PATH 0x21 6174dc55edSMark Brown #define WM8961_LOUT2_VOLUME 0x28 6274dc55edSMark Brown #define WM8961_ROUT2_VOLUME 0x29 6374dc55edSMark Brown #define WM8961_PWR_MGMT_3 0x2F 6474dc55edSMark Brown #define WM8961_ADDITIONAL_CONTROL_4 0x30 6574dc55edSMark Brown #define WM8961_CLASS_D_CONTROL_1 0x31 6674dc55edSMark Brown #define WM8961_CLASS_D_CONTROL_2 0x33 6774dc55edSMark Brown #define WM8961_CLOCKING_4 0x38 6874dc55edSMark Brown #define WM8961_DSP_SIDETONE_0 0x39 6974dc55edSMark Brown #define WM8961_DSP_SIDETONE_1 0x3A 7074dc55edSMark Brown #define WM8961_DC_SERVO_0 0x3C 7174dc55edSMark Brown #define WM8961_DC_SERVO_1 0x3D 7274dc55edSMark Brown #define WM8961_DC_SERVO_3 0x3F 7374dc55edSMark Brown #define WM8961_DC_SERVO_5 0x41 7474dc55edSMark Brown #define WM8961_ANALOGUE_PGA_BIAS 0x44 7574dc55edSMark Brown #define WM8961_ANALOGUE_HP_0 0x45 7674dc55edSMark Brown #define WM8961_ANALOGUE_HP_2 0x47 7774dc55edSMark Brown #define WM8961_CHARGE_PUMP_1 0x48 7874dc55edSMark Brown #define WM8961_CHARGE_PUMP_B 0x52 7974dc55edSMark Brown #define WM8961_WRITE_SEQUENCER_1 0x57 8074dc55edSMark Brown #define WM8961_WRITE_SEQUENCER_2 0x58 8174dc55edSMark Brown #define WM8961_WRITE_SEQUENCER_3 0x59 8274dc55edSMark Brown #define WM8961_WRITE_SEQUENCER_4 0x5A 8374dc55edSMark Brown #define WM8961_WRITE_SEQUENCER_5 0x5B 8474dc55edSMark Brown #define WM8961_WRITE_SEQUENCER_6 0x5C 8574dc55edSMark Brown #define WM8961_WRITE_SEQUENCER_7 0x5D 8674dc55edSMark Brown #define WM8961_GENERAL_TEST_1 0xFC 8774dc55edSMark Brown 8874dc55edSMark Brown 8974dc55edSMark Brown /* 9074dc55edSMark Brown * Field Definitions. 9174dc55edSMark Brown */ 9274dc55edSMark Brown 9374dc55edSMark Brown /* 9474dc55edSMark Brown * R0 (0x00) - Left Input volume 9574dc55edSMark Brown */ 9674dc55edSMark Brown #define WM8961_IPVU 0x0100 /* IPVU */ 9774dc55edSMark Brown #define WM8961_IPVU_MASK 0x0100 /* IPVU */ 9874dc55edSMark Brown #define WM8961_IPVU_SHIFT 8 /* IPVU */ 9974dc55edSMark Brown #define WM8961_IPVU_WIDTH 1 /* IPVU */ 10074dc55edSMark Brown #define WM8961_LINMUTE 0x0080 /* LINMUTE */ 10174dc55edSMark Brown #define WM8961_LINMUTE_MASK 0x0080 /* LINMUTE */ 10274dc55edSMark Brown #define WM8961_LINMUTE_SHIFT 7 /* LINMUTE */ 10374dc55edSMark Brown #define WM8961_LINMUTE_WIDTH 1 /* LINMUTE */ 10474dc55edSMark Brown #define WM8961_LIZC 0x0040 /* LIZC */ 10574dc55edSMark Brown #define WM8961_LIZC_MASK 0x0040 /* LIZC */ 10674dc55edSMark Brown #define WM8961_LIZC_SHIFT 6 /* LIZC */ 10774dc55edSMark Brown #define WM8961_LIZC_WIDTH 1 /* LIZC */ 10874dc55edSMark Brown #define WM8961_LINVOL_MASK 0x003F /* LINVOL - [5:0] */ 10974dc55edSMark Brown #define WM8961_LINVOL_SHIFT 0 /* LINVOL - [5:0] */ 11074dc55edSMark Brown #define WM8961_LINVOL_WIDTH 6 /* LINVOL - [5:0] */ 11174dc55edSMark Brown 11274dc55edSMark Brown /* 11374dc55edSMark Brown * R1 (0x01) - Right Input volume 11474dc55edSMark Brown */ 11574dc55edSMark Brown #define WM8961_DEVICE_ID_MASK 0xF000 /* DEVICE_ID - [15:12] */ 11674dc55edSMark Brown #define WM8961_DEVICE_ID_SHIFT 12 /* DEVICE_ID - [15:12] */ 11774dc55edSMark Brown #define WM8961_DEVICE_ID_WIDTH 4 /* DEVICE_ID - [15:12] */ 11874dc55edSMark Brown #define WM8961_CHIP_REV_MASK 0x0E00 /* CHIP_REV - [11:9] */ 11974dc55edSMark Brown #define WM8961_CHIP_REV_SHIFT 9 /* CHIP_REV - [11:9] */ 12074dc55edSMark Brown #define WM8961_CHIP_REV_WIDTH 3 /* CHIP_REV - [11:9] */ 12174dc55edSMark Brown #define WM8961_IPVU 0x0100 /* IPVU */ 12274dc55edSMark Brown #define WM8961_IPVU_MASK 0x0100 /* IPVU */ 12374dc55edSMark Brown #define WM8961_IPVU_SHIFT 8 /* IPVU */ 12474dc55edSMark Brown #define WM8961_IPVU_WIDTH 1 /* IPVU */ 12574dc55edSMark Brown #define WM8961_RINMUTE 0x0080 /* RINMUTE */ 12674dc55edSMark Brown #define WM8961_RINMUTE_MASK 0x0080 /* RINMUTE */ 12774dc55edSMark Brown #define WM8961_RINMUTE_SHIFT 7 /* RINMUTE */ 12874dc55edSMark Brown #define WM8961_RINMUTE_WIDTH 1 /* RINMUTE */ 12974dc55edSMark Brown #define WM8961_RIZC 0x0040 /* RIZC */ 13074dc55edSMark Brown #define WM8961_RIZC_MASK 0x0040 /* RIZC */ 13174dc55edSMark Brown #define WM8961_RIZC_SHIFT 6 /* RIZC */ 13274dc55edSMark Brown #define WM8961_RIZC_WIDTH 1 /* RIZC */ 13374dc55edSMark Brown #define WM8961_RINVOL_MASK 0x003F /* RINVOL - [5:0] */ 13474dc55edSMark Brown #define WM8961_RINVOL_SHIFT 0 /* RINVOL - [5:0] */ 13574dc55edSMark Brown #define WM8961_RINVOL_WIDTH 6 /* RINVOL - [5:0] */ 13674dc55edSMark Brown 13774dc55edSMark Brown /* 13874dc55edSMark Brown * R2 (0x02) - LOUT1 volume 13974dc55edSMark Brown */ 14074dc55edSMark Brown #define WM8961_OUT1VU 0x0100 /* OUT1VU */ 14174dc55edSMark Brown #define WM8961_OUT1VU_MASK 0x0100 /* OUT1VU */ 14274dc55edSMark Brown #define WM8961_OUT1VU_SHIFT 8 /* OUT1VU */ 14374dc55edSMark Brown #define WM8961_OUT1VU_WIDTH 1 /* OUT1VU */ 14474dc55edSMark Brown #define WM8961_LO1ZC 0x0080 /* LO1ZC */ 14574dc55edSMark Brown #define WM8961_LO1ZC_MASK 0x0080 /* LO1ZC */ 14674dc55edSMark Brown #define WM8961_LO1ZC_SHIFT 7 /* LO1ZC */ 14774dc55edSMark Brown #define WM8961_LO1ZC_WIDTH 1 /* LO1ZC */ 14874dc55edSMark Brown #define WM8961_LOUT1VOL_MASK 0x007F /* LOUT1VOL - [6:0] */ 14974dc55edSMark Brown #define WM8961_LOUT1VOL_SHIFT 0 /* LOUT1VOL - [6:0] */ 15074dc55edSMark Brown #define WM8961_LOUT1VOL_WIDTH 7 /* LOUT1VOL - [6:0] */ 15174dc55edSMark Brown 15274dc55edSMark Brown /* 15374dc55edSMark Brown * R3 (0x03) - ROUT1 volume 15474dc55edSMark Brown */ 15574dc55edSMark Brown #define WM8961_OUT1VU 0x0100 /* OUT1VU */ 15674dc55edSMark Brown #define WM8961_OUT1VU_MASK 0x0100 /* OUT1VU */ 15774dc55edSMark Brown #define WM8961_OUT1VU_SHIFT 8 /* OUT1VU */ 15874dc55edSMark Brown #define WM8961_OUT1VU_WIDTH 1 /* OUT1VU */ 15974dc55edSMark Brown #define WM8961_RO1ZC 0x0080 /* RO1ZC */ 16074dc55edSMark Brown #define WM8961_RO1ZC_MASK 0x0080 /* RO1ZC */ 16174dc55edSMark Brown #define WM8961_RO1ZC_SHIFT 7 /* RO1ZC */ 16274dc55edSMark Brown #define WM8961_RO1ZC_WIDTH 1 /* RO1ZC */ 16374dc55edSMark Brown #define WM8961_ROUT1VOL_MASK 0x007F /* ROUT1VOL - [6:0] */ 16474dc55edSMark Brown #define WM8961_ROUT1VOL_SHIFT 0 /* ROUT1VOL - [6:0] */ 16574dc55edSMark Brown #define WM8961_ROUT1VOL_WIDTH 7 /* ROUT1VOL - [6:0] */ 16674dc55edSMark Brown 16774dc55edSMark Brown /* 16874dc55edSMark Brown * R4 (0x04) - Clocking1 16974dc55edSMark Brown */ 17074dc55edSMark Brown #define WM8961_ADCDIV_MASK 0x01C0 /* ADCDIV - [8:6] */ 17174dc55edSMark Brown #define WM8961_ADCDIV_SHIFT 6 /* ADCDIV - [8:6] */ 17274dc55edSMark Brown #define WM8961_ADCDIV_WIDTH 3 /* ADCDIV - [8:6] */ 17374dc55edSMark Brown #define WM8961_DACDIV_MASK 0x0038 /* DACDIV - [5:3] */ 17474dc55edSMark Brown #define WM8961_DACDIV_SHIFT 3 /* DACDIV - [5:3] */ 17574dc55edSMark Brown #define WM8961_DACDIV_WIDTH 3 /* DACDIV - [5:3] */ 17674dc55edSMark Brown #define WM8961_MCLKDIV 0x0004 /* MCLKDIV */ 17774dc55edSMark Brown #define WM8961_MCLKDIV_MASK 0x0004 /* MCLKDIV */ 17874dc55edSMark Brown #define WM8961_MCLKDIV_SHIFT 2 /* MCLKDIV */ 17974dc55edSMark Brown #define WM8961_MCLKDIV_WIDTH 1 /* MCLKDIV */ 18074dc55edSMark Brown 18174dc55edSMark Brown /* 18274dc55edSMark Brown * R5 (0x05) - ADC & DAC Control 1 18374dc55edSMark Brown */ 18474dc55edSMark Brown #define WM8961_ADCPOL_MASK 0x0060 /* ADCPOL - [6:5] */ 18574dc55edSMark Brown #define WM8961_ADCPOL_SHIFT 5 /* ADCPOL - [6:5] */ 18674dc55edSMark Brown #define WM8961_ADCPOL_WIDTH 2 /* ADCPOL - [6:5] */ 18774dc55edSMark Brown #define WM8961_DACMU 0x0008 /* DACMU */ 18874dc55edSMark Brown #define WM8961_DACMU_MASK 0x0008 /* DACMU */ 18974dc55edSMark Brown #define WM8961_DACMU_SHIFT 3 /* DACMU */ 19074dc55edSMark Brown #define WM8961_DACMU_WIDTH 1 /* DACMU */ 19174dc55edSMark Brown #define WM8961_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */ 19274dc55edSMark Brown #define WM8961_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */ 19374dc55edSMark Brown #define WM8961_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */ 19474dc55edSMark Brown #define WM8961_ADCHPD 0x0001 /* ADCHPD */ 19574dc55edSMark Brown #define WM8961_ADCHPD_MASK 0x0001 /* ADCHPD */ 19674dc55edSMark Brown #define WM8961_ADCHPD_SHIFT 0 /* ADCHPD */ 19774dc55edSMark Brown #define WM8961_ADCHPD_WIDTH 1 /* ADCHPD */ 19874dc55edSMark Brown 19974dc55edSMark Brown /* 20074dc55edSMark Brown * R6 (0x06) - ADC & DAC Control 2 20174dc55edSMark Brown */ 20274dc55edSMark Brown #define WM8961_ADC_HPF_CUT_MASK 0x0180 /* ADC_HPF_CUT - [8:7] */ 20374dc55edSMark Brown #define WM8961_ADC_HPF_CUT_SHIFT 7 /* ADC_HPF_CUT - [8:7] */ 20474dc55edSMark Brown #define WM8961_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [8:7] */ 20574dc55edSMark Brown #define WM8961_DACPOL_MASK 0x0060 /* DACPOL - [6:5] */ 20674dc55edSMark Brown #define WM8961_DACPOL_SHIFT 5 /* DACPOL - [6:5] */ 20774dc55edSMark Brown #define WM8961_DACPOL_WIDTH 2 /* DACPOL - [6:5] */ 20874dc55edSMark Brown #define WM8961_DACSMM 0x0008 /* DACSMM */ 20974dc55edSMark Brown #define WM8961_DACSMM_MASK 0x0008 /* DACSMM */ 21074dc55edSMark Brown #define WM8961_DACSMM_SHIFT 3 /* DACSMM */ 21174dc55edSMark Brown #define WM8961_DACSMM_WIDTH 1 /* DACSMM */ 21274dc55edSMark Brown #define WM8961_DACMR 0x0004 /* DACMR */ 21374dc55edSMark Brown #define WM8961_DACMR_MASK 0x0004 /* DACMR */ 21474dc55edSMark Brown #define WM8961_DACMR_SHIFT 2 /* DACMR */ 21574dc55edSMark Brown #define WM8961_DACMR_WIDTH 1 /* DACMR */ 21674dc55edSMark Brown #define WM8961_DACSLOPE 0x0002 /* DACSLOPE */ 21774dc55edSMark Brown #define WM8961_DACSLOPE_MASK 0x0002 /* DACSLOPE */ 21874dc55edSMark Brown #define WM8961_DACSLOPE_SHIFT 1 /* DACSLOPE */ 21974dc55edSMark Brown #define WM8961_DACSLOPE_WIDTH 1 /* DACSLOPE */ 22074dc55edSMark Brown #define WM8961_DAC_OSR128 0x0001 /* DAC_OSR128 */ 22174dc55edSMark Brown #define WM8961_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ 22274dc55edSMark Brown #define WM8961_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ 22374dc55edSMark Brown #define WM8961_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ 22474dc55edSMark Brown 22574dc55edSMark Brown /* 22674dc55edSMark Brown * R7 (0x07) - Audio Interface 0 22774dc55edSMark Brown */ 22874dc55edSMark Brown #define WM8961_ALRSWAP 0x0100 /* ALRSWAP */ 22974dc55edSMark Brown #define WM8961_ALRSWAP_MASK 0x0100 /* ALRSWAP */ 23074dc55edSMark Brown #define WM8961_ALRSWAP_SHIFT 8 /* ALRSWAP */ 23174dc55edSMark Brown #define WM8961_ALRSWAP_WIDTH 1 /* ALRSWAP */ 23274dc55edSMark Brown #define WM8961_BCLKINV 0x0080 /* BCLKINV */ 23374dc55edSMark Brown #define WM8961_BCLKINV_MASK 0x0080 /* BCLKINV */ 23474dc55edSMark Brown #define WM8961_BCLKINV_SHIFT 7 /* BCLKINV */ 23574dc55edSMark Brown #define WM8961_BCLKINV_WIDTH 1 /* BCLKINV */ 23674dc55edSMark Brown #define WM8961_MS 0x0040 /* MS */ 23774dc55edSMark Brown #define WM8961_MS_MASK 0x0040 /* MS */ 23874dc55edSMark Brown #define WM8961_MS_SHIFT 6 /* MS */ 23974dc55edSMark Brown #define WM8961_MS_WIDTH 1 /* MS */ 24074dc55edSMark Brown #define WM8961_DLRSWAP 0x0020 /* DLRSWAP */ 24174dc55edSMark Brown #define WM8961_DLRSWAP_MASK 0x0020 /* DLRSWAP */ 24274dc55edSMark Brown #define WM8961_DLRSWAP_SHIFT 5 /* DLRSWAP */ 24374dc55edSMark Brown #define WM8961_DLRSWAP_WIDTH 1 /* DLRSWAP */ 24474dc55edSMark Brown #define WM8961_LRP 0x0010 /* LRP */ 24574dc55edSMark Brown #define WM8961_LRP_MASK 0x0010 /* LRP */ 24674dc55edSMark Brown #define WM8961_LRP_SHIFT 4 /* LRP */ 24774dc55edSMark Brown #define WM8961_LRP_WIDTH 1 /* LRP */ 24874dc55edSMark Brown #define WM8961_WL_MASK 0x000C /* WL - [3:2] */ 24974dc55edSMark Brown #define WM8961_WL_SHIFT 2 /* WL - [3:2] */ 25074dc55edSMark Brown #define WM8961_WL_WIDTH 2 /* WL - [3:2] */ 25174dc55edSMark Brown #define WM8961_FORMAT_MASK 0x0003 /* FORMAT - [1:0] */ 25274dc55edSMark Brown #define WM8961_FORMAT_SHIFT 0 /* FORMAT - [1:0] */ 25374dc55edSMark Brown #define WM8961_FORMAT_WIDTH 2 /* FORMAT - [1:0] */ 25474dc55edSMark Brown 25574dc55edSMark Brown /* 25674dc55edSMark Brown * R8 (0x08) - Clocking2 25774dc55edSMark Brown */ 25874dc55edSMark Brown #define WM8961_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */ 25974dc55edSMark Brown #define WM8961_DCLKDIV_SHIFT 6 /* DCLKDIV - [8:6] */ 26074dc55edSMark Brown #define WM8961_DCLKDIV_WIDTH 3 /* DCLKDIV - [8:6] */ 26174dc55edSMark Brown #define WM8961_CLK_SYS_ENA 0x0020 /* CLK_SYS_ENA */ 26274dc55edSMark Brown #define WM8961_CLK_SYS_ENA_MASK 0x0020 /* CLK_SYS_ENA */ 26374dc55edSMark Brown #define WM8961_CLK_SYS_ENA_SHIFT 5 /* CLK_SYS_ENA */ 26474dc55edSMark Brown #define WM8961_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */ 26574dc55edSMark Brown #define WM8961_CLK_DSP_ENA 0x0010 /* CLK_DSP_ENA */ 26674dc55edSMark Brown #define WM8961_CLK_DSP_ENA_MASK 0x0010 /* CLK_DSP_ENA */ 26774dc55edSMark Brown #define WM8961_CLK_DSP_ENA_SHIFT 4 /* CLK_DSP_ENA */ 26874dc55edSMark Brown #define WM8961_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */ 26974dc55edSMark Brown #define WM8961_BCLKDIV_MASK 0x000F /* BCLKDIV - [3:0] */ 27074dc55edSMark Brown #define WM8961_BCLKDIV_SHIFT 0 /* BCLKDIV - [3:0] */ 27174dc55edSMark Brown #define WM8961_BCLKDIV_WIDTH 4 /* BCLKDIV - [3:0] */ 27274dc55edSMark Brown 27374dc55edSMark Brown /* 27474dc55edSMark Brown * R9 (0x09) - Audio Interface 1 27574dc55edSMark Brown */ 27674dc55edSMark Brown #define WM8961_DACCOMP_MASK 0x0018 /* DACCOMP - [4:3] */ 27774dc55edSMark Brown #define WM8961_DACCOMP_SHIFT 3 /* DACCOMP - [4:3] */ 27874dc55edSMark Brown #define WM8961_DACCOMP_WIDTH 2 /* DACCOMP - [4:3] */ 27974dc55edSMark Brown #define WM8961_ADCCOMP_MASK 0x0006 /* ADCCOMP - [2:1] */ 28074dc55edSMark Brown #define WM8961_ADCCOMP_SHIFT 1 /* ADCCOMP - [2:1] */ 28174dc55edSMark Brown #define WM8961_ADCCOMP_WIDTH 2 /* ADCCOMP - [2:1] */ 28274dc55edSMark Brown #define WM8961_LOOPBACK 0x0001 /* LOOPBACK */ 28374dc55edSMark Brown #define WM8961_LOOPBACK_MASK 0x0001 /* LOOPBACK */ 28474dc55edSMark Brown #define WM8961_LOOPBACK_SHIFT 0 /* LOOPBACK */ 28574dc55edSMark Brown #define WM8961_LOOPBACK_WIDTH 1 /* LOOPBACK */ 28674dc55edSMark Brown 28774dc55edSMark Brown /* 28874dc55edSMark Brown * R10 (0x0A) - Left DAC volume 28974dc55edSMark Brown */ 29074dc55edSMark Brown #define WM8961_DACVU 0x0100 /* DACVU */ 29174dc55edSMark Brown #define WM8961_DACVU_MASK 0x0100 /* DACVU */ 29274dc55edSMark Brown #define WM8961_DACVU_SHIFT 8 /* DACVU */ 29374dc55edSMark Brown #define WM8961_DACVU_WIDTH 1 /* DACVU */ 29474dc55edSMark Brown #define WM8961_LDACVOL_MASK 0x00FF /* LDACVOL - [7:0] */ 29574dc55edSMark Brown #define WM8961_LDACVOL_SHIFT 0 /* LDACVOL - [7:0] */ 29674dc55edSMark Brown #define WM8961_LDACVOL_WIDTH 8 /* LDACVOL - [7:0] */ 29774dc55edSMark Brown 29874dc55edSMark Brown /* 29974dc55edSMark Brown * R11 (0x0B) - Right DAC volume 30074dc55edSMark Brown */ 30174dc55edSMark Brown #define WM8961_DACVU 0x0100 /* DACVU */ 30274dc55edSMark Brown #define WM8961_DACVU_MASK 0x0100 /* DACVU */ 30374dc55edSMark Brown #define WM8961_DACVU_SHIFT 8 /* DACVU */ 30474dc55edSMark Brown #define WM8961_DACVU_WIDTH 1 /* DACVU */ 30574dc55edSMark Brown #define WM8961_RDACVOL_MASK 0x00FF /* RDACVOL - [7:0] */ 30674dc55edSMark Brown #define WM8961_RDACVOL_SHIFT 0 /* RDACVOL - [7:0] */ 30774dc55edSMark Brown #define WM8961_RDACVOL_WIDTH 8 /* RDACVOL - [7:0] */ 30874dc55edSMark Brown 30974dc55edSMark Brown /* 31074dc55edSMark Brown * R14 (0x0E) - Audio Interface 2 31174dc55edSMark Brown */ 31274dc55edSMark Brown #define WM8961_LRCLK_RATE_MASK 0x01FF /* LRCLK_RATE - [8:0] */ 31374dc55edSMark Brown #define WM8961_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [8:0] */ 31474dc55edSMark Brown #define WM8961_LRCLK_RATE_WIDTH 9 /* LRCLK_RATE - [8:0] */ 31574dc55edSMark Brown 31674dc55edSMark Brown /* 31774dc55edSMark Brown * R15 (0x0F) - Software Reset 31874dc55edSMark Brown */ 31974dc55edSMark Brown #define WM8961_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */ 32074dc55edSMark Brown #define WM8961_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */ 32174dc55edSMark Brown #define WM8961_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */ 32274dc55edSMark Brown 32374dc55edSMark Brown /* 32474dc55edSMark Brown * R17 (0x11) - ALC1 32574dc55edSMark Brown */ 32674dc55edSMark Brown #define WM8961_ALCSEL_MASK 0x0180 /* ALCSEL - [8:7] */ 32774dc55edSMark Brown #define WM8961_ALCSEL_SHIFT 7 /* ALCSEL - [8:7] */ 32874dc55edSMark Brown #define WM8961_ALCSEL_WIDTH 2 /* ALCSEL - [8:7] */ 32974dc55edSMark Brown #define WM8961_MAXGAIN_MASK 0x0070 /* MAXGAIN - [6:4] */ 33074dc55edSMark Brown #define WM8961_MAXGAIN_SHIFT 4 /* MAXGAIN - [6:4] */ 33174dc55edSMark Brown #define WM8961_MAXGAIN_WIDTH 3 /* MAXGAIN - [6:4] */ 33274dc55edSMark Brown #define WM8961_ALCL_MASK 0x000F /* ALCL - [3:0] */ 33374dc55edSMark Brown #define WM8961_ALCL_SHIFT 0 /* ALCL - [3:0] */ 33474dc55edSMark Brown #define WM8961_ALCL_WIDTH 4 /* ALCL - [3:0] */ 33574dc55edSMark Brown 33674dc55edSMark Brown /* 33774dc55edSMark Brown * R18 (0x12) - ALC2 33874dc55edSMark Brown */ 33974dc55edSMark Brown #define WM8961_ALCZC 0x0080 /* ALCZC */ 34074dc55edSMark Brown #define WM8961_ALCZC_MASK 0x0080 /* ALCZC */ 34174dc55edSMark Brown #define WM8961_ALCZC_SHIFT 7 /* ALCZC */ 34274dc55edSMark Brown #define WM8961_ALCZC_WIDTH 1 /* ALCZC */ 34374dc55edSMark Brown #define WM8961_MINGAIN_MASK 0x0070 /* MINGAIN - [6:4] */ 34474dc55edSMark Brown #define WM8961_MINGAIN_SHIFT 4 /* MINGAIN - [6:4] */ 34574dc55edSMark Brown #define WM8961_MINGAIN_WIDTH 3 /* MINGAIN - [6:4] */ 34674dc55edSMark Brown #define WM8961_HLD_MASK 0x000F /* HLD - [3:0] */ 34774dc55edSMark Brown #define WM8961_HLD_SHIFT 0 /* HLD - [3:0] */ 34874dc55edSMark Brown #define WM8961_HLD_WIDTH 4 /* HLD - [3:0] */ 34974dc55edSMark Brown 35074dc55edSMark Brown /* 35174dc55edSMark Brown * R19 (0x13) - ALC3 35274dc55edSMark Brown */ 35374dc55edSMark Brown #define WM8961_ALCMODE 0x0100 /* ALCMODE */ 35474dc55edSMark Brown #define WM8961_ALCMODE_MASK 0x0100 /* ALCMODE */ 35574dc55edSMark Brown #define WM8961_ALCMODE_SHIFT 8 /* ALCMODE */ 35674dc55edSMark Brown #define WM8961_ALCMODE_WIDTH 1 /* ALCMODE */ 35774dc55edSMark Brown #define WM8961_DCY_MASK 0x00F0 /* DCY - [7:4] */ 35874dc55edSMark Brown #define WM8961_DCY_SHIFT 4 /* DCY - [7:4] */ 35974dc55edSMark Brown #define WM8961_DCY_WIDTH 4 /* DCY - [7:4] */ 36074dc55edSMark Brown #define WM8961_ATK_MASK 0x000F /* ATK - [3:0] */ 36174dc55edSMark Brown #define WM8961_ATK_SHIFT 0 /* ATK - [3:0] */ 36274dc55edSMark Brown #define WM8961_ATK_WIDTH 4 /* ATK - [3:0] */ 36374dc55edSMark Brown 36474dc55edSMark Brown /* 36574dc55edSMark Brown * R20 (0x14) - Noise Gate 36674dc55edSMark Brown */ 36774dc55edSMark Brown #define WM8961_NGTH_MASK 0x00F8 /* NGTH - [7:3] */ 36874dc55edSMark Brown #define WM8961_NGTH_SHIFT 3 /* NGTH - [7:3] */ 36974dc55edSMark Brown #define WM8961_NGTH_WIDTH 5 /* NGTH - [7:3] */ 37074dc55edSMark Brown #define WM8961_NGG 0x0002 /* NGG */ 37174dc55edSMark Brown #define WM8961_NGG_MASK 0x0002 /* NGG */ 37274dc55edSMark Brown #define WM8961_NGG_SHIFT 1 /* NGG */ 37374dc55edSMark Brown #define WM8961_NGG_WIDTH 1 /* NGG */ 37474dc55edSMark Brown #define WM8961_NGAT 0x0001 /* NGAT */ 37574dc55edSMark Brown #define WM8961_NGAT_MASK 0x0001 /* NGAT */ 37674dc55edSMark Brown #define WM8961_NGAT_SHIFT 0 /* NGAT */ 37774dc55edSMark Brown #define WM8961_NGAT_WIDTH 1 /* NGAT */ 37874dc55edSMark Brown 37974dc55edSMark Brown /* 38074dc55edSMark Brown * R21 (0x15) - Left ADC volume 38174dc55edSMark Brown */ 38274dc55edSMark Brown #define WM8961_ADCVU 0x0100 /* ADCVU */ 38374dc55edSMark Brown #define WM8961_ADCVU_MASK 0x0100 /* ADCVU */ 38474dc55edSMark Brown #define WM8961_ADCVU_SHIFT 8 /* ADCVU */ 38574dc55edSMark Brown #define WM8961_ADCVU_WIDTH 1 /* ADCVU */ 38674dc55edSMark Brown #define WM8961_LADCVOL_MASK 0x00FF /* LADCVOL - [7:0] */ 38774dc55edSMark Brown #define WM8961_LADCVOL_SHIFT 0 /* LADCVOL - [7:0] */ 38874dc55edSMark Brown #define WM8961_LADCVOL_WIDTH 8 /* LADCVOL - [7:0] */ 38974dc55edSMark Brown 39074dc55edSMark Brown /* 39174dc55edSMark Brown * R22 (0x16) - Right ADC volume 39274dc55edSMark Brown */ 39374dc55edSMark Brown #define WM8961_ADCVU 0x0100 /* ADCVU */ 39474dc55edSMark Brown #define WM8961_ADCVU_MASK 0x0100 /* ADCVU */ 39574dc55edSMark Brown #define WM8961_ADCVU_SHIFT 8 /* ADCVU */ 39674dc55edSMark Brown #define WM8961_ADCVU_WIDTH 1 /* ADCVU */ 39774dc55edSMark Brown #define WM8961_RADCVOL_MASK 0x00FF /* RADCVOL - [7:0] */ 39874dc55edSMark Brown #define WM8961_RADCVOL_SHIFT 0 /* RADCVOL - [7:0] */ 39974dc55edSMark Brown #define WM8961_RADCVOL_WIDTH 8 /* RADCVOL - [7:0] */ 40074dc55edSMark Brown 40174dc55edSMark Brown /* 40274dc55edSMark Brown * R23 (0x17) - Additional control(1) 40374dc55edSMark Brown */ 40474dc55edSMark Brown #define WM8961_TSDEN 0x0100 /* TSDEN */ 40574dc55edSMark Brown #define WM8961_TSDEN_MASK 0x0100 /* TSDEN */ 40674dc55edSMark Brown #define WM8961_TSDEN_SHIFT 8 /* TSDEN */ 40774dc55edSMark Brown #define WM8961_TSDEN_WIDTH 1 /* TSDEN */ 40874dc55edSMark Brown #define WM8961_DMONOMIX 0x0010 /* DMONOMIX */ 40974dc55edSMark Brown #define WM8961_DMONOMIX_MASK 0x0010 /* DMONOMIX */ 41074dc55edSMark Brown #define WM8961_DMONOMIX_SHIFT 4 /* DMONOMIX */ 41174dc55edSMark Brown #define WM8961_DMONOMIX_WIDTH 1 /* DMONOMIX */ 41274dc55edSMark Brown #define WM8961_TOEN 0x0001 /* TOEN */ 41374dc55edSMark Brown #define WM8961_TOEN_MASK 0x0001 /* TOEN */ 41474dc55edSMark Brown #define WM8961_TOEN_SHIFT 0 /* TOEN */ 41574dc55edSMark Brown #define WM8961_TOEN_WIDTH 1 /* TOEN */ 41674dc55edSMark Brown 41774dc55edSMark Brown /* 41874dc55edSMark Brown * R24 (0x18) - Additional control(2) 41974dc55edSMark Brown */ 42074dc55edSMark Brown #define WM8961_TRIS 0x0008 /* TRIS */ 42174dc55edSMark Brown #define WM8961_TRIS_MASK 0x0008 /* TRIS */ 42274dc55edSMark Brown #define WM8961_TRIS_SHIFT 3 /* TRIS */ 42374dc55edSMark Brown #define WM8961_TRIS_WIDTH 1 /* TRIS */ 42474dc55edSMark Brown 42574dc55edSMark Brown /* 42674dc55edSMark Brown * R25 (0x19) - Pwr Mgmt (1) 42774dc55edSMark Brown */ 42874dc55edSMark Brown #define WM8961_VMIDSEL_MASK 0x0180 /* VMIDSEL - [8:7] */ 42974dc55edSMark Brown #define WM8961_VMIDSEL_SHIFT 7 /* VMIDSEL - [8:7] */ 43074dc55edSMark Brown #define WM8961_VMIDSEL_WIDTH 2 /* VMIDSEL - [8:7] */ 43174dc55edSMark Brown #define WM8961_VREF 0x0040 /* VREF */ 43274dc55edSMark Brown #define WM8961_VREF_MASK 0x0040 /* VREF */ 43374dc55edSMark Brown #define WM8961_VREF_SHIFT 6 /* VREF */ 43474dc55edSMark Brown #define WM8961_VREF_WIDTH 1 /* VREF */ 43574dc55edSMark Brown #define WM8961_AINL 0x0020 /* AINL */ 43674dc55edSMark Brown #define WM8961_AINL_MASK 0x0020 /* AINL */ 43774dc55edSMark Brown #define WM8961_AINL_SHIFT 5 /* AINL */ 43874dc55edSMark Brown #define WM8961_AINL_WIDTH 1 /* AINL */ 43974dc55edSMark Brown #define WM8961_AINR 0x0010 /* AINR */ 44074dc55edSMark Brown #define WM8961_AINR_MASK 0x0010 /* AINR */ 44174dc55edSMark Brown #define WM8961_AINR_SHIFT 4 /* AINR */ 44274dc55edSMark Brown #define WM8961_AINR_WIDTH 1 /* AINR */ 44374dc55edSMark Brown #define WM8961_ADCL 0x0008 /* ADCL */ 44474dc55edSMark Brown #define WM8961_ADCL_MASK 0x0008 /* ADCL */ 44574dc55edSMark Brown #define WM8961_ADCL_SHIFT 3 /* ADCL */ 44674dc55edSMark Brown #define WM8961_ADCL_WIDTH 1 /* ADCL */ 44774dc55edSMark Brown #define WM8961_ADCR 0x0004 /* ADCR */ 44874dc55edSMark Brown #define WM8961_ADCR_MASK 0x0004 /* ADCR */ 44974dc55edSMark Brown #define WM8961_ADCR_SHIFT 2 /* ADCR */ 45074dc55edSMark Brown #define WM8961_ADCR_WIDTH 1 /* ADCR */ 45174dc55edSMark Brown #define WM8961_MICB 0x0002 /* MICB */ 45274dc55edSMark Brown #define WM8961_MICB_MASK 0x0002 /* MICB */ 45374dc55edSMark Brown #define WM8961_MICB_SHIFT 1 /* MICB */ 45474dc55edSMark Brown #define WM8961_MICB_WIDTH 1 /* MICB */ 45574dc55edSMark Brown 45674dc55edSMark Brown /* 45774dc55edSMark Brown * R26 (0x1A) - Pwr Mgmt (2) 45874dc55edSMark Brown */ 45974dc55edSMark Brown #define WM8961_DACL 0x0100 /* DACL */ 46074dc55edSMark Brown #define WM8961_DACL_MASK 0x0100 /* DACL */ 46174dc55edSMark Brown #define WM8961_DACL_SHIFT 8 /* DACL */ 46274dc55edSMark Brown #define WM8961_DACL_WIDTH 1 /* DACL */ 46374dc55edSMark Brown #define WM8961_DACR 0x0080 /* DACR */ 46474dc55edSMark Brown #define WM8961_DACR_MASK 0x0080 /* DACR */ 46574dc55edSMark Brown #define WM8961_DACR_SHIFT 7 /* DACR */ 46674dc55edSMark Brown #define WM8961_DACR_WIDTH 1 /* DACR */ 46774dc55edSMark Brown #define WM8961_LOUT1_PGA 0x0040 /* LOUT1_PGA */ 46874dc55edSMark Brown #define WM8961_LOUT1_PGA_MASK 0x0040 /* LOUT1_PGA */ 46974dc55edSMark Brown #define WM8961_LOUT1_PGA_SHIFT 6 /* LOUT1_PGA */ 47074dc55edSMark Brown #define WM8961_LOUT1_PGA_WIDTH 1 /* LOUT1_PGA */ 47174dc55edSMark Brown #define WM8961_ROUT1_PGA 0x0020 /* ROUT1_PGA */ 47274dc55edSMark Brown #define WM8961_ROUT1_PGA_MASK 0x0020 /* ROUT1_PGA */ 47374dc55edSMark Brown #define WM8961_ROUT1_PGA_SHIFT 5 /* ROUT1_PGA */ 47474dc55edSMark Brown #define WM8961_ROUT1_PGA_WIDTH 1 /* ROUT1_PGA */ 47574dc55edSMark Brown #define WM8961_SPKL_PGA 0x0010 /* SPKL_PGA */ 47674dc55edSMark Brown #define WM8961_SPKL_PGA_MASK 0x0010 /* SPKL_PGA */ 47774dc55edSMark Brown #define WM8961_SPKL_PGA_SHIFT 4 /* SPKL_PGA */ 47874dc55edSMark Brown #define WM8961_SPKL_PGA_WIDTH 1 /* SPKL_PGA */ 47974dc55edSMark Brown #define WM8961_SPKR_PGA 0x0008 /* SPKR_PGA */ 48074dc55edSMark Brown #define WM8961_SPKR_PGA_MASK 0x0008 /* SPKR_PGA */ 48174dc55edSMark Brown #define WM8961_SPKR_PGA_SHIFT 3 /* SPKR_PGA */ 48274dc55edSMark Brown #define WM8961_SPKR_PGA_WIDTH 1 /* SPKR_PGA */ 48374dc55edSMark Brown 48474dc55edSMark Brown /* 48574dc55edSMark Brown * R27 (0x1B) - Additional Control (3) 48674dc55edSMark Brown */ 48774dc55edSMark Brown #define WM8961_SAMPLE_RATE_MASK 0x0007 /* SAMPLE_RATE - [2:0] */ 48874dc55edSMark Brown #define WM8961_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [2:0] */ 48974dc55edSMark Brown #define WM8961_SAMPLE_RATE_WIDTH 3 /* SAMPLE_RATE - [2:0] */ 49074dc55edSMark Brown 49174dc55edSMark Brown /* 49274dc55edSMark Brown * R28 (0x1C) - Anti-pop 49374dc55edSMark Brown */ 49474dc55edSMark Brown #define WM8961_BUFDCOPEN 0x0010 /* BUFDCOPEN */ 49574dc55edSMark Brown #define WM8961_BUFDCOPEN_MASK 0x0010 /* BUFDCOPEN */ 49674dc55edSMark Brown #define WM8961_BUFDCOPEN_SHIFT 4 /* BUFDCOPEN */ 49774dc55edSMark Brown #define WM8961_BUFDCOPEN_WIDTH 1 /* BUFDCOPEN */ 49874dc55edSMark Brown #define WM8961_BUFIOEN 0x0008 /* BUFIOEN */ 49974dc55edSMark Brown #define WM8961_BUFIOEN_MASK 0x0008 /* BUFIOEN */ 50074dc55edSMark Brown #define WM8961_BUFIOEN_SHIFT 3 /* BUFIOEN */ 50174dc55edSMark Brown #define WM8961_BUFIOEN_WIDTH 1 /* BUFIOEN */ 50274dc55edSMark Brown #define WM8961_SOFT_ST 0x0004 /* SOFT_ST */ 50374dc55edSMark Brown #define WM8961_SOFT_ST_MASK 0x0004 /* SOFT_ST */ 50474dc55edSMark Brown #define WM8961_SOFT_ST_SHIFT 2 /* SOFT_ST */ 50574dc55edSMark Brown #define WM8961_SOFT_ST_WIDTH 1 /* SOFT_ST */ 50674dc55edSMark Brown 50774dc55edSMark Brown /* 50874dc55edSMark Brown * R30 (0x1E) - Clocking 3 50974dc55edSMark Brown */ 51074dc55edSMark Brown #define WM8961_CLK_TO_DIV_MASK 0x0180 /* CLK_TO_DIV - [8:7] */ 51174dc55edSMark Brown #define WM8961_CLK_TO_DIV_SHIFT 7 /* CLK_TO_DIV - [8:7] */ 51274dc55edSMark Brown #define WM8961_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [8:7] */ 51374dc55edSMark Brown #define WM8961_CLK_256K_DIV_MASK 0x007E /* CLK_256K_DIV - [6:1] */ 51474dc55edSMark Brown #define WM8961_CLK_256K_DIV_SHIFT 1 /* CLK_256K_DIV - [6:1] */ 51574dc55edSMark Brown #define WM8961_CLK_256K_DIV_WIDTH 6 /* CLK_256K_DIV - [6:1] */ 51674dc55edSMark Brown #define WM8961_MANUAL_MODE 0x0001 /* MANUAL_MODE */ 51774dc55edSMark Brown #define WM8961_MANUAL_MODE_MASK 0x0001 /* MANUAL_MODE */ 51874dc55edSMark Brown #define WM8961_MANUAL_MODE_SHIFT 0 /* MANUAL_MODE */ 51974dc55edSMark Brown #define WM8961_MANUAL_MODE_WIDTH 1 /* MANUAL_MODE */ 52074dc55edSMark Brown 52174dc55edSMark Brown /* 52274dc55edSMark Brown * R32 (0x20) - ADCL signal path 52374dc55edSMark Brown */ 52474dc55edSMark Brown #define WM8961_LMICBOOST_MASK 0x0030 /* LMICBOOST - [5:4] */ 52574dc55edSMark Brown #define WM8961_LMICBOOST_SHIFT 4 /* LMICBOOST - [5:4] */ 52674dc55edSMark Brown #define WM8961_LMICBOOST_WIDTH 2 /* LMICBOOST - [5:4] */ 52774dc55edSMark Brown 52874dc55edSMark Brown /* 52974dc55edSMark Brown * R33 (0x21) - ADCR signal path 53074dc55edSMark Brown */ 53174dc55edSMark Brown #define WM8961_RMICBOOST_MASK 0x0030 /* RMICBOOST - [5:4] */ 53274dc55edSMark Brown #define WM8961_RMICBOOST_SHIFT 4 /* RMICBOOST - [5:4] */ 53374dc55edSMark Brown #define WM8961_RMICBOOST_WIDTH 2 /* RMICBOOST - [5:4] */ 53474dc55edSMark Brown 53574dc55edSMark Brown /* 53674dc55edSMark Brown * R40 (0x28) - LOUT2 volume 53774dc55edSMark Brown */ 53874dc55edSMark Brown #define WM8961_SPKVU 0x0100 /* SPKVU */ 53974dc55edSMark Brown #define WM8961_SPKVU_MASK 0x0100 /* SPKVU */ 54074dc55edSMark Brown #define WM8961_SPKVU_SHIFT 8 /* SPKVU */ 54174dc55edSMark Brown #define WM8961_SPKVU_WIDTH 1 /* SPKVU */ 54274dc55edSMark Brown #define WM8961_SPKLZC 0x0080 /* SPKLZC */ 54374dc55edSMark Brown #define WM8961_SPKLZC_MASK 0x0080 /* SPKLZC */ 54474dc55edSMark Brown #define WM8961_SPKLZC_SHIFT 7 /* SPKLZC */ 54574dc55edSMark Brown #define WM8961_SPKLZC_WIDTH 1 /* SPKLZC */ 54674dc55edSMark Brown #define WM8961_SPKLVOL_MASK 0x007F /* SPKLVOL - [6:0] */ 54774dc55edSMark Brown #define WM8961_SPKLVOL_SHIFT 0 /* SPKLVOL - [6:0] */ 54874dc55edSMark Brown #define WM8961_SPKLVOL_WIDTH 7 /* SPKLVOL - [6:0] */ 54974dc55edSMark Brown 55074dc55edSMark Brown /* 55174dc55edSMark Brown * R41 (0x29) - ROUT2 volume 55274dc55edSMark Brown */ 55374dc55edSMark Brown #define WM8961_SPKVU 0x0100 /* SPKVU */ 55474dc55edSMark Brown #define WM8961_SPKVU_MASK 0x0100 /* SPKVU */ 55574dc55edSMark Brown #define WM8961_SPKVU_SHIFT 8 /* SPKVU */ 55674dc55edSMark Brown #define WM8961_SPKVU_WIDTH 1 /* SPKVU */ 55774dc55edSMark Brown #define WM8961_SPKRZC 0x0080 /* SPKRZC */ 55874dc55edSMark Brown #define WM8961_SPKRZC_MASK 0x0080 /* SPKRZC */ 55974dc55edSMark Brown #define WM8961_SPKRZC_SHIFT 7 /* SPKRZC */ 56074dc55edSMark Brown #define WM8961_SPKRZC_WIDTH 1 /* SPKRZC */ 56174dc55edSMark Brown #define WM8961_SPKRVOL_MASK 0x007F /* SPKRVOL - [6:0] */ 56274dc55edSMark Brown #define WM8961_SPKRVOL_SHIFT 0 /* SPKRVOL - [6:0] */ 56374dc55edSMark Brown #define WM8961_SPKRVOL_WIDTH 7 /* SPKRVOL - [6:0] */ 56474dc55edSMark Brown 56574dc55edSMark Brown /* 56674dc55edSMark Brown * R47 (0x2F) - Pwr Mgmt (3) 56774dc55edSMark Brown */ 56874dc55edSMark Brown #define WM8961_TEMP_SHUT 0x0002 /* TEMP_SHUT */ 56974dc55edSMark Brown #define WM8961_TEMP_SHUT_MASK 0x0002 /* TEMP_SHUT */ 57074dc55edSMark Brown #define WM8961_TEMP_SHUT_SHIFT 1 /* TEMP_SHUT */ 57174dc55edSMark Brown #define WM8961_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */ 57274dc55edSMark Brown #define WM8961_TEMP_WARN 0x0001 /* TEMP_WARN */ 57374dc55edSMark Brown #define WM8961_TEMP_WARN_MASK 0x0001 /* TEMP_WARN */ 57474dc55edSMark Brown #define WM8961_TEMP_WARN_SHIFT 0 /* TEMP_WARN */ 57574dc55edSMark Brown #define WM8961_TEMP_WARN_WIDTH 1 /* TEMP_WARN */ 57674dc55edSMark Brown 57774dc55edSMark Brown /* 57874dc55edSMark Brown * R48 (0x30) - Additional Control (4) 57974dc55edSMark Brown */ 58074dc55edSMark Brown #define WM8961_TSENSEN 0x0002 /* TSENSEN */ 58174dc55edSMark Brown #define WM8961_TSENSEN_MASK 0x0002 /* TSENSEN */ 58274dc55edSMark Brown #define WM8961_TSENSEN_SHIFT 1 /* TSENSEN */ 58374dc55edSMark Brown #define WM8961_TSENSEN_WIDTH 1 /* TSENSEN */ 58474dc55edSMark Brown #define WM8961_MBSEL 0x0001 /* MBSEL */ 58574dc55edSMark Brown #define WM8961_MBSEL_MASK 0x0001 /* MBSEL */ 58674dc55edSMark Brown #define WM8961_MBSEL_SHIFT 0 /* MBSEL */ 58774dc55edSMark Brown #define WM8961_MBSEL_WIDTH 1 /* MBSEL */ 58874dc55edSMark Brown 58974dc55edSMark Brown /* 59074dc55edSMark Brown * R49 (0x31) - Class D Control 1 59174dc55edSMark Brown */ 59274dc55edSMark Brown #define WM8961_SPKR_ENA 0x0080 /* SPKR_ENA */ 59374dc55edSMark Brown #define WM8961_SPKR_ENA_MASK 0x0080 /* SPKR_ENA */ 59474dc55edSMark Brown #define WM8961_SPKR_ENA_SHIFT 7 /* SPKR_ENA */ 59574dc55edSMark Brown #define WM8961_SPKR_ENA_WIDTH 1 /* SPKR_ENA */ 59674dc55edSMark Brown #define WM8961_SPKL_ENA 0x0040 /* SPKL_ENA */ 59774dc55edSMark Brown #define WM8961_SPKL_ENA_MASK 0x0040 /* SPKL_ENA */ 59874dc55edSMark Brown #define WM8961_SPKL_ENA_SHIFT 6 /* SPKL_ENA */ 59974dc55edSMark Brown #define WM8961_SPKL_ENA_WIDTH 1 /* SPKL_ENA */ 60074dc55edSMark Brown 60174dc55edSMark Brown /* 60274dc55edSMark Brown * R51 (0x33) - Class D Control 2 60374dc55edSMark Brown */ 60474dc55edSMark Brown #define WM8961_CLASSD_ACGAIN_MASK 0x0007 /* CLASSD_ACGAIN - [2:0] */ 60574dc55edSMark Brown #define WM8961_CLASSD_ACGAIN_SHIFT 0 /* CLASSD_ACGAIN - [2:0] */ 60674dc55edSMark Brown #define WM8961_CLASSD_ACGAIN_WIDTH 3 /* CLASSD_ACGAIN - [2:0] */ 60774dc55edSMark Brown 60874dc55edSMark Brown /* 60974dc55edSMark Brown * R56 (0x38) - Clocking 4 61074dc55edSMark Brown */ 61174dc55edSMark Brown #define WM8961_CLK_DCS_DIV_MASK 0x01E0 /* CLK_DCS_DIV - [8:5] */ 61274dc55edSMark Brown #define WM8961_CLK_DCS_DIV_SHIFT 5 /* CLK_DCS_DIV - [8:5] */ 61374dc55edSMark Brown #define WM8961_CLK_DCS_DIV_WIDTH 4 /* CLK_DCS_DIV - [8:5] */ 61474dc55edSMark Brown #define WM8961_CLK_SYS_RATE_MASK 0x001E /* CLK_SYS_RATE - [4:1] */ 61574dc55edSMark Brown #define WM8961_CLK_SYS_RATE_SHIFT 1 /* CLK_SYS_RATE - [4:1] */ 61674dc55edSMark Brown #define WM8961_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [4:1] */ 61774dc55edSMark Brown 61874dc55edSMark Brown /* 61974dc55edSMark Brown * R57 (0x39) - DSP Sidetone 0 62074dc55edSMark Brown */ 62174dc55edSMark Brown #define WM8961_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */ 62274dc55edSMark Brown #define WM8961_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */ 62374dc55edSMark Brown #define WM8961_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */ 62474dc55edSMark Brown #define WM8961_ADC_TO_DACR_MASK 0x000C /* ADC_TO_DACR - [3:2] */ 62574dc55edSMark Brown #define WM8961_ADC_TO_DACR_SHIFT 2 /* ADC_TO_DACR - [3:2] */ 62674dc55edSMark Brown #define WM8961_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [3:2] */ 62774dc55edSMark Brown 62874dc55edSMark Brown /* 62974dc55edSMark Brown * R58 (0x3A) - DSP Sidetone 1 63074dc55edSMark Brown */ 63174dc55edSMark Brown #define WM8961_ADCL_DAC_SVOL_MASK 0x00F0 /* ADCL_DAC_SVOL - [7:4] */ 63274dc55edSMark Brown #define WM8961_ADCL_DAC_SVOL_SHIFT 4 /* ADCL_DAC_SVOL - [7:4] */ 63374dc55edSMark Brown #define WM8961_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [7:4] */ 63474dc55edSMark Brown #define WM8961_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */ 63574dc55edSMark Brown #define WM8961_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */ 63674dc55edSMark Brown #define WM8961_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */ 63774dc55edSMark Brown 63874dc55edSMark Brown /* 63974dc55edSMark Brown * R60 (0x3C) - DC Servo 0 64074dc55edSMark Brown */ 64174dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_INL 0x0080 /* DCS_ENA_CHAN_INL */ 64274dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_INL_MASK 0x0080 /* DCS_ENA_CHAN_INL */ 64374dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_INL_SHIFT 7 /* DCS_ENA_CHAN_INL */ 64474dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_INL_WIDTH 1 /* DCS_ENA_CHAN_INL */ 64574dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_INL 0x0040 /* DCS_TRIG_STARTUP_INL */ 64674dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_INL_MASK 0x0040 /* DCS_TRIG_STARTUP_INL */ 64774dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_INL_SHIFT 6 /* DCS_TRIG_STARTUP_INL */ 64874dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_INL_WIDTH 1 /* DCS_TRIG_STARTUP_INL */ 64974dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_INL 0x0010 /* DCS_TRIG_SERIES_INL */ 65074dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_INL_MASK 0x0010 /* DCS_TRIG_SERIES_INL */ 65174dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_INL_SHIFT 4 /* DCS_TRIG_SERIES_INL */ 65274dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_INL_WIDTH 1 /* DCS_TRIG_SERIES_INL */ 65374dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_INR 0x0008 /* DCS_ENA_CHAN_INR */ 65474dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_INR_MASK 0x0008 /* DCS_ENA_CHAN_INR */ 65574dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_INR_SHIFT 3 /* DCS_ENA_CHAN_INR */ 65674dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_INR_WIDTH 1 /* DCS_ENA_CHAN_INR */ 65774dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_INR 0x0004 /* DCS_TRIG_STARTUP_INR */ 65874dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_INR_MASK 0x0004 /* DCS_TRIG_STARTUP_INR */ 65974dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_INR_SHIFT 2 /* DCS_TRIG_STARTUP_INR */ 66074dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_INR_WIDTH 1 /* DCS_TRIG_STARTUP_INR */ 66174dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_INR 0x0001 /* DCS_TRIG_SERIES_INR */ 66274dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_INR_MASK 0x0001 /* DCS_TRIG_SERIES_INR */ 66374dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_INR_SHIFT 0 /* DCS_TRIG_SERIES_INR */ 66474dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_INR_WIDTH 1 /* DCS_TRIG_SERIES_INR */ 66574dc55edSMark Brown 66674dc55edSMark Brown /* 66774dc55edSMark Brown * R61 (0x3D) - DC Servo 1 66874dc55edSMark Brown */ 66974dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_HPL 0x0080 /* DCS_ENA_CHAN_HPL */ 67074dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_HPL_MASK 0x0080 /* DCS_ENA_CHAN_HPL */ 67174dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_HPL_SHIFT 7 /* DCS_ENA_CHAN_HPL */ 67274dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_HPL_WIDTH 1 /* DCS_ENA_CHAN_HPL */ 67374dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_HPL 0x0040 /* DCS_TRIG_STARTUP_HPL */ 67474dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_HPL_MASK 0x0040 /* DCS_TRIG_STARTUP_HPL */ 67574dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_HPL_SHIFT 6 /* DCS_TRIG_STARTUP_HPL */ 67674dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_HPL_WIDTH 1 /* DCS_TRIG_STARTUP_HPL */ 67774dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_HPL 0x0010 /* DCS_TRIG_SERIES_HPL */ 67874dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_HPL_MASK 0x0010 /* DCS_TRIG_SERIES_HPL */ 67974dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_HPL_SHIFT 4 /* DCS_TRIG_SERIES_HPL */ 68074dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_HPL_WIDTH 1 /* DCS_TRIG_SERIES_HPL */ 68174dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_HPR 0x0008 /* DCS_ENA_CHAN_HPR */ 68274dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_HPR_MASK 0x0008 /* DCS_ENA_CHAN_HPR */ 68374dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_HPR_SHIFT 3 /* DCS_ENA_CHAN_HPR */ 68474dc55edSMark Brown #define WM8961_DCS_ENA_CHAN_HPR_WIDTH 1 /* DCS_ENA_CHAN_HPR */ 68574dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_HPR 0x0004 /* DCS_TRIG_STARTUP_HPR */ 68674dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_HPR_MASK 0x0004 /* DCS_TRIG_STARTUP_HPR */ 68774dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_HPR_SHIFT 2 /* DCS_TRIG_STARTUP_HPR */ 68874dc55edSMark Brown #define WM8961_DCS_TRIG_STARTUP_HPR_WIDTH 1 /* DCS_TRIG_STARTUP_HPR */ 68974dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_HPR 0x0001 /* DCS_TRIG_SERIES_HPR */ 69074dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_HPR_MASK 0x0001 /* DCS_TRIG_SERIES_HPR */ 69174dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_HPR_SHIFT 0 /* DCS_TRIG_SERIES_HPR */ 69274dc55edSMark Brown #define WM8961_DCS_TRIG_SERIES_HPR_WIDTH 1 /* DCS_TRIG_SERIES_HPR */ 69374dc55edSMark Brown 69474dc55edSMark Brown /* 69574dc55edSMark Brown * R63 (0x3F) - DC Servo 3 69674dc55edSMark Brown */ 69774dc55edSMark Brown #define WM8961_DCS_FILT_BW_SERIES_MASK 0x0030 /* DCS_FILT_BW_SERIES - [5:4] */ 69874dc55edSMark Brown #define WM8961_DCS_FILT_BW_SERIES_SHIFT 4 /* DCS_FILT_BW_SERIES - [5:4] */ 69974dc55edSMark Brown #define WM8961_DCS_FILT_BW_SERIES_WIDTH 2 /* DCS_FILT_BW_SERIES - [5:4] */ 70074dc55edSMark Brown 70174dc55edSMark Brown /* 70274dc55edSMark Brown * R65 (0x41) - DC Servo 5 70374dc55edSMark Brown */ 70474dc55edSMark Brown #define WM8961_DCS_SERIES_NO_HP_MASK 0x007F /* DCS_SERIES_NO_HP - [6:0] */ 70574dc55edSMark Brown #define WM8961_DCS_SERIES_NO_HP_SHIFT 0 /* DCS_SERIES_NO_HP - [6:0] */ 70674dc55edSMark Brown #define WM8961_DCS_SERIES_NO_HP_WIDTH 7 /* DCS_SERIES_NO_HP - [6:0] */ 70774dc55edSMark Brown 70874dc55edSMark Brown /* 70974dc55edSMark Brown * R68 (0x44) - Analogue PGA Bias 71074dc55edSMark Brown */ 71174dc55edSMark Brown #define WM8961_HP_PGAS_BIAS_MASK 0x0007 /* HP_PGAS_BIAS - [2:0] */ 71274dc55edSMark Brown #define WM8961_HP_PGAS_BIAS_SHIFT 0 /* HP_PGAS_BIAS - [2:0] */ 71374dc55edSMark Brown #define WM8961_HP_PGAS_BIAS_WIDTH 3 /* HP_PGAS_BIAS - [2:0] */ 71474dc55edSMark Brown 71574dc55edSMark Brown /* 71674dc55edSMark Brown * R69 (0x45) - Analogue HP 0 71774dc55edSMark Brown */ 71874dc55edSMark Brown #define WM8961_HPL_RMV_SHORT 0x0080 /* HPL_RMV_SHORT */ 71974dc55edSMark Brown #define WM8961_HPL_RMV_SHORT_MASK 0x0080 /* HPL_RMV_SHORT */ 72074dc55edSMark Brown #define WM8961_HPL_RMV_SHORT_SHIFT 7 /* HPL_RMV_SHORT */ 72174dc55edSMark Brown #define WM8961_HPL_RMV_SHORT_WIDTH 1 /* HPL_RMV_SHORT */ 72274dc55edSMark Brown #define WM8961_HPL_ENA_OUTP 0x0040 /* HPL_ENA_OUTP */ 72374dc55edSMark Brown #define WM8961_HPL_ENA_OUTP_MASK 0x0040 /* HPL_ENA_OUTP */ 72474dc55edSMark Brown #define WM8961_HPL_ENA_OUTP_SHIFT 6 /* HPL_ENA_OUTP */ 72574dc55edSMark Brown #define WM8961_HPL_ENA_OUTP_WIDTH 1 /* HPL_ENA_OUTP */ 72674dc55edSMark Brown #define WM8961_HPL_ENA_DLY 0x0020 /* HPL_ENA_DLY */ 72774dc55edSMark Brown #define WM8961_HPL_ENA_DLY_MASK 0x0020 /* HPL_ENA_DLY */ 72874dc55edSMark Brown #define WM8961_HPL_ENA_DLY_SHIFT 5 /* HPL_ENA_DLY */ 72974dc55edSMark Brown #define WM8961_HPL_ENA_DLY_WIDTH 1 /* HPL_ENA_DLY */ 73074dc55edSMark Brown #define WM8961_HPL_ENA 0x0010 /* HPL_ENA */ 73174dc55edSMark Brown #define WM8961_HPL_ENA_MASK 0x0010 /* HPL_ENA */ 73274dc55edSMark Brown #define WM8961_HPL_ENA_SHIFT 4 /* HPL_ENA */ 73374dc55edSMark Brown #define WM8961_HPL_ENA_WIDTH 1 /* HPL_ENA */ 73474dc55edSMark Brown #define WM8961_HPR_RMV_SHORT 0x0008 /* HPR_RMV_SHORT */ 73574dc55edSMark Brown #define WM8961_HPR_RMV_SHORT_MASK 0x0008 /* HPR_RMV_SHORT */ 73674dc55edSMark Brown #define WM8961_HPR_RMV_SHORT_SHIFT 3 /* HPR_RMV_SHORT */ 73774dc55edSMark Brown #define WM8961_HPR_RMV_SHORT_WIDTH 1 /* HPR_RMV_SHORT */ 73874dc55edSMark Brown #define WM8961_HPR_ENA_OUTP 0x0004 /* HPR_ENA_OUTP */ 73974dc55edSMark Brown #define WM8961_HPR_ENA_OUTP_MASK 0x0004 /* HPR_ENA_OUTP */ 74074dc55edSMark Brown #define WM8961_HPR_ENA_OUTP_SHIFT 2 /* HPR_ENA_OUTP */ 74174dc55edSMark Brown #define WM8961_HPR_ENA_OUTP_WIDTH 1 /* HPR_ENA_OUTP */ 74274dc55edSMark Brown #define WM8961_HPR_ENA_DLY 0x0002 /* HPR_ENA_DLY */ 74374dc55edSMark Brown #define WM8961_HPR_ENA_DLY_MASK 0x0002 /* HPR_ENA_DLY */ 74474dc55edSMark Brown #define WM8961_HPR_ENA_DLY_SHIFT 1 /* HPR_ENA_DLY */ 74574dc55edSMark Brown #define WM8961_HPR_ENA_DLY_WIDTH 1 /* HPR_ENA_DLY */ 74674dc55edSMark Brown #define WM8961_HPR_ENA 0x0001 /* HPR_ENA */ 74774dc55edSMark Brown #define WM8961_HPR_ENA_MASK 0x0001 /* HPR_ENA */ 74874dc55edSMark Brown #define WM8961_HPR_ENA_SHIFT 0 /* HPR_ENA */ 74974dc55edSMark Brown #define WM8961_HPR_ENA_WIDTH 1 /* HPR_ENA */ 75074dc55edSMark Brown 75174dc55edSMark Brown /* 75274dc55edSMark Brown * R71 (0x47) - Analogue HP 2 75374dc55edSMark Brown */ 75474dc55edSMark Brown #define WM8961_HPL_VOL_MASK 0x01C0 /* HPL_VOL - [8:6] */ 75574dc55edSMark Brown #define WM8961_HPL_VOL_SHIFT 6 /* HPL_VOL - [8:6] */ 75674dc55edSMark Brown #define WM8961_HPL_VOL_WIDTH 3 /* HPL_VOL - [8:6] */ 75774dc55edSMark Brown #define WM8961_HPR_VOL_MASK 0x0038 /* HPR_VOL - [5:3] */ 75874dc55edSMark Brown #define WM8961_HPR_VOL_SHIFT 3 /* HPR_VOL - [5:3] */ 75974dc55edSMark Brown #define WM8961_HPR_VOL_WIDTH 3 /* HPR_VOL - [5:3] */ 76074dc55edSMark Brown #define WM8961_HP_BIAS_BOOST_MASK 0x0007 /* HP_BIAS_BOOST - [2:0] */ 76174dc55edSMark Brown #define WM8961_HP_BIAS_BOOST_SHIFT 0 /* HP_BIAS_BOOST - [2:0] */ 76274dc55edSMark Brown #define WM8961_HP_BIAS_BOOST_WIDTH 3 /* HP_BIAS_BOOST - [2:0] */ 76374dc55edSMark Brown 76474dc55edSMark Brown /* 76574dc55edSMark Brown * R72 (0x48) - Charge Pump 1 76674dc55edSMark Brown */ 76774dc55edSMark Brown #define WM8961_CP_ENA 0x0001 /* CP_ENA */ 76874dc55edSMark Brown #define WM8961_CP_ENA_MASK 0x0001 /* CP_ENA */ 76974dc55edSMark Brown #define WM8961_CP_ENA_SHIFT 0 /* CP_ENA */ 77074dc55edSMark Brown #define WM8961_CP_ENA_WIDTH 1 /* CP_ENA */ 77174dc55edSMark Brown 77274dc55edSMark Brown /* 77374dc55edSMark Brown * R82 (0x52) - Charge Pump B 77474dc55edSMark Brown */ 77574dc55edSMark Brown #define WM8961_CP_DYN_PWR_MASK 0x0003 /* CP_DYN_PWR - [1:0] */ 77674dc55edSMark Brown #define WM8961_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR - [1:0] */ 77774dc55edSMark Brown #define WM8961_CP_DYN_PWR_WIDTH 2 /* CP_DYN_PWR - [1:0] */ 77874dc55edSMark Brown 77974dc55edSMark Brown /* 78074dc55edSMark Brown * R87 (0x57) - Write Sequencer 1 78174dc55edSMark Brown */ 78274dc55edSMark Brown #define WM8961_WSEQ_ENA 0x0020 /* WSEQ_ENA */ 78374dc55edSMark Brown #define WM8961_WSEQ_ENA_MASK 0x0020 /* WSEQ_ENA */ 78474dc55edSMark Brown #define WM8961_WSEQ_ENA_SHIFT 5 /* WSEQ_ENA */ 78574dc55edSMark Brown #define WM8961_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 78674dc55edSMark Brown #define WM8961_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */ 78774dc55edSMark Brown #define WM8961_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */ 78874dc55edSMark Brown #define WM8961_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */ 78974dc55edSMark Brown 79074dc55edSMark Brown /* 79174dc55edSMark Brown * R88 (0x58) - Write Sequencer 2 79274dc55edSMark Brown */ 79374dc55edSMark Brown #define WM8961_WSEQ_EOS 0x0100 /* WSEQ_EOS */ 79474dc55edSMark Brown #define WM8961_WSEQ_EOS_MASK 0x0100 /* WSEQ_EOS */ 79574dc55edSMark Brown #define WM8961_WSEQ_EOS_SHIFT 8 /* WSEQ_EOS */ 79674dc55edSMark Brown #define WM8961_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */ 79774dc55edSMark Brown #define WM8961_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */ 79874dc55edSMark Brown #define WM8961_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */ 79974dc55edSMark Brown #define WM8961_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */ 80074dc55edSMark Brown 80174dc55edSMark Brown /* 80274dc55edSMark Brown * R89 (0x59) - Write Sequencer 3 80374dc55edSMark Brown */ 80474dc55edSMark Brown #define WM8961_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */ 80574dc55edSMark Brown #define WM8961_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */ 80674dc55edSMark Brown #define WM8961_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */ 80774dc55edSMark Brown 80874dc55edSMark Brown /* 80974dc55edSMark Brown * R90 (0x5A) - Write Sequencer 4 81074dc55edSMark Brown */ 81174dc55edSMark Brown #define WM8961_WSEQ_ABORT 0x0100 /* WSEQ_ABORT */ 81274dc55edSMark Brown #define WM8961_WSEQ_ABORT_MASK 0x0100 /* WSEQ_ABORT */ 81374dc55edSMark Brown #define WM8961_WSEQ_ABORT_SHIFT 8 /* WSEQ_ABORT */ 81474dc55edSMark Brown #define WM8961_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 81574dc55edSMark Brown #define WM8961_WSEQ_START 0x0080 /* WSEQ_START */ 81674dc55edSMark Brown #define WM8961_WSEQ_START_MASK 0x0080 /* WSEQ_START */ 81774dc55edSMark Brown #define WM8961_WSEQ_START_SHIFT 7 /* WSEQ_START */ 81874dc55edSMark Brown #define WM8961_WSEQ_START_WIDTH 1 /* WSEQ_START */ 81974dc55edSMark Brown #define WM8961_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */ 82074dc55edSMark Brown #define WM8961_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */ 82174dc55edSMark Brown #define WM8961_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */ 82274dc55edSMark Brown 82374dc55edSMark Brown /* 82474dc55edSMark Brown * R91 (0x5B) - Write Sequencer 5 82574dc55edSMark Brown */ 82674dc55edSMark Brown #define WM8961_WSEQ_DATA_WIDTH_MASK 0x0070 /* WSEQ_DATA_WIDTH - [6:4] */ 82774dc55edSMark Brown #define WM8961_WSEQ_DATA_WIDTH_SHIFT 4 /* WSEQ_DATA_WIDTH - [6:4] */ 82874dc55edSMark Brown #define WM8961_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [6:4] */ 82974dc55edSMark Brown #define WM8961_WSEQ_DATA_START_MASK 0x000F /* WSEQ_DATA_START - [3:0] */ 83074dc55edSMark Brown #define WM8961_WSEQ_DATA_START_SHIFT 0 /* WSEQ_DATA_START - [3:0] */ 83174dc55edSMark Brown #define WM8961_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [3:0] */ 83274dc55edSMark Brown 83374dc55edSMark Brown /* 83474dc55edSMark Brown * R92 (0x5C) - Write Sequencer 6 83574dc55edSMark Brown */ 83674dc55edSMark Brown #define WM8961_WSEQ_DELAY_MASK 0x000F /* WSEQ_DELAY - [3:0] */ 83774dc55edSMark Brown #define WM8961_WSEQ_DELAY_SHIFT 0 /* WSEQ_DELAY - [3:0] */ 83874dc55edSMark Brown #define WM8961_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [3:0] */ 83974dc55edSMark Brown 84074dc55edSMark Brown /* 84174dc55edSMark Brown * R93 (0x5D) - Write Sequencer 7 84274dc55edSMark Brown */ 84374dc55edSMark Brown #define WM8961_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ 84474dc55edSMark Brown #define WM8961_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ 84574dc55edSMark Brown #define WM8961_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ 84674dc55edSMark Brown #define WM8961_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 84774dc55edSMark Brown 84874dc55edSMark Brown /* 84974dc55edSMark Brown * R252 (0xFC) - General test 1 85074dc55edSMark Brown */ 85174dc55edSMark Brown #define WM8961_ARA_ENA 0x0002 /* ARA_ENA */ 85274dc55edSMark Brown #define WM8961_ARA_ENA_MASK 0x0002 /* ARA_ENA */ 85374dc55edSMark Brown #define WM8961_ARA_ENA_SHIFT 1 /* ARA_ENA */ 85474dc55edSMark Brown #define WM8961_ARA_ENA_WIDTH 1 /* ARA_ENA */ 85574dc55edSMark Brown #define WM8961_AUTO_INC 0x0001 /* AUTO_INC */ 85674dc55edSMark Brown #define WM8961_AUTO_INC_MASK 0x0001 /* AUTO_INC */ 85774dc55edSMark Brown #define WM8961_AUTO_INC_SHIFT 0 /* AUTO_INC */ 85874dc55edSMark Brown #define WM8961_AUTO_INC_WIDTH 1 /* AUTO_INC */ 85974dc55edSMark Brown 86074dc55edSMark Brown #endif 861