1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2b35a28afSMark Brown /*
3b35a28afSMark Brown * wm8955.c -- WM8955 ALSA SoC Audio driver
4b35a28afSMark Brown *
5b35a28afSMark Brown * Copyright 2009 Wolfson Microelectronics plc
6b35a28afSMark Brown *
7b35a28afSMark Brown * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8b35a28afSMark Brown */
9b35a28afSMark Brown
10b35a28afSMark Brown #include <linux/module.h>
11b35a28afSMark Brown #include <linux/moduleparam.h>
12b35a28afSMark Brown #include <linux/init.h>
13b35a28afSMark Brown #include <linux/delay.h>
14b35a28afSMark Brown #include <linux/pm.h>
15b35a28afSMark Brown #include <linux/i2c.h>
1695860fdfSMark Brown #include <linux/regmap.h>
17b35a28afSMark Brown #include <linux/regulator/consumer.h>
185a0e3ad6STejun Heo #include <linux/slab.h>
19b35a28afSMark Brown #include <sound/core.h>
20b35a28afSMark Brown #include <sound/pcm.h>
21b35a28afSMark Brown #include <sound/pcm_params.h>
22b35a28afSMark Brown #include <sound/soc.h>
23b35a28afSMark Brown #include <sound/initval.h>
24b35a28afSMark Brown #include <sound/tlv.h>
25b35a28afSMark Brown #include <sound/wm8955.h>
26b35a28afSMark Brown
27b35a28afSMark Brown #include "wm8955.h"
28b35a28afSMark Brown
29b35a28afSMark Brown #define WM8955_NUM_SUPPLIES 4
30b35a28afSMark Brown static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
31b35a28afSMark Brown "DCVDD",
32b35a28afSMark Brown "DBVDD",
33b35a28afSMark Brown "HPVDD",
34b35a28afSMark Brown "AVDD",
35b35a28afSMark Brown };
36b35a28afSMark Brown
37b35a28afSMark Brown /* codec private data */
38b35a28afSMark Brown struct wm8955_priv {
3995860fdfSMark Brown struct regmap *regmap;
40f0fba2adSLiam Girdwood
41b35a28afSMark Brown unsigned int mclk_rate;
42b35a28afSMark Brown
43b35a28afSMark Brown int deemph;
44b35a28afSMark Brown int fs;
45b35a28afSMark Brown
46b35a28afSMark Brown struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
47b35a28afSMark Brown };
48b35a28afSMark Brown
4995860fdfSMark Brown static const struct reg_default wm8955_reg_defaults[] = {
5095860fdfSMark Brown { 2, 0x0079 }, /* R2 - LOUT1 volume */
5195860fdfSMark Brown { 3, 0x0079 }, /* R3 - ROUT1 volume */
5295860fdfSMark Brown { 5, 0x0008 }, /* R5 - DAC Control */
5395860fdfSMark Brown { 7, 0x000A }, /* R7 - Audio Interface */
5495860fdfSMark Brown { 8, 0x0000 }, /* R8 - Sample Rate */
5595860fdfSMark Brown { 10, 0x00FF }, /* R10 - Left DAC volume */
5695860fdfSMark Brown { 11, 0x00FF }, /* R11 - Right DAC volume */
5795860fdfSMark Brown { 12, 0x000F }, /* R12 - Bass control */
5895860fdfSMark Brown { 13, 0x000F }, /* R13 - Treble control */
5995860fdfSMark Brown { 23, 0x00C1 }, /* R23 - Additional control (1) */
6095860fdfSMark Brown { 24, 0x0000 }, /* R24 - Additional control (2) */
6195860fdfSMark Brown { 25, 0x0000 }, /* R25 - Power Management (1) */
6295860fdfSMark Brown { 26, 0x0000 }, /* R26 - Power Management (2) */
6395860fdfSMark Brown { 27, 0x0000 }, /* R27 - Additional Control (3) */
6495860fdfSMark Brown { 34, 0x0050 }, /* R34 - Left out Mix (1) */
6595860fdfSMark Brown { 35, 0x0050 }, /* R35 - Left out Mix (2) */
6695860fdfSMark Brown { 36, 0x0050 }, /* R36 - Right out Mix (1) */
6795860fdfSMark Brown { 37, 0x0050 }, /* R37 - Right Out Mix (2) */
6895860fdfSMark Brown { 38, 0x0050 }, /* R38 - Mono out Mix (1) */
6995860fdfSMark Brown { 39, 0x0050 }, /* R39 - Mono out Mix (2) */
7095860fdfSMark Brown { 40, 0x0079 }, /* R40 - LOUT2 volume */
7195860fdfSMark Brown { 41, 0x0079 }, /* R41 - ROUT2 volume */
7295860fdfSMark Brown { 42, 0x0079 }, /* R42 - MONOOUT volume */
7395860fdfSMark Brown { 43, 0x0000 }, /* R43 - Clocking / PLL */
7495860fdfSMark Brown { 44, 0x0103 }, /* R44 - PLL Control 1 */
7595860fdfSMark Brown { 45, 0x0024 }, /* R45 - PLL Control 2 */
7695860fdfSMark Brown { 46, 0x01BA }, /* R46 - PLL Control 3 */
7795860fdfSMark Brown { 59, 0x0000 }, /* R59 - PLL Control 4 */
78b35a28afSMark Brown };
79b35a28afSMark Brown
wm8955_writeable(struct device * dev,unsigned int reg)8095860fdfSMark Brown static bool wm8955_writeable(struct device *dev, unsigned int reg)
8195860fdfSMark Brown {
8295860fdfSMark Brown switch (reg) {
8395860fdfSMark Brown case WM8955_LOUT1_VOLUME:
8495860fdfSMark Brown case WM8955_ROUT1_VOLUME:
8595860fdfSMark Brown case WM8955_DAC_CONTROL:
8695860fdfSMark Brown case WM8955_AUDIO_INTERFACE:
8795860fdfSMark Brown case WM8955_SAMPLE_RATE:
8895860fdfSMark Brown case WM8955_LEFT_DAC_VOLUME:
8995860fdfSMark Brown case WM8955_RIGHT_DAC_VOLUME:
9095860fdfSMark Brown case WM8955_BASS_CONTROL:
9195860fdfSMark Brown case WM8955_TREBLE_CONTROL:
9295860fdfSMark Brown case WM8955_RESET:
9395860fdfSMark Brown case WM8955_ADDITIONAL_CONTROL_1:
9495860fdfSMark Brown case WM8955_ADDITIONAL_CONTROL_2:
9595860fdfSMark Brown case WM8955_POWER_MANAGEMENT_1:
9695860fdfSMark Brown case WM8955_POWER_MANAGEMENT_2:
9795860fdfSMark Brown case WM8955_ADDITIONAL_CONTROL_3:
9895860fdfSMark Brown case WM8955_LEFT_OUT_MIX_1:
9995860fdfSMark Brown case WM8955_LEFT_OUT_MIX_2:
10095860fdfSMark Brown case WM8955_RIGHT_OUT_MIX_1:
10195860fdfSMark Brown case WM8955_RIGHT_OUT_MIX_2:
10295860fdfSMark Brown case WM8955_MONO_OUT_MIX_1:
10395860fdfSMark Brown case WM8955_MONO_OUT_MIX_2:
10495860fdfSMark Brown case WM8955_LOUT2_VOLUME:
10595860fdfSMark Brown case WM8955_ROUT2_VOLUME:
10695860fdfSMark Brown case WM8955_MONOOUT_VOLUME:
10795860fdfSMark Brown case WM8955_CLOCKING_PLL:
10895860fdfSMark Brown case WM8955_PLL_CONTROL_1:
10995860fdfSMark Brown case WM8955_PLL_CONTROL_2:
11095860fdfSMark Brown case WM8955_PLL_CONTROL_3:
11195860fdfSMark Brown case WM8955_PLL_CONTROL_4:
11295860fdfSMark Brown return true;
11395860fdfSMark Brown default:
11495860fdfSMark Brown return false;
11595860fdfSMark Brown }
11695860fdfSMark Brown }
11795860fdfSMark Brown
wm8955_volatile(struct device * dev,unsigned int reg)11895860fdfSMark Brown static bool wm8955_volatile(struct device *dev, unsigned int reg)
11995860fdfSMark Brown {
12095860fdfSMark Brown switch (reg) {
12195860fdfSMark Brown case WM8955_RESET:
12295860fdfSMark Brown return true;
12395860fdfSMark Brown default:
12495860fdfSMark Brown return false;
12595860fdfSMark Brown }
12695860fdfSMark Brown }
12795860fdfSMark Brown
wm8955_reset(struct snd_soc_component * component)12869b626e6SKuninori Morimoto static int wm8955_reset(struct snd_soc_component *component)
129b35a28afSMark Brown {
13069b626e6SKuninori Morimoto return snd_soc_component_write(component, WM8955_RESET, 0);
131b35a28afSMark Brown }
132b35a28afSMark Brown
133b35a28afSMark Brown struct pll_factors {
134b35a28afSMark Brown int n;
135b35a28afSMark Brown int k;
136b35a28afSMark Brown int outdiv;
137b35a28afSMark Brown };
138b35a28afSMark Brown
139b35a28afSMark Brown /* The size in bits of the FLL divide multiplied by 10
140b35a28afSMark Brown * to allow rounding later */
141b35a28afSMark Brown #define FIXED_FLL_SIZE ((1 << 22) * 10)
142b35a28afSMark Brown
wm8955_pll_factors(struct device * dev,int Fref,int Fout,struct pll_factors * pll)143e8758a5eSChristophe JAILLET static int wm8955_pll_factors(struct device *dev,
144b35a28afSMark Brown int Fref, int Fout, struct pll_factors *pll)
145b35a28afSMark Brown {
146b35a28afSMark Brown u64 Kpart;
147b35a28afSMark Brown unsigned int K, Ndiv, Nmod, target;
148b35a28afSMark Brown
149b35a28afSMark Brown dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout);
150b35a28afSMark Brown
151b35a28afSMark Brown /* The oscilator should run at should be 90-100MHz, and
152b35a28afSMark Brown * there's a divide by 4 plus an optional divide by 2 in the
153b35a28afSMark Brown * output path to generate the system clock. The clock table
154b35a28afSMark Brown * is sortd so we should always generate a suitable target. */
155b35a28afSMark Brown target = Fout * 4;
156b35a28afSMark Brown if (target < 90000000) {
157b35a28afSMark Brown pll->outdiv = 1;
158b35a28afSMark Brown target *= 2;
159b35a28afSMark Brown } else {
160b35a28afSMark Brown pll->outdiv = 0;
161b35a28afSMark Brown }
162b35a28afSMark Brown
163b35a28afSMark Brown WARN_ON(target < 90000000 || target > 100000000);
164b35a28afSMark Brown
165b35a28afSMark Brown dev_dbg(dev, "Fvco=%dHz\n", target);
166b35a28afSMark Brown
167b35a28afSMark Brown /* Now, calculate N.K */
168b35a28afSMark Brown Ndiv = target / Fref;
169b35a28afSMark Brown
170b35a28afSMark Brown pll->n = Ndiv;
171b35a28afSMark Brown Nmod = target % Fref;
172b35a28afSMark Brown dev_dbg(dev, "Nmod=%d\n", Nmod);
173b35a28afSMark Brown
174b35a28afSMark Brown /* Calculate fractional part - scale up so we can round. */
175b35a28afSMark Brown Kpart = FIXED_FLL_SIZE * (long long)Nmod;
176b35a28afSMark Brown
177b35a28afSMark Brown do_div(Kpart, Fref);
178b35a28afSMark Brown
179b35a28afSMark Brown K = Kpart & 0xFFFFFFFF;
180b35a28afSMark Brown
181b35a28afSMark Brown if ((K % 10) >= 5)
182b35a28afSMark Brown K += 5;
183b35a28afSMark Brown
184b35a28afSMark Brown /* Move down to proper range now rounding is done */
185b35a28afSMark Brown pll->k = K / 10;
186b35a28afSMark Brown
187b35a28afSMark Brown dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
188b35a28afSMark Brown
189b35a28afSMark Brown return 0;
190b35a28afSMark Brown }
191b35a28afSMark Brown
19225985edcSLucas De Marchi /* Lookup table specifying SRATE (table 25 in datasheet); some of the
193b35a28afSMark Brown * output frequencies have been rounded to the standard frequencies
194b35a28afSMark Brown * they are intended to match where the error is slight. */
195b35a28afSMark Brown static struct {
196b35a28afSMark Brown int mclk;
197b35a28afSMark Brown int fs;
198b35a28afSMark Brown int usb;
199b35a28afSMark Brown int sr;
200b35a28afSMark Brown } clock_cfgs[] = {
201b35a28afSMark Brown { 18432000, 8000, 0, 3, },
202b35a28afSMark Brown { 18432000, 12000, 0, 9, },
203b35a28afSMark Brown { 18432000, 16000, 0, 11, },
204b35a28afSMark Brown { 18432000, 24000, 0, 29, },
205b35a28afSMark Brown { 18432000, 32000, 0, 13, },
206b35a28afSMark Brown { 18432000, 48000, 0, 1, },
207b35a28afSMark Brown { 18432000, 96000, 0, 15, },
208b35a28afSMark Brown
209b35a28afSMark Brown { 16934400, 8018, 0, 19, },
210b35a28afSMark Brown { 16934400, 11025, 0, 25, },
211b35a28afSMark Brown { 16934400, 22050, 0, 27, },
212b35a28afSMark Brown { 16934400, 44100, 0, 17, },
213b35a28afSMark Brown { 16934400, 88200, 0, 31, },
214b35a28afSMark Brown
215b35a28afSMark Brown { 12000000, 8000, 1, 2, },
216b35a28afSMark Brown { 12000000, 11025, 1, 25, },
217b35a28afSMark Brown { 12000000, 12000, 1, 8, },
218b35a28afSMark Brown { 12000000, 16000, 1, 10, },
219b35a28afSMark Brown { 12000000, 22050, 1, 27, },
220b35a28afSMark Brown { 12000000, 24000, 1, 28, },
221b35a28afSMark Brown { 12000000, 32000, 1, 12, },
222b35a28afSMark Brown { 12000000, 44100, 1, 17, },
223b35a28afSMark Brown { 12000000, 48000, 1, 0, },
224b35a28afSMark Brown { 12000000, 88200, 1, 31, },
225b35a28afSMark Brown { 12000000, 96000, 1, 14, },
226b35a28afSMark Brown
227b35a28afSMark Brown { 12288000, 8000, 0, 2, },
228b35a28afSMark Brown { 12288000, 12000, 0, 8, },
229b35a28afSMark Brown { 12288000, 16000, 0, 10, },
230b35a28afSMark Brown { 12288000, 24000, 0, 28, },
231b35a28afSMark Brown { 12288000, 32000, 0, 12, },
232b35a28afSMark Brown { 12288000, 48000, 0, 0, },
233b35a28afSMark Brown { 12288000, 96000, 0, 14, },
234b35a28afSMark Brown
235b35a28afSMark Brown { 12289600, 8018, 0, 18, },
236b35a28afSMark Brown { 12289600, 11025, 0, 24, },
237b35a28afSMark Brown { 12289600, 22050, 0, 26, },
238b35a28afSMark Brown { 11289600, 44100, 0, 16, },
239b35a28afSMark Brown { 11289600, 88200, 0, 31, },
240b35a28afSMark Brown };
241b35a28afSMark Brown
wm8955_configure_clocking(struct snd_soc_component * component)24269b626e6SKuninori Morimoto static int wm8955_configure_clocking(struct snd_soc_component *component)
243b35a28afSMark Brown {
24469b626e6SKuninori Morimoto struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
245b35a28afSMark Brown int i, ret, val;
246b35a28afSMark Brown int clocking = 0;
247b35a28afSMark Brown int srate = 0;
248b35a28afSMark Brown int sr = -1;
249b35a28afSMark Brown struct pll_factors pll;
250b35a28afSMark Brown
251b35a28afSMark Brown /* If we're not running a sample rate currently just pick one */
252b35a28afSMark Brown if (wm8955->fs == 0)
253b35a28afSMark Brown wm8955->fs = 8000;
254b35a28afSMark Brown
255b35a28afSMark Brown /* Can we generate an exact output? */
256b35a28afSMark Brown for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) {
257b35a28afSMark Brown if (wm8955->fs != clock_cfgs[i].fs)
258b35a28afSMark Brown continue;
259b35a28afSMark Brown sr = i;
260b35a28afSMark Brown
261b35a28afSMark Brown if (wm8955->mclk_rate == clock_cfgs[i].mclk)
262b35a28afSMark Brown break;
263b35a28afSMark Brown }
264b35a28afSMark Brown
265b35a28afSMark Brown /* We should never get here with an unsupported sample rate */
266b35a28afSMark Brown if (sr == -1) {
26769b626e6SKuninori Morimoto dev_err(component->dev, "Sample rate %dHz unsupported\n",
268b35a28afSMark Brown wm8955->fs);
269b35a28afSMark Brown WARN_ON(sr == -1);
270b35a28afSMark Brown return -EINVAL;
271b35a28afSMark Brown }
272b35a28afSMark Brown
273b35a28afSMark Brown if (i == ARRAY_SIZE(clock_cfgs)) {
274b35a28afSMark Brown /* If we can't generate the right clock from MCLK then
275b35a28afSMark Brown * we should configure the PLL to supply us with an
276b35a28afSMark Brown * appropriate clock.
277b35a28afSMark Brown */
278b35a28afSMark Brown clocking |= WM8955_MCLKSEL;
279b35a28afSMark Brown
280b35a28afSMark Brown /* Use the last divider configuration we saw for the
281b35a28afSMark Brown * sample rate. */
282e8758a5eSChristophe JAILLET ret = wm8955_pll_factors(component->dev, wm8955->mclk_rate,
283b35a28afSMark Brown clock_cfgs[sr].mclk, &pll);
284b35a28afSMark Brown if (ret != 0) {
28569b626e6SKuninori Morimoto dev_err(component->dev,
286b35a28afSMark Brown "Unable to generate %dHz from %dHz MCLK\n",
287b35a28afSMark Brown wm8955->fs, wm8955->mclk_rate);
288b35a28afSMark Brown return -EINVAL;
289b35a28afSMark Brown }
290b35a28afSMark Brown
29169b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_1,
292b35a28afSMark Brown WM8955_N_MASK | WM8955_K_21_18_MASK,
293b35a28afSMark Brown (pll.n << WM8955_N_SHIFT) |
294b35a28afSMark Brown pll.k >> 18);
29569b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_2,
296b35a28afSMark Brown WM8955_K_17_9_MASK,
297b35a28afSMark Brown (pll.k >> 9) & WM8955_K_17_9_MASK);
29869b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_3,
299b35a28afSMark Brown WM8955_K_8_0_MASK,
300b35a28afSMark Brown pll.k & WM8955_K_8_0_MASK);
301b35a28afSMark Brown if (pll.k)
30269b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_4,
303b35a28afSMark Brown WM8955_KEN, WM8955_KEN);
304b35a28afSMark Brown else
30569b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_4,
306b35a28afSMark Brown WM8955_KEN, 0);
307b35a28afSMark Brown
308b35a28afSMark Brown if (pll.outdiv)
309b35a28afSMark Brown val = WM8955_PLL_RB | WM8955_PLLOUTDIV2;
310b35a28afSMark Brown else
311b35a28afSMark Brown val = WM8955_PLL_RB;
312b35a28afSMark Brown
313b35a28afSMark Brown /* Now start the PLL running */
31469b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
315b35a28afSMark Brown WM8955_PLL_RB | WM8955_PLLOUTDIV2, val);
31669b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
317b35a28afSMark Brown WM8955_PLLEN, WM8955_PLLEN);
318b35a28afSMark Brown }
319b35a28afSMark Brown
320b35a28afSMark Brown srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT);
321b35a28afSMark Brown
32269b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_SAMPLE_RATE,
323b35a28afSMark Brown WM8955_USB | WM8955_SR_MASK, srate);
32469b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
325b35a28afSMark Brown WM8955_MCLKSEL, clocking);
326b35a28afSMark Brown
327b35a28afSMark Brown return 0;
328b35a28afSMark Brown }
329b35a28afSMark Brown
wm8955_sysclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)330b35a28afSMark Brown static int wm8955_sysclk(struct snd_soc_dapm_widget *w,
331b35a28afSMark Brown struct snd_kcontrol *kcontrol, int event)
332b35a28afSMark Brown {
33369b626e6SKuninori Morimoto struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
334b35a28afSMark Brown int ret = 0;
335b35a28afSMark Brown
336b35a28afSMark Brown /* Always disable the clocks - if we're doing reconfiguration this
337b35a28afSMark Brown * avoids misclocking.
338b35a28afSMark Brown */
33969b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
340b35a28afSMark Brown WM8955_DIGENB, 0);
34169b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
342b35a28afSMark Brown WM8955_PLL_RB | WM8955_PLLEN, 0);
343b35a28afSMark Brown
344b35a28afSMark Brown switch (event) {
345b35a28afSMark Brown case SND_SOC_DAPM_POST_PMD:
346b35a28afSMark Brown break;
347b35a28afSMark Brown case SND_SOC_DAPM_PRE_PMU:
34869b626e6SKuninori Morimoto ret = wm8955_configure_clocking(component);
349b35a28afSMark Brown break;
350b35a28afSMark Brown default:
351b35a28afSMark Brown ret = -EINVAL;
352b35a28afSMark Brown break;
353b35a28afSMark Brown }
354b35a28afSMark Brown
355b35a28afSMark Brown return ret;
356b35a28afSMark Brown }
357b35a28afSMark Brown
358b35a28afSMark Brown static int deemph_settings[] = { 0, 32000, 44100, 48000 };
359b35a28afSMark Brown
wm8955_set_deemph(struct snd_soc_component * component)36069b626e6SKuninori Morimoto static int wm8955_set_deemph(struct snd_soc_component *component)
361b35a28afSMark Brown {
36269b626e6SKuninori Morimoto struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
363b35a28afSMark Brown int val, i, best;
364b35a28afSMark Brown
365b35a28afSMark Brown /* If we're using deemphasis select the nearest available sample
366b35a28afSMark Brown * rate.
367b35a28afSMark Brown */
368b35a28afSMark Brown if (wm8955->deemph) {
369b35a28afSMark Brown best = 1;
370b35a28afSMark Brown for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
371b35a28afSMark Brown if (abs(deemph_settings[i] - wm8955->fs) <
372b35a28afSMark Brown abs(deemph_settings[best] - wm8955->fs))
373b35a28afSMark Brown best = i;
374b35a28afSMark Brown }
375b35a28afSMark Brown
376b35a28afSMark Brown val = best << WM8955_DEEMPH_SHIFT;
377b35a28afSMark Brown } else {
378b35a28afSMark Brown val = 0;
379b35a28afSMark Brown }
380b35a28afSMark Brown
38169b626e6SKuninori Morimoto dev_dbg(component->dev, "Set deemphasis %d\n", val);
382b35a28afSMark Brown
38369b626e6SKuninori Morimoto return snd_soc_component_update_bits(component, WM8955_DAC_CONTROL,
384b35a28afSMark Brown WM8955_DEEMPH_MASK, val);
385b35a28afSMark Brown }
386b35a28afSMark Brown
wm8955_get_deemph(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)387b35a28afSMark Brown static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
388b35a28afSMark Brown struct snd_ctl_elem_value *ucontrol)
389b35a28afSMark Brown {
39069b626e6SKuninori Morimoto struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
39169b626e6SKuninori Morimoto struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
392b35a28afSMark Brown
39307892b10STakashi Iwai ucontrol->value.integer.value[0] = wm8955->deemph;
3943f343f85SDmitry Artamonow return 0;
395b35a28afSMark Brown }
396b35a28afSMark Brown
wm8955_put_deemph(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)397b35a28afSMark Brown static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
398b35a28afSMark Brown struct snd_ctl_elem_value *ucontrol)
399b35a28afSMark Brown {
40069b626e6SKuninori Morimoto struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
40169b626e6SKuninori Morimoto struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
4023e2a71b2SDan Carpenter unsigned int deemph = ucontrol->value.integer.value[0];
403b35a28afSMark Brown
404b35a28afSMark Brown if (deemph > 1)
405b35a28afSMark Brown return -EINVAL;
406b35a28afSMark Brown
407b35a28afSMark Brown wm8955->deemph = deemph;
408b35a28afSMark Brown
40969b626e6SKuninori Morimoto return wm8955_set_deemph(component);
410b35a28afSMark Brown }
411b35a28afSMark Brown
412b35a28afSMark Brown static const char *bass_mode_text[] = {
413b35a28afSMark Brown "Linear", "Adaptive",
414b35a28afSMark Brown };
415b35a28afSMark Brown
41654db41c1STakashi Iwai static SOC_ENUM_SINGLE_DECL(bass_mode, WM8955_BASS_CONTROL, 7, bass_mode_text);
417b35a28afSMark Brown
418b35a28afSMark Brown static const char *bass_cutoff_text[] = {
419b35a28afSMark Brown "Low", "High"
420b35a28afSMark Brown };
421b35a28afSMark Brown
42254db41c1STakashi Iwai static SOC_ENUM_SINGLE_DECL(bass_cutoff, WM8955_BASS_CONTROL, 6,
42354db41c1STakashi Iwai bass_cutoff_text);
424b35a28afSMark Brown
425b35a28afSMark Brown static const char *treble_cutoff_text[] = {
426b35a28afSMark Brown "High", "Low"
427b35a28afSMark Brown };
428b35a28afSMark Brown
42954db41c1STakashi Iwai static SOC_ENUM_SINGLE_DECL(treble_cutoff, WM8955_TREBLE_CONTROL, 2,
43054db41c1STakashi Iwai treble_cutoff_text);
431b35a28afSMark Brown
432b35a28afSMark Brown static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
433b35a28afSMark Brown static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0);
434b35a28afSMark Brown static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
435b35a28afSMark Brown static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0);
436b35a28afSMark Brown static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
437b35a28afSMark Brown static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1);
438b35a28afSMark Brown
439b35a28afSMark Brown static const struct snd_kcontrol_new wm8955_snd_controls[] = {
440b35a28afSMark Brown SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME,
441b35a28afSMark Brown WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv),
442b35a28afSMark Brown SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1,
443b35a28afSMark Brown atten_tlv),
444b35a28afSMark Brown SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
445b35a28afSMark Brown wm8955_get_deemph, wm8955_put_deemph),
446b35a28afSMark Brown
447b35a28afSMark Brown SOC_ENUM("Bass Mode", bass_mode),
448b35a28afSMark Brown SOC_ENUM("Bass Cutoff", bass_cutoff),
449b35a28afSMark Brown SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1),
450b35a28afSMark Brown
451b35a28afSMark Brown SOC_ENUM("Treble Cutoff", treble_cutoff),
452b35a28afSMark Brown SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv),
453b35a28afSMark Brown
454b35a28afSMark Brown SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1,
455b35a28afSMark Brown bypass_tlv),
456b35a28afSMark Brown SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1,
457b35a28afSMark Brown bypass_tlv),
458b35a28afSMark Brown
459b35a28afSMark Brown SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1,
460b35a28afSMark Brown bypass_tlv),
461b35a28afSMark Brown SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1,
462b35a28afSMark Brown bypass_tlv),
463b35a28afSMark Brown
464b35a28afSMark Brown /* Not a stereo pair so they line up with the DAPM switches */
465b35a28afSMark Brown SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1,
466b35a28afSMark Brown mono_tlv),
467b35a28afSMark Brown SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1,
468b35a28afSMark Brown mono_tlv),
469b35a28afSMark Brown
470b35a28afSMark Brown SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME,
471b35a28afSMark Brown WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv),
472b35a28afSMark Brown SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME,
473b35a28afSMark Brown WM8955_ROUT1_VOLUME, 7, 1, 0),
474b35a28afSMark Brown
475b35a28afSMark Brown SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME,
476b35a28afSMark Brown WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv),
477b35a28afSMark Brown SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME,
478b35a28afSMark Brown WM8955_ROUT2_VOLUME, 7, 1, 0),
479b35a28afSMark Brown
480b35a28afSMark Brown SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv),
481b35a28afSMark Brown SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0),
482b35a28afSMark Brown };
483b35a28afSMark Brown
484b35a28afSMark Brown static const struct snd_kcontrol_new lmixer[] = {
485b35a28afSMark Brown SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0),
486b35a28afSMark Brown SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0),
487b35a28afSMark Brown SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0),
488b35a28afSMark Brown SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0),
489b35a28afSMark Brown };
490b35a28afSMark Brown
491b35a28afSMark Brown static const struct snd_kcontrol_new rmixer[] = {
492b35a28afSMark Brown SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0),
493b35a28afSMark Brown SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0),
494b35a28afSMark Brown SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0),
495b35a28afSMark Brown SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0),
496b35a28afSMark Brown };
497b35a28afSMark Brown
498b35a28afSMark Brown static const struct snd_kcontrol_new mmixer[] = {
499b35a28afSMark Brown SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0),
500b35a28afSMark Brown SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0),
501b35a28afSMark Brown SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0),
502b35a28afSMark Brown SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0),
503b35a28afSMark Brown };
504b35a28afSMark Brown
505b35a28afSMark Brown static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = {
506b35a28afSMark Brown SND_SOC_DAPM_INPUT("MONOIN-"),
507b35a28afSMark Brown SND_SOC_DAPM_INPUT("MONOIN+"),
508b35a28afSMark Brown SND_SOC_DAPM_INPUT("LINEINR"),
509b35a28afSMark Brown SND_SOC_DAPM_INPUT("LINEINL"),
510b35a28afSMark Brown
511b35a28afSMark Brown SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0),
512b35a28afSMark Brown
513b35a28afSMark Brown SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk,
514b35a28afSMark Brown SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
515b35a28afSMark Brown SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0),
516b35a28afSMark Brown
517b35a28afSMark Brown SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0),
518b35a28afSMark Brown SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0),
519b35a28afSMark Brown
520b35a28afSMark Brown SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
521b35a28afSMark Brown SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
522b35a28afSMark Brown SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
523b35a28afSMark Brown SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0),
524b35a28afSMark Brown SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0),
525b35a28afSMark Brown SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
526b35a28afSMark Brown
527b35a28afSMark Brown /* The names are chosen to make the control names nice */
528b35a28afSMark Brown SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0,
529b35a28afSMark Brown lmixer, ARRAY_SIZE(lmixer)),
530b35a28afSMark Brown SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0,
531b35a28afSMark Brown rmixer, ARRAY_SIZE(rmixer)),
532b35a28afSMark Brown SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0,
533b35a28afSMark Brown mmixer, ARRAY_SIZE(mmixer)),
534b35a28afSMark Brown
535b35a28afSMark Brown SND_SOC_DAPM_OUTPUT("LOUT1"),
536b35a28afSMark Brown SND_SOC_DAPM_OUTPUT("ROUT1"),
537b35a28afSMark Brown SND_SOC_DAPM_OUTPUT("LOUT2"),
538b35a28afSMark Brown SND_SOC_DAPM_OUTPUT("ROUT2"),
539b35a28afSMark Brown SND_SOC_DAPM_OUTPUT("MONOOUT"),
540b35a28afSMark Brown SND_SOC_DAPM_OUTPUT("OUT3"),
541b35a28afSMark Brown };
542b35a28afSMark Brown
5433294c4c6SMark Brown static const struct snd_soc_dapm_route wm8955_dapm_routes[] = {
544b35a28afSMark Brown { "DACL", NULL, "SYSCLK" },
545b35a28afSMark Brown { "DACR", NULL, "SYSCLK" },
546b35a28afSMark Brown
547b35a28afSMark Brown { "Mono Input", NULL, "MONOIN-" },
548b35a28afSMark Brown { "Mono Input", NULL, "MONOIN+" },
549b35a28afSMark Brown
550b35a28afSMark Brown { "Left", "Playback Switch", "DACL" },
551b35a28afSMark Brown { "Left", "Right Playback Switch", "DACR" },
552b35a28afSMark Brown { "Left", "Bypass Switch", "LINEINL" },
553b35a28afSMark Brown { "Left", "Mono Switch", "Mono Input" },
554b35a28afSMark Brown
555b35a28afSMark Brown { "Right", "Playback Switch", "DACR" },
556b35a28afSMark Brown { "Right", "Left Playback Switch", "DACL" },
557b35a28afSMark Brown { "Right", "Bypass Switch", "LINEINR" },
558b35a28afSMark Brown { "Right", "Mono Switch", "Mono Input" },
559b35a28afSMark Brown
560b35a28afSMark Brown { "Mono", "Left Playback Switch", "DACL" },
561b35a28afSMark Brown { "Mono", "Right Playback Switch", "DACR" },
562b35a28afSMark Brown { "Mono", "Left Bypass Switch", "LINEINL" },
563b35a28afSMark Brown { "Mono", "Right Bypass Switch", "LINEINR" },
564b35a28afSMark Brown
565b35a28afSMark Brown { "LOUT1 PGA", NULL, "Left" },
566b35a28afSMark Brown { "LOUT1", NULL, "TSDEN" },
567b35a28afSMark Brown { "LOUT1", NULL, "LOUT1 PGA" },
568b35a28afSMark Brown
569b35a28afSMark Brown { "ROUT1 PGA", NULL, "Right" },
570b35a28afSMark Brown { "ROUT1", NULL, "TSDEN" },
571b35a28afSMark Brown { "ROUT1", NULL, "ROUT1 PGA" },
572b35a28afSMark Brown
573b35a28afSMark Brown { "LOUT2 PGA", NULL, "Left" },
574b35a28afSMark Brown { "LOUT2", NULL, "TSDEN" },
575b35a28afSMark Brown { "LOUT2", NULL, "LOUT2 PGA" },
576b35a28afSMark Brown
577b35a28afSMark Brown { "ROUT2 PGA", NULL, "Right" },
578b35a28afSMark Brown { "ROUT2", NULL, "TSDEN" },
579b35a28afSMark Brown { "ROUT2", NULL, "ROUT2 PGA" },
580b35a28afSMark Brown
581b35a28afSMark Brown { "MOUT PGA", NULL, "Mono" },
582b35a28afSMark Brown { "MONOOUT", NULL, "MOUT PGA" },
583b35a28afSMark Brown
584b35a28afSMark Brown /* OUT3 not currently implemented */
585b35a28afSMark Brown { "OUT3", NULL, "OUT3 PGA" },
586b35a28afSMark Brown };
587b35a28afSMark Brown
wm8955_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)588b35a28afSMark Brown static int wm8955_hw_params(struct snd_pcm_substream *substream,
589b35a28afSMark Brown struct snd_pcm_hw_params *params,
590b35a28afSMark Brown struct snd_soc_dai *dai)
591b35a28afSMark Brown {
59269b626e6SKuninori Morimoto struct snd_soc_component *component = dai->component;
59369b626e6SKuninori Morimoto struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
594b35a28afSMark Brown int ret;
595b35a28afSMark Brown int wl;
596b35a28afSMark Brown
5971df93ca3SMark Brown switch (params_width(params)) {
5981df93ca3SMark Brown case 16:
599b35a28afSMark Brown wl = 0;
600b35a28afSMark Brown break;
6011df93ca3SMark Brown case 20:
602b35a28afSMark Brown wl = 0x4;
603b35a28afSMark Brown break;
6041df93ca3SMark Brown case 24:
605b35a28afSMark Brown wl = 0x8;
606b35a28afSMark Brown break;
6071df93ca3SMark Brown case 32:
608b35a28afSMark Brown wl = 0xc;
609b35a28afSMark Brown break;
610b35a28afSMark Brown default:
611b35a28afSMark Brown return -EINVAL;
612b35a28afSMark Brown }
61369b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_AUDIO_INTERFACE,
614b35a28afSMark Brown WM8955_WL_MASK, wl);
615b35a28afSMark Brown
616b35a28afSMark Brown wm8955->fs = params_rate(params);
61769b626e6SKuninori Morimoto wm8955_set_deemph(component);
618b35a28afSMark Brown
619b35a28afSMark Brown /* If the chip is clocked then disable the clocks and force a
620b35a28afSMark Brown * reconfiguration, otherwise DAPM will power up the
621b35a28afSMark Brown * clocks for us later. */
6226d75dfc3SKuninori Morimoto ret = snd_soc_component_read(component, WM8955_POWER_MANAGEMENT_1);
623b35a28afSMark Brown if (ret < 0)
624b35a28afSMark Brown return ret;
625b35a28afSMark Brown if (ret & WM8955_DIGENB) {
62669b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
627b35a28afSMark Brown WM8955_DIGENB, 0);
62869b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
629b35a28afSMark Brown WM8955_PLL_RB | WM8955_PLLEN, 0);
630b35a28afSMark Brown
63169b626e6SKuninori Morimoto wm8955_configure_clocking(component);
632b35a28afSMark Brown }
633b35a28afSMark Brown
634b35a28afSMark Brown return 0;
635b35a28afSMark Brown }
636b35a28afSMark Brown
637b35a28afSMark Brown
wm8955_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)638b35a28afSMark Brown static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id,
639b35a28afSMark Brown unsigned int freq, int dir)
640b35a28afSMark Brown {
64169b626e6SKuninori Morimoto struct snd_soc_component *component = dai->component;
64269b626e6SKuninori Morimoto struct wm8955_priv *priv = snd_soc_component_get_drvdata(component);
643b35a28afSMark Brown int div;
644b35a28afSMark Brown
645b35a28afSMark Brown switch (clk_id) {
646b35a28afSMark Brown case WM8955_CLK_MCLK:
647b35a28afSMark Brown if (freq > 15000000) {
648b35a28afSMark Brown priv->mclk_rate = freq /= 2;
649b35a28afSMark Brown div = WM8955_MCLKDIV2;
650b35a28afSMark Brown } else {
651b35a28afSMark Brown priv->mclk_rate = freq;
652b35a28afSMark Brown div = 0;
653b35a28afSMark Brown }
654b35a28afSMark Brown
65569b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_SAMPLE_RATE,
656b35a28afSMark Brown WM8955_MCLKDIV2, div);
657b35a28afSMark Brown break;
658b35a28afSMark Brown
659b35a28afSMark Brown default:
660b35a28afSMark Brown return -EINVAL;
661b35a28afSMark Brown }
662b35a28afSMark Brown
663b35a28afSMark Brown dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
664b35a28afSMark Brown
665b35a28afSMark Brown return 0;
666b35a28afSMark Brown }
667b35a28afSMark Brown
wm8955_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)668b35a28afSMark Brown static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
669b35a28afSMark Brown {
67069b626e6SKuninori Morimoto struct snd_soc_component *component = dai->component;
671b35a28afSMark Brown u16 aif = 0;
672b35a28afSMark Brown
673b35a28afSMark Brown switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
674b35a28afSMark Brown case SND_SOC_DAIFMT_CBS_CFS:
675b35a28afSMark Brown break;
676b35a28afSMark Brown case SND_SOC_DAIFMT_CBM_CFM:
677b35a28afSMark Brown aif |= WM8955_MS;
678b35a28afSMark Brown break;
679b35a28afSMark Brown default:
680b35a28afSMark Brown return -EINVAL;
681b35a28afSMark Brown }
682b35a28afSMark Brown
683b35a28afSMark Brown switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
684b35a28afSMark Brown case SND_SOC_DAIFMT_DSP_B:
685b35a28afSMark Brown aif |= WM8955_LRP;
6863e146b55SGustavo A. R. Silva fallthrough;
687b35a28afSMark Brown case SND_SOC_DAIFMT_DSP_A:
688b35a28afSMark Brown aif |= 0x3;
689b35a28afSMark Brown break;
690b35a28afSMark Brown case SND_SOC_DAIFMT_I2S:
691b35a28afSMark Brown aif |= 0x2;
692b35a28afSMark Brown break;
693b35a28afSMark Brown case SND_SOC_DAIFMT_RIGHT_J:
694b35a28afSMark Brown break;
695b35a28afSMark Brown case SND_SOC_DAIFMT_LEFT_J:
696b35a28afSMark Brown aif |= 0x1;
697b35a28afSMark Brown break;
698b35a28afSMark Brown default:
699b35a28afSMark Brown return -EINVAL;
700b35a28afSMark Brown }
701b35a28afSMark Brown
702b35a28afSMark Brown switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
703b35a28afSMark Brown case SND_SOC_DAIFMT_DSP_A:
704b35a28afSMark Brown case SND_SOC_DAIFMT_DSP_B:
705b35a28afSMark Brown /* frame inversion not valid for DSP modes */
706b35a28afSMark Brown switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
707b35a28afSMark Brown case SND_SOC_DAIFMT_NB_NF:
708b35a28afSMark Brown break;
709b35a28afSMark Brown case SND_SOC_DAIFMT_IB_NF:
710b35a28afSMark Brown aif |= WM8955_BCLKINV;
711b35a28afSMark Brown break;
712b35a28afSMark Brown default:
713b35a28afSMark Brown return -EINVAL;
714b35a28afSMark Brown }
715b35a28afSMark Brown break;
716b35a28afSMark Brown
717b35a28afSMark Brown case SND_SOC_DAIFMT_I2S:
718b35a28afSMark Brown case SND_SOC_DAIFMT_RIGHT_J:
719b35a28afSMark Brown case SND_SOC_DAIFMT_LEFT_J:
720b35a28afSMark Brown switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
721b35a28afSMark Brown case SND_SOC_DAIFMT_NB_NF:
722b35a28afSMark Brown break;
723b35a28afSMark Brown case SND_SOC_DAIFMT_IB_IF:
724b35a28afSMark Brown aif |= WM8955_BCLKINV | WM8955_LRP;
725b35a28afSMark Brown break;
726b35a28afSMark Brown case SND_SOC_DAIFMT_IB_NF:
727b35a28afSMark Brown aif |= WM8955_BCLKINV;
728b35a28afSMark Brown break;
729b35a28afSMark Brown case SND_SOC_DAIFMT_NB_IF:
730b35a28afSMark Brown aif |= WM8955_LRP;
731b35a28afSMark Brown break;
732b35a28afSMark Brown default:
733b35a28afSMark Brown return -EINVAL;
734b35a28afSMark Brown }
735b35a28afSMark Brown break;
736b35a28afSMark Brown default:
737b35a28afSMark Brown return -EINVAL;
738b35a28afSMark Brown }
739b35a28afSMark Brown
74069b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_AUDIO_INTERFACE,
741b35a28afSMark Brown WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV |
742b35a28afSMark Brown WM8955_LRP, aif);
743b35a28afSMark Brown
744b35a28afSMark Brown return 0;
745b35a28afSMark Brown }
746b35a28afSMark Brown
747b35a28afSMark Brown
wm8955_mute(struct snd_soc_dai * codec_dai,int mute,int direction)74826d3c16eSKuninori Morimoto static int wm8955_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
749b35a28afSMark Brown {
75069b626e6SKuninori Morimoto struct snd_soc_component *component = codec_dai->component;
751b35a28afSMark Brown int val;
752b35a28afSMark Brown
753b35a28afSMark Brown if (mute)
754b35a28afSMark Brown val = WM8955_DACMU;
755b35a28afSMark Brown else
756b35a28afSMark Brown val = 0;
757b35a28afSMark Brown
75869b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_DAC_CONTROL, WM8955_DACMU, val);
759b35a28afSMark Brown
760b35a28afSMark Brown return 0;
761b35a28afSMark Brown }
762b35a28afSMark Brown
wm8955_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)76369b626e6SKuninori Morimoto static int wm8955_set_bias_level(struct snd_soc_component *component,
764b35a28afSMark Brown enum snd_soc_bias_level level)
765b35a28afSMark Brown {
76669b626e6SKuninori Morimoto struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
76795860fdfSMark Brown int ret;
768b35a28afSMark Brown
769b35a28afSMark Brown switch (level) {
770b35a28afSMark Brown case SND_SOC_BIAS_ON:
771b35a28afSMark Brown break;
772b35a28afSMark Brown
773b35a28afSMark Brown case SND_SOC_BIAS_PREPARE:
774b35a28afSMark Brown /* VMID resistance 2*50k */
77569b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
776b35a28afSMark Brown WM8955_VMIDSEL_MASK,
777b35a28afSMark Brown 0x1 << WM8955_VMIDSEL_SHIFT);
778b35a28afSMark Brown
779b35a28afSMark Brown /* Default bias current */
78069b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_1,
781b35a28afSMark Brown WM8955_VSEL_MASK,
782b35a28afSMark Brown 0x2 << WM8955_VSEL_SHIFT);
783b35a28afSMark Brown break;
784b35a28afSMark Brown
785b35a28afSMark Brown case SND_SOC_BIAS_STANDBY:
78669b626e6SKuninori Morimoto if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
787b35a28afSMark Brown ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
788b35a28afSMark Brown wm8955->supplies);
789b35a28afSMark Brown if (ret != 0) {
79069b626e6SKuninori Morimoto dev_err(component->dev,
791b35a28afSMark Brown "Failed to enable supplies: %d\n",
792b35a28afSMark Brown ret);
793b35a28afSMark Brown return ret;
794b35a28afSMark Brown }
795b35a28afSMark Brown
79695860fdfSMark Brown regcache_sync(wm8955->regmap);
797b35a28afSMark Brown
798b35a28afSMark Brown /* Enable VREF and VMID */
79969b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
800b35a28afSMark Brown WM8955_VREF |
801b35a28afSMark Brown WM8955_VMIDSEL_MASK,
802b35a28afSMark Brown WM8955_VREF |
803b35a28afSMark Brown 0x3 << WM8955_VREF_SHIFT);
804b35a28afSMark Brown
805b35a28afSMark Brown /* Let VMID ramp */
806b35a28afSMark Brown msleep(500);
807b35a28afSMark Brown
808b35a28afSMark Brown /* High resistance VROI to maintain outputs */
80969b626e6SKuninori Morimoto snd_soc_component_update_bits(component,
810b35a28afSMark Brown WM8955_ADDITIONAL_CONTROL_3,
811b35a28afSMark Brown WM8955_VROI, WM8955_VROI);
812b35a28afSMark Brown }
813b35a28afSMark Brown
814b35a28afSMark Brown /* Maintain VMID with 2*250k */
81569b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
816b35a28afSMark Brown WM8955_VMIDSEL_MASK,
817b35a28afSMark Brown 0x2 << WM8955_VMIDSEL_SHIFT);
818b35a28afSMark Brown
819b35a28afSMark Brown /* Minimum bias current */
82069b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_1,
821b35a28afSMark Brown WM8955_VSEL_MASK, 0);
822b35a28afSMark Brown break;
823b35a28afSMark Brown
824b35a28afSMark Brown case SND_SOC_BIAS_OFF:
825b35a28afSMark Brown /* Low resistance VROI to help discharge */
82669b626e6SKuninori Morimoto snd_soc_component_update_bits(component,
827b35a28afSMark Brown WM8955_ADDITIONAL_CONTROL_3,
828b35a28afSMark Brown WM8955_VROI, 0);
829b35a28afSMark Brown
830b35a28afSMark Brown /* Turn off VMID and VREF */
83169b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
832b35a28afSMark Brown WM8955_VREF |
833b35a28afSMark Brown WM8955_VMIDSEL_MASK, 0);
834b35a28afSMark Brown
835b35a28afSMark Brown regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies),
836b35a28afSMark Brown wm8955->supplies);
837b35a28afSMark Brown break;
838b35a28afSMark Brown }
839b35a28afSMark Brown return 0;
840b35a28afSMark Brown }
841b35a28afSMark Brown
842b35a28afSMark Brown #define WM8955_RATES SNDRV_PCM_RATE_8000_96000
843b35a28afSMark Brown
844b35a28afSMark Brown #define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
845b35a28afSMark Brown SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
846b35a28afSMark Brown
84785e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops wm8955_dai_ops = {
848b35a28afSMark Brown .set_sysclk = wm8955_set_sysclk,
849b35a28afSMark Brown .set_fmt = wm8955_set_fmt,
850b35a28afSMark Brown .hw_params = wm8955_hw_params,
85126d3c16eSKuninori Morimoto .mute_stream = wm8955_mute,
85226d3c16eSKuninori Morimoto .no_capture_mute = 1,
853b35a28afSMark Brown };
854b35a28afSMark Brown
855f0fba2adSLiam Girdwood static struct snd_soc_dai_driver wm8955_dai = {
856f0fba2adSLiam Girdwood .name = "wm8955-hifi",
857b35a28afSMark Brown .playback = {
858b35a28afSMark Brown .stream_name = "Playback",
859b35a28afSMark Brown .channels_min = 2,
860b35a28afSMark Brown .channels_max = 2,
861b35a28afSMark Brown .rates = WM8955_RATES,
862b35a28afSMark Brown .formats = WM8955_FORMATS,
863b35a28afSMark Brown },
864b35a28afSMark Brown .ops = &wm8955_dai_ops,
865b35a28afSMark Brown };
866b35a28afSMark Brown
wm8955_probe(struct snd_soc_component * component)86769b626e6SKuninori Morimoto static int wm8955_probe(struct snd_soc_component *component)
868b35a28afSMark Brown {
86969b626e6SKuninori Morimoto struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
87069b626e6SKuninori Morimoto struct wm8955_pdata *pdata = dev_get_platdata(component->dev);
871f0fba2adSLiam Girdwood int ret, i;
872b35a28afSMark Brown
873b35a28afSMark Brown for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
874b35a28afSMark Brown wm8955->supplies[i].supply = wm8955_supply_names[i];
875b35a28afSMark Brown
87669b626e6SKuninori Morimoto ret = devm_regulator_bulk_get(component->dev, ARRAY_SIZE(wm8955->supplies),
877b35a28afSMark Brown wm8955->supplies);
878b35a28afSMark Brown if (ret != 0) {
87969b626e6SKuninori Morimoto dev_err(component->dev, "Failed to request supplies: %d\n", ret);
880f0fba2adSLiam Girdwood return ret;
881b35a28afSMark Brown }
882b35a28afSMark Brown
883b35a28afSMark Brown ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
884b35a28afSMark Brown wm8955->supplies);
885b35a28afSMark Brown if (ret != 0) {
88669b626e6SKuninori Morimoto dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
887e90c7b45SFabio Estevam return ret;
888b35a28afSMark Brown }
889b35a28afSMark Brown
89069b626e6SKuninori Morimoto ret = wm8955_reset(component);
891b35a28afSMark Brown if (ret < 0) {
89269b626e6SKuninori Morimoto dev_err(component->dev, "Failed to issue reset: %d\n", ret);
893b35a28afSMark Brown goto err_enable;
894b35a28afSMark Brown }
895b35a28afSMark Brown
896b35a28afSMark Brown /* Change some default settings - latch VU and enable ZC */
89769b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_LEFT_DAC_VOLUME,
898a1b3b5eeSMark Brown WM8955_LDVU, WM8955_LDVU);
89969b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_RIGHT_DAC_VOLUME,
900a1b3b5eeSMark Brown WM8955_RDVU, WM8955_RDVU);
90169b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_LOUT1_VOLUME,
902a1b3b5eeSMark Brown WM8955_LO1VU | WM8955_LO1ZC,
903a1b3b5eeSMark Brown WM8955_LO1VU | WM8955_LO1ZC);
90469b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_ROUT1_VOLUME,
905a1b3b5eeSMark Brown WM8955_RO1VU | WM8955_RO1ZC,
906a1b3b5eeSMark Brown WM8955_RO1VU | WM8955_RO1ZC);
90769b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_LOUT2_VOLUME,
908a1b3b5eeSMark Brown WM8955_LO2VU | WM8955_LO2ZC,
909a1b3b5eeSMark Brown WM8955_LO2VU | WM8955_LO2ZC);
91069b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_ROUT2_VOLUME,
911a1b3b5eeSMark Brown WM8955_RO2VU | WM8955_RO2ZC,
912a1b3b5eeSMark Brown WM8955_RO2VU | WM8955_RO2ZC);
91369b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_MONOOUT_VOLUME,
914a1b3b5eeSMark Brown WM8955_MOZC, WM8955_MOZC);
915b35a28afSMark Brown
916b35a28afSMark Brown /* Also enable adaptive bass boost by default */
91769b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_BASS_CONTROL, WM8955_BB, WM8955_BB);
918b35a28afSMark Brown
919b35a28afSMark Brown /* Set platform data values */
920f0fba2adSLiam Girdwood if (pdata) {
921f0fba2adSLiam Girdwood if (pdata->out2_speaker)
92269b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_2,
92395860fdfSMark Brown WM8955_ROUT2INV, WM8955_ROUT2INV);
924b35a28afSMark Brown
925f0fba2adSLiam Girdwood if (pdata->monoin_diff)
92669b626e6SKuninori Morimoto snd_soc_component_update_bits(component, WM8955_MONO_OUT_MIX_1,
92795860fdfSMark Brown WM8955_DMEN, WM8955_DMEN);
928b35a28afSMark Brown }
929b35a28afSMark Brown
93069b626e6SKuninori Morimoto snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
931b35a28afSMark Brown
932b35a28afSMark Brown /* Bias level configuration will have done an extra enable */
933b35a28afSMark Brown regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
934b35a28afSMark Brown
935b35a28afSMark Brown return 0;
936b35a28afSMark Brown
937b35a28afSMark Brown err_enable:
938b35a28afSMark Brown regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
939b35a28afSMark Brown return ret;
940b35a28afSMark Brown }
941b35a28afSMark Brown
94269b626e6SKuninori Morimoto static const struct snd_soc_component_driver soc_component_dev_wm8955 = {
943f0fba2adSLiam Girdwood .probe = wm8955_probe,
944f0fba2adSLiam Girdwood .set_bias_level = wm8955_set_bias_level,
9453294c4c6SMark Brown .controls = wm8955_snd_controls,
9463294c4c6SMark Brown .num_controls = ARRAY_SIZE(wm8955_snd_controls),
9473294c4c6SMark Brown .dapm_widgets = wm8955_dapm_widgets,
9483294c4c6SMark Brown .num_dapm_widgets = ARRAY_SIZE(wm8955_dapm_widgets),
9493294c4c6SMark Brown .dapm_routes = wm8955_dapm_routes,
9503294c4c6SMark Brown .num_dapm_routes = ARRAY_SIZE(wm8955_dapm_routes),
95169b626e6SKuninori Morimoto .suspend_bias_off = 1,
95269b626e6SKuninori Morimoto .idle_bias_on = 1,
95369b626e6SKuninori Morimoto .use_pmdown_time = 1,
95469b626e6SKuninori Morimoto .endianness = 1,
95595860fdfSMark Brown };
95695860fdfSMark Brown
95795860fdfSMark Brown static const struct regmap_config wm8955_regmap = {
95895860fdfSMark Brown .reg_bits = 7,
95995860fdfSMark Brown .val_bits = 9,
96095860fdfSMark Brown
96195860fdfSMark Brown .max_register = WM8955_MAX_REGISTER,
96295860fdfSMark Brown .volatile_reg = wm8955_volatile,
96395860fdfSMark Brown .writeable_reg = wm8955_writeable,
96495860fdfSMark Brown
965*6066d156SMark Brown .cache_type = REGCACHE_MAPLE,
96695860fdfSMark Brown .reg_defaults = wm8955_reg_defaults,
96795860fdfSMark Brown .num_reg_defaults = ARRAY_SIZE(wm8955_reg_defaults),
968f0fba2adSLiam Girdwood };
969f0fba2adSLiam Girdwood
wm8955_i2c_probe(struct i2c_client * i2c)97097b0b6e3SStephen Kitt static int wm8955_i2c_probe(struct i2c_client *i2c)
971b35a28afSMark Brown {
972b35a28afSMark Brown struct wm8955_priv *wm8955;
973f0fba2adSLiam Girdwood int ret;
974b35a28afSMark Brown
975ba5c88d0SMark Brown wm8955 = devm_kzalloc(&i2c->dev, sizeof(struct wm8955_priv),
976ba5c88d0SMark Brown GFP_KERNEL);
977b35a28afSMark Brown if (wm8955 == NULL)
978b35a28afSMark Brown return -ENOMEM;
979b35a28afSMark Brown
980385b27f5SSachin Kamat wm8955->regmap = devm_regmap_init_i2c(i2c, &wm8955_regmap);
98195860fdfSMark Brown if (IS_ERR(wm8955->regmap)) {
98295860fdfSMark Brown ret = PTR_ERR(wm8955->regmap);
98395860fdfSMark Brown dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
98495860fdfSMark Brown ret);
98595860fdfSMark Brown return ret;
98695860fdfSMark Brown }
98795860fdfSMark Brown
988b35a28afSMark Brown i2c_set_clientdata(i2c, wm8955);
989b35a28afSMark Brown
99069b626e6SKuninori Morimoto ret = devm_snd_soc_register_component(&i2c->dev,
99169b626e6SKuninori Morimoto &soc_component_dev_wm8955, &wm8955_dai, 1);
992ba5c88d0SMark Brown
993f0fba2adSLiam Girdwood return ret;
994b35a28afSMark Brown }
995b35a28afSMark Brown
996b35a28afSMark Brown static const struct i2c_device_id wm8955_i2c_id[] = {
997b35a28afSMark Brown { "wm8955", 0 },
998b35a28afSMark Brown { }
999b35a28afSMark Brown };
1000b35a28afSMark Brown MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id);
1001b35a28afSMark Brown
1002b35a28afSMark Brown static struct i2c_driver wm8955_i2c_driver = {
1003b35a28afSMark Brown .driver = {
1004091edccfSMark Brown .name = "wm8955",
1005b35a28afSMark Brown },
10069abcd240SUwe Kleine-König .probe = wm8955_i2c_probe,
1007b35a28afSMark Brown .id_table = wm8955_i2c_id,
1008b35a28afSMark Brown };
1009b35a28afSMark Brown
101007c9c32bSSachin Kamat module_i2c_driver(wm8955_i2c_driver);
1011b35a28afSMark Brown
1012b35a28afSMark Brown MODULE_DESCRIPTION("ASoC WM8955 driver");
1013b35a28afSMark Brown MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1014b35a28afSMark Brown MODULE_LICENSE("GPL");
1015