1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2017-2018, Linaro Limited 4 5 #include <linux/module.h> 6 #include <linux/init.h> 7 #include <linux/platform_device.h> 8 #include <linux/device.h> 9 #include <linux/wait.h> 10 #include <linux/bitops.h> 11 #include <linux/regulator/consumer.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/kernel.h> 15 #include <linux/slimbus.h> 16 #include <sound/soc.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc-dapm.h> 19 #include <linux/of_gpio.h> 20 #include <linux/of.h> 21 #include <linux/of_irq.h> 22 #include <sound/tlv.h> 23 #include <sound/info.h> 24 #include "wcd9335.h" 25 #include "wcd-clsh-v2.h" 26 27 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 28 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 29 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 30 /* Fractional Rates */ 31 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100) 32 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 33 SNDRV_PCM_FMTBIT_S24_LE) 34 35 /* slave port water mark level 36 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 37 */ 38 #define SLAVE_PORT_WATER_MARK_6BYTES 0 39 #define SLAVE_PORT_WATER_MARK_9BYTES 1 40 #define SLAVE_PORT_WATER_MARK_12BYTES 2 41 #define SLAVE_PORT_WATER_MARK_15BYTES 3 42 #define SLAVE_PORT_WATER_MARK_SHIFT 1 43 #define SLAVE_PORT_ENABLE 1 44 #define SLAVE_PORT_DISABLE 0 45 #define WCD9335_SLIM_WATER_MARK_VAL \ 46 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 47 (SLAVE_PORT_ENABLE)) 48 49 #define WCD9335_SLIM_NUM_PORT_REG 3 50 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2) 51 52 #define WCD9335_MCLK_CLK_12P288MHZ 12288000 53 #define WCD9335_MCLK_CLK_9P6MHZ 9600000 54 55 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000 56 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0) 57 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1) 58 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2) 59 60 #define WCD9335_NUM_INTERPOLATORS 9 61 #define WCD9335_RX_START 16 62 #define WCD9335_SLIM_CH_START 128 63 #define WCD9335_MAX_MICBIAS 4 64 #define WCD9335_MAX_VALID_ADC_MUX 13 65 #define WCD9335_INVALID_ADC_MUX 9 66 67 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60 68 #define CF_MIN_3DB_4HZ 0x0 69 #define CF_MIN_3DB_75HZ 0x1 70 #define CF_MIN_3DB_150HZ 0x2 71 #define WCD9335_DMIC_CLK_DIV_2 0x0 72 #define WCD9335_DMIC_CLK_DIV_3 0x1 73 #define WCD9335_DMIC_CLK_DIV_4 0x2 74 #define WCD9335_DMIC_CLK_DIV_6 0x3 75 #define WCD9335_DMIC_CLK_DIV_8 0x4 76 #define WCD9335_DMIC_CLK_DIV_16 0x5 77 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02 78 #define WCD9335_AMIC_PWR_LEVEL_LP 0 79 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1 80 #define WCD9335_AMIC_PWR_LEVEL_HP 2 81 #define WCD9335_AMIC_PWR_LVL_MASK 0x60 82 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5 83 84 #define WCD9335_DEC_PWR_LVL_MASK 0x06 85 #define WCD9335_DEC_PWR_LVL_LP 0x02 86 #define WCD9335_DEC_PWR_LVL_HP 0x04 87 #define WCD9335_DEC_PWR_LVL_DF 0x00 88 89 #define WCD9335_SLIM_RX_CH(p) \ 90 {.port = p + WCD9335_RX_START, .shift = p,} 91 92 #define WCD9335_SLIM_TX_CH(p) \ 93 {.port = p, .shift = p,} 94 95 /* vout step value */ 96 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25) 97 98 #define WCD9335_INTERPOLATOR_PATH(id) \ 99 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 100 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 101 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 102 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 103 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 104 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 105 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 106 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 107 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 108 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 109 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 110 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 111 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 112 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 113 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 114 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 115 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 116 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 117 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 118 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 119 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 120 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 121 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 122 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 123 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 124 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 125 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 126 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 127 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 128 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 129 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 130 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 131 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 132 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 133 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 134 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \ 135 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \ 136 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 137 {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"} 138 139 #define WCD9335_ADC_MUX_PATH(id) \ 140 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 141 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 142 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 143 {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \ 144 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \ 145 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \ 146 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 147 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 148 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 149 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 150 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 151 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 152 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 153 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 154 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 155 {"AMIC MUX" #id, "ADC4", "ADC4"}, \ 156 {"AMIC MUX" #id, "ADC5", "ADC5"}, \ 157 {"AMIC MUX" #id, "ADC6", "ADC6"} 158 159 enum { 160 WCD9335_RX0 = 0, 161 WCD9335_RX1, 162 WCD9335_RX2, 163 WCD9335_RX3, 164 WCD9335_RX4, 165 WCD9335_RX5, 166 WCD9335_RX6, 167 WCD9335_RX7, 168 WCD9335_RX8, 169 WCD9335_RX9, 170 WCD9335_RX10, 171 WCD9335_RX11, 172 WCD9335_RX12, 173 WCD9335_RX_MAX, 174 }; 175 176 enum { 177 WCD9335_TX0 = 0, 178 WCD9335_TX1, 179 WCD9335_TX2, 180 WCD9335_TX3, 181 WCD9335_TX4, 182 WCD9335_TX5, 183 WCD9335_TX6, 184 WCD9335_TX7, 185 WCD9335_TX8, 186 WCD9335_TX9, 187 WCD9335_TX10, 188 WCD9335_TX11, 189 WCD9335_TX12, 190 WCD9335_TX13, 191 WCD9335_TX14, 192 WCD9335_TX15, 193 WCD9335_TX_MAX, 194 }; 195 196 enum { 197 SIDO_SOURCE_INTERNAL = 0, 198 SIDO_SOURCE_RCO_BG, 199 }; 200 201 enum wcd9335_sido_voltage { 202 SIDO_VOLTAGE_SVS_MV = 950, 203 SIDO_VOLTAGE_NOMINAL_MV = 1100, 204 }; 205 206 enum { 207 AIF1_PB = 0, 208 AIF1_CAP, 209 AIF2_PB, 210 AIF2_CAP, 211 AIF3_PB, 212 AIF3_CAP, 213 AIF4_PB, 214 NUM_CODEC_DAIS, 215 }; 216 217 enum { 218 COMPANDER_1, /* HPH_L */ 219 COMPANDER_2, /* HPH_R */ 220 COMPANDER_3, /* LO1_DIFF */ 221 COMPANDER_4, /* LO2_DIFF */ 222 COMPANDER_5, /* LO3_SE */ 223 COMPANDER_6, /* LO4_SE */ 224 COMPANDER_7, /* SWR SPK CH1 */ 225 COMPANDER_8, /* SWR SPK CH2 */ 226 COMPANDER_MAX, 227 }; 228 229 enum { 230 INTn_2_INP_SEL_ZERO = 0, 231 INTn_2_INP_SEL_RX0, 232 INTn_2_INP_SEL_RX1, 233 INTn_2_INP_SEL_RX2, 234 INTn_2_INP_SEL_RX3, 235 INTn_2_INP_SEL_RX4, 236 INTn_2_INP_SEL_RX5, 237 INTn_2_INP_SEL_RX6, 238 INTn_2_INP_SEL_RX7, 239 INTn_2_INP_SEL_PROXIMITY, 240 }; 241 242 enum { 243 INTn_1_MIX_INP_SEL_ZERO = 0, 244 INTn_1_MIX_INP_SEL_DEC0, 245 INTn_1_MIX_INP_SEL_DEC1, 246 INTn_1_MIX_INP_SEL_IIR0, 247 INTn_1_MIX_INP_SEL_IIR1, 248 INTn_1_MIX_INP_SEL_RX0, 249 INTn_1_MIX_INP_SEL_RX1, 250 INTn_1_MIX_INP_SEL_RX2, 251 INTn_1_MIX_INP_SEL_RX3, 252 INTn_1_MIX_INP_SEL_RX4, 253 INTn_1_MIX_INP_SEL_RX5, 254 INTn_1_MIX_INP_SEL_RX6, 255 INTn_1_MIX_INP_SEL_RX7, 256 257 }; 258 259 enum { 260 INTERP_EAR = 0, 261 INTERP_HPHL, 262 INTERP_HPHR, 263 INTERP_LO1, 264 INTERP_LO2, 265 INTERP_LO3, 266 INTERP_LO4, 267 INTERP_SPKR1, 268 INTERP_SPKR2, 269 }; 270 271 enum wcd_clock_type { 272 WCD_CLK_OFF, 273 WCD_CLK_RCO, 274 WCD_CLK_MCLK, 275 }; 276 277 enum { 278 MIC_BIAS_1 = 1, 279 MIC_BIAS_2, 280 MIC_BIAS_3, 281 MIC_BIAS_4 282 }; 283 284 enum { 285 MICB_PULLUP_ENABLE, 286 MICB_PULLUP_DISABLE, 287 MICB_ENABLE, 288 MICB_DISABLE, 289 }; 290 291 struct wcd9335_slim_ch { 292 u32 ch_num; 293 u16 port; 294 u16 shift; 295 struct list_head list; 296 }; 297 298 struct wcd_slim_codec_dai_data { 299 struct list_head slim_ch_list; 300 struct slim_stream_config sconfig; 301 struct slim_stream_runtime *sruntime; 302 }; 303 304 struct wcd9335_codec { 305 struct device *dev; 306 struct clk *mclk; 307 struct clk *native_clk; 308 u32 mclk_rate; 309 u8 version; 310 311 struct slim_device *slim; 312 struct slim_device *slim_ifc_dev; 313 struct regmap *regmap; 314 struct regmap *if_regmap; 315 struct regmap_irq_chip_data *irq_data; 316 317 struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX]; 318 struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX]; 319 u32 num_rx_port; 320 u32 num_tx_port; 321 322 int sido_input_src; 323 enum wcd9335_sido_voltage sido_voltage; 324 325 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 326 struct snd_soc_component *component; 327 328 int master_bias_users; 329 int clk_mclk_users; 330 int clk_rco_users; 331 int sido_ccl_cnt; 332 enum wcd_clock_type clk_type; 333 334 struct wcd_clsh_ctrl *clsh_ctrl; 335 u32 hph_mode; 336 int prim_int_users[WCD9335_NUM_INTERPOLATORS]; 337 338 int comp_enabled[COMPANDER_MAX]; 339 340 int intr1; 341 int reset_gpio; 342 struct regulator_bulk_data supplies[WCD9335_MAX_SUPPLY]; 343 344 unsigned int rx_port_value[WCD9335_RX_MAX]; 345 unsigned int tx_port_value; 346 int hph_l_gain; 347 int hph_r_gain; 348 u32 rx_bias_count; 349 350 /*TX*/ 351 int micb_ref[WCD9335_MAX_MICBIAS]; 352 int pullup_ref[WCD9335_MAX_MICBIAS]; 353 354 int dmic_0_1_clk_cnt; 355 int dmic_2_3_clk_cnt; 356 int dmic_4_5_clk_cnt; 357 int dmic_sample_rate; 358 int mad_dmic_sample_rate; 359 360 int native_clk_users; 361 }; 362 363 struct wcd9335_irq { 364 int irq; 365 irqreturn_t (*handler)(int irq, void *data); 366 char *name; 367 }; 368 369 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = { 370 WCD9335_SLIM_TX_CH(0), 371 WCD9335_SLIM_TX_CH(1), 372 WCD9335_SLIM_TX_CH(2), 373 WCD9335_SLIM_TX_CH(3), 374 WCD9335_SLIM_TX_CH(4), 375 WCD9335_SLIM_TX_CH(5), 376 WCD9335_SLIM_TX_CH(6), 377 WCD9335_SLIM_TX_CH(7), 378 WCD9335_SLIM_TX_CH(8), 379 WCD9335_SLIM_TX_CH(9), 380 WCD9335_SLIM_TX_CH(10), 381 WCD9335_SLIM_TX_CH(11), 382 WCD9335_SLIM_TX_CH(12), 383 WCD9335_SLIM_TX_CH(13), 384 WCD9335_SLIM_TX_CH(14), 385 WCD9335_SLIM_TX_CH(15), 386 }; 387 388 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = { 389 WCD9335_SLIM_RX_CH(0), /* 16 */ 390 WCD9335_SLIM_RX_CH(1), /* 17 */ 391 WCD9335_SLIM_RX_CH(2), 392 WCD9335_SLIM_RX_CH(3), 393 WCD9335_SLIM_RX_CH(4), 394 WCD9335_SLIM_RX_CH(5), 395 WCD9335_SLIM_RX_CH(6), 396 WCD9335_SLIM_RX_CH(7), 397 WCD9335_SLIM_RX_CH(8), 398 WCD9335_SLIM_RX_CH(9), 399 WCD9335_SLIM_RX_CH(10), 400 WCD9335_SLIM_RX_CH(11), 401 WCD9335_SLIM_RX_CH(12), 402 }; 403 404 struct interp_sample_rate { 405 int rate; 406 int rate_val; 407 }; 408 409 static struct interp_sample_rate int_mix_rate_val[] = { 410 {48000, 0x4}, /* 48K */ 411 {96000, 0x5}, /* 96K */ 412 {192000, 0x6}, /* 192K */ 413 }; 414 415 static struct interp_sample_rate int_prim_rate_val[] = { 416 {8000, 0x0}, /* 8K */ 417 {16000, 0x1}, /* 16K */ 418 {24000, -EINVAL},/* 24K */ 419 {32000, 0x3}, /* 32K */ 420 {48000, 0x4}, /* 48K */ 421 {96000, 0x5}, /* 96K */ 422 {192000, 0x6}, /* 192K */ 423 {384000, 0x7}, /* 384K */ 424 {44100, 0x8}, /* 44.1K */ 425 }; 426 427 struct wcd9335_reg_mask_val { 428 u16 reg; 429 u8 mask; 430 u8 val; 431 }; 432 433 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = { 434 /* Rbuckfly/R_EAR(32) */ 435 {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00}, 436 {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60}, 437 {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00}, 438 {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50}, 439 {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50}, 440 {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08}, 441 {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08}, 442 {WCD9335_ANA_LO_1_2, 0x3C, 0X3C}, 443 {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00}, 444 {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40}, 445 {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03}, 446 {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02}, 447 {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01}, 448 {WCD9335_EAR_CMBUFF, 0x08, 0x00}, 449 {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 450 {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 451 {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 452 {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 453 {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80}, 454 {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80}, 455 {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01}, 456 {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01}, 457 {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01}, 458 {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01}, 459 {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01}, 460 {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01}, 461 {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01}, 462 {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01}, 463 {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01}, 464 {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01}, 465 {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01}, 466 {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01}, 467 {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01}, 468 {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01}, 469 {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01}, 470 {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01}, 471 {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01}, 472 {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01}, 473 {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01}, 474 {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01}, 475 {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08}, 476 {WCD9335_RCO_CTRL_2, 0x0F, 0x08}, 477 {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10}, 478 {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20}, 479 {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A}, 480 {WCD9335_HPH_L_TEST, 0x01, 0x01}, 481 {WCD9335_HPH_R_TEST, 0x01, 0x01}, 482 {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12}, 483 {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08}, 484 {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18}, 485 {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12}, 486 {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08}, 487 {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18}, 488 {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45}, 489 {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4}, 490 {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08}, 491 {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02}, 492 }; 493 494 /* Cutoff frequency for high pass filter */ 495 static const char * const cf_text[] = { 496 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 497 }; 498 499 static const char * const rx_cf_text[] = { 500 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 501 "CF_NEG_3DB_0P48HZ" 502 }; 503 504 static const char * const rx_int0_7_mix_mux_text[] = { 505 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 506 "RX6", "RX7", "PROXIMITY" 507 }; 508 509 static const char * const rx_int_mix_mux_text[] = { 510 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 511 "RX6", "RX7" 512 }; 513 514 static const char * const rx_prim_mix_text[] = { 515 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 516 "RX3", "RX4", "RX5", "RX6", "RX7" 517 }; 518 519 static const char * const rx_int_dem_inp_mux_text[] = { 520 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 521 }; 522 523 static const char * const rx_int0_interp_mux_text[] = { 524 "ZERO", "RX INT0 MIX2", 525 }; 526 527 static const char * const rx_int1_interp_mux_text[] = { 528 "ZERO", "RX INT1 MIX2", 529 }; 530 531 static const char * const rx_int2_interp_mux_text[] = { 532 "ZERO", "RX INT2 MIX2", 533 }; 534 535 static const char * const rx_int3_interp_mux_text[] = { 536 "ZERO", "RX INT3 MIX2", 537 }; 538 539 static const char * const rx_int4_interp_mux_text[] = { 540 "ZERO", "RX INT4 MIX2", 541 }; 542 543 static const char * const rx_int5_interp_mux_text[] = { 544 "ZERO", "RX INT5 MIX2", 545 }; 546 547 static const char * const rx_int6_interp_mux_text[] = { 548 "ZERO", "RX INT6 MIX2", 549 }; 550 551 static const char * const rx_int7_interp_mux_text[] = { 552 "ZERO", "RX INT7 MIX2", 553 }; 554 555 static const char * const rx_int8_interp_mux_text[] = { 556 "ZERO", "RX INT8 SEC MIX" 557 }; 558 559 static const char * const rx_hph_mode_mux_text[] = { 560 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 561 "Class-H Hi-Fi Low Power" 562 }; 563 564 static const char *const slim_rx_mux_text[] = { 565 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 566 }; 567 568 static const char * const adc_mux_text[] = { 569 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 570 }; 571 572 static const char * const dmic_mux_text[] = { 573 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 574 "SMIC0", "SMIC1", "SMIC2", "SMIC3" 575 }; 576 577 static const char * const dmic_mux_alt_text[] = { 578 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 579 }; 580 581 static const char * const amic_mux_text[] = { 582 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6" 583 }; 584 585 static const char * const sb_tx0_mux_text[] = { 586 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 587 }; 588 589 static const char * const sb_tx1_mux_text[] = { 590 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 591 }; 592 593 static const char * const sb_tx2_mux_text[] = { 594 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 595 }; 596 597 static const char * const sb_tx3_mux_text[] = { 598 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 599 }; 600 601 static const char * const sb_tx4_mux_text[] = { 602 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 603 }; 604 605 static const char * const sb_tx5_mux_text[] = { 606 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 607 }; 608 609 static const char * const sb_tx6_mux_text[] = { 610 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 611 }; 612 613 static const char * const sb_tx7_mux_text[] = { 614 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 615 }; 616 617 static const char * const sb_tx8_mux_text[] = { 618 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 619 }; 620 621 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 622 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 623 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 624 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 625 626 static const struct soc_enum cf_dec0_enum = 627 SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 628 629 static const struct soc_enum cf_dec1_enum = 630 SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 631 632 static const struct soc_enum cf_dec2_enum = 633 SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 634 635 static const struct soc_enum cf_dec3_enum = 636 SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 637 638 static const struct soc_enum cf_dec4_enum = 639 SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 640 641 static const struct soc_enum cf_dec5_enum = 642 SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 643 644 static const struct soc_enum cf_dec6_enum = 645 SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 646 647 static const struct soc_enum cf_dec7_enum = 648 SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 649 650 static const struct soc_enum cf_dec8_enum = 651 SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 652 653 static const struct soc_enum cf_int0_1_enum = 654 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 655 656 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2, 657 rx_cf_text); 658 659 static const struct soc_enum cf_int1_1_enum = 660 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 661 662 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2, 663 rx_cf_text); 664 665 static const struct soc_enum cf_int2_1_enum = 666 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 667 668 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2, 669 rx_cf_text); 670 671 static const struct soc_enum cf_int3_1_enum = 672 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 673 674 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2, 675 rx_cf_text); 676 677 static const struct soc_enum cf_int4_1_enum = 678 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 679 680 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2, 681 rx_cf_text); 682 683 static const struct soc_enum cf_int5_1_enum = 684 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text); 685 686 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2, 687 rx_cf_text); 688 689 static const struct soc_enum cf_int6_1_enum = 690 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text); 691 692 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2, 693 rx_cf_text); 694 695 static const struct soc_enum cf_int7_1_enum = 696 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 697 698 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2, 699 rx_cf_text); 700 701 static const struct soc_enum cf_int8_1_enum = 702 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 703 704 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2, 705 rx_cf_text); 706 707 static const struct soc_enum rx_hph_mode_mux_enum = 708 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 709 rx_hph_mode_mux_text); 710 711 static const struct soc_enum slim_rx_mux_enum = 712 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 713 714 static const struct soc_enum rx_int0_2_mux_chain_enum = 715 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 716 rx_int0_7_mix_mux_text); 717 718 static const struct soc_enum rx_int1_2_mux_chain_enum = 719 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 720 rx_int_mix_mux_text); 721 722 static const struct soc_enum rx_int2_2_mux_chain_enum = 723 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 724 rx_int_mix_mux_text); 725 726 static const struct soc_enum rx_int3_2_mux_chain_enum = 727 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 728 rx_int_mix_mux_text); 729 730 static const struct soc_enum rx_int4_2_mux_chain_enum = 731 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 732 rx_int_mix_mux_text); 733 734 static const struct soc_enum rx_int5_2_mux_chain_enum = 735 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9, 736 rx_int_mix_mux_text); 737 738 static const struct soc_enum rx_int6_2_mux_chain_enum = 739 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9, 740 rx_int_mix_mux_text); 741 742 static const struct soc_enum rx_int7_2_mux_chain_enum = 743 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 744 rx_int0_7_mix_mux_text); 745 746 static const struct soc_enum rx_int8_2_mux_chain_enum = 747 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 748 rx_int_mix_mux_text); 749 750 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 751 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 752 rx_prim_mix_text); 753 754 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 755 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 756 rx_prim_mix_text); 757 758 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 759 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 760 rx_prim_mix_text); 761 762 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 763 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 764 rx_prim_mix_text); 765 766 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 767 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 768 rx_prim_mix_text); 769 770 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 771 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 772 rx_prim_mix_text); 773 774 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 775 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 776 rx_prim_mix_text); 777 778 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 779 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 780 rx_prim_mix_text); 781 782 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 783 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 784 rx_prim_mix_text); 785 786 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 787 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 788 rx_prim_mix_text); 789 790 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 791 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 792 rx_prim_mix_text); 793 794 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 795 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 796 rx_prim_mix_text); 797 798 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 799 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 800 rx_prim_mix_text); 801 802 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 803 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 804 rx_prim_mix_text); 805 806 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 807 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 808 rx_prim_mix_text); 809 810 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum = 811 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13, 812 rx_prim_mix_text); 813 814 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum = 815 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13, 816 rx_prim_mix_text); 817 818 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum = 819 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13, 820 rx_prim_mix_text); 821 822 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum = 823 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13, 824 rx_prim_mix_text); 825 826 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum = 827 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13, 828 rx_prim_mix_text); 829 830 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum = 831 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13, 832 rx_prim_mix_text); 833 834 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 835 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 836 rx_prim_mix_text); 837 838 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 839 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 840 rx_prim_mix_text); 841 842 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 843 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 844 rx_prim_mix_text); 845 846 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 847 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 848 rx_prim_mix_text); 849 850 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 851 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 852 rx_prim_mix_text); 853 854 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 855 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 856 rx_prim_mix_text); 857 858 static const struct soc_enum rx_int0_dem_inp_mux_enum = 859 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0, 860 ARRAY_SIZE(rx_int_dem_inp_mux_text), 861 rx_int_dem_inp_mux_text); 862 863 static const struct soc_enum rx_int1_dem_inp_mux_enum = 864 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0, 865 ARRAY_SIZE(rx_int_dem_inp_mux_text), 866 rx_int_dem_inp_mux_text); 867 868 static const struct soc_enum rx_int2_dem_inp_mux_enum = 869 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0, 870 ARRAY_SIZE(rx_int_dem_inp_mux_text), 871 rx_int_dem_inp_mux_text); 872 873 static const struct soc_enum rx_int0_interp_mux_enum = 874 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2, 875 rx_int0_interp_mux_text); 876 877 static const struct soc_enum rx_int1_interp_mux_enum = 878 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2, 879 rx_int1_interp_mux_text); 880 881 static const struct soc_enum rx_int2_interp_mux_enum = 882 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2, 883 rx_int2_interp_mux_text); 884 885 static const struct soc_enum rx_int3_interp_mux_enum = 886 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2, 887 rx_int3_interp_mux_text); 888 889 static const struct soc_enum rx_int4_interp_mux_enum = 890 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2, 891 rx_int4_interp_mux_text); 892 893 static const struct soc_enum rx_int5_interp_mux_enum = 894 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2, 895 rx_int5_interp_mux_text); 896 897 static const struct soc_enum rx_int6_interp_mux_enum = 898 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2, 899 rx_int6_interp_mux_text); 900 901 static const struct soc_enum rx_int7_interp_mux_enum = 902 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2, 903 rx_int7_interp_mux_text); 904 905 static const struct soc_enum rx_int8_interp_mux_enum = 906 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2, 907 rx_int8_interp_mux_text); 908 909 static const struct soc_enum tx_adc_mux0_chain_enum = 910 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4, 911 adc_mux_text); 912 913 static const struct soc_enum tx_adc_mux1_chain_enum = 914 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4, 915 adc_mux_text); 916 917 static const struct soc_enum tx_adc_mux2_chain_enum = 918 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4, 919 adc_mux_text); 920 921 static const struct soc_enum tx_adc_mux3_chain_enum = 922 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4, 923 adc_mux_text); 924 925 static const struct soc_enum tx_adc_mux4_chain_enum = 926 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4, 927 adc_mux_text); 928 929 static const struct soc_enum tx_adc_mux5_chain_enum = 930 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4, 931 adc_mux_text); 932 933 static const struct soc_enum tx_adc_mux6_chain_enum = 934 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4, 935 adc_mux_text); 936 937 static const struct soc_enum tx_adc_mux7_chain_enum = 938 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4, 939 adc_mux_text); 940 941 static const struct soc_enum tx_adc_mux8_chain_enum = 942 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4, 943 adc_mux_text); 944 945 static const struct soc_enum tx_dmic_mux0_enum = 946 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11, 947 dmic_mux_text); 948 949 static const struct soc_enum tx_dmic_mux1_enum = 950 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11, 951 dmic_mux_text); 952 953 static const struct soc_enum tx_dmic_mux2_enum = 954 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11, 955 dmic_mux_text); 956 957 static const struct soc_enum tx_dmic_mux3_enum = 958 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11, 959 dmic_mux_text); 960 961 static const struct soc_enum tx_dmic_mux4_enum = 962 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 963 dmic_mux_alt_text); 964 965 static const struct soc_enum tx_dmic_mux5_enum = 966 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 967 dmic_mux_alt_text); 968 969 static const struct soc_enum tx_dmic_mux6_enum = 970 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 971 dmic_mux_alt_text); 972 973 static const struct soc_enum tx_dmic_mux7_enum = 974 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 975 dmic_mux_alt_text); 976 977 static const struct soc_enum tx_dmic_mux8_enum = 978 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 979 dmic_mux_alt_text); 980 981 static const struct soc_enum tx_amic_mux0_enum = 982 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7, 983 amic_mux_text); 984 985 static const struct soc_enum tx_amic_mux1_enum = 986 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7, 987 amic_mux_text); 988 989 static const struct soc_enum tx_amic_mux2_enum = 990 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7, 991 amic_mux_text); 992 993 static const struct soc_enum tx_amic_mux3_enum = 994 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7, 995 amic_mux_text); 996 997 static const struct soc_enum tx_amic_mux4_enum = 998 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7, 999 amic_mux_text); 1000 1001 static const struct soc_enum tx_amic_mux5_enum = 1002 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7, 1003 amic_mux_text); 1004 1005 static const struct soc_enum tx_amic_mux6_enum = 1006 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7, 1007 amic_mux_text); 1008 1009 static const struct soc_enum tx_amic_mux7_enum = 1010 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7, 1011 amic_mux_text); 1012 1013 static const struct soc_enum tx_amic_mux8_enum = 1014 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7, 1015 amic_mux_text); 1016 1017 static const struct soc_enum sb_tx0_mux_enum = 1018 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4, 1019 sb_tx0_mux_text); 1020 1021 static const struct soc_enum sb_tx1_mux_enum = 1022 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4, 1023 sb_tx1_mux_text); 1024 1025 static const struct soc_enum sb_tx2_mux_enum = 1026 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4, 1027 sb_tx2_mux_text); 1028 1029 static const struct soc_enum sb_tx3_mux_enum = 1030 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4, 1031 sb_tx3_mux_text); 1032 1033 static const struct soc_enum sb_tx4_mux_enum = 1034 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4, 1035 sb_tx4_mux_text); 1036 1037 static const struct soc_enum sb_tx5_mux_enum = 1038 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4, 1039 sb_tx5_mux_text); 1040 1041 static const struct soc_enum sb_tx6_mux_enum = 1042 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4, 1043 sb_tx6_mux_text); 1044 1045 static const struct soc_enum sb_tx7_mux_enum = 1046 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4, 1047 sb_tx7_mux_text); 1048 1049 static const struct soc_enum sb_tx8_mux_enum = 1050 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4, 1051 sb_tx8_mux_text); 1052 1053 static const struct snd_kcontrol_new rx_int0_2_mux = 1054 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 1055 1056 static const struct snd_kcontrol_new rx_int1_2_mux = 1057 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 1058 1059 static const struct snd_kcontrol_new rx_int2_2_mux = 1060 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 1061 1062 static const struct snd_kcontrol_new rx_int3_2_mux = 1063 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 1064 1065 static const struct snd_kcontrol_new rx_int4_2_mux = 1066 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 1067 1068 static const struct snd_kcontrol_new rx_int5_2_mux = 1069 SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum); 1070 1071 static const struct snd_kcontrol_new rx_int6_2_mux = 1072 SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum); 1073 1074 static const struct snd_kcontrol_new rx_int7_2_mux = 1075 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 1076 1077 static const struct snd_kcontrol_new rx_int8_2_mux = 1078 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 1079 1080 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 1081 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 1082 1083 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 1084 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 1085 1086 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 1087 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 1088 1089 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 1090 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 1091 1092 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 1093 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 1094 1095 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 1096 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 1097 1098 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 1099 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 1100 1101 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 1102 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 1103 1104 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 1105 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 1106 1107 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 1108 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 1109 1110 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 1111 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 1112 1113 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 1114 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 1115 1116 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 1117 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 1118 1119 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 1120 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 1121 1122 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 1123 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 1124 1125 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux = 1126 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum); 1127 1128 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux = 1129 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum); 1130 1131 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux = 1132 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum); 1133 1134 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux = 1135 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum); 1136 1137 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux = 1138 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum); 1139 1140 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux = 1141 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum); 1142 1143 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 1144 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 1145 1146 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 1147 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 1148 1149 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 1150 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 1151 1152 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 1153 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 1154 1155 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 1156 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 1157 1158 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 1159 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 1160 1161 static const struct snd_kcontrol_new rx_int0_interp_mux = 1162 SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum); 1163 1164 static const struct snd_kcontrol_new rx_int1_interp_mux = 1165 SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum); 1166 1167 static const struct snd_kcontrol_new rx_int2_interp_mux = 1168 SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum); 1169 1170 static const struct snd_kcontrol_new rx_int3_interp_mux = 1171 SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum); 1172 1173 static const struct snd_kcontrol_new rx_int4_interp_mux = 1174 SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum); 1175 1176 static const struct snd_kcontrol_new rx_int5_interp_mux = 1177 SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum); 1178 1179 static const struct snd_kcontrol_new rx_int6_interp_mux = 1180 SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum); 1181 1182 static const struct snd_kcontrol_new rx_int7_interp_mux = 1183 SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum); 1184 1185 static const struct snd_kcontrol_new rx_int8_interp_mux = 1186 SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum); 1187 1188 static const struct snd_kcontrol_new tx_dmic_mux0 = 1189 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 1190 1191 static const struct snd_kcontrol_new tx_dmic_mux1 = 1192 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 1193 1194 static const struct snd_kcontrol_new tx_dmic_mux2 = 1195 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 1196 1197 static const struct snd_kcontrol_new tx_dmic_mux3 = 1198 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 1199 1200 static const struct snd_kcontrol_new tx_dmic_mux4 = 1201 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 1202 1203 static const struct snd_kcontrol_new tx_dmic_mux5 = 1204 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 1205 1206 static const struct snd_kcontrol_new tx_dmic_mux6 = 1207 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 1208 1209 static const struct snd_kcontrol_new tx_dmic_mux7 = 1210 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 1211 1212 static const struct snd_kcontrol_new tx_dmic_mux8 = 1213 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 1214 1215 static const struct snd_kcontrol_new tx_amic_mux0 = 1216 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 1217 1218 static const struct snd_kcontrol_new tx_amic_mux1 = 1219 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 1220 1221 static const struct snd_kcontrol_new tx_amic_mux2 = 1222 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 1223 1224 static const struct snd_kcontrol_new tx_amic_mux3 = 1225 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 1226 1227 static const struct snd_kcontrol_new tx_amic_mux4 = 1228 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 1229 1230 static const struct snd_kcontrol_new tx_amic_mux5 = 1231 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 1232 1233 static const struct snd_kcontrol_new tx_amic_mux6 = 1234 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 1235 1236 static const struct snd_kcontrol_new tx_amic_mux7 = 1237 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 1238 1239 static const struct snd_kcontrol_new tx_amic_mux8 = 1240 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 1241 1242 static const struct snd_kcontrol_new sb_tx0_mux = 1243 SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum); 1244 1245 static const struct snd_kcontrol_new sb_tx1_mux = 1246 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum); 1247 1248 static const struct snd_kcontrol_new sb_tx2_mux = 1249 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum); 1250 1251 static const struct snd_kcontrol_new sb_tx3_mux = 1252 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum); 1253 1254 static const struct snd_kcontrol_new sb_tx4_mux = 1255 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum); 1256 1257 static const struct snd_kcontrol_new sb_tx5_mux = 1258 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum); 1259 1260 static const struct snd_kcontrol_new sb_tx6_mux = 1261 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum); 1262 1263 static const struct snd_kcontrol_new sb_tx7_mux = 1264 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum); 1265 1266 static const struct snd_kcontrol_new sb_tx8_mux = 1267 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum); 1268 1269 static int slim_rx_mux_get(struct snd_kcontrol *kc, 1270 struct snd_ctl_elem_value *ucontrol) 1271 { 1272 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 1273 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev); 1274 u32 port_id = w->shift; 1275 1276 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id]; 1277 1278 return 0; 1279 } 1280 1281 static int slim_rx_mux_put(struct snd_kcontrol *kc, 1282 struct snd_ctl_elem_value *ucontrol) 1283 { 1284 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 1285 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev); 1286 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1287 struct snd_soc_dapm_update *update = NULL; 1288 u32 port_id = w->shift; 1289 1290 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0]) 1291 return 0; 1292 1293 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0]; 1294 1295 /* Remove channel from any list it's in before adding it to a new one */ 1296 list_del_init(&wcd->rx_chs[port_id].list); 1297 1298 switch (wcd->rx_port_value[port_id]) { 1299 case 0: 1300 /* Channel already removed from lists. Nothing to do here */ 1301 break; 1302 case 1: 1303 list_add_tail(&wcd->rx_chs[port_id].list, 1304 &wcd->dai[AIF1_PB].slim_ch_list); 1305 break; 1306 case 2: 1307 list_add_tail(&wcd->rx_chs[port_id].list, 1308 &wcd->dai[AIF2_PB].slim_ch_list); 1309 break; 1310 case 3: 1311 list_add_tail(&wcd->rx_chs[port_id].list, 1312 &wcd->dai[AIF3_PB].slim_ch_list); 1313 break; 1314 case 4: 1315 list_add_tail(&wcd->rx_chs[port_id].list, 1316 &wcd->dai[AIF4_PB].slim_ch_list); 1317 break; 1318 default: 1319 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]); 1320 goto err; 1321 } 1322 1323 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id], 1324 e, update); 1325 1326 return 0; 1327 err: 1328 return -EINVAL; 1329 } 1330 1331 static int slim_tx_mixer_get(struct snd_kcontrol *kc, 1332 struct snd_ctl_elem_value *ucontrol) 1333 { 1334 1335 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1336 struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev); 1337 1338 ucontrol->value.integer.value[0] = wcd->tx_port_value; 1339 1340 return 0; 1341 } 1342 1343 static int slim_tx_mixer_put(struct snd_kcontrol *kc, 1344 struct snd_ctl_elem_value *ucontrol) 1345 { 1346 1347 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 1348 struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev); 1349 struct snd_soc_dapm_update *update = NULL; 1350 struct soc_mixer_control *mixer = 1351 (struct soc_mixer_control *)kc->private_value; 1352 int enable = ucontrol->value.integer.value[0]; 1353 int dai_id = widget->shift; 1354 int port_id = mixer->shift; 1355 1356 switch (dai_id) { 1357 case AIF1_CAP: 1358 case AIF2_CAP: 1359 case AIF3_CAP: 1360 /* only add to the list if value not set */ 1361 if (enable && !(wcd->tx_port_value & BIT(port_id))) { 1362 wcd->tx_port_value |= BIT(port_id); 1363 list_add_tail(&wcd->tx_chs[port_id].list, 1364 &wcd->dai[dai_id].slim_ch_list); 1365 } else if (!enable && (wcd->tx_port_value & BIT(port_id))) { 1366 wcd->tx_port_value &= ~BIT(port_id); 1367 list_del_init(&wcd->tx_chs[port_id].list); 1368 } 1369 break; 1370 default: 1371 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id); 1372 return -EINVAL; 1373 } 1374 1375 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 1376 1377 return 0; 1378 } 1379 1380 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = { 1381 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 1382 slim_rx_mux_get, slim_rx_mux_put), 1383 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 1384 slim_rx_mux_get, slim_rx_mux_put), 1385 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 1386 slim_rx_mux_get, slim_rx_mux_put), 1387 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 1388 slim_rx_mux_get, slim_rx_mux_put), 1389 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 1390 slim_rx_mux_get, slim_rx_mux_put), 1391 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 1392 slim_rx_mux_get, slim_rx_mux_put), 1393 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 1394 slim_rx_mux_get, slim_rx_mux_put), 1395 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 1396 slim_rx_mux_get, slim_rx_mux_put), 1397 }; 1398 1399 static const struct snd_kcontrol_new aif1_cap_mixer[] = { 1400 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1401 slim_tx_mixer_get, slim_tx_mixer_put), 1402 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1403 slim_tx_mixer_get, slim_tx_mixer_put), 1404 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1405 slim_tx_mixer_get, slim_tx_mixer_put), 1406 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1407 slim_tx_mixer_get, slim_tx_mixer_put), 1408 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1409 slim_tx_mixer_get, slim_tx_mixer_put), 1410 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1411 slim_tx_mixer_get, slim_tx_mixer_put), 1412 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1413 slim_tx_mixer_get, slim_tx_mixer_put), 1414 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1415 slim_tx_mixer_get, slim_tx_mixer_put), 1416 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1417 slim_tx_mixer_get, slim_tx_mixer_put), 1418 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1419 slim_tx_mixer_get, slim_tx_mixer_put), 1420 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1421 slim_tx_mixer_get, slim_tx_mixer_put), 1422 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1423 slim_tx_mixer_get, slim_tx_mixer_put), 1424 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1425 slim_tx_mixer_get, slim_tx_mixer_put), 1426 }; 1427 1428 static const struct snd_kcontrol_new aif2_cap_mixer[] = { 1429 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1430 slim_tx_mixer_get, slim_tx_mixer_put), 1431 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1432 slim_tx_mixer_get, slim_tx_mixer_put), 1433 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1434 slim_tx_mixer_get, slim_tx_mixer_put), 1435 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1436 slim_tx_mixer_get, slim_tx_mixer_put), 1437 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1438 slim_tx_mixer_get, slim_tx_mixer_put), 1439 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1440 slim_tx_mixer_get, slim_tx_mixer_put), 1441 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1442 slim_tx_mixer_get, slim_tx_mixer_put), 1443 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1444 slim_tx_mixer_get, slim_tx_mixer_put), 1445 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1446 slim_tx_mixer_get, slim_tx_mixer_put), 1447 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1448 slim_tx_mixer_get, slim_tx_mixer_put), 1449 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1450 slim_tx_mixer_get, slim_tx_mixer_put), 1451 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1452 slim_tx_mixer_get, slim_tx_mixer_put), 1453 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1454 slim_tx_mixer_get, slim_tx_mixer_put), 1455 }; 1456 1457 static const struct snd_kcontrol_new aif3_cap_mixer[] = { 1458 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1459 slim_tx_mixer_get, slim_tx_mixer_put), 1460 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1461 slim_tx_mixer_get, slim_tx_mixer_put), 1462 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1463 slim_tx_mixer_get, slim_tx_mixer_put), 1464 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1465 slim_tx_mixer_get, slim_tx_mixer_put), 1466 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1467 slim_tx_mixer_get, slim_tx_mixer_put), 1468 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1469 slim_tx_mixer_get, slim_tx_mixer_put), 1470 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1471 slim_tx_mixer_get, slim_tx_mixer_put), 1472 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1473 slim_tx_mixer_get, slim_tx_mixer_put), 1474 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1475 slim_tx_mixer_get, slim_tx_mixer_put), 1476 }; 1477 1478 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc, 1479 struct snd_ctl_elem_value *ucontrol) 1480 { 1481 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1482 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 1483 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1484 unsigned int val, reg, sel; 1485 1486 val = ucontrol->value.enumerated.item[0]; 1487 1488 switch (e->reg) { 1489 case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 1490 reg = WCD9335_CDC_TX0_TX_PATH_CFG0; 1491 break; 1492 case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 1493 reg = WCD9335_CDC_TX1_TX_PATH_CFG0; 1494 break; 1495 case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 1496 reg = WCD9335_CDC_TX2_TX_PATH_CFG0; 1497 break; 1498 case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 1499 reg = WCD9335_CDC_TX3_TX_PATH_CFG0; 1500 break; 1501 case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0: 1502 reg = WCD9335_CDC_TX4_TX_PATH_CFG0; 1503 break; 1504 case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0: 1505 reg = WCD9335_CDC_TX5_TX_PATH_CFG0; 1506 break; 1507 case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0: 1508 reg = WCD9335_CDC_TX6_TX_PATH_CFG0; 1509 break; 1510 case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0: 1511 reg = WCD9335_CDC_TX7_TX_PATH_CFG0; 1512 break; 1513 case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0: 1514 reg = WCD9335_CDC_TX8_TX_PATH_CFG0; 1515 break; 1516 default: 1517 return -EINVAL; 1518 } 1519 1520 /* AMIC: 0, DMIC: 1 */ 1521 sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL; 1522 snd_soc_component_update_bits(component, reg, 1523 WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK, 1524 sel); 1525 1526 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1527 } 1528 1529 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc, 1530 struct snd_ctl_elem_value *ucontrol) 1531 { 1532 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1533 struct snd_soc_component *component; 1534 int reg, val; 1535 1536 component = snd_soc_dapm_kcontrol_component(kc); 1537 val = ucontrol->value.enumerated.item[0]; 1538 1539 if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0) 1540 reg = WCD9335_CDC_RX0_RX_PATH_CFG0; 1541 else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0) 1542 reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 1543 else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0) 1544 reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 1545 else 1546 return -EINVAL; 1547 1548 /* Set Look Ahead Delay */ 1549 snd_soc_component_update_bits(component, reg, 1550 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK, 1551 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0); 1552 /* Set DEM INP Select */ 1553 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1554 } 1555 1556 static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 1557 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 1558 snd_soc_dapm_get_enum_double, 1559 wcd9335_int_dem_inp_mux_put); 1560 1561 static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 1562 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 1563 snd_soc_dapm_get_enum_double, 1564 wcd9335_int_dem_inp_mux_put); 1565 1566 static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 1567 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 1568 snd_soc_dapm_get_enum_double, 1569 wcd9335_int_dem_inp_mux_put); 1570 1571 static const struct snd_kcontrol_new tx_adc_mux0 = 1572 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum, 1573 snd_soc_dapm_get_enum_double, 1574 wcd9335_put_dec_enum); 1575 1576 static const struct snd_kcontrol_new tx_adc_mux1 = 1577 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum, 1578 snd_soc_dapm_get_enum_double, 1579 wcd9335_put_dec_enum); 1580 1581 static const struct snd_kcontrol_new tx_adc_mux2 = 1582 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum, 1583 snd_soc_dapm_get_enum_double, 1584 wcd9335_put_dec_enum); 1585 1586 static const struct snd_kcontrol_new tx_adc_mux3 = 1587 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum, 1588 snd_soc_dapm_get_enum_double, 1589 wcd9335_put_dec_enum); 1590 1591 static const struct snd_kcontrol_new tx_adc_mux4 = 1592 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum, 1593 snd_soc_dapm_get_enum_double, 1594 wcd9335_put_dec_enum); 1595 1596 static const struct snd_kcontrol_new tx_adc_mux5 = 1597 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum, 1598 snd_soc_dapm_get_enum_double, 1599 wcd9335_put_dec_enum); 1600 1601 static const struct snd_kcontrol_new tx_adc_mux6 = 1602 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum, 1603 snd_soc_dapm_get_enum_double, 1604 wcd9335_put_dec_enum); 1605 1606 static const struct snd_kcontrol_new tx_adc_mux7 = 1607 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum, 1608 snd_soc_dapm_get_enum_double, 1609 wcd9335_put_dec_enum); 1610 1611 static const struct snd_kcontrol_new tx_adc_mux8 = 1612 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum, 1613 snd_soc_dapm_get_enum_double, 1614 wcd9335_put_dec_enum); 1615 1616 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1617 int rate_val, 1618 u32 rate) 1619 { 1620 struct snd_soc_component *component = dai->component; 1621 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 1622 struct wcd9335_slim_ch *ch; 1623 int val, j; 1624 1625 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1626 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1627 val = snd_soc_component_read(component, 1628 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1629 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1630 1631 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) 1632 snd_soc_component_update_bits(component, 1633 WCD9335_CDC_RX_PATH_MIX_CTL(j), 1634 WCD9335_CDC_MIX_PCM_RATE_MASK, 1635 rate_val); 1636 } 1637 } 1638 1639 return 0; 1640 } 1641 1642 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1643 u8 rate_val, 1644 u32 rate) 1645 { 1646 struct snd_soc_component *comp = dai->component; 1647 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 1648 struct wcd9335_slim_ch *ch; 1649 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1650 int inp, j; 1651 1652 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1653 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0; 1654 /* 1655 * Loop through all interpolator MUX inputs and find out 1656 * to which interpolator input, the slim rx port 1657 * is connected 1658 */ 1659 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1660 cfg0 = snd_soc_component_read(comp, 1661 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1662 cfg1 = snd_soc_component_read(comp, 1663 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1664 1665 inp0_sel = cfg0 & 1666 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1667 inp1_sel = (cfg0 >> 4) & 1668 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1669 inp2_sel = (cfg1 >> 4) & 1670 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1671 1672 if ((inp0_sel == inp) || (inp1_sel == inp) || 1673 (inp2_sel == inp)) { 1674 /* rate is in Hz */ 1675 if ((j == 0) && (rate == 44100)) 1676 dev_info(wcd->dev, 1677 "Cannot set 44.1KHz on INT0\n"); 1678 else 1679 snd_soc_component_update_bits(comp, 1680 WCD9335_CDC_RX_PATH_CTL(j), 1681 WCD9335_CDC_MIX_PCM_RATE_MASK, 1682 rate_val); 1683 } 1684 } 1685 } 1686 1687 return 0; 1688 } 1689 1690 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate) 1691 { 1692 int i; 1693 1694 /* set mixing path rate */ 1695 for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) { 1696 if (rate == int_mix_rate_val[i].rate) { 1697 wcd9335_set_mix_interpolator_rate(dai, 1698 int_mix_rate_val[i].rate_val, rate); 1699 break; 1700 } 1701 } 1702 1703 /* set primary path sample rate */ 1704 for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) { 1705 if (rate == int_prim_rate_val[i].rate) { 1706 wcd9335_set_prim_interpolator_rate(dai, 1707 int_prim_rate_val[i].rate_val, rate); 1708 break; 1709 } 1710 } 1711 1712 return 0; 1713 } 1714 1715 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd, 1716 struct wcd_slim_codec_dai_data *dai_data, 1717 int direction) 1718 { 1719 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1720 struct slim_stream_config *cfg = &dai_data->sconfig; 1721 struct wcd9335_slim_ch *ch; 1722 u16 payload = 0; 1723 int ret, i; 1724 1725 cfg->ch_count = 0; 1726 cfg->direction = direction; 1727 cfg->port_mask = 0; 1728 1729 /* Configure slave interface device */ 1730 list_for_each_entry(ch, slim_ch_list, list) { 1731 cfg->ch_count++; 1732 payload |= 1 << ch->shift; 1733 cfg->port_mask |= BIT(ch->port); 1734 } 1735 1736 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1737 if (!cfg->chs) 1738 return -ENOMEM; 1739 1740 i = 0; 1741 list_for_each_entry(ch, slim_ch_list, list) { 1742 cfg->chs[i++] = ch->ch_num; 1743 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1744 /* write to interface device */ 1745 ret = regmap_write(wcd->if_regmap, 1746 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1747 payload); 1748 1749 if (ret < 0) 1750 goto err; 1751 1752 /* configure the slave port for water mark and enable*/ 1753 ret = regmap_write(wcd->if_regmap, 1754 WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port), 1755 WCD9335_SLIM_WATER_MARK_VAL); 1756 if (ret < 0) 1757 goto err; 1758 } else { 1759 ret = regmap_write(wcd->if_regmap, 1760 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1761 payload & 0x00FF); 1762 if (ret < 0) 1763 goto err; 1764 1765 /* ports 8,9 */ 1766 ret = regmap_write(wcd->if_regmap, 1767 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1768 (payload & 0xFF00)>>8); 1769 if (ret < 0) 1770 goto err; 1771 1772 /* configure the slave port for water mark and enable*/ 1773 ret = regmap_write(wcd->if_regmap, 1774 WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port), 1775 WCD9335_SLIM_WATER_MARK_VAL); 1776 1777 if (ret < 0) 1778 goto err; 1779 } 1780 } 1781 1782 dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM"); 1783 1784 return 0; 1785 1786 err: 1787 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1788 kfree(cfg->chs); 1789 cfg->chs = NULL; 1790 1791 return ret; 1792 } 1793 1794 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai, 1795 u8 rate_val, u32 rate) 1796 { 1797 struct snd_soc_component *comp = dai->component; 1798 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 1799 u8 shift = 0, shift_val = 0, tx_mux_sel; 1800 struct wcd9335_slim_ch *ch; 1801 int tx_port, tx_port_reg; 1802 int decimator = -1; 1803 1804 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1805 tx_port = ch->port; 1806 if ((tx_port == 12) || (tx_port >= 14)) { 1807 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1808 tx_port, dai->id); 1809 return -EINVAL; 1810 } 1811 /* Find the SB TX MUX input - which decimator is connected */ 1812 if (tx_port < 4) { 1813 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0; 1814 shift = (tx_port << 1); 1815 shift_val = 0x03; 1816 } else if (tx_port < 8) { 1817 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1; 1818 shift = ((tx_port - 4) << 1); 1819 shift_val = 0x03; 1820 } else if (tx_port < 11) { 1821 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2; 1822 shift = ((tx_port - 8) << 1); 1823 shift_val = 0x03; 1824 } else if (tx_port == 11) { 1825 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1826 shift = 0; 1827 shift_val = 0x0F; 1828 } else if (tx_port == 13) { 1829 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1830 shift = 4; 1831 shift_val = 0x03; 1832 } else { 1833 return -EINVAL; 1834 } 1835 1836 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) & 1837 (shift_val << shift); 1838 1839 tx_mux_sel = tx_mux_sel >> shift; 1840 if (tx_port <= 8) { 1841 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1842 decimator = tx_port; 1843 } else if (tx_port <= 10) { 1844 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1845 decimator = ((tx_port == 9) ? 7 : 6); 1846 } else if (tx_port == 11) { 1847 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1848 decimator = tx_mux_sel - 1; 1849 } else if (tx_port == 13) { 1850 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1851 decimator = 5; 1852 } 1853 1854 if (decimator >= 0) { 1855 snd_soc_component_update_bits(comp, 1856 WCD9335_CDC_TX_PATH_CTL(decimator), 1857 WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1858 rate_val); 1859 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) { 1860 /* Check if the TX Mux input is RX MIX TXn */ 1861 dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n", 1862 tx_port, tx_port); 1863 } else { 1864 dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n", 1865 decimator); 1866 return -EINVAL; 1867 } 1868 } 1869 1870 return 0; 1871 } 1872 1873 static int wcd9335_hw_params(struct snd_pcm_substream *substream, 1874 struct snd_pcm_hw_params *params, 1875 struct snd_soc_dai *dai) 1876 { 1877 struct wcd9335_codec *wcd; 1878 int ret, tx_fs_rate = 0; 1879 1880 wcd = snd_soc_component_get_drvdata(dai->component); 1881 1882 switch (substream->stream) { 1883 case SNDRV_PCM_STREAM_PLAYBACK: 1884 ret = wcd9335_set_interpolator_rate(dai, params_rate(params)); 1885 if (ret) { 1886 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1887 params_rate(params)); 1888 return ret; 1889 } 1890 switch (params_width(params)) { 1891 case 16 ... 24: 1892 wcd->dai[dai->id].sconfig.bps = params_width(params); 1893 break; 1894 default: 1895 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1896 __func__, params_width(params)); 1897 return -EINVAL; 1898 } 1899 break; 1900 1901 case SNDRV_PCM_STREAM_CAPTURE: 1902 switch (params_rate(params)) { 1903 case 8000: 1904 tx_fs_rate = 0; 1905 break; 1906 case 16000: 1907 tx_fs_rate = 1; 1908 break; 1909 case 32000: 1910 tx_fs_rate = 3; 1911 break; 1912 case 48000: 1913 tx_fs_rate = 4; 1914 break; 1915 case 96000: 1916 tx_fs_rate = 5; 1917 break; 1918 case 192000: 1919 tx_fs_rate = 6; 1920 break; 1921 case 384000: 1922 tx_fs_rate = 7; 1923 break; 1924 default: 1925 dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n", 1926 __func__, params_rate(params)); 1927 return -EINVAL; 1928 1929 } 1930 1931 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate, 1932 params_rate(params)); 1933 if (ret < 0) { 1934 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1935 return ret; 1936 } 1937 switch (params_width(params)) { 1938 case 16 ... 32: 1939 wcd->dai[dai->id].sconfig.bps = params_width(params); 1940 break; 1941 default: 1942 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1943 __func__, params_width(params)); 1944 return -EINVAL; 1945 } 1946 break; 1947 default: 1948 dev_err(wcd->dev, "Invalid stream type %d\n", 1949 substream->stream); 1950 return -EINVAL; 1951 } 1952 1953 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1954 wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1955 1956 return 0; 1957 } 1958 1959 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd, 1960 struct snd_soc_dai *dai) 1961 { 1962 struct wcd_slim_codec_dai_data *dai_data; 1963 struct wcd9335_codec *wcd; 1964 struct slim_stream_config *cfg; 1965 1966 wcd = snd_soc_component_get_drvdata(dai->component); 1967 1968 dai_data = &wcd->dai[dai->id]; 1969 1970 switch (cmd) { 1971 case SNDRV_PCM_TRIGGER_START: 1972 case SNDRV_PCM_TRIGGER_RESUME: 1973 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1974 cfg = &dai_data->sconfig; 1975 slim_stream_prepare(dai_data->sruntime, cfg); 1976 slim_stream_enable(dai_data->sruntime); 1977 break; 1978 case SNDRV_PCM_TRIGGER_STOP: 1979 case SNDRV_PCM_TRIGGER_SUSPEND: 1980 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1981 slim_stream_unprepare(dai_data->sruntime); 1982 slim_stream_disable(dai_data->sruntime); 1983 break; 1984 default: 1985 break; 1986 } 1987 1988 return 0; 1989 } 1990 1991 static int wcd9335_set_channel_map(struct snd_soc_dai *dai, 1992 unsigned int tx_num, unsigned int *tx_slot, 1993 unsigned int rx_num, unsigned int *rx_slot) 1994 { 1995 struct wcd9335_codec *wcd; 1996 int i; 1997 1998 wcd = snd_soc_component_get_drvdata(dai->component); 1999 2000 if (!tx_slot || !rx_slot) { 2001 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 2002 tx_slot, rx_slot); 2003 return -EINVAL; 2004 } 2005 2006 wcd->num_rx_port = rx_num; 2007 for (i = 0; i < rx_num; i++) { 2008 wcd->rx_chs[i].ch_num = rx_slot[i]; 2009 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 2010 } 2011 2012 wcd->num_tx_port = tx_num; 2013 for (i = 0; i < tx_num; i++) { 2014 wcd->tx_chs[i].ch_num = tx_slot[i]; 2015 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 2016 } 2017 2018 return 0; 2019 } 2020 2021 static int wcd9335_get_channel_map(struct snd_soc_dai *dai, 2022 unsigned int *tx_num, unsigned int *tx_slot, 2023 unsigned int *rx_num, unsigned int *rx_slot) 2024 { 2025 struct wcd9335_slim_ch *ch; 2026 struct wcd9335_codec *wcd; 2027 int i = 0; 2028 2029 wcd = snd_soc_component_get_drvdata(dai->component); 2030 2031 switch (dai->id) { 2032 case AIF1_PB: 2033 case AIF2_PB: 2034 case AIF3_PB: 2035 case AIF4_PB: 2036 if (!rx_slot || !rx_num) { 2037 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 2038 rx_slot, rx_num); 2039 return -EINVAL; 2040 } 2041 2042 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2043 rx_slot[i++] = ch->ch_num; 2044 2045 *rx_num = i; 2046 break; 2047 case AIF1_CAP: 2048 case AIF2_CAP: 2049 case AIF3_CAP: 2050 if (!tx_slot || !tx_num) { 2051 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 2052 tx_slot, tx_num); 2053 return -EINVAL; 2054 } 2055 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2056 tx_slot[i++] = ch->ch_num; 2057 2058 *tx_num = i; 2059 break; 2060 default: 2061 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 2062 break; 2063 } 2064 2065 return 0; 2066 } 2067 2068 static const struct snd_soc_dai_ops wcd9335_dai_ops = { 2069 .hw_params = wcd9335_hw_params, 2070 .trigger = wcd9335_trigger, 2071 .set_channel_map = wcd9335_set_channel_map, 2072 .get_channel_map = wcd9335_get_channel_map, 2073 }; 2074 2075 static struct snd_soc_dai_driver wcd9335_slim_dais[] = { 2076 [0] = { 2077 .name = "wcd9335_rx1", 2078 .id = AIF1_PB, 2079 .playback = { 2080 .stream_name = "AIF1 Playback", 2081 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2082 SNDRV_PCM_RATE_384000, 2083 .formats = WCD9335_FORMATS_S16_S24_LE, 2084 .rate_max = 384000, 2085 .rate_min = 8000, 2086 .channels_min = 1, 2087 .channels_max = 2, 2088 }, 2089 .ops = &wcd9335_dai_ops, 2090 }, 2091 [1] = { 2092 .name = "wcd9335_tx1", 2093 .id = AIF1_CAP, 2094 .capture = { 2095 .stream_name = "AIF1 Capture", 2096 .rates = WCD9335_RATES_MASK, 2097 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2098 .rate_min = 8000, 2099 .rate_max = 192000, 2100 .channels_min = 1, 2101 .channels_max = 4, 2102 }, 2103 .ops = &wcd9335_dai_ops, 2104 }, 2105 [2] = { 2106 .name = "wcd9335_rx2", 2107 .id = AIF2_PB, 2108 .playback = { 2109 .stream_name = "AIF2 Playback", 2110 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2111 SNDRV_PCM_RATE_384000, 2112 .formats = WCD9335_FORMATS_S16_S24_LE, 2113 .rate_min = 8000, 2114 .rate_max = 384000, 2115 .channels_min = 1, 2116 .channels_max = 2, 2117 }, 2118 .ops = &wcd9335_dai_ops, 2119 }, 2120 [3] = { 2121 .name = "wcd9335_tx2", 2122 .id = AIF2_CAP, 2123 .capture = { 2124 .stream_name = "AIF2 Capture", 2125 .rates = WCD9335_RATES_MASK, 2126 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2127 .rate_min = 8000, 2128 .rate_max = 192000, 2129 .channels_min = 1, 2130 .channels_max = 4, 2131 }, 2132 .ops = &wcd9335_dai_ops, 2133 }, 2134 [4] = { 2135 .name = "wcd9335_rx3", 2136 .id = AIF3_PB, 2137 .playback = { 2138 .stream_name = "AIF3 Playback", 2139 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2140 SNDRV_PCM_RATE_384000, 2141 .formats = WCD9335_FORMATS_S16_S24_LE, 2142 .rate_min = 8000, 2143 .rate_max = 384000, 2144 .channels_min = 1, 2145 .channels_max = 2, 2146 }, 2147 .ops = &wcd9335_dai_ops, 2148 }, 2149 [5] = { 2150 .name = "wcd9335_tx3", 2151 .id = AIF3_CAP, 2152 .capture = { 2153 .stream_name = "AIF3 Capture", 2154 .rates = WCD9335_RATES_MASK, 2155 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2156 .rate_min = 8000, 2157 .rate_max = 192000, 2158 .channels_min = 1, 2159 .channels_max = 4, 2160 }, 2161 .ops = &wcd9335_dai_ops, 2162 }, 2163 [6] = { 2164 .name = "wcd9335_rx4", 2165 .id = AIF4_PB, 2166 .playback = { 2167 .stream_name = "AIF4 Playback", 2168 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2169 SNDRV_PCM_RATE_384000, 2170 .formats = WCD9335_FORMATS_S16_S24_LE, 2171 .rate_min = 8000, 2172 .rate_max = 384000, 2173 .channels_min = 1, 2174 .channels_max = 2, 2175 }, 2176 .ops = &wcd9335_dai_ops, 2177 }, 2178 }; 2179 2180 static int wcd9335_get_compander(struct snd_kcontrol *kc, 2181 struct snd_ctl_elem_value *ucontrol) 2182 { 2183 2184 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2185 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 2186 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2187 2188 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 2189 return 0; 2190 } 2191 2192 static int wcd9335_set_compander(struct snd_kcontrol *kc, 2193 struct snd_ctl_elem_value *ucontrol) 2194 { 2195 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2196 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2197 int comp = ((struct soc_mixer_control *) kc->private_value)->shift; 2198 int value = ucontrol->value.integer.value[0]; 2199 int sel; 2200 2201 wcd->comp_enabled[comp] = value; 2202 sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER : 2203 WCD9335_HPH_GAIN_SRC_SEL_REGISTER; 2204 2205 /* Any specific register configuration for compander */ 2206 switch (comp) { 2207 case COMPANDER_1: 2208 /* Set Gain Source Select based on compander enable/disable */ 2209 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 2210 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2211 break; 2212 case COMPANDER_2: 2213 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 2214 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2215 break; 2216 case COMPANDER_5: 2217 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN, 2218 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2219 break; 2220 case COMPANDER_6: 2221 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN, 2222 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2223 break; 2224 default: 2225 break; 2226 } 2227 2228 return 0; 2229 } 2230 2231 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc, 2232 struct snd_ctl_elem_value *ucontrol) 2233 { 2234 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2235 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2236 2237 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 2238 2239 return 0; 2240 } 2241 2242 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc, 2243 struct snd_ctl_elem_value *ucontrol) 2244 { 2245 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2246 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2247 u32 mode_val; 2248 2249 mode_val = ucontrol->value.enumerated.item[0]; 2250 2251 if (mode_val == 0) { 2252 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 2253 mode_val = CLS_H_HIFI; 2254 } 2255 wcd->hph_mode = mode_val; 2256 2257 return 0; 2258 } 2259 2260 static const struct snd_kcontrol_new wcd9335_snd_controls[] = { 2261 /* -84dB min - 40dB max */ 2262 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL, 2263 -84, 40, digital_gain), 2264 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL, 2265 -84, 40, digital_gain), 2266 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL, 2267 -84, 40, digital_gain), 2268 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL, 2269 -84, 40, digital_gain), 2270 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL, 2271 -84, 40, digital_gain), 2272 SOC_SINGLE_S8_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL, 2273 -84, 40, digital_gain), 2274 SOC_SINGLE_S8_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL, 2275 -84, 40, digital_gain), 2276 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL, 2277 -84, 40, digital_gain), 2278 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL, 2279 -84, 40, digital_gain), 2280 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", WCD9335_CDC_RX0_RX_VOL_MIX_CTL, 2281 -84, 40, digital_gain), 2282 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", WCD9335_CDC_RX1_RX_VOL_MIX_CTL, 2283 -84, 40, digital_gain), 2284 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", WCD9335_CDC_RX2_RX_VOL_MIX_CTL, 2285 -84, 40, digital_gain), 2286 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", WCD9335_CDC_RX3_RX_VOL_MIX_CTL, 2287 -84, 40, digital_gain), 2288 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", WCD9335_CDC_RX4_RX_VOL_MIX_CTL, 2289 -84, 40, digital_gain), 2290 SOC_SINGLE_S8_TLV("RX5 Mix Digital Volume", WCD9335_CDC_RX5_RX_VOL_MIX_CTL, 2291 -84, 40, digital_gain), 2292 SOC_SINGLE_S8_TLV("RX6 Mix Digital Volume", WCD9335_CDC_RX6_RX_VOL_MIX_CTL, 2293 -84, 40, digital_gain), 2294 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", WCD9335_CDC_RX7_RX_VOL_MIX_CTL, 2295 -84, 40, digital_gain), 2296 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", WCD9335_CDC_RX8_RX_VOL_MIX_CTL, 2297 -84, 40, digital_gain), 2298 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 2299 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 2300 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 2301 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 2302 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 2303 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 2304 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 2305 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 2306 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 2307 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 2308 SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum), 2309 SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum), 2310 SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum), 2311 SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum), 2312 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 2313 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 2314 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 2315 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 2316 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 2317 wcd9335_get_compander, wcd9335_set_compander), 2318 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 2319 wcd9335_get_compander, wcd9335_set_compander), 2320 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 2321 wcd9335_get_compander, wcd9335_set_compander), 2322 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 2323 wcd9335_get_compander, wcd9335_set_compander), 2324 SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0, 2325 wcd9335_get_compander, wcd9335_set_compander), 2326 SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0, 2327 wcd9335_get_compander, wcd9335_set_compander), 2328 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 2329 wcd9335_get_compander, wcd9335_set_compander), 2330 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 2331 wcd9335_get_compander, wcd9335_set_compander), 2332 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2333 wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put), 2334 2335 /* Gain Controls */ 2336 SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1, 2337 ear_pa_gain), 2338 SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1, 2339 line_gain), 2340 SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1, 2341 line_gain), 2342 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER, 2343 3, 16, 1, line_gain), 2344 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER, 2345 3, 16, 1, line_gain), 2346 SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1, 2347 line_gain), 2348 SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1, 2349 line_gain), 2350 2351 SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0, 2352 analog_gain), 2353 SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0, 2354 analog_gain), 2355 SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0, 2356 analog_gain), 2357 SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0, 2358 analog_gain), 2359 SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0, 2360 analog_gain), 2361 SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0, 2362 analog_gain), 2363 2364 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 2365 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 2366 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 2367 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 2368 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 2369 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 2370 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 2371 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 2372 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 2373 }; 2374 2375 static const struct snd_soc_dapm_route wcd9335_audio_map[] = { 2376 {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"}, 2377 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"}, 2378 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"}, 2379 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"}, 2380 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"}, 2381 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"}, 2382 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"}, 2383 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"}, 2384 2385 {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"}, 2386 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"}, 2387 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"}, 2388 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"}, 2389 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"}, 2390 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"}, 2391 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"}, 2392 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"}, 2393 2394 {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"}, 2395 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"}, 2396 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"}, 2397 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"}, 2398 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"}, 2399 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"}, 2400 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"}, 2401 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"}, 2402 2403 {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"}, 2404 {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"}, 2405 {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"}, 2406 {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"}, 2407 {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"}, 2408 {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"}, 2409 {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"}, 2410 {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"}, 2411 2412 {"SLIM RX0", NULL, "SLIM RX0 MUX"}, 2413 {"SLIM RX1", NULL, "SLIM RX1 MUX"}, 2414 {"SLIM RX2", NULL, "SLIM RX2 MUX"}, 2415 {"SLIM RX3", NULL, "SLIM RX3 MUX"}, 2416 {"SLIM RX4", NULL, "SLIM RX4 MUX"}, 2417 {"SLIM RX5", NULL, "SLIM RX5 MUX"}, 2418 {"SLIM RX6", NULL, "SLIM RX6 MUX"}, 2419 {"SLIM RX7", NULL, "SLIM RX7 MUX"}, 2420 2421 WCD9335_INTERPOLATOR_PATH(0), 2422 WCD9335_INTERPOLATOR_PATH(1), 2423 WCD9335_INTERPOLATOR_PATH(2), 2424 WCD9335_INTERPOLATOR_PATH(3), 2425 WCD9335_INTERPOLATOR_PATH(4), 2426 WCD9335_INTERPOLATOR_PATH(5), 2427 WCD9335_INTERPOLATOR_PATH(6), 2428 WCD9335_INTERPOLATOR_PATH(7), 2429 WCD9335_INTERPOLATOR_PATH(8), 2430 2431 /* EAR PA */ 2432 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"}, 2433 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 2434 {"RX INT0 DAC", NULL, "RX_BIAS"}, 2435 {"EAR PA", NULL, "RX INT0 DAC"}, 2436 {"EAR", NULL, "EAR PA"}, 2437 2438 /* HPHL */ 2439 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"}, 2440 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 2441 {"RX INT1 DAC", NULL, "RX_BIAS"}, 2442 {"HPHL PA", NULL, "RX INT1 DAC"}, 2443 {"HPHL", NULL, "HPHL PA"}, 2444 2445 /* HPHR */ 2446 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"}, 2447 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 2448 {"RX INT2 DAC", NULL, "RX_BIAS"}, 2449 {"HPHR PA", NULL, "RX INT2 DAC"}, 2450 {"HPHR", NULL, "HPHR PA"}, 2451 2452 /* LINEOUT1 */ 2453 {"RX INT3 DAC", NULL, "RX INT3 INTERP"}, 2454 {"RX INT3 DAC", NULL, "RX_BIAS"}, 2455 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 2456 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 2457 2458 /* LINEOUT2 */ 2459 {"RX INT4 DAC", NULL, "RX INT4 INTERP"}, 2460 {"RX INT4 DAC", NULL, "RX_BIAS"}, 2461 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 2462 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 2463 2464 /* LINEOUT3 */ 2465 {"RX INT5 DAC", NULL, "RX INT5 INTERP"}, 2466 {"RX INT5 DAC", NULL, "RX_BIAS"}, 2467 {"LINEOUT3 PA", NULL, "RX INT5 DAC"}, 2468 {"LINEOUT3", NULL, "LINEOUT3 PA"}, 2469 2470 /* LINEOUT4 */ 2471 {"RX INT6 DAC", NULL, "RX INT6 INTERP"}, 2472 {"RX INT6 DAC", NULL, "RX_BIAS"}, 2473 {"LINEOUT4 PA", NULL, "RX INT6 DAC"}, 2474 {"LINEOUT4", NULL, "LINEOUT4 PA"}, 2475 2476 /* SLIMBUS Connections */ 2477 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 2478 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 2479 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 2480 2481 /* ADC Mux */ 2482 WCD9335_ADC_MUX_PATH(0), 2483 WCD9335_ADC_MUX_PATH(1), 2484 WCD9335_ADC_MUX_PATH(2), 2485 WCD9335_ADC_MUX_PATH(3), 2486 WCD9335_ADC_MUX_PATH(4), 2487 WCD9335_ADC_MUX_PATH(5), 2488 WCD9335_ADC_MUX_PATH(6), 2489 WCD9335_ADC_MUX_PATH(7), 2490 WCD9335_ADC_MUX_PATH(8), 2491 2492 /* ADC Connections */ 2493 {"ADC1", NULL, "AMIC1"}, 2494 {"ADC2", NULL, "AMIC2"}, 2495 {"ADC3", NULL, "AMIC3"}, 2496 {"ADC4", NULL, "AMIC4"}, 2497 {"ADC5", NULL, "AMIC5"}, 2498 {"ADC6", NULL, "AMIC6"}, 2499 }; 2500 2501 static int wcd9335_micbias_control(struct snd_soc_component *component, 2502 int micb_num, int req, bool is_dapm) 2503 { 2504 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component); 2505 int micb_index = micb_num - 1; 2506 u16 micb_reg; 2507 2508 if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) { 2509 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n", 2510 micb_index); 2511 return -EINVAL; 2512 } 2513 2514 switch (micb_num) { 2515 case MIC_BIAS_1: 2516 micb_reg = WCD9335_ANA_MICB1; 2517 break; 2518 case MIC_BIAS_2: 2519 micb_reg = WCD9335_ANA_MICB2; 2520 break; 2521 case MIC_BIAS_3: 2522 micb_reg = WCD9335_ANA_MICB3; 2523 break; 2524 case MIC_BIAS_4: 2525 micb_reg = WCD9335_ANA_MICB4; 2526 break; 2527 default: 2528 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2529 __func__, micb_num); 2530 return -EINVAL; 2531 } 2532 2533 switch (req) { 2534 case MICB_PULLUP_ENABLE: 2535 wcd->pullup_ref[micb_index]++; 2536 if ((wcd->pullup_ref[micb_index] == 1) && 2537 (wcd->micb_ref[micb_index] == 0)) 2538 snd_soc_component_update_bits(component, micb_reg, 2539 0xC0, 0x80); 2540 break; 2541 case MICB_PULLUP_DISABLE: 2542 wcd->pullup_ref[micb_index]--; 2543 if ((wcd->pullup_ref[micb_index] == 0) && 2544 (wcd->micb_ref[micb_index] == 0)) 2545 snd_soc_component_update_bits(component, micb_reg, 2546 0xC0, 0x00); 2547 break; 2548 case MICB_ENABLE: 2549 wcd->micb_ref[micb_index]++; 2550 if (wcd->micb_ref[micb_index] == 1) 2551 snd_soc_component_update_bits(component, micb_reg, 2552 0xC0, 0x40); 2553 break; 2554 case MICB_DISABLE: 2555 wcd->micb_ref[micb_index]--; 2556 if ((wcd->micb_ref[micb_index] == 0) && 2557 (wcd->pullup_ref[micb_index] > 0)) 2558 snd_soc_component_update_bits(component, micb_reg, 2559 0xC0, 0x80); 2560 else if ((wcd->micb_ref[micb_index] == 0) && 2561 (wcd->pullup_ref[micb_index] == 0)) { 2562 snd_soc_component_update_bits(component, micb_reg, 2563 0xC0, 0x00); 2564 } 2565 break; 2566 } 2567 2568 return 0; 2569 } 2570 2571 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2572 int event) 2573 { 2574 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2575 int micb_num; 2576 2577 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1"))) 2578 micb_num = MIC_BIAS_1; 2579 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2"))) 2580 micb_num = MIC_BIAS_2; 2581 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3"))) 2582 micb_num = MIC_BIAS_3; 2583 else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4"))) 2584 micb_num = MIC_BIAS_4; 2585 else 2586 return -EINVAL; 2587 2588 switch (event) { 2589 case SND_SOC_DAPM_PRE_PMU: 2590 /* 2591 * MIC BIAS can also be requested by MBHC, 2592 * so use ref count to handle micbias pullup 2593 * and enable requests 2594 */ 2595 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true); 2596 break; 2597 case SND_SOC_DAPM_POST_PMU: 2598 /* wait for cnp time */ 2599 usleep_range(1000, 1100); 2600 break; 2601 case SND_SOC_DAPM_POST_PMD: 2602 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true); 2603 break; 2604 } 2605 2606 return 0; 2607 } 2608 2609 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2610 struct snd_kcontrol *kc, int event) 2611 { 2612 return __wcd9335_codec_enable_micbias(w, event); 2613 } 2614 2615 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp, 2616 u16 amic_reg, bool set) 2617 { 2618 u8 mask = 0x20; 2619 u8 val; 2620 2621 if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 || 2622 amic_reg == WCD9335_ANA_AMIC5) 2623 mask = 0x40; 2624 2625 val = set ? mask : 0x00; 2626 2627 switch (amic_reg) { 2628 case WCD9335_ANA_AMIC1: 2629 case WCD9335_ANA_AMIC2: 2630 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask, 2631 val); 2632 break; 2633 case WCD9335_ANA_AMIC3: 2634 case WCD9335_ANA_AMIC4: 2635 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask, 2636 val); 2637 break; 2638 case WCD9335_ANA_AMIC5: 2639 case WCD9335_ANA_AMIC6: 2640 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask, 2641 val); 2642 break; 2643 default: 2644 dev_err(comp->dev, "%s: invalid amic: %d\n", 2645 __func__, amic_reg); 2646 break; 2647 } 2648 } 2649 2650 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w, 2651 struct snd_kcontrol *kc, int event) 2652 { 2653 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2654 2655 switch (event) { 2656 case SND_SOC_DAPM_PRE_PMU: 2657 wcd9335_codec_set_tx_hold(comp, w->reg, true); 2658 break; 2659 default: 2660 break; 2661 } 2662 2663 return 0; 2664 } 2665 2666 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp, 2667 int adc_mux_n) 2668 { 2669 int mux_sel, reg, mreg; 2670 2671 if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX || 2672 adc_mux_n == WCD9335_INVALID_ADC_MUX) 2673 return 0; 2674 2675 /* Check whether adc mux input is AMIC or DMIC */ 2676 if (adc_mux_n < 4) { 2677 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n; 2678 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n; 2679 mux_sel = snd_soc_component_read(comp, reg) & 0x3; 2680 } else { 2681 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4; 2682 mreg = reg; 2683 mux_sel = snd_soc_component_read(comp, reg) >> 6; 2684 } 2685 2686 if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC) 2687 return 0; 2688 2689 return snd_soc_component_read(comp, mreg) & 0x07; 2690 } 2691 2692 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 2693 int amic) 2694 { 2695 u16 pwr_level_reg = 0; 2696 2697 switch (amic) { 2698 case 1: 2699 case 2: 2700 pwr_level_reg = WCD9335_ANA_AMIC1; 2701 break; 2702 2703 case 3: 2704 case 4: 2705 pwr_level_reg = WCD9335_ANA_AMIC3; 2706 break; 2707 2708 case 5: 2709 case 6: 2710 pwr_level_reg = WCD9335_ANA_AMIC5; 2711 break; 2712 default: 2713 dev_err(comp->dev, "invalid amic: %d\n", amic); 2714 break; 2715 } 2716 2717 return pwr_level_reg; 2718 } 2719 2720 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w, 2721 struct snd_kcontrol *kc, int event) 2722 { 2723 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2724 unsigned int decimator; 2725 char *dec_adc_mux_name = NULL; 2726 char *widget_name = NULL; 2727 char *wname; 2728 int ret = 0, amic_n; 2729 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 2730 u16 tx_gain_ctl_reg; 2731 char *dec; 2732 u8 hpf_coff_freq; 2733 2734 widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL); 2735 if (!widget_name) 2736 return -ENOMEM; 2737 2738 wname = widget_name; 2739 dec_adc_mux_name = strsep(&widget_name, " "); 2740 if (!dec_adc_mux_name) { 2741 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2742 __func__, w->name); 2743 ret = -EINVAL; 2744 goto out; 2745 } 2746 dec_adc_mux_name = widget_name; 2747 2748 dec = strpbrk(dec_adc_mux_name, "012345678"); 2749 if (!dec) { 2750 dev_err(comp->dev, "%s: decimator index not found\n", 2751 __func__); 2752 ret = -EINVAL; 2753 goto out; 2754 } 2755 2756 ret = kstrtouint(dec, 10, &decimator); 2757 if (ret < 0) { 2758 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2759 __func__, wname); 2760 ret = -EINVAL; 2761 goto out; 2762 } 2763 2764 tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator; 2765 hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 2766 dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 2767 tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator; 2768 2769 switch (event) { 2770 case SND_SOC_DAPM_PRE_PMU: 2771 amic_n = wcd9335_codec_find_amic_input(comp, decimator); 2772 if (amic_n) 2773 pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp, 2774 amic_n); 2775 2776 if (pwr_level_reg) { 2777 switch ((snd_soc_component_read(comp, pwr_level_reg) & 2778 WCD9335_AMIC_PWR_LVL_MASK) >> 2779 WCD9335_AMIC_PWR_LVL_SHIFT) { 2780 case WCD9335_AMIC_PWR_LEVEL_LP: 2781 snd_soc_component_update_bits(comp, dec_cfg_reg, 2782 WCD9335_DEC_PWR_LVL_MASK, 2783 WCD9335_DEC_PWR_LVL_LP); 2784 break; 2785 2786 case WCD9335_AMIC_PWR_LEVEL_HP: 2787 snd_soc_component_update_bits(comp, dec_cfg_reg, 2788 WCD9335_DEC_PWR_LVL_MASK, 2789 WCD9335_DEC_PWR_LVL_HP); 2790 break; 2791 case WCD9335_AMIC_PWR_LEVEL_DEFAULT: 2792 default: 2793 snd_soc_component_update_bits(comp, dec_cfg_reg, 2794 WCD9335_DEC_PWR_LVL_MASK, 2795 WCD9335_DEC_PWR_LVL_DF); 2796 break; 2797 } 2798 } 2799 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 2800 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2801 2802 if (hpf_coff_freq != CF_MIN_3DB_150HZ) 2803 snd_soc_component_update_bits(comp, dec_cfg_reg, 2804 TX_HPF_CUT_OFF_FREQ_MASK, 2805 CF_MIN_3DB_150HZ << 5); 2806 /* Enable TX PGA Mute */ 2807 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2808 0x10, 0x10); 2809 /* Enable APC */ 2810 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08); 2811 break; 2812 case SND_SOC_DAPM_POST_PMU: 2813 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00); 2814 2815 if (decimator == 0) { 2816 snd_soc_component_write(comp, 2817 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2818 snd_soc_component_write(comp, 2819 WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3); 2820 snd_soc_component_write(comp, 2821 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2822 snd_soc_component_write(comp, 2823 WCD9335_MBHC_ZDET_RAMP_CTL, 0x03); 2824 } 2825 2826 snd_soc_component_update_bits(comp, hpf_gate_reg, 2827 0x01, 0x01); 2828 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2829 0x10, 0x00); 2830 snd_soc_component_write(comp, tx_gain_ctl_reg, 2831 snd_soc_component_read(comp, tx_gain_ctl_reg)); 2832 break; 2833 case SND_SOC_DAPM_PRE_PMD: 2834 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 2835 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2836 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10); 2837 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00); 2838 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 2839 snd_soc_component_update_bits(comp, dec_cfg_reg, 2840 TX_HPF_CUT_OFF_FREQ_MASK, 2841 hpf_coff_freq << 5); 2842 } 2843 break; 2844 case SND_SOC_DAPM_POST_PMD: 2845 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00); 2846 break; 2847 } 2848 out: 2849 kfree(wname); 2850 return ret; 2851 } 2852 2853 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component, 2854 u32 mclk_rate, u32 dmic_clk_rate) 2855 { 2856 u32 div_factor; 2857 u8 dmic_ctl_val; 2858 2859 dev_err(component->dev, 2860 "%s: mclk_rate = %d, dmic_sample_rate = %d\n", 2861 __func__, mclk_rate, dmic_clk_rate); 2862 2863 /* Default value to return in case of error */ 2864 if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 2865 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2866 else 2867 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2868 2869 if (dmic_clk_rate == 0) { 2870 dev_err(component->dev, 2871 "%s: dmic_sample_rate cannot be 0\n", 2872 __func__); 2873 goto done; 2874 } 2875 2876 div_factor = mclk_rate / dmic_clk_rate; 2877 switch (div_factor) { 2878 case 2: 2879 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2880 break; 2881 case 3: 2882 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2883 break; 2884 case 4: 2885 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4; 2886 break; 2887 case 6: 2888 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6; 2889 break; 2890 case 8: 2891 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8; 2892 break; 2893 case 16: 2894 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16; 2895 break; 2896 default: 2897 dev_err(component->dev, 2898 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n", 2899 __func__, div_factor, mclk_rate, dmic_clk_rate); 2900 break; 2901 } 2902 2903 done: 2904 return dmic_ctl_val; 2905 } 2906 2907 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w, 2908 struct snd_kcontrol *kc, int event) 2909 { 2910 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2911 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 2912 u8 dmic_clk_en = 0x01; 2913 u16 dmic_clk_reg; 2914 s32 *dmic_clk_cnt; 2915 u8 dmic_rate_val, dmic_rate_shift = 1; 2916 unsigned int dmic; 2917 int ret; 2918 char *wname; 2919 2920 wname = strpbrk(w->name, "012345"); 2921 if (!wname) { 2922 dev_err(comp->dev, "%s: widget not found\n", __func__); 2923 return -EINVAL; 2924 } 2925 2926 ret = kstrtouint(wname, 10, &dmic); 2927 if (ret < 0) { 2928 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 2929 __func__); 2930 return -EINVAL; 2931 } 2932 2933 switch (dmic) { 2934 case 0: 2935 case 1: 2936 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt); 2937 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL; 2938 break; 2939 case 2: 2940 case 3: 2941 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt); 2942 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL; 2943 break; 2944 case 4: 2945 case 5: 2946 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt); 2947 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL; 2948 break; 2949 default: 2950 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 2951 __func__); 2952 return -EINVAL; 2953 } 2954 2955 switch (event) { 2956 case SND_SOC_DAPM_PRE_PMU: 2957 dmic_rate_val = 2958 wcd9335_get_dmic_clk_val(comp, 2959 wcd->mclk_rate, 2960 wcd->dmic_sample_rate); 2961 2962 (*dmic_clk_cnt)++; 2963 if (*dmic_clk_cnt == 1) { 2964 snd_soc_component_update_bits(comp, dmic_clk_reg, 2965 0x07 << dmic_rate_shift, 2966 dmic_rate_val << dmic_rate_shift); 2967 snd_soc_component_update_bits(comp, dmic_clk_reg, 2968 dmic_clk_en, dmic_clk_en); 2969 } 2970 2971 break; 2972 case SND_SOC_DAPM_POST_PMD: 2973 dmic_rate_val = 2974 wcd9335_get_dmic_clk_val(comp, 2975 wcd->mclk_rate, 2976 wcd->mad_dmic_sample_rate); 2977 (*dmic_clk_cnt)--; 2978 if (*dmic_clk_cnt == 0) { 2979 snd_soc_component_update_bits(comp, dmic_clk_reg, 2980 dmic_clk_en, 0); 2981 snd_soc_component_update_bits(comp, dmic_clk_reg, 2982 0x07 << dmic_rate_shift, 2983 dmic_rate_val << dmic_rate_shift); 2984 } 2985 break; 2986 } 2987 2988 return 0; 2989 } 2990 2991 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 2992 struct snd_soc_component *component) 2993 { 2994 int port_num = 0; 2995 unsigned short reg = 0; 2996 unsigned int val = 0; 2997 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2998 struct wcd9335_slim_ch *ch; 2999 3000 list_for_each_entry(ch, &dai->slim_ch_list, list) { 3001 if (ch->port >= WCD9335_RX_START) { 3002 port_num = ch->port - WCD9335_RX_START; 3003 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 3004 } else { 3005 port_num = ch->port; 3006 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 3007 } 3008 3009 regmap_read(wcd->if_regmap, reg, &val); 3010 if (!(val & BIT(port_num % 8))) 3011 regmap_write(wcd->if_regmap, reg, 3012 val | BIT(port_num % 8)); 3013 } 3014 } 3015 3016 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w, 3017 struct snd_kcontrol *kc, 3018 int event) 3019 { 3020 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3021 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 3022 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 3023 3024 switch (event) { 3025 case SND_SOC_DAPM_POST_PMU: 3026 wcd9335_codec_enable_int_port(dai, comp); 3027 break; 3028 case SND_SOC_DAPM_POST_PMD: 3029 kfree(dai->sconfig.chs); 3030 3031 break; 3032 } 3033 3034 return 0; 3035 } 3036 3037 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 3038 struct snd_kcontrol *kc, int event) 3039 { 3040 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3041 u16 gain_reg; 3042 int offset_val = 0; 3043 int val = 0; 3044 3045 switch (w->reg) { 3046 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3047 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL; 3048 break; 3049 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3050 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL; 3051 break; 3052 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3053 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL; 3054 break; 3055 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3056 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL; 3057 break; 3058 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3059 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL; 3060 break; 3061 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3062 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL; 3063 break; 3064 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3065 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL; 3066 break; 3067 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3068 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL; 3069 break; 3070 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3071 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL; 3072 break; 3073 default: 3074 dev_err(comp->dev, "%s: No gain register avail for %s\n", 3075 __func__, w->name); 3076 return 0; 3077 } 3078 3079 switch (event) { 3080 case SND_SOC_DAPM_POST_PMU: 3081 val = snd_soc_component_read(comp, gain_reg); 3082 val += offset_val; 3083 snd_soc_component_write(comp, gain_reg, val); 3084 break; 3085 case SND_SOC_DAPM_POST_PMD: 3086 break; 3087 } 3088 3089 return 0; 3090 } 3091 3092 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind) 3093 { 3094 u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3095 3096 switch (reg) { 3097 case WCD9335_CDC_RX0_RX_PATH_CTL: 3098 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3099 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3100 *ind = 0; 3101 break; 3102 case WCD9335_CDC_RX1_RX_PATH_CTL: 3103 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3104 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3105 *ind = 1; 3106 break; 3107 case WCD9335_CDC_RX2_RX_PATH_CTL: 3108 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3109 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3110 *ind = 2; 3111 break; 3112 case WCD9335_CDC_RX3_RX_PATH_CTL: 3113 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3114 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3115 *ind = 3; 3116 break; 3117 case WCD9335_CDC_RX4_RX_PATH_CTL: 3118 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3119 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3120 *ind = 4; 3121 break; 3122 case WCD9335_CDC_RX5_RX_PATH_CTL: 3123 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3124 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3125 *ind = 5; 3126 break; 3127 case WCD9335_CDC_RX6_RX_PATH_CTL: 3128 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3129 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3130 *ind = 6; 3131 break; 3132 case WCD9335_CDC_RX7_RX_PATH_CTL: 3133 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3134 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3135 *ind = 7; 3136 break; 3137 case WCD9335_CDC_RX8_RX_PATH_CTL: 3138 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3139 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3140 *ind = 8; 3141 break; 3142 } 3143 3144 return prim_int_reg; 3145 } 3146 3147 static void wcd9335_codec_hd2_control(struct snd_soc_component *component, 3148 u16 prim_int_reg, int event) 3149 { 3150 u16 hd2_scale_reg; 3151 u16 hd2_enable_reg = 0; 3152 3153 if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) { 3154 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3; 3155 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 3156 } 3157 if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) { 3158 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3; 3159 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 3160 } 3161 3162 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 3163 snd_soc_component_update_bits(component, hd2_scale_reg, 3164 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3165 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500); 3166 snd_soc_component_update_bits(component, hd2_scale_reg, 3167 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3168 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2); 3169 snd_soc_component_update_bits(component, hd2_enable_reg, 3170 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3171 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE); 3172 } 3173 3174 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 3175 snd_soc_component_update_bits(component, hd2_enable_reg, 3176 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3177 WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE); 3178 snd_soc_component_update_bits(component, hd2_scale_reg, 3179 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3180 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1); 3181 snd_soc_component_update_bits(component, hd2_scale_reg, 3182 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3183 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 3184 } 3185 } 3186 3187 static int wcd9335_codec_enable_prim_interpolator( 3188 struct snd_soc_component *comp, 3189 u16 reg, int event) 3190 { 3191 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3192 u16 ind = 0; 3193 int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind); 3194 3195 switch (event) { 3196 case SND_SOC_DAPM_PRE_PMU: 3197 wcd->prim_int_users[ind]++; 3198 if (wcd->prim_int_users[ind] == 1) { 3199 snd_soc_component_update_bits(comp, prim_int_reg, 3200 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3201 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3202 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3203 snd_soc_component_update_bits(comp, prim_int_reg, 3204 WCD9335_CDC_RX_CLK_EN_MASK, 3205 WCD9335_CDC_RX_CLK_ENABLE); 3206 } 3207 3208 if ((reg != prim_int_reg) && 3209 ((snd_soc_component_read(comp, prim_int_reg)) & 3210 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)) 3211 snd_soc_component_update_bits(comp, reg, 3212 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3213 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3214 break; 3215 case SND_SOC_DAPM_POST_PMD: 3216 wcd->prim_int_users[ind]--; 3217 if (wcd->prim_int_users[ind] == 0) { 3218 snd_soc_component_update_bits(comp, prim_int_reg, 3219 WCD9335_CDC_RX_CLK_EN_MASK, 3220 WCD9335_CDC_RX_CLK_DISABLE); 3221 snd_soc_component_update_bits(comp, prim_int_reg, 3222 WCD9335_CDC_RX_RESET_MASK, 3223 WCD9335_CDC_RX_RESET_ENABLE); 3224 snd_soc_component_update_bits(comp, prim_int_reg, 3225 WCD9335_CDC_RX_RESET_MASK, 3226 WCD9335_CDC_RX_RESET_DISABLE); 3227 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3228 } 3229 break; 3230 } 3231 3232 return 0; 3233 } 3234 3235 static int wcd9335_config_compander(struct snd_soc_component *component, 3236 int interp_n, int event) 3237 { 3238 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3239 int comp; 3240 u16 comp_ctl0_reg, rx_path_cfg0_reg; 3241 3242 /* EAR does not have compander */ 3243 if (!interp_n) 3244 return 0; 3245 3246 comp = interp_n - 1; 3247 if (!wcd->comp_enabled[comp]) 3248 return 0; 3249 3250 comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp); 3251 rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp); 3252 3253 if (SND_SOC_DAPM_EVENT_ON(event)) { 3254 /* Enable Compander Clock */ 3255 snd_soc_component_update_bits(component, comp_ctl0_reg, 3256 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3257 WCD9335_CDC_COMPANDER_CLK_ENABLE); 3258 /* Reset comander */ 3259 snd_soc_component_update_bits(component, comp_ctl0_reg, 3260 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3261 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3262 snd_soc_component_update_bits(component, comp_ctl0_reg, 3263 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3264 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3265 /* Enables DRE in this path */ 3266 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3267 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3268 WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE); 3269 } 3270 3271 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3272 snd_soc_component_update_bits(component, comp_ctl0_reg, 3273 WCD9335_CDC_COMPANDER_HALT_MASK, 3274 WCD9335_CDC_COMPANDER_HALT); 3275 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3276 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3277 WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE); 3278 3279 snd_soc_component_update_bits(component, comp_ctl0_reg, 3280 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3281 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3282 snd_soc_component_update_bits(component, comp_ctl0_reg, 3283 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3284 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3285 snd_soc_component_update_bits(component, comp_ctl0_reg, 3286 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3287 WCD9335_CDC_COMPANDER_CLK_DISABLE); 3288 snd_soc_component_update_bits(component, comp_ctl0_reg, 3289 WCD9335_CDC_COMPANDER_HALT_MASK, 3290 WCD9335_CDC_COMPANDER_NOHALT); 3291 } 3292 3293 return 0; 3294 } 3295 3296 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w, 3297 struct snd_kcontrol *kc, int event) 3298 { 3299 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3300 u16 gain_reg; 3301 u16 reg; 3302 int val; 3303 int offset_val = 0; 3304 3305 if (!(strcmp(w->name, "RX INT0 INTERP"))) { 3306 reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3307 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL; 3308 } else if (!(strcmp(w->name, "RX INT1 INTERP"))) { 3309 reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3310 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL; 3311 } else if (!(strcmp(w->name, "RX INT2 INTERP"))) { 3312 reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3313 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL; 3314 } else if (!(strcmp(w->name, "RX INT3 INTERP"))) { 3315 reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3316 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL; 3317 } else if (!(strcmp(w->name, "RX INT4 INTERP"))) { 3318 reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3319 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL; 3320 } else if (!(strcmp(w->name, "RX INT5 INTERP"))) { 3321 reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3322 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL; 3323 } else if (!(strcmp(w->name, "RX INT6 INTERP"))) { 3324 reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3325 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL; 3326 } else if (!(strcmp(w->name, "RX INT7 INTERP"))) { 3327 reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3328 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL; 3329 } else if (!(strcmp(w->name, "RX INT8 INTERP"))) { 3330 reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3331 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL; 3332 } else { 3333 dev_err(comp->dev, "%s: Interpolator reg not found\n", 3334 __func__); 3335 return -EINVAL; 3336 } 3337 3338 switch (event) { 3339 case SND_SOC_DAPM_PRE_PMU: 3340 /* Reset if needed */ 3341 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3342 break; 3343 case SND_SOC_DAPM_POST_PMU: 3344 wcd9335_config_compander(comp, w->shift, event); 3345 val = snd_soc_component_read(comp, gain_reg); 3346 val += offset_val; 3347 snd_soc_component_write(comp, gain_reg, val); 3348 break; 3349 case SND_SOC_DAPM_POST_PMD: 3350 wcd9335_config_compander(comp, w->shift, event); 3351 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3352 break; 3353 } 3354 3355 return 0; 3356 } 3357 3358 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component, 3359 u8 gain) 3360 { 3361 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3362 u8 hph_l_en, hph_r_en; 3363 u8 l_val, r_val; 3364 u8 hph_pa_status; 3365 bool is_hphl_pa, is_hphr_pa; 3366 3367 hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH); 3368 is_hphl_pa = hph_pa_status >> 7; 3369 is_hphr_pa = (hph_pa_status & 0x40) >> 6; 3370 3371 hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN); 3372 hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN); 3373 3374 l_val = (hph_l_en & 0xC0) | 0x20 | gain; 3375 r_val = (hph_r_en & 0xC0) | 0x20 | gain; 3376 3377 /* 3378 * Set HPH_L & HPH_R gain source selection to REGISTER 3379 * for better click and pop only if corresponding PAs are 3380 * not enabled. Also cache the values of the HPHL/R 3381 * PA gains to be applied after PAs are enabled 3382 */ 3383 if ((l_val != hph_l_en) && !is_hphl_pa) { 3384 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val); 3385 wcd->hph_l_gain = hph_l_en & 0x1F; 3386 } 3387 3388 if ((r_val != hph_r_en) && !is_hphr_pa) { 3389 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val); 3390 wcd->hph_r_gain = hph_r_en & 0x1F; 3391 } 3392 } 3393 3394 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp, 3395 int event) 3396 { 3397 if (SND_SOC_DAPM_EVENT_ON(event)) { 3398 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3399 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3400 0x06); 3401 snd_soc_component_update_bits(comp, 3402 WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3403 0xF0, 0x40); 3404 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3405 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3406 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3407 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3408 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3409 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3410 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3411 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3412 0x0C); 3413 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3414 } 3415 3416 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3417 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3418 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3419 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3420 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3421 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3422 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3423 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3424 0x8A); 3425 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3426 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3427 0x0A); 3428 } 3429 } 3430 3431 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp, 3432 int event) 3433 { 3434 if (SND_SOC_DAPM_EVENT_ON(event)) { 3435 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3436 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3437 0x0C); 3438 wcd9335_codec_hph_mode_gain_opt(comp, 0x10); 3439 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3440 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3441 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3442 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3443 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3444 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3445 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3446 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3447 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE); 3448 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3449 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3450 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE); 3451 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3452 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK, 3453 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60); 3454 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3455 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK, 3456 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60); 3457 snd_soc_component_update_bits(comp, 3458 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01); 3459 snd_soc_component_update_bits(comp, 3460 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10); 3461 } 3462 3463 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3464 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO, 3465 0x88); 3466 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL, 3467 0x33); 3468 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3469 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3470 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE); 3471 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3472 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3473 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE); 3474 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3475 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3476 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3477 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3478 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3479 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3480 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN, 3481 WCD9335_HPH_CONST_SEL_L_MASK, 3482 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3483 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN, 3484 WCD9335_HPH_CONST_SEL_L_MASK, 3485 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3486 } 3487 } 3488 3489 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp, 3490 int event) 3491 { 3492 if (SND_SOC_DAPM_EVENT_ON(event)) { 3493 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3494 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3495 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3496 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3497 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3498 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3499 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3500 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3501 0x0C); 3502 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3503 } 3504 3505 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3506 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3507 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3508 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3509 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3510 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3511 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3512 } 3513 } 3514 3515 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component, 3516 int event, int mode) 3517 { 3518 switch (mode) { 3519 case CLS_H_LP: 3520 wcd9335_codec_hph_lp_config(component, event); 3521 break; 3522 case CLS_H_LOHIFI: 3523 wcd9335_codec_hph_lohifi_config(component, event); 3524 break; 3525 case CLS_H_HIFI: 3526 wcd9335_codec_hph_hifi_config(component, event); 3527 break; 3528 } 3529 } 3530 3531 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 3532 struct snd_kcontrol *kc, 3533 int event) 3534 { 3535 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3536 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3537 int hph_mode = wcd->hph_mode; 3538 u8 dem_inp; 3539 3540 switch (event) { 3541 case SND_SOC_DAPM_PRE_PMU: 3542 /* Read DEM INP Select */ 3543 dem_inp = snd_soc_component_read(comp, 3544 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03; 3545 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3546 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3547 dev_err(comp->dev, "Incorrect DEM Input\n"); 3548 return -EINVAL; 3549 } 3550 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3551 WCD_CLSH_STATE_HPHL, 3552 ((hph_mode == CLS_H_LOHIFI) ? 3553 CLS_H_HIFI : hph_mode)); 3554 3555 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3556 3557 break; 3558 case SND_SOC_DAPM_POST_PMU: 3559 usleep_range(1000, 1100); 3560 break; 3561 case SND_SOC_DAPM_PRE_PMD: 3562 break; 3563 case SND_SOC_DAPM_POST_PMD: 3564 /* 1000us required as per HW requirement */ 3565 usleep_range(1000, 1100); 3566 3567 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3568 WCD_CLSH_STATE_HPHR)) 3569 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3570 3571 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3572 WCD_CLSH_STATE_HPHL, 3573 ((hph_mode == CLS_H_LOHIFI) ? 3574 CLS_H_HIFI : hph_mode)); 3575 break; 3576 } 3577 3578 return 0; 3579 } 3580 3581 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 3582 struct snd_kcontrol *kc, int event) 3583 { 3584 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3585 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3586 3587 switch (event) { 3588 case SND_SOC_DAPM_PRE_PMU: 3589 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3590 WCD_CLSH_STATE_LO, CLS_AB); 3591 break; 3592 case SND_SOC_DAPM_POST_PMD: 3593 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3594 WCD_CLSH_STATE_LO, CLS_AB); 3595 break; 3596 } 3597 3598 return 0; 3599 } 3600 3601 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 3602 struct snd_kcontrol *kc, int event) 3603 { 3604 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3605 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3606 3607 switch (event) { 3608 case SND_SOC_DAPM_PRE_PMU: 3609 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3610 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3611 3612 break; 3613 case SND_SOC_DAPM_POST_PMD: 3614 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3615 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3616 break; 3617 } 3618 3619 return 0; 3620 } 3621 3622 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd, 3623 int mode, int event) 3624 { 3625 u8 scale_val = 0; 3626 3627 switch (event) { 3628 case SND_SOC_DAPM_POST_PMU: 3629 switch (mode) { 3630 case CLS_H_HIFI: 3631 scale_val = 0x3; 3632 break; 3633 case CLS_H_LOHIFI: 3634 scale_val = 0x1; 3635 break; 3636 } 3637 break; 3638 case SND_SOC_DAPM_PRE_PMD: 3639 scale_val = 0x6; 3640 break; 3641 } 3642 3643 if (scale_val) 3644 snd_soc_component_update_bits(wcd->component, 3645 WCD9335_HPH_PA_CTL1, 3646 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3647 scale_val << 1); 3648 if (SND_SOC_DAPM_EVENT_ON(event)) { 3649 if (wcd->comp_enabled[COMPANDER_1] || 3650 wcd->comp_enabled[COMPANDER_2]) { 3651 /* GAIN Source Selection */ 3652 snd_soc_component_update_bits(wcd->component, 3653 WCD9335_HPH_L_EN, 3654 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3655 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3656 snd_soc_component_update_bits(wcd->component, 3657 WCD9335_HPH_R_EN, 3658 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3659 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3660 snd_soc_component_update_bits(wcd->component, 3661 WCD9335_HPH_AUTO_CHOP, 3662 WCD9335_HPH_AUTO_CHOP_MASK, 3663 WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE); 3664 } 3665 snd_soc_component_update_bits(wcd->component, 3666 WCD9335_HPH_L_EN, 3667 WCD9335_HPH_PA_GAIN_MASK, 3668 wcd->hph_l_gain); 3669 snd_soc_component_update_bits(wcd->component, 3670 WCD9335_HPH_R_EN, 3671 WCD9335_HPH_PA_GAIN_MASK, 3672 wcd->hph_r_gain); 3673 } 3674 3675 if (SND_SOC_DAPM_EVENT_OFF(event)) 3676 snd_soc_component_update_bits(wcd->component, 3677 WCD9335_HPH_AUTO_CHOP, 3678 WCD9335_HPH_AUTO_CHOP_MASK, 3679 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN); 3680 } 3681 3682 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 3683 struct snd_kcontrol *kc, 3684 int event) 3685 { 3686 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3687 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3688 int hph_mode = wcd->hph_mode; 3689 u8 dem_inp; 3690 3691 switch (event) { 3692 case SND_SOC_DAPM_PRE_PMU: 3693 3694 /* Read DEM INP Select */ 3695 dem_inp = snd_soc_component_read(comp, 3696 WCD9335_CDC_RX2_RX_PATH_SEC0) & 3697 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK; 3698 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3699 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3700 dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n", 3701 hph_mode); 3702 return -EINVAL; 3703 } 3704 3705 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, 3706 WCD_CLSH_EVENT_PRE_DAC, 3707 WCD_CLSH_STATE_HPHR, 3708 ((hph_mode == CLS_H_LOHIFI) ? 3709 CLS_H_HIFI : hph_mode)); 3710 3711 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3712 3713 break; 3714 case SND_SOC_DAPM_POST_PMD: 3715 /* 1000us required as per HW requirement */ 3716 usleep_range(1000, 1100); 3717 3718 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3719 WCD_CLSH_STATE_HPHL)) 3720 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3721 3722 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3723 WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ? 3724 CLS_H_HIFI : hph_mode)); 3725 break; 3726 } 3727 3728 return 0; 3729 } 3730 3731 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 3732 struct snd_kcontrol *kc, 3733 int event) 3734 { 3735 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3736 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3737 int hph_mode = wcd->hph_mode; 3738 3739 switch (event) { 3740 case SND_SOC_DAPM_PRE_PMU: 3741 break; 3742 case SND_SOC_DAPM_POST_PMU: 3743 /* 3744 * 7ms sleep is required after PA is enabled as per 3745 * HW requirement 3746 */ 3747 usleep_range(7000, 7100); 3748 3749 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3750 snd_soc_component_update_bits(comp, 3751 WCD9335_CDC_RX1_RX_PATH_CTL, 3752 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3753 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3754 3755 /* Remove mix path mute if it is enabled */ 3756 if ((snd_soc_component_read(comp, 3757 WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) & 3758 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3759 snd_soc_component_update_bits(comp, 3760 WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 3761 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3762 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3763 3764 break; 3765 case SND_SOC_DAPM_PRE_PMD: 3766 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3767 break; 3768 case SND_SOC_DAPM_POST_PMD: 3769 /* 5ms sleep is required after PA is disabled as per 3770 * HW requirement 3771 */ 3772 usleep_range(5000, 5500); 3773 break; 3774 } 3775 3776 return 0; 3777 } 3778 3779 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w, 3780 struct snd_kcontrol *kc, 3781 int event) 3782 { 3783 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3784 int vol_reg = 0, mix_vol_reg = 0; 3785 3786 if (w->reg == WCD9335_ANA_LO_1_2) { 3787 if (w->shift == 7) { 3788 vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3789 mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL; 3790 } else if (w->shift == 6) { 3791 vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3792 mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL; 3793 } 3794 } else if (w->reg == WCD9335_ANA_LO_3_4) { 3795 if (w->shift == 7) { 3796 vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3797 mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL; 3798 } else if (w->shift == 6) { 3799 vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3800 mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL; 3801 } 3802 } else { 3803 dev_err(comp->dev, "Error enabling lineout PA\n"); 3804 return -EINVAL; 3805 } 3806 3807 switch (event) { 3808 case SND_SOC_DAPM_POST_PMU: 3809 /* 5ms sleep is required after PA is enabled as per 3810 * HW requirement 3811 */ 3812 usleep_range(5000, 5500); 3813 snd_soc_component_update_bits(comp, vol_reg, 3814 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3815 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3816 3817 /* Remove mix path mute if it is enabled */ 3818 if ((snd_soc_component_read(comp, mix_vol_reg)) & 3819 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3820 snd_soc_component_update_bits(comp, mix_vol_reg, 3821 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3822 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3823 break; 3824 case SND_SOC_DAPM_POST_PMD: 3825 /* 5ms sleep is required after PA is disabled as per 3826 * HW requirement 3827 */ 3828 usleep_range(5000, 5500); 3829 break; 3830 } 3831 3832 return 0; 3833 } 3834 3835 static void wcd9335_codec_init_flyback(struct snd_soc_component *component) 3836 { 3837 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 3838 WCD9335_HPH_CONST_SEL_L_MASK, 3839 WCD9335_HPH_CONST_SEL_L_BYPASS); 3840 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 3841 WCD9335_HPH_CONST_SEL_L_MASK, 3842 WCD9335_HPH_CONST_SEL_L_BYPASS); 3843 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3844 WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK, 3845 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3846 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3847 WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK, 3848 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3849 } 3850 3851 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w, 3852 struct snd_kcontrol *kc, int event) 3853 { 3854 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3855 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3856 3857 switch (event) { 3858 case SND_SOC_DAPM_PRE_PMU: 3859 wcd->rx_bias_count++; 3860 if (wcd->rx_bias_count == 1) { 3861 wcd9335_codec_init_flyback(comp); 3862 snd_soc_component_update_bits(comp, 3863 WCD9335_ANA_RX_SUPPLIES, 3864 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3865 WCD9335_ANA_RX_BIAS_ENABLE); 3866 } 3867 break; 3868 case SND_SOC_DAPM_POST_PMD: 3869 wcd->rx_bias_count--; 3870 if (!wcd->rx_bias_count) 3871 snd_soc_component_update_bits(comp, 3872 WCD9335_ANA_RX_SUPPLIES, 3873 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3874 WCD9335_ANA_RX_BIAS_DISABLE); 3875 break; 3876 } 3877 3878 return 0; 3879 } 3880 3881 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 3882 struct snd_kcontrol *kc, int event) 3883 { 3884 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3885 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3886 int hph_mode = wcd->hph_mode; 3887 3888 switch (event) { 3889 case SND_SOC_DAPM_PRE_PMU: 3890 break; 3891 case SND_SOC_DAPM_POST_PMU: 3892 /* 3893 * 7ms sleep is required after PA is enabled as per 3894 * HW requirement 3895 */ 3896 usleep_range(7000, 7100); 3897 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3898 snd_soc_component_update_bits(comp, 3899 WCD9335_CDC_RX2_RX_PATH_CTL, 3900 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3901 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3902 /* Remove mix path mute if it is enabled */ 3903 if ((snd_soc_component_read(comp, 3904 WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) & 3905 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3906 snd_soc_component_update_bits(comp, 3907 WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 3908 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3909 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3910 3911 break; 3912 3913 case SND_SOC_DAPM_PRE_PMD: 3914 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3915 break; 3916 case SND_SOC_DAPM_POST_PMD: 3917 /* 5ms sleep is required after PA is disabled as per 3918 * HW requirement 3919 */ 3920 usleep_range(5000, 5500); 3921 break; 3922 } 3923 3924 return 0; 3925 } 3926 3927 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 3928 struct snd_kcontrol *kc, int event) 3929 { 3930 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3931 3932 switch (event) { 3933 case SND_SOC_DAPM_POST_PMU: 3934 /* 5ms sleep is required after PA is enabled as per 3935 * HW requirement 3936 */ 3937 usleep_range(5000, 5500); 3938 snd_soc_component_update_bits(comp, 3939 WCD9335_CDC_RX0_RX_PATH_CTL, 3940 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3941 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3942 /* Remove mix path mute if it is enabled */ 3943 if ((snd_soc_component_read(comp, 3944 WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) & 3945 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3946 snd_soc_component_update_bits(comp, 3947 WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 3948 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3949 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3950 break; 3951 case SND_SOC_DAPM_POST_PMD: 3952 /* 5ms sleep is required after PA is disabled as per 3953 * HW requirement 3954 */ 3955 usleep_range(5000, 5500); 3956 3957 break; 3958 } 3959 3960 return 0; 3961 } 3962 3963 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data) 3964 { 3965 struct wcd9335_codec *wcd = data; 3966 unsigned long status = 0; 3967 int i, j, port_id; 3968 unsigned int val, int_val = 0; 3969 irqreturn_t ret = IRQ_NONE; 3970 bool tx; 3971 unsigned short reg = 0; 3972 3973 for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 3974 i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 3975 regmap_read(wcd->if_regmap, i, &val); 3976 status |= ((u32)val << (8 * j)); 3977 } 3978 3979 for_each_set_bit(j, &status, 32) { 3980 tx = (j >= 16); 3981 port_id = (tx ? j - 16 : j); 3982 regmap_read(wcd->if_regmap, 3983 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 3984 if (val) { 3985 if (!tx) 3986 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 3987 (port_id / 8); 3988 else 3989 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 3990 (port_id / 8); 3991 regmap_read( 3992 wcd->if_regmap, reg, &int_val); 3993 /* 3994 * Ignore interrupts for ports for which the 3995 * interrupts are not specifically enabled. 3996 */ 3997 if (!(int_val & (1 << (port_id % 8)))) 3998 continue; 3999 } 4000 4001 if (val & WCD9335_SLIM_IRQ_OVERFLOW) 4002 dev_err_ratelimited(wcd->dev, 4003 "%s: overflow error on %s port %d, value %x\n", 4004 __func__, (tx ? "TX" : "RX"), port_id, val); 4005 4006 if (val & WCD9335_SLIM_IRQ_UNDERFLOW) 4007 dev_err_ratelimited(wcd->dev, 4008 "%s: underflow error on %s port %d, value %x\n", 4009 __func__, (tx ? "TX" : "RX"), port_id, val); 4010 4011 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) || 4012 (val & WCD9335_SLIM_IRQ_UNDERFLOW)) { 4013 if (!tx) 4014 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 4015 (port_id / 8); 4016 else 4017 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 4018 (port_id / 8); 4019 regmap_read( 4020 wcd->if_regmap, reg, &int_val); 4021 if (int_val & (1 << (port_id % 8))) { 4022 int_val = int_val ^ (1 << (port_id % 8)); 4023 regmap_write(wcd->if_regmap, 4024 reg, int_val); 4025 } 4026 } 4027 4028 regmap_write(wcd->if_regmap, 4029 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 4030 BIT(j % 8)); 4031 ret = IRQ_HANDLED; 4032 } 4033 4034 return ret; 4035 } 4036 4037 static struct wcd9335_irq wcd9335_irqs[] = { 4038 { 4039 .irq = WCD9335_IRQ_SLIMBUS, 4040 .handler = wcd9335_slimbus_irq, 4041 .name = "SLIM Slave", 4042 }, 4043 }; 4044 4045 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd) 4046 { 4047 int irq, ret, i; 4048 4049 for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) { 4050 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq); 4051 if (irq < 0) { 4052 dev_err(wcd->dev, "Failed to get %s\n", 4053 wcd9335_irqs[i].name); 4054 return irq; 4055 } 4056 4057 ret = devm_request_threaded_irq(wcd->dev, irq, NULL, 4058 wcd9335_irqs[i].handler, 4059 IRQF_TRIGGER_RISING | 4060 IRQF_ONESHOT, 4061 wcd9335_irqs[i].name, wcd); 4062 if (ret) { 4063 dev_err(wcd->dev, "Failed to request %s\n", 4064 wcd9335_irqs[i].name); 4065 return ret; 4066 } 4067 } 4068 4069 /* enable interrupts on all slave ports */ 4070 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4071 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4072 0xFF); 4073 4074 return ret; 4075 } 4076 4077 static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd) 4078 { 4079 int i; 4080 4081 /* disable interrupts on all slave ports */ 4082 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4083 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4084 0x00); 4085 } 4086 4087 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd, 4088 bool ccl_flag) 4089 { 4090 struct snd_soc_component *comp = wcd->component; 4091 4092 if (ccl_flag) { 4093 if (++wcd->sido_ccl_cnt == 1) 4094 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4095 WCD9335_SIDO_SIDO_CCL_DEF_VALUE); 4096 } else { 4097 if (wcd->sido_ccl_cnt == 0) { 4098 dev_err(wcd->dev, "sido_ccl already disabled\n"); 4099 return; 4100 } 4101 if (--wcd->sido_ccl_cnt == 0) 4102 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4103 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF); 4104 } 4105 } 4106 4107 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd) 4108 { 4109 wcd->master_bias_users++; 4110 if (wcd->master_bias_users == 1) { 4111 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4112 WCD9335_ANA_BIAS_EN_MASK, 4113 WCD9335_ANA_BIAS_ENABLE); 4114 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4115 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4116 WCD9335_ANA_BIAS_PRECHRG_ENABLE); 4117 /* 4118 * 1ms delay is required after pre-charge is enabled 4119 * as per HW requirement 4120 */ 4121 usleep_range(1000, 1100); 4122 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4123 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4124 WCD9335_ANA_BIAS_PRECHRG_DISABLE); 4125 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4126 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4127 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4128 } 4129 4130 return 0; 4131 } 4132 4133 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd) 4134 { 4135 /* Enable mclk requires master bias to be enabled first */ 4136 if (wcd->master_bias_users <= 0) 4137 return -EINVAL; 4138 4139 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) || 4140 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) { 4141 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n", 4142 wcd->clk_type); 4143 return -EINVAL; 4144 } 4145 4146 if (++wcd->clk_mclk_users == 1) { 4147 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4148 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4149 WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE); 4150 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4151 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4152 WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL); 4153 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4154 WCD9335_ANA_CLK_MCLK_EN_MASK, 4155 WCD9335_ANA_CLK_MCLK_ENABLE); 4156 regmap_update_bits(wcd->regmap, 4157 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 4158 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK, 4159 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE); 4160 regmap_update_bits(wcd->regmap, 4161 WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL, 4162 WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK, 4163 WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE); 4164 /* 4165 * 10us sleep is required after clock is enabled 4166 * as per HW requirement 4167 */ 4168 usleep_range(10, 15); 4169 } 4170 4171 wcd->clk_type = WCD_CLK_MCLK; 4172 4173 return 0; 4174 } 4175 4176 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd) 4177 { 4178 if (wcd->clk_mclk_users <= 0) 4179 return -EINVAL; 4180 4181 if (--wcd->clk_mclk_users == 0) { 4182 if (wcd->clk_rco_users > 0) { 4183 /* MCLK to RCO switch */ 4184 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4185 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4186 WCD9335_ANA_CLK_MCLK_SRC_RCO); 4187 wcd->clk_type = WCD_CLK_RCO; 4188 } else { 4189 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4190 WCD9335_ANA_CLK_MCLK_EN_MASK, 4191 WCD9335_ANA_CLK_MCLK_DISABLE); 4192 wcd->clk_type = WCD_CLK_OFF; 4193 } 4194 4195 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4196 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4197 WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE); 4198 } 4199 4200 return 0; 4201 } 4202 4203 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd) 4204 { 4205 if (wcd->master_bias_users <= 0) 4206 return -EINVAL; 4207 4208 wcd->master_bias_users--; 4209 if (wcd->master_bias_users == 0) { 4210 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4211 WCD9335_ANA_BIAS_EN_MASK, 4212 WCD9335_ANA_BIAS_DISABLE); 4213 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4214 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4215 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4216 } 4217 return 0; 4218 } 4219 4220 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd, 4221 bool enable) 4222 { 4223 int ret = 0; 4224 4225 if (enable) { 4226 wcd9335_cdc_sido_ccl_enable(wcd, true); 4227 ret = clk_prepare_enable(wcd->mclk); 4228 if (ret) { 4229 dev_err(wcd->dev, "%s: ext clk enable failed\n", 4230 __func__); 4231 goto err; 4232 } 4233 /* get BG */ 4234 wcd9335_enable_master_bias(wcd); 4235 /* get MCLK */ 4236 wcd9335_enable_mclk(wcd); 4237 4238 } else { 4239 /* put MCLK */ 4240 wcd9335_disable_mclk(wcd); 4241 /* put BG */ 4242 wcd9335_disable_master_bias(wcd); 4243 clk_disable_unprepare(wcd->mclk); 4244 wcd9335_cdc_sido_ccl_enable(wcd, false); 4245 } 4246 err: 4247 return ret; 4248 } 4249 4250 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd, 4251 enum wcd9335_sido_voltage req_mv) 4252 { 4253 struct snd_soc_component *comp = wcd->component; 4254 int vout_d_val; 4255 4256 if (req_mv == wcd->sido_voltage) 4257 return; 4258 4259 /* compute the vout_d step value */ 4260 vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) & 4261 WCD9335_ANA_BUCK_VOUT_MASK; 4262 snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val); 4263 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4264 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4265 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE); 4266 4267 /* 1 msec sleep required after SIDO Vout_D voltage change */ 4268 usleep_range(1000, 1100); 4269 wcd->sido_voltage = req_mv; 4270 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4271 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4272 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE); 4273 } 4274 4275 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd, 4276 enum wcd9335_sido_voltage req_mv) 4277 { 4278 int ret = 0; 4279 4280 /* enable mclk before setting SIDO voltage */ 4281 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4282 if (ret) { 4283 dev_err(wcd->dev, "Ext clk enable failed\n"); 4284 goto err; 4285 } 4286 4287 wcd9335_codec_apply_sido_voltage(wcd, req_mv); 4288 wcd9335_cdc_req_mclk_enable(wcd, false); 4289 4290 err: 4291 return ret; 4292 } 4293 4294 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component, 4295 int enable) 4296 { 4297 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4298 int ret; 4299 4300 if (enable) { 4301 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4302 if (ret) 4303 return ret; 4304 4305 wcd9335_codec_apply_sido_voltage(wcd, 4306 SIDO_VOLTAGE_NOMINAL_MV); 4307 } else { 4308 wcd9335_codec_update_sido_voltage(wcd, 4309 wcd->sido_voltage); 4310 wcd9335_cdc_req_mclk_enable(wcd, false); 4311 } 4312 4313 return 0; 4314 } 4315 4316 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w, 4317 struct snd_kcontrol *kc, int event) 4318 { 4319 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4320 4321 switch (event) { 4322 case SND_SOC_DAPM_PRE_PMU: 4323 return _wcd9335_codec_enable_mclk(comp, true); 4324 case SND_SOC_DAPM_POST_PMD: 4325 return _wcd9335_codec_enable_mclk(comp, false); 4326 } 4327 4328 return 0; 4329 } 4330 4331 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = { 4332 /* TODO SPK1 & SPK2 OUT*/ 4333 SND_SOC_DAPM_OUTPUT("EAR"), 4334 SND_SOC_DAPM_OUTPUT("HPHL"), 4335 SND_SOC_DAPM_OUTPUT("HPHR"), 4336 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 4337 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 4338 SND_SOC_DAPM_OUTPUT("LINEOUT3"), 4339 SND_SOC_DAPM_OUTPUT("LINEOUT4"), 4340 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 4341 AIF1_PB, 0, wcd9335_codec_enable_slim, 4342 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4343 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 4344 AIF2_PB, 0, wcd9335_codec_enable_slim, 4345 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4346 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 4347 AIF3_PB, 0, wcd9335_codec_enable_slim, 4348 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4349 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 4350 AIF4_PB, 0, wcd9335_codec_enable_slim, 4351 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4352 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0, 4353 &slim_rx_mux[WCD9335_RX0]), 4354 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0, 4355 &slim_rx_mux[WCD9335_RX1]), 4356 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0, 4357 &slim_rx_mux[WCD9335_RX2]), 4358 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0, 4359 &slim_rx_mux[WCD9335_RX3]), 4360 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0, 4361 &slim_rx_mux[WCD9335_RX4]), 4362 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0, 4363 &slim_rx_mux[WCD9335_RX5]), 4364 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0, 4365 &slim_rx_mux[WCD9335_RX6]), 4366 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0, 4367 &slim_rx_mux[WCD9335_RX7]), 4368 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 4369 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4370 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4371 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 4372 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 4373 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 4374 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 4375 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 4376 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 4377 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path, 4378 SND_SOC_DAPM_POST_PMU), 4379 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 4380 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path, 4381 SND_SOC_DAPM_POST_PMU), 4382 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 4383 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path, 4384 SND_SOC_DAPM_POST_PMU), 4385 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL, 4386 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path, 4387 SND_SOC_DAPM_POST_PMU), 4388 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL, 4389 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path, 4390 SND_SOC_DAPM_POST_PMU), 4391 SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL, 4392 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path, 4393 SND_SOC_DAPM_POST_PMU), 4394 SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL, 4395 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path, 4396 SND_SOC_DAPM_POST_PMU), 4397 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL, 4398 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path, 4399 SND_SOC_DAPM_POST_PMU), 4400 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL, 4401 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path, 4402 SND_SOC_DAPM_POST_PMU), 4403 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4404 &rx_int0_1_mix_inp0_mux), 4405 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4406 &rx_int0_1_mix_inp1_mux), 4407 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4408 &rx_int0_1_mix_inp2_mux), 4409 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4410 &rx_int1_1_mix_inp0_mux), 4411 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4412 &rx_int1_1_mix_inp1_mux), 4413 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4414 &rx_int1_1_mix_inp2_mux), 4415 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4416 &rx_int2_1_mix_inp0_mux), 4417 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4418 &rx_int2_1_mix_inp1_mux), 4419 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4420 &rx_int2_1_mix_inp2_mux), 4421 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4422 &rx_int3_1_mix_inp0_mux), 4423 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4424 &rx_int3_1_mix_inp1_mux), 4425 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4426 &rx_int3_1_mix_inp2_mux), 4427 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4428 &rx_int4_1_mix_inp0_mux), 4429 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4430 &rx_int4_1_mix_inp1_mux), 4431 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4432 &rx_int4_1_mix_inp2_mux), 4433 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4434 &rx_int5_1_mix_inp0_mux), 4435 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4436 &rx_int5_1_mix_inp1_mux), 4437 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4438 &rx_int5_1_mix_inp2_mux), 4439 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4440 &rx_int6_1_mix_inp0_mux), 4441 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4442 &rx_int6_1_mix_inp1_mux), 4443 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4444 &rx_int6_1_mix_inp2_mux), 4445 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4446 &rx_int7_1_mix_inp0_mux), 4447 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4448 &rx_int7_1_mix_inp1_mux), 4449 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4450 &rx_int7_1_mix_inp2_mux), 4451 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4452 &rx_int8_1_mix_inp0_mux), 4453 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4454 &rx_int8_1_mix_inp1_mux), 4455 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4456 &rx_int8_1_mix_inp2_mux), 4457 4458 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4459 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4460 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4461 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4462 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4463 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4464 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4465 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4466 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4467 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4468 SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4469 SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4470 SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4471 SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4472 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4473 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4474 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4475 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4476 4477 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4478 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4479 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4480 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4481 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4482 SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4483 SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4484 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4485 SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4486 4487 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 4488 &rx_int0_dem_inp_mux), 4489 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 4490 &rx_int1_dem_inp_mux), 4491 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 4492 &rx_int2_dem_inp_mux), 4493 4494 SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM, 4495 INTERP_EAR, 0, &rx_int0_interp_mux, 4496 wcd9335_codec_enable_interpolator, 4497 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4498 SND_SOC_DAPM_POST_PMD), 4499 SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM, 4500 INTERP_HPHL, 0, &rx_int1_interp_mux, 4501 wcd9335_codec_enable_interpolator, 4502 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4503 SND_SOC_DAPM_POST_PMD), 4504 SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM, 4505 INTERP_HPHR, 0, &rx_int2_interp_mux, 4506 wcd9335_codec_enable_interpolator, 4507 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4508 SND_SOC_DAPM_POST_PMD), 4509 SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM, 4510 INTERP_LO1, 0, &rx_int3_interp_mux, 4511 wcd9335_codec_enable_interpolator, 4512 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4513 SND_SOC_DAPM_POST_PMD), 4514 SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM, 4515 INTERP_LO2, 0, &rx_int4_interp_mux, 4516 wcd9335_codec_enable_interpolator, 4517 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4518 SND_SOC_DAPM_POST_PMD), 4519 SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM, 4520 INTERP_LO3, 0, &rx_int5_interp_mux, 4521 wcd9335_codec_enable_interpolator, 4522 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4523 SND_SOC_DAPM_POST_PMD), 4524 SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM, 4525 INTERP_LO4, 0, &rx_int6_interp_mux, 4526 wcd9335_codec_enable_interpolator, 4527 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4528 SND_SOC_DAPM_POST_PMD), 4529 SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM, 4530 INTERP_SPKR1, 0, &rx_int7_interp_mux, 4531 wcd9335_codec_enable_interpolator, 4532 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4533 SND_SOC_DAPM_POST_PMD), 4534 SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM, 4535 INTERP_SPKR2, 0, &rx_int8_interp_mux, 4536 wcd9335_codec_enable_interpolator, 4537 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4538 SND_SOC_DAPM_POST_PMD), 4539 4540 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 4541 0, 0, wcd9335_codec_ear_dac_event, 4542 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4543 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4544 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH, 4545 5, 0, wcd9335_codec_hphl_dac_event, 4546 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4547 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4548 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH, 4549 4, 0, wcd9335_codec_hphr_dac_event, 4550 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4551 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4552 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 4553 0, 0, wcd9335_codec_lineout_dac_event, 4554 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4555 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 4556 0, 0, wcd9335_codec_lineout_dac_event, 4557 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4558 SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM, 4559 0, 0, wcd9335_codec_lineout_dac_event, 4560 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4561 SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM, 4562 0, 0, wcd9335_codec_lineout_dac_event, 4563 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4564 SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0, 4565 wcd9335_codec_enable_hphl_pa, 4566 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4567 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4568 SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0, 4569 wcd9335_codec_enable_hphr_pa, 4570 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4571 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4572 SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0, 4573 wcd9335_codec_enable_ear_pa, 4574 SND_SOC_DAPM_POST_PMU | 4575 SND_SOC_DAPM_POST_PMD), 4576 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0, 4577 wcd9335_codec_enable_lineout_pa, 4578 SND_SOC_DAPM_POST_PMU | 4579 SND_SOC_DAPM_POST_PMD), 4580 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0, 4581 wcd9335_codec_enable_lineout_pa, 4582 SND_SOC_DAPM_POST_PMU | 4583 SND_SOC_DAPM_POST_PMD), 4584 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0, 4585 wcd9335_codec_enable_lineout_pa, 4586 SND_SOC_DAPM_POST_PMU | 4587 SND_SOC_DAPM_POST_PMD), 4588 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0, 4589 wcd9335_codec_enable_lineout_pa, 4590 SND_SOC_DAPM_POST_PMU | 4591 SND_SOC_DAPM_POST_PMD), 4592 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0, 4593 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU | 4594 SND_SOC_DAPM_POST_PMD), 4595 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 4596 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU | 4597 SND_SOC_DAPM_POST_PMD), 4598 4599 /* TX */ 4600 SND_SOC_DAPM_INPUT("AMIC1"), 4601 SND_SOC_DAPM_INPUT("AMIC2"), 4602 SND_SOC_DAPM_INPUT("AMIC3"), 4603 SND_SOC_DAPM_INPUT("AMIC4"), 4604 SND_SOC_DAPM_INPUT("AMIC5"), 4605 SND_SOC_DAPM_INPUT("AMIC6"), 4606 4607 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 4608 AIF1_CAP, 0, wcd9335_codec_enable_slim, 4609 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4610 4611 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 4612 AIF2_CAP, 0, wcd9335_codec_enable_slim, 4613 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4614 4615 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 4616 AIF3_CAP, 0, wcd9335_codec_enable_slim, 4617 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4618 4619 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0, 4620 wcd9335_codec_enable_micbias, 4621 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4622 SND_SOC_DAPM_POST_PMD), 4623 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0, 4624 wcd9335_codec_enable_micbias, 4625 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4626 SND_SOC_DAPM_POST_PMD), 4627 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0, 4628 wcd9335_codec_enable_micbias, 4629 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4630 SND_SOC_DAPM_POST_PMD), 4631 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0, 4632 wcd9335_codec_enable_micbias, 4633 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4634 SND_SOC_DAPM_POST_PMD), 4635 4636 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0, 4637 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4638 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0, 4639 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4640 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0, 4641 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4642 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0, 4643 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4644 SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0, 4645 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4646 SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0, 4647 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4648 4649 /* Digital Mic Inputs */ 4650 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 4651 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4652 SND_SOC_DAPM_POST_PMD), 4653 4654 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 4655 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4656 SND_SOC_DAPM_POST_PMD), 4657 4658 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 4659 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4660 SND_SOC_DAPM_POST_PMD), 4661 4662 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 4663 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4664 SND_SOC_DAPM_POST_PMD), 4665 4666 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 4667 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4668 SND_SOC_DAPM_POST_PMD), 4669 4670 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 4671 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4672 SND_SOC_DAPM_POST_PMD), 4673 4674 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, 4675 &tx_dmic_mux0), 4676 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, 4677 &tx_dmic_mux1), 4678 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, 4679 &tx_dmic_mux2), 4680 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, 4681 &tx_dmic_mux3), 4682 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, 4683 &tx_dmic_mux4), 4684 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, 4685 &tx_dmic_mux5), 4686 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, 4687 &tx_dmic_mux6), 4688 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, 4689 &tx_dmic_mux7), 4690 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, 4691 &tx_dmic_mux8), 4692 4693 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, 4694 &tx_amic_mux0), 4695 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, 4696 &tx_amic_mux1), 4697 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, 4698 &tx_amic_mux2), 4699 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, 4700 &tx_amic_mux3), 4701 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, 4702 &tx_amic_mux4), 4703 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, 4704 &tx_amic_mux5), 4705 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, 4706 &tx_amic_mux6), 4707 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, 4708 &tx_amic_mux7), 4709 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, 4710 &tx_amic_mux8), 4711 4712 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 4713 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)), 4714 4715 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 4716 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)), 4717 4718 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 4719 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)), 4720 4721 SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0, 4722 &sb_tx0_mux), 4723 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0, 4724 &sb_tx1_mux), 4725 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0, 4726 &sb_tx2_mux), 4727 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0, 4728 &sb_tx3_mux), 4729 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0, 4730 &sb_tx4_mux), 4731 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0, 4732 &sb_tx5_mux), 4733 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0, 4734 &sb_tx6_mux), 4735 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0, 4736 &sb_tx7_mux), 4737 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0, 4738 &sb_tx8_mux), 4739 4740 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0, 4741 &tx_adc_mux0, wcd9335_codec_enable_dec, 4742 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4743 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4744 4745 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0, 4746 &tx_adc_mux1, wcd9335_codec_enable_dec, 4747 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4748 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4749 4750 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0, 4751 &tx_adc_mux2, wcd9335_codec_enable_dec, 4752 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4753 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4754 4755 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0, 4756 &tx_adc_mux3, wcd9335_codec_enable_dec, 4757 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4758 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4759 4760 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0, 4761 &tx_adc_mux4, wcd9335_codec_enable_dec, 4762 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4763 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4764 4765 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0, 4766 &tx_adc_mux5, wcd9335_codec_enable_dec, 4767 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4768 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4769 4770 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0, 4771 &tx_adc_mux6, wcd9335_codec_enable_dec, 4772 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4773 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4774 4775 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0, 4776 &tx_adc_mux7, wcd9335_codec_enable_dec, 4777 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4778 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4779 4780 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0, 4781 &tx_adc_mux8, wcd9335_codec_enable_dec, 4782 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4783 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4784 }; 4785 4786 static void wcd9335_enable_sido_buck(struct snd_soc_component *component) 4787 { 4788 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4789 4790 snd_soc_component_update_bits(component, WCD9335_ANA_RCO, 4791 WCD9335_ANA_RCO_BG_EN_MASK, 4792 WCD9335_ANA_RCO_BG_ENABLE); 4793 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4794 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK, 4795 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT); 4796 /* 100us sleep needed after IREF settings */ 4797 usleep_range(100, 110); 4798 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4799 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK, 4800 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT); 4801 /* 100us sleep needed after VREF settings */ 4802 usleep_range(100, 110); 4803 wcd->sido_input_src = SIDO_SOURCE_RCO_BG; 4804 } 4805 4806 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp) 4807 { 4808 _wcd9335_codec_enable_mclk(comp, true); 4809 snd_soc_component_update_bits(comp, 4810 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 4811 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK, 4812 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE); 4813 /* 4814 * 5ms sleep required after enabling efuse control 4815 * before checking the status. 4816 */ 4817 usleep_range(5000, 5500); 4818 4819 if (!(snd_soc_component_read(comp, 4820 WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) & 4821 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK)) 4822 WARN(1, "%s: Efuse sense is not complete\n", __func__); 4823 4824 wcd9335_enable_sido_buck(comp); 4825 _wcd9335_codec_enable_mclk(comp, false); 4826 4827 return 0; 4828 } 4829 4830 static void wcd9335_codec_init(struct snd_soc_component *component) 4831 { 4832 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4833 int i; 4834 4835 /* ungate MCLK and set clk rate */ 4836 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE, 4837 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0); 4838 4839 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4840 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4841 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4842 4843 for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++) 4844 snd_soc_component_update_bits(component, 4845 wcd9335_codec_reg_init[i].reg, 4846 wcd9335_codec_reg_init[i].mask, 4847 wcd9335_codec_reg_init[i].val); 4848 4849 wcd9335_enable_efuse_sensing(component); 4850 } 4851 4852 static int wcd9335_codec_probe(struct snd_soc_component *component) 4853 { 4854 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4855 int ret; 4856 int i; 4857 4858 snd_soc_component_init_regmap(component, wcd->regmap); 4859 /* Class-H Init*/ 4860 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335); 4861 if (IS_ERR(wcd->clsh_ctrl)) 4862 return PTR_ERR(wcd->clsh_ctrl); 4863 4864 /* Default HPH Mode to Class-H HiFi */ 4865 wcd->hph_mode = CLS_H_HIFI; 4866 wcd->component = component; 4867 4868 wcd9335_codec_init(component); 4869 4870 for (i = 0; i < NUM_CODEC_DAIS; i++) 4871 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 4872 4873 ret = wcd9335_setup_irqs(wcd); 4874 if (ret) 4875 goto free_clsh_ctrl; 4876 4877 return 0; 4878 4879 free_clsh_ctrl: 4880 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4881 return ret; 4882 } 4883 4884 static void wcd9335_codec_remove(struct snd_soc_component *comp) 4885 { 4886 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4887 4888 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4889 wcd9335_teardown_irqs(wcd); 4890 } 4891 4892 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp, 4893 int clk_id, int source, 4894 unsigned int freq, int dir) 4895 { 4896 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4897 4898 wcd->mclk_rate = freq; 4899 4900 if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ) 4901 snd_soc_component_update_bits(comp, 4902 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4903 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4904 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ); 4905 else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 4906 snd_soc_component_update_bits(comp, 4907 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4908 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4909 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4910 4911 return clk_set_rate(wcd->mclk, freq); 4912 } 4913 4914 static const struct snd_soc_component_driver wcd9335_component_drv = { 4915 .probe = wcd9335_codec_probe, 4916 .remove = wcd9335_codec_remove, 4917 .set_sysclk = wcd9335_codec_set_sysclk, 4918 .controls = wcd9335_snd_controls, 4919 .num_controls = ARRAY_SIZE(wcd9335_snd_controls), 4920 .dapm_widgets = wcd9335_dapm_widgets, 4921 .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets), 4922 .dapm_routes = wcd9335_audio_map, 4923 .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map), 4924 .endianness = 1, 4925 }; 4926 4927 static int wcd9335_probe(struct wcd9335_codec *wcd) 4928 { 4929 struct device *dev = wcd->dev; 4930 4931 memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs)); 4932 memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs)); 4933 4934 wcd->sido_input_src = SIDO_SOURCE_INTERNAL; 4935 wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV; 4936 4937 return devm_snd_soc_register_component(dev, &wcd9335_component_drv, 4938 wcd9335_slim_dais, 4939 ARRAY_SIZE(wcd9335_slim_dais)); 4940 } 4941 4942 static const struct regmap_range_cfg wcd9335_ranges[] = { 4943 { 4944 .name = "WCD9335", 4945 .range_min = 0x0, 4946 .range_max = WCD9335_MAX_REGISTER, 4947 .selector_reg = WCD9335_SEL_REGISTER, 4948 .selector_mask = 0xff, 4949 .selector_shift = 0, 4950 .window_start = 0x800, 4951 .window_len = 0x100, 4952 }, 4953 }; 4954 4955 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg) 4956 { 4957 switch (reg) { 4958 case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3: 4959 case WCD9335_ANA_MBHC_RESULT_3: 4960 case WCD9335_ANA_MBHC_RESULT_2: 4961 case WCD9335_ANA_MBHC_RESULT_1: 4962 case WCD9335_ANA_MBHC_MECH: 4963 case WCD9335_ANA_MBHC_ELECT: 4964 case WCD9335_ANA_MBHC_ZDET: 4965 case WCD9335_ANA_MICB2: 4966 case WCD9335_ANA_RCO: 4967 case WCD9335_ANA_BIAS: 4968 return true; 4969 default: 4970 return false; 4971 } 4972 } 4973 4974 static struct regmap_config wcd9335_regmap_config = { 4975 .reg_bits = 16, 4976 .val_bits = 8, 4977 .cache_type = REGCACHE_RBTREE, 4978 .max_register = WCD9335_MAX_REGISTER, 4979 .can_multi_write = true, 4980 .ranges = wcd9335_ranges, 4981 .num_ranges = ARRAY_SIZE(wcd9335_ranges), 4982 .volatile_reg = wcd9335_is_volatile_register, 4983 }; 4984 4985 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = { 4986 { 4987 .name = "WCD9335-IFC-DEV", 4988 .range_min = 0x0, 4989 .range_max = WCD9335_MAX_REGISTER, 4990 .selector_reg = WCD9335_SEL_REGISTER, 4991 .selector_mask = 0xfff, 4992 .selector_shift = 0, 4993 .window_start = 0x800, 4994 .window_len = 0x400, 4995 }, 4996 }; 4997 4998 static struct regmap_config wcd9335_ifc_regmap_config = { 4999 .reg_bits = 16, 5000 .val_bits = 8, 5001 .can_multi_write = true, 5002 .max_register = WCD9335_MAX_REGISTER, 5003 .ranges = wcd9335_ifc_ranges, 5004 .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges), 5005 }; 5006 5007 static const struct regmap_irq wcd9335_codec_irqs[] = { 5008 /* INTR_REG 0 */ 5009 [WCD9335_IRQ_SLIMBUS] = { 5010 .reg_offset = 0, 5011 .mask = BIT(0), 5012 .type = { 5013 .type_reg_offset = 0, 5014 .types_supported = IRQ_TYPE_EDGE_BOTH, 5015 .type_reg_mask = BIT(0), 5016 }, 5017 }, 5018 }; 5019 5020 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = { 5021 .name = "wcd9335_pin1_irq", 5022 .status_base = WCD9335_INTR_PIN1_STATUS0, 5023 .mask_base = WCD9335_INTR_PIN1_MASK0, 5024 .ack_base = WCD9335_INTR_PIN1_CLEAR0, 5025 .type_base = WCD9335_INTR_LEVEL0, 5026 .num_type_reg = 4, 5027 .num_regs = 4, 5028 .irqs = wcd9335_codec_irqs, 5029 .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs), 5030 }; 5031 5032 static int wcd9335_parse_dt(struct wcd9335_codec *wcd) 5033 { 5034 struct device *dev = wcd->dev; 5035 struct device_node *np = dev->of_node; 5036 int ret; 5037 5038 wcd->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0); 5039 if (wcd->reset_gpio < 0) { 5040 dev_err(dev, "Reset GPIO missing from DT\n"); 5041 return wcd->reset_gpio; 5042 } 5043 5044 wcd->mclk = devm_clk_get(dev, "mclk"); 5045 if (IS_ERR(wcd->mclk)) { 5046 dev_err(dev, "mclk not found\n"); 5047 return PTR_ERR(wcd->mclk); 5048 } 5049 5050 wcd->native_clk = devm_clk_get(dev, "slimbus"); 5051 if (IS_ERR(wcd->native_clk)) { 5052 dev_err(dev, "slimbus clock not found\n"); 5053 return PTR_ERR(wcd->native_clk); 5054 } 5055 5056 wcd->supplies[0].supply = "vdd-buck"; 5057 wcd->supplies[1].supply = "vdd-buck-sido"; 5058 wcd->supplies[2].supply = "vdd-tx"; 5059 wcd->supplies[3].supply = "vdd-rx"; 5060 wcd->supplies[4].supply = "vdd-io"; 5061 5062 ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, wcd->supplies); 5063 if (ret) { 5064 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 5065 return ret; 5066 } 5067 5068 return 0; 5069 } 5070 5071 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd) 5072 { 5073 struct device *dev = wcd->dev; 5074 int ret; 5075 5076 ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, wcd->supplies); 5077 if (ret) { 5078 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 5079 return ret; 5080 } 5081 5082 /* 5083 * For WCD9335, it takes about 600us for the Vout_A and 5084 * Vout_D to be ready after BUCK_SIDO is powered up. 5085 * SYS_RST_N shouldn't be pulled high during this time 5086 * Toggle the reset line to make sure the reset pulse is 5087 * correctly applied 5088 */ 5089 usleep_range(600, 650); 5090 5091 gpio_direction_output(wcd->reset_gpio, 0); 5092 msleep(20); 5093 gpio_set_value(wcd->reset_gpio, 1); 5094 msleep(20); 5095 5096 return 0; 5097 } 5098 5099 static int wcd9335_bring_up(struct wcd9335_codec *wcd) 5100 { 5101 struct regmap *rm = wcd->regmap; 5102 int val, byte0; 5103 5104 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val); 5105 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0); 5106 5107 if ((val < 0) || (byte0 < 0)) { 5108 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n"); 5109 return -EINVAL; 5110 } 5111 5112 if (byte0 == 0x1) { 5113 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n"); 5114 wcd->version = WCD9335_VERSION_2_0; 5115 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01); 5116 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00); 5117 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F); 5118 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65); 5119 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5); 5120 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7); 5121 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3); 5122 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3); 5123 } else { 5124 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n"); 5125 return -EINVAL; 5126 } 5127 5128 return 0; 5129 } 5130 5131 static int wcd9335_irq_init(struct wcd9335_codec *wcd) 5132 { 5133 int ret; 5134 5135 /* 5136 * INTR1 consists of all possible interrupt sources Ear OCP, 5137 * HPH OCP, MBHC, MAD, VBAT, and SVA 5138 * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA 5139 */ 5140 wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1"); 5141 if (wcd->intr1 < 0) { 5142 if (wcd->intr1 != -EPROBE_DEFER) 5143 dev_err(wcd->dev, "Unable to configure IRQ\n"); 5144 5145 return wcd->intr1; 5146 } 5147 5148 ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1, 5149 IRQF_TRIGGER_HIGH, 0, 5150 &wcd9335_regmap_irq1_chip, &wcd->irq_data); 5151 if (ret) 5152 dev_err(wcd->dev, "Failed to register IRQ chip: %d\n", ret); 5153 5154 return ret; 5155 } 5156 5157 static int wcd9335_slim_probe(struct slim_device *slim) 5158 { 5159 struct device *dev = &slim->dev; 5160 struct wcd9335_codec *wcd; 5161 int ret; 5162 5163 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL); 5164 if (!wcd) 5165 return -ENOMEM; 5166 5167 wcd->dev = dev; 5168 ret = wcd9335_parse_dt(wcd); 5169 if (ret) { 5170 dev_err(dev, "Error parsing DT: %d\n", ret); 5171 return ret; 5172 } 5173 5174 ret = wcd9335_power_on_reset(wcd); 5175 if (ret) 5176 return ret; 5177 5178 dev_set_drvdata(dev, wcd); 5179 5180 return 0; 5181 } 5182 5183 static int wcd9335_slim_status(struct slim_device *sdev, 5184 enum slim_device_status status) 5185 { 5186 struct device *dev = &sdev->dev; 5187 struct device_node *ifc_dev_np; 5188 struct wcd9335_codec *wcd; 5189 int ret; 5190 5191 wcd = dev_get_drvdata(dev); 5192 5193 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5194 if (!ifc_dev_np) { 5195 dev_err(dev, "No Interface device found\n"); 5196 return -EINVAL; 5197 } 5198 5199 wcd->slim = sdev; 5200 wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np); 5201 of_node_put(ifc_dev_np); 5202 if (!wcd->slim_ifc_dev) { 5203 dev_err(dev, "Unable to get SLIM Interface device\n"); 5204 return -EINVAL; 5205 } 5206 5207 slim_get_logical_addr(wcd->slim_ifc_dev); 5208 5209 wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config); 5210 if (IS_ERR(wcd->regmap)) { 5211 dev_err(dev, "Failed to allocate slim register map\n"); 5212 return PTR_ERR(wcd->regmap); 5213 } 5214 5215 wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev, 5216 &wcd9335_ifc_regmap_config); 5217 if (IS_ERR(wcd->if_regmap)) { 5218 dev_err(dev, "Failed to allocate ifc register map\n"); 5219 return PTR_ERR(wcd->if_regmap); 5220 } 5221 5222 ret = wcd9335_bring_up(wcd); 5223 if (ret) { 5224 dev_err(dev, "Failed to bringup WCD9335\n"); 5225 return ret; 5226 } 5227 5228 ret = wcd9335_irq_init(wcd); 5229 if (ret) 5230 return ret; 5231 5232 wcd9335_probe(wcd); 5233 5234 return 0; 5235 } 5236 5237 static const struct slim_device_id wcd9335_slim_id[] = { 5238 {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0}, 5239 {} 5240 }; 5241 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id); 5242 5243 static struct slim_driver wcd9335_slim_driver = { 5244 .driver = { 5245 .name = "wcd9335-slim", 5246 }, 5247 .probe = wcd9335_slim_probe, 5248 .device_status = wcd9335_slim_status, 5249 .id_table = wcd9335_slim_id, 5250 }; 5251 5252 module_slim_driver(wcd9335_slim_driver); 5253 MODULE_DESCRIPTION("WCD9335 slim driver"); 5254 MODULE_LICENSE("GPL v2"); 5255 MODULE_ALIAS("slim:217:1a0:*"); 5256