xref: /openbmc/linux/sound/soc/codecs/tas2770.h (revision 1a476abc723e644248dba975b71122fcf878703b)
1*1a476abcSFrank Shi /* SPDX-License-Identifier: GPL-2.0
2*1a476abcSFrank Shi  *
3*1a476abcSFrank Shi  * ALSA SoC TAS2770 codec driver
4*1a476abcSFrank Shi  *
5*1a476abcSFrank Shi  *  Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
6*1a476abcSFrank Shi  */
7*1a476abcSFrank Shi #ifndef __TAS2770__
8*1a476abcSFrank Shi #define __TAS2770__
9*1a476abcSFrank Shi 
10*1a476abcSFrank Shi /* Book Control Register (available in page0 of each book) */
11*1a476abcSFrank Shi #define TAS2770_BOOKCTL_PAGE            0
12*1a476abcSFrank Shi #define TAS2770_BOOKCTL_REG         127
13*1a476abcSFrank Shi #define TAS2770_REG(page, reg)        ((page * 128) + reg)
14*1a476abcSFrank Shi     /* Page */
15*1a476abcSFrank Shi #define TAS2770_PAGE  TAS2770_REG(0X0, 0x00)
16*1a476abcSFrank Shi #define TAS2770_PAGE_PAGE_MASK  255
17*1a476abcSFrank Shi     /* Software Reset */
18*1a476abcSFrank Shi #define TAS2770_SW_RST  TAS2770_REG(0X0, 0x01)
19*1a476abcSFrank Shi #define TAS2770_RST  BIT(0)
20*1a476abcSFrank Shi     /* Power Control */
21*1a476abcSFrank Shi #define TAS2770_PWR_CTRL  TAS2770_REG(0X0, 0x02)
22*1a476abcSFrank Shi #define TAS2770_PWR_CTRL_MASK  0x3
23*1a476abcSFrank Shi #define TAS2770_PWR_CTRL_ACTIVE  0x0
24*1a476abcSFrank Shi #define TAS2770_PWR_CTRL_MUTE  BIT(0)
25*1a476abcSFrank Shi #define TAS2770_PWR_CTRL_SHUTDOWN  0x2
26*1a476abcSFrank Shi     /* Playback Configuration Reg0 */
27*1a476abcSFrank Shi #define TAS2770_PLAY_CFG_REG0  TAS2770_REG(0X0, 0x03)
28*1a476abcSFrank Shi     /* Playback Configuration Reg1 */
29*1a476abcSFrank Shi #define TAS2770_PLAY_CFG_REG1  TAS2770_REG(0X0, 0x04)
30*1a476abcSFrank Shi     /* Playback Configuration Reg2 */
31*1a476abcSFrank Shi #define TAS2770_PLAY_CFG_REG2  TAS2770_REG(0X0, 0x05)
32*1a476abcSFrank Shi #define TAS2770_PLAY_CFG_REG2_VMAX 0xc9
33*1a476abcSFrank Shi     /* Misc Configuration Reg0 */
34*1a476abcSFrank Shi #define TAS2770_MSC_CFG_REG0  TAS2770_REG(0X0, 0x07)
35*1a476abcSFrank Shi     /* TDM Configuration Reg0 */
36*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG0  TAS2770_REG(0X0, 0x0A)
37*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG0_SMP_MASK  BIT(5)
38*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG0_SMP_48KHZ  0x0
39*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG0_SMP_44_1KHZ  BIT(5)
40*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG0_31_MASK  0xe
41*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG0_31_44_1_48KHZ  0x6
42*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG0_31_88_2_96KHZ  0x8
43*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG0_31_176_4_192KHZ  0xa
44*1a476abcSFrank Shi     /* TDM Configuration Reg1 */
45*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG1  TAS2770_REG(0X0, 0x0B)
46*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG1_MASK 0x3e
47*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG1_51_SHIFT  1
48*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG1_RX_MASK  BIT(0)
49*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG1_RX_RSING  0x0
50*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG1_RX_FALING  BIT(0)
51*1a476abcSFrank Shi     /* TDM Configuration Reg2 */
52*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG2  TAS2770_REG(0X0, 0x0C)
53*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG2_RXW_MASK  0xc
54*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG2_RXW_16BITS  0x0
55*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG2_RXW_24BITS  0x8
56*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG2_RXW_32BITS  0xc
57*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG2_RXS_MASK    0x3
58*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG2_RXS_16BITS  0x0
59*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG2_RXS_24BITS  BIT(0)
60*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG2_RXS_32BITS  0x2
61*1a476abcSFrank Shi     /* TDM Configuration Reg3 */
62*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG3  TAS2770_REG(0X0, 0x0D)
63*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG3_RXS_MASK  0xf0
64*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG3_RXS_SHIFT 0x4
65*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG3_30_MASK  0xf
66*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG3_30_SHIFT 0
67*1a476abcSFrank Shi     /* TDM Configuration Reg5 */
68*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG5  TAS2770_REG(0X0, 0x0F)
69*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG5_VSNS_MASK  BIT(6)
70*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG5_VSNS_ENABLE  BIT(6)
71*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG5_50_MASK  0x3f
72*1a476abcSFrank Shi     /* TDM Configuration Reg6 */
73*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG6  TAS2770_REG(0X0, 0x10)
74*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG6_ISNS_MASK  BIT(6)
75*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG6_ISNS_ENABLE  BIT(6)
76*1a476abcSFrank Shi #define TAS2770_TDM_CFG_REG6_50_MASK  0x3f
77*1a476abcSFrank Shi     /* Brown Out Prevention Reg0 */
78*1a476abcSFrank Shi #define TAS2770_BO_PRV_REG0  TAS2770_REG(0X0, 0x1B)
79*1a476abcSFrank Shi     /* Interrupt MASK Reg0 */
80*1a476abcSFrank Shi #define TAS2770_INT_MASK_REG0  TAS2770_REG(0X0, 0x20)
81*1a476abcSFrank Shi #define TAS2770_INT_REG0_DEFAULT  0xfc
82*1a476abcSFrank Shi #define TAS2770_INT_MASK_REG0_DISABLE 0xff
83*1a476abcSFrank Shi     /* Interrupt MASK Reg1 */
84*1a476abcSFrank Shi #define TAS2770_INT_MASK_REG1  TAS2770_REG(0X0, 0x21)
85*1a476abcSFrank Shi #define TAS2770_INT_REG1_DEFAULT  0xb1
86*1a476abcSFrank Shi #define TAS2770_INT_MASK_REG1_DISABLE 0xff
87*1a476abcSFrank Shi     /* Live-Interrupt Reg0 */
88*1a476abcSFrank Shi #define TAS2770_LVE_INT_REG0  TAS2770_REG(0X0, 0x22)
89*1a476abcSFrank Shi     /* Live-Interrupt Reg1 */
90*1a476abcSFrank Shi #define TAS2770_LVE_INT_REG1  TAS2770_REG(0X0, 0x23)
91*1a476abcSFrank Shi     /* Latched-Interrupt Reg0 */
92*1a476abcSFrank Shi #define TAS2770_LAT_INT_REG0  TAS2770_REG(0X0, 0x24)
93*1a476abcSFrank Shi #define TAS2770_LAT_INT_REG0_OCE_FLG  BIT(1)
94*1a476abcSFrank Shi #define TAS2770_LAT_INT_REG0_OTE_FLG  BIT(0)
95*1a476abcSFrank Shi     /* Latched-Interrupt Reg1 */
96*1a476abcSFrank Shi #define TAS2770_LAT_INT_REG1  TAS2770_REG(0X0, 0x25)
97*1a476abcSFrank Shi #define TAS2770_LAT_INT_REG1_VBA_TOV  BIT(3)
98*1a476abcSFrank Shi #define TAS2770_LAT_INT_REG1_VBA_TUV  BIT(2)
99*1a476abcSFrank Shi #define TAS2770_LAT_INT_REG1_BOUT_FLG  BIT(1)
100*1a476abcSFrank Shi     /* VBAT MSB */
101*1a476abcSFrank Shi #define TAS2770_VBAT_MSB  TAS2770_REG(0X0, 0x27)
102*1a476abcSFrank Shi     /* VBAT LSB */
103*1a476abcSFrank Shi #define TAS2770_VBAT_LSB  TAS2770_REG(0X0, 0x28)
104*1a476abcSFrank Shi     /* TEMP MSB */
105*1a476abcSFrank Shi #define TAS2770_TEMP_MSB  TAS2770_REG(0X0, 0x29)
106*1a476abcSFrank Shi     /* TEMP LSB */
107*1a476abcSFrank Shi #define TAS2770_TEMP_LSB  TAS2770_REG(0X0, 0x2A)
108*1a476abcSFrank Shi     /* Interrupt Configuration */
109*1a476abcSFrank Shi #define TAS2770_INT_CFG  TAS2770_REG(0X0, 0x30)
110*1a476abcSFrank Shi     /* Misc IRQ */
111*1a476abcSFrank Shi #define TAS2770_MISC_IRQ  TAS2770_REG(0X0, 0x32)
112*1a476abcSFrank Shi     /* Clock Configuration */
113*1a476abcSFrank Shi #define TAS2770_CLK_CGF  TAS2770_REG(0X0, 0x3C)
114*1a476abcSFrank Shi     /* TDM Clock detection monitor */
115*1a476abcSFrank Shi #define TAS2770_TDM_CLK_DETC  TAS2770_REG(0X0, 0x77)
116*1a476abcSFrank Shi     /* Revision and PG ID */
117*1a476abcSFrank Shi #define TAS2770_REV_AND_GPID  TAS2770_REG(0X0, 0x7D)
118*1a476abcSFrank Shi 
119*1a476abcSFrank Shi #define TAS2770_POWER_ACTIVE 0
120*1a476abcSFrank Shi #define TAS2770_POWER_MUTE 1
121*1a476abcSFrank Shi #define TAS2770_POWER_SHUTDOWN 2
122*1a476abcSFrank Shi #define ERROR_OVER_CURRENT  0x0000001
123*1a476abcSFrank Shi #define ERROR_DIE_OVERTEMP  0x0000002
124*1a476abcSFrank Shi #define ERROR_OVER_VOLTAGE  0x0000004
125*1a476abcSFrank Shi #define ERROR_UNDER_VOLTAGE 0x0000008
126*1a476abcSFrank Shi #define ERROR_BROWNOUT      0x0000010
127*1a476abcSFrank Shi #define ERROR_CLASSD_PWR    0x0000020
128*1a476abcSFrank Shi #define TAS2770_SLOT_16BIT  16
129*1a476abcSFrank Shi #define TAS2770_SLOT_32BIT  32
130*1a476abcSFrank Shi #define TAS2770_I2C_RETRY_COUNT      3
131*1a476abcSFrank Shi 
132*1a476abcSFrank Shi struct tas2770_register {
133*1a476abcSFrank Shi 	int book;
134*1a476abcSFrank Shi 	int page;
135*1a476abcSFrank Shi 	int reg;
136*1a476abcSFrank Shi };
137*1a476abcSFrank Shi 
138*1a476abcSFrank Shi struct tas2770_dai_cfg {
139*1a476abcSFrank Shi 	unsigned int dai_fmt;
140*1a476abcSFrank Shi 	unsigned int tdm_delay;
141*1a476abcSFrank Shi };
142*1a476abcSFrank Shi 
143*1a476abcSFrank Shi struct tas2770_priv {
144*1a476abcSFrank Shi 	struct device *dev;
145*1a476abcSFrank Shi 	struct regmap *regmap;
146*1a476abcSFrank Shi 	struct snd_soc_codec *codec;
147*1a476abcSFrank Shi 	struct snd_soc_component *component;
148*1a476abcSFrank Shi 	struct mutex dev_lock;
149*1a476abcSFrank Shi 	struct hrtimer mtimer;
150*1a476abcSFrank Shi 	int power_state;
151*1a476abcSFrank Shi 	int asi_format;
152*1a476abcSFrank Shi 	struct gpio_desc *reset_gpio;
153*1a476abcSFrank Shi 	int sampling_rate;
154*1a476abcSFrank Shi 	int frame_size;
155*1a476abcSFrank Shi 	int channel_size;
156*1a476abcSFrank Shi 	int slot_width;
157*1a476abcSFrank Shi 	int v_sense_slot;
158*1a476abcSFrank Shi 	int i_sense_slot;
159*1a476abcSFrank Shi 	bool runtime_suspend;
160*1a476abcSFrank Shi 	unsigned int err_code;
161*1a476abcSFrank Shi 	struct mutex codec_lock;
162*1a476abcSFrank Shi };
163*1a476abcSFrank Shi 
164*1a476abcSFrank Shi #endif /* __TAS2770__ */
165