1 /* 2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver 3 * 4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/slab.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/clk.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/driver.h> 21 #include <linux/regulator/machine.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/of_device.h> 24 #include <sound/core.h> 25 #include <sound/tlv.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/soc-dapm.h> 30 #include <sound/initval.h> 31 32 #include "sgtl5000.h" 33 34 #define SGTL5000_DAP_REG_OFFSET 0x0100 35 #define SGTL5000_MAX_REG_OFFSET 0x013A 36 37 /* default value of sgtl5000 registers */ 38 static const struct reg_default sgtl5000_reg_defaults[] = { 39 { SGTL5000_CHIP_DIG_POWER, 0x0000 }, 40 { SGTL5000_CHIP_CLK_CTRL, 0x0008 }, 41 { SGTL5000_CHIP_I2S_CTRL, 0x0010 }, 42 { SGTL5000_CHIP_SSS_CTRL, 0x0010 }, 43 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c }, 44 { SGTL5000_CHIP_DAC_VOL, 0x3c3c }, 45 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f }, 46 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 }, 47 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 }, 48 { SGTL5000_CHIP_ANA_CTRL, 0x0111 }, 49 { SGTL5000_CHIP_LINREG_CTRL, 0x0000 }, 50 { SGTL5000_CHIP_REF_CTRL, 0x0000 }, 51 { SGTL5000_CHIP_MIC_CTRL, 0x0000 }, 52 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 }, 53 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 }, 54 { SGTL5000_CHIP_ANA_POWER, 0x7060 }, 55 { SGTL5000_CHIP_PLL_CTRL, 0x5000 }, 56 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 }, 57 { SGTL5000_CHIP_ANA_STATUS, 0x0000 }, 58 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 }, 59 { SGTL5000_CHIP_ANA_TEST2, 0x0000 }, 60 { SGTL5000_DAP_CTRL, 0x0000 }, 61 { SGTL5000_DAP_PEQ, 0x0000 }, 62 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 }, 63 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f }, 64 { SGTL5000_DAP_AUDIO_EQ, 0x0000 }, 65 { SGTL5000_DAP_SURROUND, 0x0040 }, 66 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f }, 67 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f }, 68 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f }, 69 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f }, 70 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f }, 71 { SGTL5000_DAP_MAIN_CHAN, 0x8000 }, 72 { SGTL5000_DAP_MIX_CHAN, 0x0000 }, 73 { SGTL5000_DAP_AVC_CTRL, 0x0510 }, 74 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 }, 75 { SGTL5000_DAP_AVC_ATTACK, 0x0028 }, 76 { SGTL5000_DAP_AVC_DECAY, 0x0050 }, 77 }; 78 79 /* regulator supplies for sgtl5000, VDDD is an optional external supply */ 80 enum sgtl5000_regulator_supplies { 81 VDDA, 82 VDDIO, 83 VDDD, 84 SGTL5000_SUPPLY_NUM 85 }; 86 87 /* vddd is optional supply */ 88 static const char *supply_names[SGTL5000_SUPPLY_NUM] = { 89 "VDDA", 90 "VDDIO", 91 "VDDD" 92 }; 93 94 #define LDO_CONSUMER_NAME "VDDD_LDO" 95 #define LDO_VOLTAGE 1200000 96 97 static struct regulator_consumer_supply ldo_consumer[] = { 98 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL), 99 }; 100 101 static struct regulator_init_data ldo_init_data = { 102 .constraints = { 103 .min_uV = 1200000, 104 .max_uV = 1200000, 105 .valid_modes_mask = REGULATOR_MODE_NORMAL, 106 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 107 }, 108 .num_consumer_supplies = 1, 109 .consumer_supplies = &ldo_consumer[0], 110 }; 111 112 /* 113 * sgtl5000 internal ldo regulator, 114 * enabled when VDDD not provided 115 */ 116 struct ldo_regulator { 117 struct regulator_desc desc; 118 struct regulator_dev *dev; 119 int voltage; 120 void *codec_data; 121 bool enabled; 122 }; 123 124 /* sgtl5000 private structure in codec */ 125 struct sgtl5000_priv { 126 int sysclk; /* sysclk rate */ 127 int master; /* i2s master or not */ 128 int fmt; /* i2s data format */ 129 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; 130 struct ldo_regulator *ldo; 131 struct regmap *regmap; 132 struct clk *mclk; 133 int revision; 134 }; 135 136 /* 137 * mic_bias power on/off share the same register bits with 138 * output impedance of mic bias, when power on mic bias, we 139 * need reclaim it to impedance value. 140 * 0x0 = Powered off 141 * 0x1 = 2Kohm 142 * 0x2 = 4Kohm 143 * 0x3 = 8Kohm 144 */ 145 static int mic_bias_event(struct snd_soc_dapm_widget *w, 146 struct snd_kcontrol *kcontrol, int event) 147 { 148 switch (event) { 149 case SND_SOC_DAPM_POST_PMU: 150 /* change mic bias resistor to 4Kohm */ 151 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, 152 SGTL5000_BIAS_R_MASK, 153 SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT); 154 break; 155 156 case SND_SOC_DAPM_PRE_PMD: 157 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, 158 SGTL5000_BIAS_R_MASK, 0); 159 break; 160 } 161 return 0; 162 } 163 164 /* 165 * As manual described, ADC/DAC only works when VAG powerup, 166 * So enabled VAG before ADC/DAC up. 167 * In power down case, we need wait 400ms when vag fully ramped down. 168 */ 169 static int power_vag_event(struct snd_soc_dapm_widget *w, 170 struct snd_kcontrol *kcontrol, int event) 171 { 172 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP; 173 174 switch (event) { 175 case SND_SOC_DAPM_POST_PMU: 176 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, 177 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); 178 break; 179 180 case SND_SOC_DAPM_PRE_PMD: 181 /* 182 * Don't clear VAG_POWERUP, when both DAC and ADC are 183 * operational to prevent inadvertently starving the 184 * other one of them. 185 */ 186 if ((snd_soc_read(w->codec, SGTL5000_CHIP_ANA_POWER) & 187 mask) != mask) { 188 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, 189 SGTL5000_VAG_POWERUP, 0); 190 msleep(400); 191 } 192 break; 193 default: 194 break; 195 } 196 197 return 0; 198 } 199 200 /* input sources for ADC */ 201 static const char *adc_mux_text[] = { 202 "MIC_IN", "LINE_IN" 203 }; 204 205 static SOC_ENUM_SINGLE_DECL(adc_enum, 206 SGTL5000_CHIP_ANA_CTRL, 2, 207 adc_mux_text); 208 209 static const struct snd_kcontrol_new adc_mux = 210 SOC_DAPM_ENUM("Capture Mux", adc_enum); 211 212 /* input sources for DAC */ 213 static const char *dac_mux_text[] = { 214 "DAC", "LINE_IN" 215 }; 216 217 static SOC_ENUM_SINGLE_DECL(dac_enum, 218 SGTL5000_CHIP_ANA_CTRL, 6, 219 dac_mux_text); 220 221 static const struct snd_kcontrol_new dac_mux = 222 SOC_DAPM_ENUM("Headphone Mux", dac_enum); 223 224 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { 225 SND_SOC_DAPM_INPUT("LINE_IN"), 226 SND_SOC_DAPM_INPUT("MIC_IN"), 227 228 SND_SOC_DAPM_OUTPUT("HP_OUT"), 229 SND_SOC_DAPM_OUTPUT("LINE_OUT"), 230 231 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, 232 mic_bias_event, 233 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 234 235 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0), 236 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), 237 238 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), 239 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux), 240 241 /* aif for i2s input */ 242 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", 243 0, SGTL5000_CHIP_DIG_POWER, 244 0, 0), 245 246 /* aif for i2s output */ 247 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", 248 0, SGTL5000_CHIP_DIG_POWER, 249 1, 0), 250 251 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0), 252 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0), 253 254 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event), 255 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event), 256 }; 257 258 /* routes for sgtl5000 */ 259 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = { 260 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ 261 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ 262 263 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ 264 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ 265 266 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */ 267 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ 268 {"LO", NULL, "DAC"}, /* dac --> line_out */ 269 270 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ 271 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ 272 273 {"LINE_OUT", NULL, "LO"}, 274 {"HP_OUT", NULL, "HP"}, 275 }; 276 277 /* custom function to fetch info of PCM playback volume */ 278 static int dac_info_volsw(struct snd_kcontrol *kcontrol, 279 struct snd_ctl_elem_info *uinfo) 280 { 281 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 282 uinfo->count = 2; 283 uinfo->value.integer.min = 0; 284 uinfo->value.integer.max = 0xfc - 0x3c; 285 return 0; 286 } 287 288 /* 289 * custom function to get of PCM playback volume 290 * 291 * dac volume register 292 * 15-------------8-7--------------0 293 * | R channel vol | L channel vol | 294 * ------------------------------- 295 * 296 * PCM volume with 0.5017 dB steps from 0 to -90 dB 297 * 298 * register values map to dB 299 * 0x3B and less = Reserved 300 * 0x3C = 0 dB 301 * 0x3D = -0.5 dB 302 * 0xF0 = -90 dB 303 * 0xFC and greater = Muted 304 * 305 * register value map to userspace value 306 * 307 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 308 * ------------------------------ 309 * userspace value 0xc0 0 310 */ 311 static int dac_get_volsw(struct snd_kcontrol *kcontrol, 312 struct snd_ctl_elem_value *ucontrol) 313 { 314 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 315 int reg; 316 int l; 317 int r; 318 319 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL); 320 321 /* get left channel volume */ 322 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; 323 324 /* get right channel volume */ 325 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; 326 327 /* make sure value fall in (0x3c,0xfc) */ 328 l = clamp(l, 0x3c, 0xfc); 329 r = clamp(r, 0x3c, 0xfc); 330 331 /* invert it and map to userspace value */ 332 l = 0xfc - l; 333 r = 0xfc - r; 334 335 ucontrol->value.integer.value[0] = l; 336 ucontrol->value.integer.value[1] = r; 337 338 return 0; 339 } 340 341 /* 342 * custom function to put of PCM playback volume 343 * 344 * dac volume register 345 * 15-------------8-7--------------0 346 * | R channel vol | L channel vol | 347 * ------------------------------- 348 * 349 * PCM volume with 0.5017 dB steps from 0 to -90 dB 350 * 351 * register values map to dB 352 * 0x3B and less = Reserved 353 * 0x3C = 0 dB 354 * 0x3D = -0.5 dB 355 * 0xF0 = -90 dB 356 * 0xFC and greater = Muted 357 * 358 * userspace value map to register value 359 * 360 * userspace value 0xc0 0 361 * ------------------------------ 362 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 363 */ 364 static int dac_put_volsw(struct snd_kcontrol *kcontrol, 365 struct snd_ctl_elem_value *ucontrol) 366 { 367 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 368 int reg; 369 int l; 370 int r; 371 372 l = ucontrol->value.integer.value[0]; 373 r = ucontrol->value.integer.value[1]; 374 375 /* make sure userspace volume fall in (0, 0xfc-0x3c) */ 376 l = clamp(l, 0, 0xfc - 0x3c); 377 r = clamp(r, 0, 0xfc - 0x3c); 378 379 /* invert it, get the value can be set to register */ 380 l = 0xfc - l; 381 r = 0xfc - r; 382 383 /* shift to get the register value */ 384 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | 385 r << SGTL5000_DAC_VOL_RIGHT_SHIFT; 386 387 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg); 388 389 return 0; 390 } 391 392 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); 393 394 /* tlv for mic gain, 0db 20db 30db 40db */ 395 static const unsigned int mic_gain_tlv[] = { 396 TLV_DB_RANGE_HEAD(2), 397 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 398 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0), 399 }; 400 401 /* tlv for hp volume, -51.5db to 12.0db, step .5db */ 402 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); 403 404 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { 405 /* SOC_DOUBLE_S8_TLV with invert */ 406 { 407 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 408 .name = "PCM Playback Volume", 409 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | 410 SNDRV_CTL_ELEM_ACCESS_READWRITE, 411 .info = dac_info_volsw, 412 .get = dac_get_volsw, 413 .put = dac_put_volsw, 414 }, 415 416 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), 417 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", 418 SGTL5000_CHIP_ANA_ADC_CTRL, 419 8, 1, 0, capture_6db_attenuate), 420 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), 421 422 SOC_DOUBLE_TLV("Headphone Playback Volume", 423 SGTL5000_CHIP_ANA_HP_CTRL, 424 0, 8, 425 0x7f, 1, 426 headphone_volume), 427 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, 428 5, 1, 0), 429 430 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, 431 0, 3, 0, mic_gain_tlv), 432 }; 433 434 /* mute the codec used by alsa core */ 435 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) 436 { 437 struct snd_soc_codec *codec = codec_dai->codec; 438 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT; 439 440 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL, 441 adcdac_ctrl, mute ? adcdac_ctrl : 0); 442 443 return 0; 444 } 445 446 /* set codec format */ 447 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 448 { 449 struct snd_soc_codec *codec = codec_dai->codec; 450 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 451 u16 i2sctl = 0; 452 453 sgtl5000->master = 0; 454 /* 455 * i2s clock and frame master setting. 456 * ONLY support: 457 * - clock and frame slave, 458 * - clock and frame master 459 */ 460 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 461 case SND_SOC_DAIFMT_CBS_CFS: 462 break; 463 case SND_SOC_DAIFMT_CBM_CFM: 464 i2sctl |= SGTL5000_I2S_MASTER; 465 sgtl5000->master = 1; 466 break; 467 default: 468 return -EINVAL; 469 } 470 471 /* setting i2s data format */ 472 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 473 case SND_SOC_DAIFMT_DSP_A: 474 i2sctl |= SGTL5000_I2S_MODE_PCM; 475 break; 476 case SND_SOC_DAIFMT_DSP_B: 477 i2sctl |= SGTL5000_I2S_MODE_PCM; 478 i2sctl |= SGTL5000_I2S_LRALIGN; 479 break; 480 case SND_SOC_DAIFMT_I2S: 481 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; 482 break; 483 case SND_SOC_DAIFMT_RIGHT_J: 484 i2sctl |= SGTL5000_I2S_MODE_RJ; 485 i2sctl |= SGTL5000_I2S_LRPOL; 486 break; 487 case SND_SOC_DAIFMT_LEFT_J: 488 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; 489 i2sctl |= SGTL5000_I2S_LRALIGN; 490 break; 491 default: 492 return -EINVAL; 493 } 494 495 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 496 497 /* Clock inversion */ 498 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 499 case SND_SOC_DAIFMT_NB_NF: 500 break; 501 case SND_SOC_DAIFMT_IB_NF: 502 i2sctl |= SGTL5000_I2S_SCLK_INV; 503 break; 504 default: 505 return -EINVAL; 506 } 507 508 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl); 509 510 return 0; 511 } 512 513 /* set codec sysclk */ 514 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, 515 int clk_id, unsigned int freq, int dir) 516 { 517 struct snd_soc_codec *codec = codec_dai->codec; 518 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 519 520 switch (clk_id) { 521 case SGTL5000_SYSCLK: 522 sgtl5000->sysclk = freq; 523 break; 524 default: 525 return -EINVAL; 526 } 527 528 return 0; 529 } 530 531 /* 532 * set clock according to i2s frame clock, 533 * sgtl5000 provide 2 clock sources. 534 * 1. sys_mclk. sample freq can only configure to 535 * 1/256, 1/384, 1/512 of sys_mclk. 536 * 2. pll. can derive any audio clocks. 537 * 538 * clock setting rules: 539 * 1. in slave mode, only sys_mclk can use. 540 * 2. as constraint by sys_mclk, sample freq should 541 * set to 32k, 44.1k and above. 542 * 3. using sys_mclk prefer to pll to save power. 543 */ 544 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate) 545 { 546 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 547 int clk_ctl = 0; 548 int sys_fs; /* sample freq */ 549 550 /* 551 * sample freq should be divided by frame clock, 552 * if frame clock lower than 44.1khz, sample feq should set to 553 * 32khz or 44.1khz. 554 */ 555 switch (frame_rate) { 556 case 8000: 557 case 16000: 558 sys_fs = 32000; 559 break; 560 case 11025: 561 case 22050: 562 sys_fs = 44100; 563 break; 564 default: 565 sys_fs = frame_rate; 566 break; 567 } 568 569 /* set divided factor of frame clock */ 570 switch (sys_fs / frame_rate) { 571 case 4: 572 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; 573 break; 574 case 2: 575 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; 576 break; 577 case 1: 578 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; 579 break; 580 default: 581 return -EINVAL; 582 } 583 584 /* set the sys_fs according to frame rate */ 585 switch (sys_fs) { 586 case 32000: 587 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; 588 break; 589 case 44100: 590 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; 591 break; 592 case 48000: 593 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; 594 break; 595 case 96000: 596 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; 597 break; 598 default: 599 dev_err(codec->dev, "frame rate %d not supported\n", 600 frame_rate); 601 return -EINVAL; 602 } 603 604 /* 605 * calculate the divider of mclk/sample_freq, 606 * factor of freq =96k can only be 256, since mclk in range (12m,27m) 607 */ 608 switch (sgtl5000->sysclk / sys_fs) { 609 case 256: 610 clk_ctl |= SGTL5000_MCLK_FREQ_256FS << 611 SGTL5000_MCLK_FREQ_SHIFT; 612 break; 613 case 384: 614 clk_ctl |= SGTL5000_MCLK_FREQ_384FS << 615 SGTL5000_MCLK_FREQ_SHIFT; 616 break; 617 case 512: 618 clk_ctl |= SGTL5000_MCLK_FREQ_512FS << 619 SGTL5000_MCLK_FREQ_SHIFT; 620 break; 621 default: 622 /* if mclk not satisify the divider, use pll */ 623 if (sgtl5000->master) { 624 clk_ctl |= SGTL5000_MCLK_FREQ_PLL << 625 SGTL5000_MCLK_FREQ_SHIFT; 626 } else { 627 dev_err(codec->dev, 628 "PLL not supported in slave mode\n"); 629 return -EINVAL; 630 } 631 } 632 633 /* if using pll, please check manual 6.4.2 for detail */ 634 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { 635 u64 out, t; 636 int div2; 637 int pll_ctl; 638 unsigned int in, int_div, frac_div; 639 640 if (sgtl5000->sysclk > 17000000) { 641 div2 = 1; 642 in = sgtl5000->sysclk / 2; 643 } else { 644 div2 = 0; 645 in = sgtl5000->sysclk; 646 } 647 if (sys_fs == 44100) 648 out = 180633600; 649 else 650 out = 196608000; 651 t = do_div(out, in); 652 int_div = out; 653 t *= 2048; 654 do_div(t, in); 655 frac_div = t; 656 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | 657 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; 658 659 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl); 660 if (div2) 661 snd_soc_update_bits(codec, 662 SGTL5000_CHIP_CLK_TOP_CTRL, 663 SGTL5000_INPUT_FREQ_DIV2, 664 SGTL5000_INPUT_FREQ_DIV2); 665 else 666 snd_soc_update_bits(codec, 667 SGTL5000_CHIP_CLK_TOP_CTRL, 668 SGTL5000_INPUT_FREQ_DIV2, 669 0); 670 671 /* power up pll */ 672 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 673 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 674 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); 675 676 /* if using pll, clk_ctrl must be set after pll power up */ 677 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 678 } else { 679 /* otherwise, clk_ctrl must be set before pll power down */ 680 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 681 682 /* power down pll */ 683 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 684 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 685 0); 686 } 687 688 return 0; 689 } 690 691 /* 692 * Set PCM DAI bit size and sample rate. 693 * input: params_rate, params_fmt 694 */ 695 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, 696 struct snd_pcm_hw_params *params, 697 struct snd_soc_dai *dai) 698 { 699 struct snd_soc_codec *codec = dai->codec; 700 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 701 int channels = params_channels(params); 702 int i2s_ctl = 0; 703 int stereo; 704 int ret; 705 706 /* sysclk should already set */ 707 if (!sgtl5000->sysclk) { 708 dev_err(codec->dev, "%s: set sysclk first!\n", __func__); 709 return -EFAULT; 710 } 711 712 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 713 stereo = SGTL5000_DAC_STEREO; 714 else 715 stereo = SGTL5000_ADC_STEREO; 716 717 /* set mono to save power */ 718 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo, 719 channels == 1 ? 0 : stereo); 720 721 /* set codec clock base on lrclk */ 722 ret = sgtl5000_set_clock(codec, params_rate(params)); 723 if (ret) 724 return ret; 725 726 /* set i2s data format */ 727 switch (params_width(params)) { 728 case 16: 729 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 730 return -EINVAL; 731 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; 732 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << 733 SGTL5000_I2S_SCLKFREQ_SHIFT; 734 break; 735 case 20: 736 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; 737 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 738 SGTL5000_I2S_SCLKFREQ_SHIFT; 739 break; 740 case 24: 741 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; 742 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 743 SGTL5000_I2S_SCLKFREQ_SHIFT; 744 break; 745 case 32: 746 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 747 return -EINVAL; 748 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; 749 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 750 SGTL5000_I2S_SCLKFREQ_SHIFT; 751 break; 752 default: 753 return -EINVAL; 754 } 755 756 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, 757 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK, 758 i2s_ctl); 759 760 return 0; 761 } 762 763 #ifdef CONFIG_REGULATOR 764 static int ldo_regulator_is_enabled(struct regulator_dev *dev) 765 { 766 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 767 768 return ldo->enabled; 769 } 770 771 static int ldo_regulator_enable(struct regulator_dev *dev) 772 { 773 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 774 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; 775 int reg; 776 777 if (ldo_regulator_is_enabled(dev)) 778 return 0; 779 780 /* set regulator value firstly */ 781 reg = (1600 - ldo->voltage / 1000) / 50; 782 reg = clamp(reg, 0x0, 0xf); 783 784 /* amend the voltage value, unit: uV */ 785 ldo->voltage = (1600 - reg * 50) * 1000; 786 787 /* set voltage to register */ 788 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 789 SGTL5000_LINREG_VDDD_MASK, reg); 790 791 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 792 SGTL5000_LINEREG_D_POWERUP, 793 SGTL5000_LINEREG_D_POWERUP); 794 795 /* when internal ldo enabled, simple digital power can be disabled */ 796 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 797 SGTL5000_LINREG_SIMPLE_POWERUP, 798 0); 799 800 ldo->enabled = 1; 801 return 0; 802 } 803 804 static int ldo_regulator_disable(struct regulator_dev *dev) 805 { 806 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 807 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; 808 809 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 810 SGTL5000_LINEREG_D_POWERUP, 811 0); 812 813 /* clear voltage info */ 814 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 815 SGTL5000_LINREG_VDDD_MASK, 0); 816 817 ldo->enabled = 0; 818 819 return 0; 820 } 821 822 static int ldo_regulator_get_voltage(struct regulator_dev *dev) 823 { 824 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 825 826 return ldo->voltage; 827 } 828 829 static struct regulator_ops ldo_regulator_ops = { 830 .is_enabled = ldo_regulator_is_enabled, 831 .enable = ldo_regulator_enable, 832 .disable = ldo_regulator_disable, 833 .get_voltage = ldo_regulator_get_voltage, 834 }; 835 836 static int ldo_regulator_register(struct snd_soc_codec *codec, 837 struct regulator_init_data *init_data, 838 int voltage) 839 { 840 struct ldo_regulator *ldo; 841 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 842 struct regulator_config config = { }; 843 844 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL); 845 846 if (!ldo) 847 return -ENOMEM; 848 849 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL); 850 if (!ldo->desc.name) { 851 kfree(ldo); 852 dev_err(codec->dev, "failed to allocate decs name memory\n"); 853 return -ENOMEM; 854 } 855 856 ldo->desc.type = REGULATOR_VOLTAGE; 857 ldo->desc.owner = THIS_MODULE; 858 ldo->desc.ops = &ldo_regulator_ops; 859 ldo->desc.n_voltages = 1; 860 861 ldo->codec_data = codec; 862 ldo->voltage = voltage; 863 864 config.dev = codec->dev; 865 config.driver_data = ldo; 866 config.init_data = init_data; 867 868 ldo->dev = regulator_register(&ldo->desc, &config); 869 if (IS_ERR(ldo->dev)) { 870 int ret = PTR_ERR(ldo->dev); 871 872 dev_err(codec->dev, "failed to register regulator\n"); 873 kfree(ldo->desc.name); 874 kfree(ldo); 875 876 return ret; 877 } 878 sgtl5000->ldo = ldo; 879 880 return 0; 881 } 882 883 static int ldo_regulator_remove(struct snd_soc_codec *codec) 884 { 885 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 886 struct ldo_regulator *ldo = sgtl5000->ldo; 887 888 if (!ldo) 889 return 0; 890 891 regulator_unregister(ldo->dev); 892 kfree(ldo->desc.name); 893 kfree(ldo); 894 895 return 0; 896 } 897 #else 898 static int ldo_regulator_register(struct snd_soc_codec *codec, 899 struct regulator_init_data *init_data, 900 int voltage) 901 { 902 dev_err(codec->dev, "this setup needs regulator support in the kernel\n"); 903 return -EINVAL; 904 } 905 906 static int ldo_regulator_remove(struct snd_soc_codec *codec) 907 { 908 return 0; 909 } 910 #endif 911 912 /* 913 * set dac bias 914 * common state changes: 915 * startup: 916 * off --> standby --> prepare --> on 917 * standby --> prepare --> on 918 * 919 * stop: 920 * on --> prepare --> standby 921 */ 922 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, 923 enum snd_soc_bias_level level) 924 { 925 int ret; 926 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 927 928 switch (level) { 929 case SND_SOC_BIAS_ON: 930 case SND_SOC_BIAS_PREPARE: 931 break; 932 case SND_SOC_BIAS_STANDBY: 933 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 934 ret = regulator_bulk_enable( 935 ARRAY_SIZE(sgtl5000->supplies), 936 sgtl5000->supplies); 937 if (ret) 938 return ret; 939 udelay(10); 940 941 regcache_cache_only(sgtl5000->regmap, false); 942 943 ret = regcache_sync(sgtl5000->regmap); 944 if (ret != 0) { 945 dev_err(codec->dev, 946 "Failed to restore cache: %d\n", ret); 947 948 regcache_cache_only(sgtl5000->regmap, true); 949 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 950 sgtl5000->supplies); 951 952 return ret; 953 } 954 } 955 956 break; 957 case SND_SOC_BIAS_OFF: 958 regcache_cache_only(sgtl5000->regmap, true); 959 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 960 sgtl5000->supplies); 961 break; 962 } 963 964 codec->dapm.bias_level = level; 965 return 0; 966 } 967 968 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 969 SNDRV_PCM_FMTBIT_S20_3LE |\ 970 SNDRV_PCM_FMTBIT_S24_LE |\ 971 SNDRV_PCM_FMTBIT_S32_LE) 972 973 static const struct snd_soc_dai_ops sgtl5000_ops = { 974 .hw_params = sgtl5000_pcm_hw_params, 975 .digital_mute = sgtl5000_digital_mute, 976 .set_fmt = sgtl5000_set_dai_fmt, 977 .set_sysclk = sgtl5000_set_dai_sysclk, 978 }; 979 980 static struct snd_soc_dai_driver sgtl5000_dai = { 981 .name = "sgtl5000", 982 .playback = { 983 .stream_name = "Playback", 984 .channels_min = 1, 985 .channels_max = 2, 986 /* 987 * only support 8~48K + 96K, 988 * TODO modify hw_param to support more 989 */ 990 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 991 .formats = SGTL5000_FORMATS, 992 }, 993 .capture = { 994 .stream_name = "Capture", 995 .channels_min = 1, 996 .channels_max = 2, 997 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 998 .formats = SGTL5000_FORMATS, 999 }, 1000 .ops = &sgtl5000_ops, 1001 .symmetric_rates = 1, 1002 }; 1003 1004 static bool sgtl5000_volatile(struct device *dev, unsigned int reg) 1005 { 1006 switch (reg) { 1007 case SGTL5000_CHIP_ID: 1008 case SGTL5000_CHIP_ADCDAC_CTRL: 1009 case SGTL5000_CHIP_ANA_STATUS: 1010 return true; 1011 } 1012 1013 return false; 1014 } 1015 1016 static bool sgtl5000_readable(struct device *dev, unsigned int reg) 1017 { 1018 switch (reg) { 1019 case SGTL5000_CHIP_ID: 1020 case SGTL5000_CHIP_DIG_POWER: 1021 case SGTL5000_CHIP_CLK_CTRL: 1022 case SGTL5000_CHIP_I2S_CTRL: 1023 case SGTL5000_CHIP_SSS_CTRL: 1024 case SGTL5000_CHIP_ADCDAC_CTRL: 1025 case SGTL5000_CHIP_DAC_VOL: 1026 case SGTL5000_CHIP_PAD_STRENGTH: 1027 case SGTL5000_CHIP_ANA_ADC_CTRL: 1028 case SGTL5000_CHIP_ANA_HP_CTRL: 1029 case SGTL5000_CHIP_ANA_CTRL: 1030 case SGTL5000_CHIP_LINREG_CTRL: 1031 case SGTL5000_CHIP_REF_CTRL: 1032 case SGTL5000_CHIP_MIC_CTRL: 1033 case SGTL5000_CHIP_LINE_OUT_CTRL: 1034 case SGTL5000_CHIP_LINE_OUT_VOL: 1035 case SGTL5000_CHIP_ANA_POWER: 1036 case SGTL5000_CHIP_PLL_CTRL: 1037 case SGTL5000_CHIP_CLK_TOP_CTRL: 1038 case SGTL5000_CHIP_ANA_STATUS: 1039 case SGTL5000_CHIP_SHORT_CTRL: 1040 case SGTL5000_CHIP_ANA_TEST2: 1041 case SGTL5000_DAP_CTRL: 1042 case SGTL5000_DAP_PEQ: 1043 case SGTL5000_DAP_BASS_ENHANCE: 1044 case SGTL5000_DAP_BASS_ENHANCE_CTRL: 1045 case SGTL5000_DAP_AUDIO_EQ: 1046 case SGTL5000_DAP_SURROUND: 1047 case SGTL5000_DAP_FLT_COEF_ACCESS: 1048 case SGTL5000_DAP_COEF_WR_B0_MSB: 1049 case SGTL5000_DAP_COEF_WR_B0_LSB: 1050 case SGTL5000_DAP_EQ_BASS_BAND0: 1051 case SGTL5000_DAP_EQ_BASS_BAND1: 1052 case SGTL5000_DAP_EQ_BASS_BAND2: 1053 case SGTL5000_DAP_EQ_BASS_BAND3: 1054 case SGTL5000_DAP_EQ_BASS_BAND4: 1055 case SGTL5000_DAP_MAIN_CHAN: 1056 case SGTL5000_DAP_MIX_CHAN: 1057 case SGTL5000_DAP_AVC_CTRL: 1058 case SGTL5000_DAP_AVC_THRESHOLD: 1059 case SGTL5000_DAP_AVC_ATTACK: 1060 case SGTL5000_DAP_AVC_DECAY: 1061 case SGTL5000_DAP_COEF_WR_B1_MSB: 1062 case SGTL5000_DAP_COEF_WR_B1_LSB: 1063 case SGTL5000_DAP_COEF_WR_B2_MSB: 1064 case SGTL5000_DAP_COEF_WR_B2_LSB: 1065 case SGTL5000_DAP_COEF_WR_A1_MSB: 1066 case SGTL5000_DAP_COEF_WR_A1_LSB: 1067 case SGTL5000_DAP_COEF_WR_A2_MSB: 1068 case SGTL5000_DAP_COEF_WR_A2_LSB: 1069 return true; 1070 1071 default: 1072 return false; 1073 } 1074 } 1075 1076 #ifdef CONFIG_SUSPEND 1077 static int sgtl5000_suspend(struct snd_soc_codec *codec) 1078 { 1079 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); 1080 1081 return 0; 1082 } 1083 1084 static int sgtl5000_resume(struct snd_soc_codec *codec) 1085 { 1086 /* Bring the codec back up to standby to enable regulators */ 1087 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1088 1089 return 0; 1090 } 1091 #else 1092 #define sgtl5000_suspend NULL 1093 #define sgtl5000_resume NULL 1094 #endif /* CONFIG_SUSPEND */ 1095 1096 /* 1097 * sgtl5000 has 3 internal power supplies: 1098 * 1. VAG, normally set to vdda/2 1099 * 2. chargepump, set to different value 1100 * according to voltage of vdda and vddio 1101 * 3. line out VAG, normally set to vddio/2 1102 * 1103 * and should be set according to: 1104 * 1. vddd provided by external or not 1105 * 2. vdda and vddio voltage value. > 3.1v or not 1106 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd. 1107 */ 1108 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec) 1109 { 1110 int vddd; 1111 int vdda; 1112 int vddio; 1113 u16 ana_pwr; 1114 u16 lreg_ctrl; 1115 int vag; 1116 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1117 1118 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); 1119 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); 1120 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer); 1121 1122 vdda = vdda / 1000; 1123 vddio = vddio / 1000; 1124 vddd = vddd / 1000; 1125 1126 if (vdda <= 0 || vddio <= 0 || vddd < 0) { 1127 dev_err(codec->dev, "regulator voltage not set correctly\n"); 1128 1129 return -EINVAL; 1130 } 1131 1132 /* according to datasheet, maximum voltage of supplies */ 1133 if (vdda > 3600 || vddio > 3600 || vddd > 1980) { 1134 dev_err(codec->dev, 1135 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n", 1136 vdda, vddio, vddd); 1137 1138 return -EINVAL; 1139 } 1140 1141 /* reset value */ 1142 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER); 1143 ana_pwr |= SGTL5000_DAC_STEREO | 1144 SGTL5000_ADC_STEREO | 1145 SGTL5000_REFTOP_POWERUP; 1146 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL); 1147 1148 if (vddio < 3100 && vdda < 3100) { 1149 /* enable internal oscillator used for charge pump */ 1150 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL, 1151 SGTL5000_INT_OSC_EN, 1152 SGTL5000_INT_OSC_EN); 1153 /* Enable VDDC charge pump */ 1154 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; 1155 } else if (vddio >= 3100 && vdda >= 3100) { 1156 /* 1157 * if vddio and vddd > 3.1v, 1158 * charge pump should be clean before set ana_pwr 1159 */ 1160 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1161 SGTL5000_VDDC_CHRGPMP_POWERUP, 0); 1162 1163 /* VDDC use VDDIO rail */ 1164 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; 1165 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << 1166 SGTL5000_VDDC_MAN_ASSN_SHIFT; 1167 } 1168 1169 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); 1170 1171 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); 1172 1173 /* set voltage to register */ 1174 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 1175 SGTL5000_LINREG_VDDD_MASK, 0x8); 1176 1177 /* 1178 * if vddd linear reg has been enabled, 1179 * simple digital supply should be clear to get 1180 * proper VDDD voltage. 1181 */ 1182 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP) 1183 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1184 SGTL5000_LINREG_SIMPLE_POWERUP, 1185 0); 1186 else 1187 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1188 SGTL5000_LINREG_SIMPLE_POWERUP | 1189 SGTL5000_STARTUP_POWERUP, 1190 0); 1191 1192 /* 1193 * set ADC/DAC VAG to vdda / 2, 1194 * should stay in range (0.8v, 1.575v) 1195 */ 1196 vag = vdda / 2; 1197 if (vag <= SGTL5000_ANA_GND_BASE) 1198 vag = 0; 1199 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * 1200 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) 1201 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; 1202 else 1203 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; 1204 1205 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1206 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT); 1207 1208 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ 1209 vag = vddio / 2; 1210 if (vag <= SGTL5000_LINE_OUT_GND_BASE) 1211 vag = 0; 1212 else if (vag >= SGTL5000_LINE_OUT_GND_BASE + 1213 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) 1214 vag = SGTL5000_LINE_OUT_GND_MAX; 1215 else 1216 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) / 1217 SGTL5000_LINE_OUT_GND_STP; 1218 1219 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL, 1220 SGTL5000_LINE_OUT_CURRENT_MASK | 1221 SGTL5000_LINE_OUT_GND_MASK, 1222 vag << SGTL5000_LINE_OUT_GND_SHIFT | 1223 SGTL5000_LINE_OUT_CURRENT_360u << 1224 SGTL5000_LINE_OUT_CURRENT_SHIFT); 1225 1226 return 0; 1227 } 1228 1229 static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec) 1230 { 1231 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1232 int ret; 1233 1234 /* set internal ldo to 1.2v */ 1235 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE); 1236 if (ret) { 1237 dev_err(codec->dev, 1238 "Failed to register vddd internal supplies: %d\n", ret); 1239 return ret; 1240 } 1241 1242 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME; 1243 1244 dev_info(codec->dev, "Using internal LDO instead of VDDD\n"); 1245 return 0; 1246 } 1247 1248 static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) 1249 { 1250 int ret; 1251 int i; 1252 int external_vddd = 0; 1253 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1254 struct regulator *vddd; 1255 1256 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) 1257 sgtl5000->supplies[i].supply = supply_names[i]; 1258 1259 /* External VDDD only works before revision 0x11 */ 1260 if (sgtl5000->revision < 0x11) { 1261 vddd = regulator_get_optional(codec->dev, "VDDD"); 1262 if (IS_ERR(vddd)) { 1263 /* See if it's just not registered yet */ 1264 if (PTR_ERR(vddd) == -EPROBE_DEFER) 1265 return -EPROBE_DEFER; 1266 } else { 1267 external_vddd = 1; 1268 regulator_put(vddd); 1269 } 1270 } 1271 1272 if (!external_vddd) { 1273 ret = sgtl5000_replace_vddd_with_ldo(codec); 1274 if (ret) 1275 return ret; 1276 } 1277 1278 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), 1279 sgtl5000->supplies); 1280 if (ret) 1281 goto err_ldo_remove; 1282 1283 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), 1284 sgtl5000->supplies); 1285 if (ret) 1286 goto err_regulator_free; 1287 1288 /* wait for all power rails bring up */ 1289 udelay(10); 1290 1291 return 0; 1292 1293 err_regulator_free: 1294 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1295 sgtl5000->supplies); 1296 err_ldo_remove: 1297 if (!external_vddd) 1298 ldo_regulator_remove(codec); 1299 return ret; 1300 1301 } 1302 1303 static int sgtl5000_probe(struct snd_soc_codec *codec) 1304 { 1305 int ret; 1306 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1307 1308 ret = sgtl5000_enable_regulators(codec); 1309 if (ret) 1310 return ret; 1311 1312 /* power up sgtl5000 */ 1313 ret = sgtl5000_set_power_regs(codec); 1314 if (ret) 1315 goto err; 1316 1317 /* enable small pop, introduce 400ms delay in turning off */ 1318 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1319 SGTL5000_SMALL_POP, 1320 SGTL5000_SMALL_POP); 1321 1322 /* disable short cut detector */ 1323 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0); 1324 1325 /* 1326 * set i2s as default input of sound switch 1327 * TODO: add sound switch to control and dapm widge. 1328 */ 1329 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL, 1330 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT); 1331 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER, 1332 SGTL5000_ADC_EN | SGTL5000_DAC_EN); 1333 1334 /* enable dac volume ramp by default */ 1335 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, 1336 SGTL5000_DAC_VOL_RAMP_EN | 1337 SGTL5000_DAC_MUTE_RIGHT | 1338 SGTL5000_DAC_MUTE_LEFT); 1339 1340 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f); 1341 1342 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL, 1343 SGTL5000_HP_ZCD_EN | 1344 SGTL5000_ADC_ZCD_EN); 1345 1346 snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 2); 1347 1348 /* 1349 * disable DAP 1350 * TODO: 1351 * Enable DAP in kcontrol and dapm. 1352 */ 1353 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0); 1354 1355 /* leading to standby state */ 1356 ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1357 if (ret) 1358 goto err; 1359 1360 return 0; 1361 1362 err: 1363 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1364 sgtl5000->supplies); 1365 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1366 sgtl5000->supplies); 1367 ldo_regulator_remove(codec); 1368 1369 return ret; 1370 } 1371 1372 static int sgtl5000_remove(struct snd_soc_codec *codec) 1373 { 1374 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1375 1376 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); 1377 1378 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1379 sgtl5000->supplies); 1380 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1381 sgtl5000->supplies); 1382 ldo_regulator_remove(codec); 1383 1384 return 0; 1385 } 1386 1387 static struct snd_soc_codec_driver sgtl5000_driver = { 1388 .probe = sgtl5000_probe, 1389 .remove = sgtl5000_remove, 1390 .suspend = sgtl5000_suspend, 1391 .resume = sgtl5000_resume, 1392 .set_bias_level = sgtl5000_set_bias_level, 1393 .controls = sgtl5000_snd_controls, 1394 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls), 1395 .dapm_widgets = sgtl5000_dapm_widgets, 1396 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets), 1397 .dapm_routes = sgtl5000_dapm_routes, 1398 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), 1399 }; 1400 1401 static const struct regmap_config sgtl5000_regmap = { 1402 .reg_bits = 16, 1403 .val_bits = 16, 1404 .reg_stride = 2, 1405 1406 .max_register = SGTL5000_MAX_REG_OFFSET, 1407 .volatile_reg = sgtl5000_volatile, 1408 .readable_reg = sgtl5000_readable, 1409 1410 .cache_type = REGCACHE_RBTREE, 1411 .reg_defaults = sgtl5000_reg_defaults, 1412 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults), 1413 }; 1414 1415 /* 1416 * Write all the default values from sgtl5000_reg_defaults[] array into the 1417 * sgtl5000 registers, to make sure we always start with the sane registers 1418 * values as stated in the datasheet. 1419 * 1420 * Since sgtl5000 does not have a reset line, nor a reset command in software, 1421 * we follow this approach to guarantee we always start from the default values 1422 * and avoid problems like, not being able to probe after an audio playback 1423 * followed by a system reset or a 'reboot' command in Linux 1424 */ 1425 static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000) 1426 { 1427 int i, ret, val, index; 1428 1429 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) { 1430 val = sgtl5000_reg_defaults[i].def; 1431 index = sgtl5000_reg_defaults[i].reg; 1432 ret = regmap_write(sgtl5000->regmap, index, val); 1433 if (ret) 1434 return ret; 1435 } 1436 1437 return 0; 1438 } 1439 1440 static int sgtl5000_i2c_probe(struct i2c_client *client, 1441 const struct i2c_device_id *id) 1442 { 1443 struct sgtl5000_priv *sgtl5000; 1444 int ret, reg, rev; 1445 1446 sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv), 1447 GFP_KERNEL); 1448 if (!sgtl5000) 1449 return -ENOMEM; 1450 1451 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap); 1452 if (IS_ERR(sgtl5000->regmap)) { 1453 ret = PTR_ERR(sgtl5000->regmap); 1454 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret); 1455 return ret; 1456 } 1457 1458 sgtl5000->mclk = devm_clk_get(&client->dev, NULL); 1459 if (IS_ERR(sgtl5000->mclk)) { 1460 ret = PTR_ERR(sgtl5000->mclk); 1461 dev_err(&client->dev, "Failed to get mclock: %d\n", ret); 1462 /* Defer the probe to see if the clk will be provided later */ 1463 if (ret == -ENOENT) 1464 return -EPROBE_DEFER; 1465 return ret; 1466 } 1467 1468 ret = clk_prepare_enable(sgtl5000->mclk); 1469 if (ret) 1470 return ret; 1471 1472 /* read chip information */ 1473 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); 1474 if (ret) 1475 goto disable_clk; 1476 1477 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != 1478 SGTL5000_PARTID_PART_ID) { 1479 dev_err(&client->dev, 1480 "Device with ID register %x is not a sgtl5000\n", reg); 1481 ret = -ENODEV; 1482 goto disable_clk; 1483 } 1484 1485 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; 1486 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev); 1487 sgtl5000->revision = rev; 1488 1489 i2c_set_clientdata(client, sgtl5000); 1490 1491 /* Ensure sgtl5000 will start with sane register values */ 1492 ret = sgtl5000_fill_defaults(sgtl5000); 1493 if (ret) 1494 goto disable_clk; 1495 1496 ret = snd_soc_register_codec(&client->dev, 1497 &sgtl5000_driver, &sgtl5000_dai, 1); 1498 if (ret) 1499 goto disable_clk; 1500 1501 return 0; 1502 1503 disable_clk: 1504 clk_disable_unprepare(sgtl5000->mclk); 1505 return ret; 1506 } 1507 1508 static int sgtl5000_i2c_remove(struct i2c_client *client) 1509 { 1510 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1511 1512 snd_soc_unregister_codec(&client->dev); 1513 clk_disable_unprepare(sgtl5000->mclk); 1514 return 0; 1515 } 1516 1517 static const struct i2c_device_id sgtl5000_id[] = { 1518 {"sgtl5000", 0}, 1519 {}, 1520 }; 1521 1522 MODULE_DEVICE_TABLE(i2c, sgtl5000_id); 1523 1524 static const struct of_device_id sgtl5000_dt_ids[] = { 1525 { .compatible = "fsl,sgtl5000", }, 1526 { /* sentinel */ } 1527 }; 1528 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids); 1529 1530 static struct i2c_driver sgtl5000_i2c_driver = { 1531 .driver = { 1532 .name = "sgtl5000", 1533 .owner = THIS_MODULE, 1534 .of_match_table = sgtl5000_dt_ids, 1535 }, 1536 .probe = sgtl5000_i2c_probe, 1537 .remove = sgtl5000_i2c_remove, 1538 .id_table = sgtl5000_id, 1539 }; 1540 1541 module_i2c_driver(sgtl5000_i2c_driver); 1542 1543 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); 1544 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); 1545 MODULE_LICENSE("GPL"); 1546