1d1ede064SJack Yu /* SPDX-License-Identifier: GPL-2.0 */ 2d1ede064SJack Yu /* 3d1ede064SJack Yu * rt715.h -- RT715 ALSA SoC audio driver header 4d1ede064SJack Yu * 5d1ede064SJack Yu * Copyright(c) 2019 Realtek Semiconductor Corp. 6d1ede064SJack Yu */ 7d1ede064SJack Yu 8d1ede064SJack Yu #ifndef __RT715_H__ 9d1ede064SJack Yu #define __RT715_H__ 10d1ede064SJack Yu 11d1ede064SJack Yu #include <linux/regulator/consumer.h> 12d1ede064SJack Yu 13d1ede064SJack Yu struct rt715_priv { 14d1ede064SJack Yu struct regmap *regmap; 15d1ede064SJack Yu struct regmap *sdw_regmap; 16d1ede064SJack Yu struct snd_soc_codec *codec; 17d1ede064SJack Yu struct sdw_slave *slave; 18d1ede064SJack Yu int dbg_nid; 19d1ede064SJack Yu int dbg_vid; 20d1ede064SJack Yu int dbg_payload; 21d1ede064SJack Yu struct sdw_bus_params params; 22d1ede064SJack Yu bool hw_init; 23d1ede064SJack Yu bool first_hw_init; 24fa2f9837SJack Yu unsigned int kctl_2ch_vol_ori[2]; 25dcca646cSJack Yu unsigned int kctl_8ch_switch_ori[8]; 26dcca646cSJack Yu unsigned int kctl_8ch_vol_ori[8]; 27d1ede064SJack Yu }; 28d1ede064SJack Yu 29d1ede064SJack Yu /* NID */ 30d1ede064SJack Yu #define RT715_AUDIO_FUNCTION_GROUP 0x01 31d1ede064SJack Yu #define RT715_MIC_ADC 0x07 32d1ede064SJack Yu #define RT715_LINE_ADC 0x08 33d1ede064SJack Yu #define RT715_MIX_ADC 0x09 34d1ede064SJack Yu #define RT715_DMIC1 0x12 35d1ede064SJack Yu #define RT715_DMIC2 0x13 36d1ede064SJack Yu #define RT715_MIC1 0x18 37d1ede064SJack Yu #define RT715_MIC2 0x19 38d1ede064SJack Yu #define RT715_LINE1 0x1a 39d1ede064SJack Yu #define RT715_LINE2 0x1b 40d1ede064SJack Yu #define RT715_DMIC3 0x1d 41d1ede064SJack Yu #define RT715_DMIC4 0x29 42d1ede064SJack Yu #define RT715_VENDOR_REGISTERS 0x20 43d1ede064SJack Yu #define RT715_MUX_IN1 0x22 44d1ede064SJack Yu #define RT715_MUX_IN2 0x23 45d1ede064SJack Yu #define RT715_MUX_IN3 0x24 46d1ede064SJack Yu #define RT715_MUX_IN4 0x25 47d1ede064SJack Yu #define RT715_MIX_ADC2 0x27 48d1ede064SJack Yu #define RT715_INLINE_CMD 0x55 49d1ede064SJack Yu 50d1ede064SJack Yu /* Index (NID:20h) */ 51*927073eeSJack Yu #define RT715_VD_CLEAR_CTRL 0x01 52d1ede064SJack Yu #define RT715_SDW_INPUT_SEL 0x39 53d1ede064SJack Yu #define RT715_EXT_DMIC_CLK_CTRL2 0x54 54d1ede064SJack Yu 55d1ede064SJack Yu /* Verb */ 56d1ede064SJack Yu #define RT715_VERB_SET_CONNECT_SEL 0x3100 57d1ede064SJack Yu #define RT715_VERB_GET_CONNECT_SEL 0xb100 58d1ede064SJack Yu #define RT715_VERB_SET_EAPD_BTLENABLE 0x3c00 59d1ede064SJack Yu #define RT715_VERB_SET_POWER_STATE 0x3500 60d1ede064SJack Yu #define RT715_VERB_SET_CHANNEL_STREAMID 0x3600 61d1ede064SJack Yu #define RT715_VERB_SET_PIN_WIDGET_CONTROL 0x3700 62d1ede064SJack Yu #define RT715_VERB_SET_CONFIG_DEFAULT1 0x4c00 63d1ede064SJack Yu #define RT715_VERB_SET_CONFIG_DEFAULT2 0x4d00 64d1ede064SJack Yu #define RT715_VERB_SET_CONFIG_DEFAULT3 0x4e00 65d1ede064SJack Yu #define RT715_VERB_SET_CONFIG_DEFAULT4 0x4f00 66d1ede064SJack Yu #define RT715_VERB_SET_UNSOLICITED_ENABLE 0x3800 67d1ede064SJack Yu #define RT715_SET_AMP_GAIN_MUTE_H 0x7300 68d1ede064SJack Yu #define RT715_SET_AMP_GAIN_MUTE_L 0x8380 69d1ede064SJack Yu #define RT715_READ_HDA_3 0x2012 70d1ede064SJack Yu #define RT715_READ_HDA_2 0x2013 71d1ede064SJack Yu #define RT715_READ_HDA_1 0x2014 72d1ede064SJack Yu #define RT715_READ_HDA_0 0x2015 73d1ede064SJack Yu #define RT715_PRIV_INDEX_W_H 0x7520 74d1ede064SJack Yu #define RT715_PRIV_INDEX_W_L 0x85a0 75*927073eeSJack Yu #define RT715_PRIV_INDEX_W_H_2 0x7500 76*927073eeSJack Yu #define RT715_PRIV_INDEX_W_L_2 0x8580 77d1ede064SJack Yu #define RT715_PRIV_DATA_W_H 0x7420 78d1ede064SJack Yu #define RT715_PRIV_DATA_W_L 0x84a0 79d1ede064SJack Yu #define RT715_PRIV_INDEX_R_H 0x9d20 80d1ede064SJack Yu #define RT715_PRIV_INDEX_R_L 0xada0 81d1ede064SJack Yu #define RT715_PRIV_DATA_R_H 0x9c20 82d1ede064SJack Yu #define RT715_PRIV_DATA_R_L 0xaca0 83d1ede064SJack Yu #define RT715_MIC_ADC_FORMAT_H 0x7207 84d1ede064SJack Yu #define RT715_MIC_ADC_FORMAT_L 0x8287 85d1ede064SJack Yu #define RT715_MIC_LINE_FORMAT_H 0x7208 86d1ede064SJack Yu #define RT715_MIC_LINE_FORMAT_L 0x8288 87d1ede064SJack Yu #define RT715_MIX_ADC_FORMAT_H 0x7209 88d1ede064SJack Yu #define RT715_MIX_ADC_FORMAT_L 0x8289 89d1ede064SJack Yu #define RT715_MIX_ADC2_FORMAT_H 0x7227 90d1ede064SJack Yu #define RT715_MIX_ADC2_FORMAT_L 0x82a7 91d1ede064SJack Yu #define RT715_FUNC_RESET 0xff01 92d1ede064SJack Yu 93d1ede064SJack Yu #define RT715_SET_AUDIO_POWER_STATE\ 94d1ede064SJack Yu (RT715_VERB_SET_POWER_STATE | RT715_AUDIO_FUNCTION_GROUP) 95d1ede064SJack Yu #define RT715_SET_PIN_DMIC1\ 96d1ede064SJack Yu (RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_DMIC1) 97d1ede064SJack Yu #define RT715_SET_PIN_DMIC2\ 98d1ede064SJack Yu (RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_DMIC2) 99d1ede064SJack Yu #define RT715_SET_PIN_DMIC3\ 100d1ede064SJack Yu (RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_DMIC3) 101d1ede064SJack Yu #define RT715_SET_PIN_DMIC4\ 102d1ede064SJack Yu (RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_DMIC4) 103d1ede064SJack Yu #define RT715_SET_PIN_MIC1\ 104d1ede064SJack Yu (RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_MIC1) 105d1ede064SJack Yu #define RT715_SET_PIN_MIC2\ 106d1ede064SJack Yu (RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_MIC2) 107d1ede064SJack Yu #define RT715_SET_PIN_LINE1\ 108d1ede064SJack Yu (RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_LINE1) 109d1ede064SJack Yu #define RT715_SET_PIN_LINE2\ 110d1ede064SJack Yu (RT715_VERB_SET_PIN_WIDGET_CONTROL | RT715_LINE2) 111d1ede064SJack Yu #define RT715_SET_MIC1_UNSOLICITED_ENABLE\ 112d1ede064SJack Yu (RT715_VERB_SET_UNSOLICITED_ENABLE | RT715_MIC1) 113d1ede064SJack Yu #define RT715_SET_MIC2_UNSOLICITED_ENABLE\ 114d1ede064SJack Yu (RT715_VERB_SET_UNSOLICITED_ENABLE | RT715_MIC2) 115d1ede064SJack Yu #define RT715_SET_STREAMID_MIC_ADC\ 116d1ede064SJack Yu (RT715_VERB_SET_CHANNEL_STREAMID | RT715_MIC_ADC) 117d1ede064SJack Yu #define RT715_SET_STREAMID_LINE_ADC\ 118d1ede064SJack Yu (RT715_VERB_SET_CHANNEL_STREAMID | RT715_LINE_ADC) 119d1ede064SJack Yu #define RT715_SET_STREAMID_MIX_ADC\ 120d1ede064SJack Yu (RT715_VERB_SET_CHANNEL_STREAMID | RT715_MIX_ADC) 121d1ede064SJack Yu #define RT715_SET_STREAMID_MIX_ADC2\ 122d1ede064SJack Yu (RT715_VERB_SET_CHANNEL_STREAMID | RT715_MIX_ADC2) 123d1ede064SJack Yu #define RT715_SET_GAIN_MIC_ADC_L\ 124d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_L | RT715_MIC_ADC) 125d1ede064SJack Yu #define RT715_SET_GAIN_MIC_ADC_H\ 126d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_H | RT715_MIC_ADC) 127d1ede064SJack Yu #define RT715_SET_GAIN_LINE_ADC_L\ 128d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_L | RT715_LINE_ADC) 129d1ede064SJack Yu #define RT715_SET_GAIN_LINE_ADC_H\ 130d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_H | RT715_LINE_ADC) 131d1ede064SJack Yu #define RT715_SET_GAIN_MIX_ADC_L\ 132d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_L | RT715_MIX_ADC) 133d1ede064SJack Yu #define RT715_SET_GAIN_MIX_ADC_H\ 134d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_H | RT715_MIX_ADC) 135d1ede064SJack Yu #define RT715_SET_GAIN_MIX_ADC2_L\ 136d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_L | RT715_MIX_ADC2) 137d1ede064SJack Yu #define RT715_SET_GAIN_MIX_ADC2_H\ 138d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_H | RT715_MIX_ADC2) 139d1ede064SJack Yu #define RT715_SET_GAIN_DMIC1_L\ 140d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_L | RT715_DMIC1) 141d1ede064SJack Yu #define RT715_SET_GAIN_DMIC1_H\ 142d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_H | RT715_DMIC1) 143d1ede064SJack Yu #define RT715_SET_GAIN_DMIC2_L\ 144d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_L | RT715_DMIC2) 145d1ede064SJack Yu #define RT715_SET_GAIN_DMIC2_H\ 146d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_H | RT715_DMIC2) 147d1ede064SJack Yu #define RT715_SET_GAIN_DMIC3_L\ 148d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_L | RT715_DMIC3) 149d1ede064SJack Yu #define RT715_SET_GAIN_DMIC3_H\ 150d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_H | RT715_DMIC3) 151d1ede064SJack Yu #define RT715_SET_GAIN_DMIC4_L\ 152d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_L | RT715_DMIC4) 153d1ede064SJack Yu #define RT715_SET_GAIN_DMIC4_H\ 154d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_H | RT715_DMIC4) 155d1ede064SJack Yu #define RT715_SET_GAIN_MIC1_L\ 156d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_L | RT715_MIC1) 157d1ede064SJack Yu #define RT715_SET_GAIN_MIC1_H\ 158d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_H | RT715_MIC1) 159d1ede064SJack Yu #define RT715_SET_GAIN_MIC2_L\ 160d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_L | RT715_MIC2) 161d1ede064SJack Yu #define RT715_SET_GAIN_MIC2_H\ 162d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_H | RT715_MIC2) 163d1ede064SJack Yu #define RT715_SET_GAIN_LINE1_L\ 164d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_L | RT715_LINE1) 165d1ede064SJack Yu #define RT715_SET_GAIN_LINE1_H\ 166d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_H | RT715_LINE1) 167d1ede064SJack Yu #define RT715_SET_GAIN_LINE2_L\ 168d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_L | RT715_LINE2) 169d1ede064SJack Yu #define RT715_SET_GAIN_LINE2_H\ 170d1ede064SJack Yu (RT715_SET_AMP_GAIN_MUTE_H | RT715_LINE2) 171d1ede064SJack Yu #define RT715_SET_DMIC1_CONFIG_DEFAULT1\ 172d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT1 | RT715_DMIC1) 173d1ede064SJack Yu #define RT715_SET_DMIC2_CONFIG_DEFAULT1\ 174d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT1 | RT715_DMIC2) 175d1ede064SJack Yu #define RT715_SET_DMIC1_CONFIG_DEFAULT2\ 176d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT2 | RT715_DMIC1) 177d1ede064SJack Yu #define RT715_SET_DMIC2_CONFIG_DEFAULT2\ 178d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT2 | RT715_DMIC2) 179d1ede064SJack Yu #define RT715_SET_DMIC1_CONFIG_DEFAULT3\ 180d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT3 | RT715_DMIC1) 181d1ede064SJack Yu #define RT715_SET_DMIC2_CONFIG_DEFAULT3\ 182d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT3 | RT715_DMIC2) 183d1ede064SJack Yu #define RT715_SET_DMIC1_CONFIG_DEFAULT4\ 184d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT4 | RT715_DMIC1) 185d1ede064SJack Yu #define RT715_SET_DMIC2_CONFIG_DEFAULT4\ 186d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT4 | RT715_DMIC2) 187d1ede064SJack Yu #define RT715_SET_DMIC3_CONFIG_DEFAULT1\ 188d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT1 | RT715_DMIC3) 189d1ede064SJack Yu #define RT715_SET_DMIC4_CONFIG_DEFAULT1\ 190d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT1 | RT715_DMIC4) 191d1ede064SJack Yu #define RT715_SET_DMIC3_CONFIG_DEFAULT2\ 192d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT2 | RT715_DMIC3) 193d1ede064SJack Yu #define RT715_SET_DMIC4_CONFIG_DEFAULT2\ 194d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT2 | RT715_DMIC4) 195d1ede064SJack Yu #define RT715_SET_DMIC3_CONFIG_DEFAULT3\ 196d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT3 | RT715_DMIC3) 197d1ede064SJack Yu #define RT715_SET_DMIC4_CONFIG_DEFAULT3\ 198d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT3 | RT715_DMIC4) 199d1ede064SJack Yu #define RT715_SET_DMIC3_CONFIG_DEFAULT4\ 200d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT4 | RT715_DMIC3) 201d1ede064SJack Yu #define RT715_SET_DMIC4_CONFIG_DEFAULT4\ 202d1ede064SJack Yu (RT715_VERB_SET_CONFIG_DEFAULT4 | RT715_DMIC4) 203d1ede064SJack Yu 204*927073eeSJack Yu /* vendor register clear ctrl-1 (0x01)(NID:20h) */ 205*927073eeSJack Yu #define RT715_CLEAR_HIDDEN_REG (0x1 << 15) 206*927073eeSJack Yu 207*927073eeSJack Yu 208d1ede064SJack Yu #define RT715_MUTE_SFT 7 209d1ede064SJack Yu #define RT715_DIR_IN_SFT 6 210d1ede064SJack Yu #define RT715_DIR_OUT_SFT 7 211d1ede064SJack Yu 212d1ede064SJack Yu enum { 213d1ede064SJack Yu RT715_AIF1, 214d1ede064SJack Yu RT715_AIF2, 215d1ede064SJack Yu }; 216d1ede064SJack Yu 21716346a3cSJack Yu #define RT715_POWER_UP_DELAY_MS 400 21816346a3cSJack Yu 219d1ede064SJack Yu int rt715_io_init(struct device *dev, struct sdw_slave *slave); 220d1ede064SJack Yu int rt715_init(struct device *dev, struct regmap *sdw_regmap, 221d1ede064SJack Yu struct regmap *regmap, struct sdw_slave *slave); 222d1ede064SJack Yu 223d1ede064SJack Yu int hda_to_sdw(unsigned int nid, unsigned int verb, unsigned int payload, 224d1ede064SJack Yu unsigned int *sdw_addr_h, unsigned int *sdw_data_h, 225d1ede064SJack Yu unsigned int *sdw_addr_l, unsigned int *sdw_data_l); 226d1ede064SJack Yu int rt715_clock_config(struct device *dev); 227d1ede064SJack Yu #endif /* __RT715_H__ */ 228