1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt5682.c -- RT5682 ALSA SoC audio component driver 4 // 5 // Copyright 2018 Realtek Semiconductor Corp. 6 // Author: Bard Liao <bardliao@realtek.com> 7 // 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/platform_device.h> 16 #include <linux/spi/spi.h> 17 #include <linux/acpi.h> 18 #include <linux/gpio.h> 19 #include <linux/of_gpio.h> 20 #include <linux/mutex.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/jack.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <sound/rt5682.h> 30 31 #include "rl6231.h" 32 #include "rt5682.h" 33 34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = { 35 "AVDD", 36 "MICVDD", 37 "VBAT", 38 }; 39 EXPORT_SYMBOL_GPL(rt5682_supply_names); 40 41 static const struct reg_sequence patch_list[] = { 42 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000}, 43 {RT5682_DAC_ADC_DIG_VOL1, 0xa020}, 44 {RT5682_I2C_CTRL, 0x000f}, 45 {RT5682_PLL2_INTERNAL, 0x8266}, 46 {RT5682_SAR_IL_CMD_3, 0x8365}, 47 }; 48 49 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev) 50 { 51 int ret; 52 53 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, 54 ARRAY_SIZE(patch_list)); 55 if (ret) 56 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret); 57 } 58 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list); 59 60 const struct reg_default rt5682_reg[RT5682_REG_NUM] = { 61 {0x0002, 0x8080}, 62 {0x0003, 0x8000}, 63 {0x0005, 0x0000}, 64 {0x0006, 0x0000}, 65 {0x0008, 0x800f}, 66 {0x000b, 0x0000}, 67 {0x0010, 0x4040}, 68 {0x0011, 0x0000}, 69 {0x0012, 0x1404}, 70 {0x0013, 0x1000}, 71 {0x0014, 0xa00a}, 72 {0x0015, 0x0404}, 73 {0x0016, 0x0404}, 74 {0x0019, 0xafaf}, 75 {0x001c, 0x2f2f}, 76 {0x001f, 0x0000}, 77 {0x0022, 0x5757}, 78 {0x0023, 0x0039}, 79 {0x0024, 0x000b}, 80 {0x0026, 0xc0c4}, 81 {0x0029, 0x8080}, 82 {0x002a, 0xa0a0}, 83 {0x002b, 0x0300}, 84 {0x0030, 0x0000}, 85 {0x003c, 0x0080}, 86 {0x0044, 0x0c0c}, 87 {0x0049, 0x0000}, 88 {0x0061, 0x0000}, 89 {0x0062, 0x0000}, 90 {0x0063, 0x003f}, 91 {0x0064, 0x0000}, 92 {0x0065, 0x0000}, 93 {0x0066, 0x0030}, 94 {0x0067, 0x0000}, 95 {0x006b, 0x0000}, 96 {0x006c, 0x0000}, 97 {0x006d, 0x2200}, 98 {0x006e, 0x0a10}, 99 {0x0070, 0x8000}, 100 {0x0071, 0x8000}, 101 {0x0073, 0x0000}, 102 {0x0074, 0x0000}, 103 {0x0075, 0x0002}, 104 {0x0076, 0x0001}, 105 {0x0079, 0x0000}, 106 {0x007a, 0x0000}, 107 {0x007b, 0x0000}, 108 {0x007c, 0x0100}, 109 {0x007e, 0x0000}, 110 {0x0080, 0x0000}, 111 {0x0081, 0x0000}, 112 {0x0082, 0x0000}, 113 {0x0083, 0x0000}, 114 {0x0084, 0x0000}, 115 {0x0085, 0x0000}, 116 {0x0086, 0x0005}, 117 {0x0087, 0x0000}, 118 {0x0088, 0x0000}, 119 {0x008c, 0x0003}, 120 {0x008d, 0x0000}, 121 {0x008e, 0x0060}, 122 {0x008f, 0x1000}, 123 {0x0091, 0x0c26}, 124 {0x0092, 0x0073}, 125 {0x0093, 0x0000}, 126 {0x0094, 0x0080}, 127 {0x0098, 0x0000}, 128 {0x009a, 0x0000}, 129 {0x009b, 0x0000}, 130 {0x009c, 0x0000}, 131 {0x009d, 0x0000}, 132 {0x009e, 0x100c}, 133 {0x009f, 0x0000}, 134 {0x00a0, 0x0000}, 135 {0x00a3, 0x0002}, 136 {0x00a4, 0x0001}, 137 {0x00ae, 0x2040}, 138 {0x00af, 0x0000}, 139 {0x00b6, 0x0000}, 140 {0x00b7, 0x0000}, 141 {0x00b8, 0x0000}, 142 {0x00b9, 0x0002}, 143 {0x00be, 0x0000}, 144 {0x00c0, 0x0160}, 145 {0x00c1, 0x82a0}, 146 {0x00c2, 0x0000}, 147 {0x00d0, 0x0000}, 148 {0x00d1, 0x2244}, 149 {0x00d2, 0x3300}, 150 {0x00d3, 0x2200}, 151 {0x00d4, 0x0000}, 152 {0x00d9, 0x0009}, 153 {0x00da, 0x0000}, 154 {0x00db, 0x0000}, 155 {0x00dc, 0x00c0}, 156 {0x00dd, 0x2220}, 157 {0x00de, 0x3131}, 158 {0x00df, 0x3131}, 159 {0x00e0, 0x3131}, 160 {0x00e2, 0x0000}, 161 {0x00e3, 0x4000}, 162 {0x00e4, 0x0aa0}, 163 {0x00e5, 0x3131}, 164 {0x00e6, 0x3131}, 165 {0x00e7, 0x3131}, 166 {0x00e8, 0x3131}, 167 {0x00ea, 0xb320}, 168 {0x00eb, 0x0000}, 169 {0x00f0, 0x0000}, 170 {0x00f1, 0x00d0}, 171 {0x00f2, 0x00d0}, 172 {0x00f6, 0x0000}, 173 {0x00fa, 0x0000}, 174 {0x00fb, 0x0000}, 175 {0x00fc, 0x0000}, 176 {0x00fd, 0x0000}, 177 {0x00fe, 0x10ec}, 178 {0x00ff, 0x6530}, 179 {0x0100, 0xa0a0}, 180 {0x010b, 0x0000}, 181 {0x010c, 0xae00}, 182 {0x010d, 0xaaa0}, 183 {0x010e, 0x8aa2}, 184 {0x010f, 0x02a2}, 185 {0x0110, 0xc000}, 186 {0x0111, 0x04a2}, 187 {0x0112, 0x2800}, 188 {0x0113, 0x0000}, 189 {0x0117, 0x0100}, 190 {0x0125, 0x0410}, 191 {0x0132, 0x6026}, 192 {0x0136, 0x5555}, 193 {0x0138, 0x3700}, 194 {0x013a, 0x2000}, 195 {0x013b, 0x2000}, 196 {0x013c, 0x2005}, 197 {0x013f, 0x0000}, 198 {0x0142, 0x0000}, 199 {0x0145, 0x0002}, 200 {0x0146, 0x0000}, 201 {0x0147, 0x0000}, 202 {0x0148, 0x0000}, 203 {0x0149, 0x0000}, 204 {0x0150, 0x79a1}, 205 {0x0156, 0xaaaa}, 206 {0x0160, 0x4ec0}, 207 {0x0161, 0x0080}, 208 {0x0162, 0x0200}, 209 {0x0163, 0x0800}, 210 {0x0164, 0x0000}, 211 {0x0165, 0x0000}, 212 {0x0166, 0x0000}, 213 {0x0167, 0x000f}, 214 {0x0168, 0x000f}, 215 {0x0169, 0x0021}, 216 {0x0190, 0x413d}, 217 {0x0194, 0x0000}, 218 {0x0195, 0x0000}, 219 {0x0197, 0x0022}, 220 {0x0198, 0x0000}, 221 {0x0199, 0x0000}, 222 {0x01af, 0x0000}, 223 {0x01b0, 0x0400}, 224 {0x01b1, 0x0000}, 225 {0x01b2, 0x0000}, 226 {0x01b3, 0x0000}, 227 {0x01b4, 0x0000}, 228 {0x01b5, 0x0000}, 229 {0x01b6, 0x01c3}, 230 {0x01b7, 0x02a0}, 231 {0x01b8, 0x03e9}, 232 {0x01b9, 0x1389}, 233 {0x01ba, 0xc351}, 234 {0x01bb, 0x0009}, 235 {0x01bc, 0x0018}, 236 {0x01bd, 0x002a}, 237 {0x01be, 0x004c}, 238 {0x01bf, 0x0097}, 239 {0x01c0, 0x433d}, 240 {0x01c2, 0x0000}, 241 {0x01c3, 0x0000}, 242 {0x01c4, 0x0000}, 243 {0x01c5, 0x0000}, 244 {0x01c6, 0x0000}, 245 {0x01c7, 0x0000}, 246 {0x01c8, 0x40af}, 247 {0x01c9, 0x0702}, 248 {0x01ca, 0x0000}, 249 {0x01cb, 0x0000}, 250 {0x01cc, 0x5757}, 251 {0x01cd, 0x5757}, 252 {0x01ce, 0x5757}, 253 {0x01cf, 0x5757}, 254 {0x01d0, 0x5757}, 255 {0x01d1, 0x5757}, 256 {0x01d2, 0x5757}, 257 {0x01d3, 0x5757}, 258 {0x01d4, 0x5757}, 259 {0x01d5, 0x5757}, 260 {0x01d6, 0x0000}, 261 {0x01d7, 0x0008}, 262 {0x01d8, 0x0029}, 263 {0x01d9, 0x3333}, 264 {0x01da, 0x0000}, 265 {0x01db, 0x0004}, 266 {0x01dc, 0x0000}, 267 {0x01de, 0x7c00}, 268 {0x01df, 0x0320}, 269 {0x01e0, 0x06a1}, 270 {0x01e1, 0x0000}, 271 {0x01e2, 0x0000}, 272 {0x01e3, 0x0000}, 273 {0x01e4, 0x0000}, 274 {0x01e6, 0x0001}, 275 {0x01e7, 0x0000}, 276 {0x01e8, 0x0000}, 277 {0x01ea, 0x0000}, 278 {0x01eb, 0x0000}, 279 {0x01ec, 0x0000}, 280 {0x01ed, 0x0000}, 281 {0x01ee, 0x0000}, 282 {0x01ef, 0x0000}, 283 {0x01f0, 0x0000}, 284 {0x01f1, 0x0000}, 285 {0x01f2, 0x0000}, 286 {0x01f3, 0x0000}, 287 {0x01f4, 0x0000}, 288 {0x0210, 0x6297}, 289 {0x0211, 0xa005}, 290 {0x0212, 0x824c}, 291 {0x0213, 0xf7ff}, 292 {0x0214, 0xf24c}, 293 {0x0215, 0x0102}, 294 {0x0216, 0x00a3}, 295 {0x0217, 0x0048}, 296 {0x0218, 0xa2c0}, 297 {0x0219, 0x0400}, 298 {0x021a, 0x00c8}, 299 {0x021b, 0x00c0}, 300 {0x021c, 0x0000}, 301 {0x0250, 0x4500}, 302 {0x0251, 0x40b3}, 303 {0x0252, 0x0000}, 304 {0x0253, 0x0000}, 305 {0x0254, 0x0000}, 306 {0x0255, 0x0000}, 307 {0x0256, 0x0000}, 308 {0x0257, 0x0000}, 309 {0x0258, 0x0000}, 310 {0x0259, 0x0000}, 311 {0x025a, 0x0005}, 312 {0x0270, 0x0000}, 313 {0x02ff, 0x0110}, 314 {0x0300, 0x001f}, 315 {0x0301, 0x032c}, 316 {0x0302, 0x5f21}, 317 {0x0303, 0x4000}, 318 {0x0304, 0x4000}, 319 {0x0305, 0x06d5}, 320 {0x0306, 0x8000}, 321 {0x0307, 0x0700}, 322 {0x0310, 0x4560}, 323 {0x0311, 0xa4a8}, 324 {0x0312, 0x7418}, 325 {0x0313, 0x0000}, 326 {0x0314, 0x0006}, 327 {0x0315, 0xffff}, 328 {0x0316, 0xc400}, 329 {0x0317, 0x0000}, 330 {0x03c0, 0x7e00}, 331 {0x03c1, 0x8000}, 332 {0x03c2, 0x8000}, 333 {0x03c3, 0x8000}, 334 {0x03c4, 0x8000}, 335 {0x03c5, 0x8000}, 336 {0x03c6, 0x8000}, 337 {0x03c7, 0x8000}, 338 {0x03c8, 0x8000}, 339 {0x03c9, 0x8000}, 340 {0x03ca, 0x8000}, 341 {0x03cb, 0x8000}, 342 {0x03cc, 0x8000}, 343 {0x03d0, 0x0000}, 344 {0x03d1, 0x0000}, 345 {0x03d2, 0x0000}, 346 {0x03d3, 0x0000}, 347 {0x03d4, 0x2000}, 348 {0x03d5, 0x2000}, 349 {0x03d6, 0x0000}, 350 {0x03d7, 0x0000}, 351 {0x03d8, 0x2000}, 352 {0x03d9, 0x2000}, 353 {0x03da, 0x2000}, 354 {0x03db, 0x2000}, 355 {0x03dc, 0x0000}, 356 {0x03dd, 0x0000}, 357 {0x03de, 0x0000}, 358 {0x03df, 0x2000}, 359 {0x03e0, 0x0000}, 360 {0x03e1, 0x0000}, 361 {0x03e2, 0x0000}, 362 {0x03e3, 0x0000}, 363 {0x03e4, 0x0000}, 364 {0x03e5, 0x0000}, 365 {0x03e6, 0x0000}, 366 {0x03e7, 0x0000}, 367 {0x03e8, 0x0000}, 368 {0x03e9, 0x0000}, 369 {0x03ea, 0x0000}, 370 {0x03eb, 0x0000}, 371 {0x03ec, 0x0000}, 372 {0x03ed, 0x0000}, 373 {0x03ee, 0x0000}, 374 {0x03ef, 0x0000}, 375 {0x03f0, 0x0800}, 376 {0x03f1, 0x0800}, 377 {0x03f2, 0x0800}, 378 {0x03f3, 0x0800}, 379 }; 380 EXPORT_SYMBOL_GPL(rt5682_reg); 381 382 bool rt5682_volatile_register(struct device *dev, unsigned int reg) 383 { 384 switch (reg) { 385 case RT5682_RESET: 386 case RT5682_CBJ_CTRL_2: 387 case RT5682_INT_ST_1: 388 case RT5682_4BTN_IL_CMD_1: 389 case RT5682_AJD1_CTRL: 390 case RT5682_HP_CALIB_CTRL_1: 391 case RT5682_DEVICE_ID: 392 case RT5682_I2C_MODE: 393 case RT5682_HP_CALIB_CTRL_10: 394 case RT5682_EFUSE_CTRL_2: 395 case RT5682_JD_TOP_VC_VTRL: 396 case RT5682_HP_IMP_SENS_CTRL_19: 397 case RT5682_IL_CMD_1: 398 case RT5682_SAR_IL_CMD_2: 399 case RT5682_SAR_IL_CMD_4: 400 case RT5682_SAR_IL_CMD_10: 401 case RT5682_SAR_IL_CMD_11: 402 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11: 403 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11: 404 return true; 405 default: 406 return false; 407 } 408 } 409 EXPORT_SYMBOL_GPL(rt5682_volatile_register); 410 411 bool rt5682_readable_register(struct device *dev, unsigned int reg) 412 { 413 switch (reg) { 414 case RT5682_RESET: 415 case RT5682_VERSION_ID: 416 case RT5682_VENDOR_ID: 417 case RT5682_DEVICE_ID: 418 case RT5682_HP_CTRL_1: 419 case RT5682_HP_CTRL_2: 420 case RT5682_HPL_GAIN: 421 case RT5682_HPR_GAIN: 422 case RT5682_I2C_CTRL: 423 case RT5682_CBJ_BST_CTRL: 424 case RT5682_CBJ_CTRL_1: 425 case RT5682_CBJ_CTRL_2: 426 case RT5682_CBJ_CTRL_3: 427 case RT5682_CBJ_CTRL_4: 428 case RT5682_CBJ_CTRL_5: 429 case RT5682_CBJ_CTRL_6: 430 case RT5682_CBJ_CTRL_7: 431 case RT5682_DAC1_DIG_VOL: 432 case RT5682_STO1_ADC_DIG_VOL: 433 case RT5682_STO1_ADC_BOOST: 434 case RT5682_HP_IMP_GAIN_1: 435 case RT5682_HP_IMP_GAIN_2: 436 case RT5682_SIDETONE_CTRL: 437 case RT5682_STO1_ADC_MIXER: 438 case RT5682_AD_DA_MIXER: 439 case RT5682_STO1_DAC_MIXER: 440 case RT5682_A_DAC1_MUX: 441 case RT5682_DIG_INF2_DATA: 442 case RT5682_REC_MIXER: 443 case RT5682_CAL_REC: 444 case RT5682_ALC_BACK_GAIN: 445 case RT5682_PWR_DIG_1: 446 case RT5682_PWR_DIG_2: 447 case RT5682_PWR_ANLG_1: 448 case RT5682_PWR_ANLG_2: 449 case RT5682_PWR_ANLG_3: 450 case RT5682_PWR_MIXER: 451 case RT5682_PWR_VOL: 452 case RT5682_CLK_DET: 453 case RT5682_RESET_LPF_CTRL: 454 case RT5682_RESET_HPF_CTRL: 455 case RT5682_DMIC_CTRL_1: 456 case RT5682_I2S1_SDP: 457 case RT5682_I2S2_SDP: 458 case RT5682_ADDA_CLK_1: 459 case RT5682_ADDA_CLK_2: 460 case RT5682_I2S1_F_DIV_CTRL_1: 461 case RT5682_I2S1_F_DIV_CTRL_2: 462 case RT5682_TDM_CTRL: 463 case RT5682_TDM_ADDA_CTRL_1: 464 case RT5682_TDM_ADDA_CTRL_2: 465 case RT5682_DATA_SEL_CTRL_1: 466 case RT5682_TDM_TCON_CTRL: 467 case RT5682_GLB_CLK: 468 case RT5682_PLL_CTRL_1: 469 case RT5682_PLL_CTRL_2: 470 case RT5682_PLL_TRACK_1: 471 case RT5682_PLL_TRACK_2: 472 case RT5682_PLL_TRACK_3: 473 case RT5682_PLL_TRACK_4: 474 case RT5682_PLL_TRACK_5: 475 case RT5682_PLL_TRACK_6: 476 case RT5682_PLL_TRACK_11: 477 case RT5682_SDW_REF_CLK: 478 case RT5682_DEPOP_1: 479 case RT5682_DEPOP_2: 480 case RT5682_HP_CHARGE_PUMP_1: 481 case RT5682_HP_CHARGE_PUMP_2: 482 case RT5682_MICBIAS_1: 483 case RT5682_MICBIAS_2: 484 case RT5682_PLL_TRACK_12: 485 case RT5682_PLL_TRACK_14: 486 case RT5682_PLL2_CTRL_1: 487 case RT5682_PLL2_CTRL_2: 488 case RT5682_PLL2_CTRL_3: 489 case RT5682_PLL2_CTRL_4: 490 case RT5682_RC_CLK_CTRL: 491 case RT5682_I2S_M_CLK_CTRL_1: 492 case RT5682_I2S2_F_DIV_CTRL_1: 493 case RT5682_I2S2_F_DIV_CTRL_2: 494 case RT5682_EQ_CTRL_1: 495 case RT5682_EQ_CTRL_2: 496 case RT5682_IRQ_CTRL_1: 497 case RT5682_IRQ_CTRL_2: 498 case RT5682_IRQ_CTRL_3: 499 case RT5682_IRQ_CTRL_4: 500 case RT5682_INT_ST_1: 501 case RT5682_GPIO_CTRL_1: 502 case RT5682_GPIO_CTRL_2: 503 case RT5682_GPIO_CTRL_3: 504 case RT5682_HP_AMP_DET_CTRL_1: 505 case RT5682_HP_AMP_DET_CTRL_2: 506 case RT5682_MID_HP_AMP_DET: 507 case RT5682_LOW_HP_AMP_DET: 508 case RT5682_DELAY_BUF_CTRL: 509 case RT5682_SV_ZCD_1: 510 case RT5682_SV_ZCD_2: 511 case RT5682_IL_CMD_1: 512 case RT5682_IL_CMD_2: 513 case RT5682_IL_CMD_3: 514 case RT5682_IL_CMD_4: 515 case RT5682_IL_CMD_5: 516 case RT5682_IL_CMD_6: 517 case RT5682_4BTN_IL_CMD_1: 518 case RT5682_4BTN_IL_CMD_2: 519 case RT5682_4BTN_IL_CMD_3: 520 case RT5682_4BTN_IL_CMD_4: 521 case RT5682_4BTN_IL_CMD_5: 522 case RT5682_4BTN_IL_CMD_6: 523 case RT5682_4BTN_IL_CMD_7: 524 case RT5682_ADC_STO1_HP_CTRL_1: 525 case RT5682_ADC_STO1_HP_CTRL_2: 526 case RT5682_AJD1_CTRL: 527 case RT5682_JD1_THD: 528 case RT5682_JD2_THD: 529 case RT5682_JD_CTRL_1: 530 case RT5682_DUMMY_1: 531 case RT5682_DUMMY_2: 532 case RT5682_DUMMY_3: 533 case RT5682_DAC_ADC_DIG_VOL1: 534 case RT5682_BIAS_CUR_CTRL_2: 535 case RT5682_BIAS_CUR_CTRL_3: 536 case RT5682_BIAS_CUR_CTRL_4: 537 case RT5682_BIAS_CUR_CTRL_5: 538 case RT5682_BIAS_CUR_CTRL_6: 539 case RT5682_BIAS_CUR_CTRL_7: 540 case RT5682_BIAS_CUR_CTRL_8: 541 case RT5682_BIAS_CUR_CTRL_9: 542 case RT5682_BIAS_CUR_CTRL_10: 543 case RT5682_VREF_REC_OP_FB_CAP_CTRL: 544 case RT5682_CHARGE_PUMP_1: 545 case RT5682_DIG_IN_CTRL_1: 546 case RT5682_PAD_DRIVING_CTRL: 547 case RT5682_SOFT_RAMP_DEPOP: 548 case RT5682_CHOP_DAC: 549 case RT5682_CHOP_ADC: 550 case RT5682_CALIB_ADC_CTRL: 551 case RT5682_VOL_TEST: 552 case RT5682_SPKVDD_DET_STA: 553 case RT5682_TEST_MODE_CTRL_1: 554 case RT5682_TEST_MODE_CTRL_2: 555 case RT5682_TEST_MODE_CTRL_3: 556 case RT5682_TEST_MODE_CTRL_4: 557 case RT5682_TEST_MODE_CTRL_5: 558 case RT5682_PLL1_INTERNAL: 559 case RT5682_PLL2_INTERNAL: 560 case RT5682_STO_NG2_CTRL_1: 561 case RT5682_STO_NG2_CTRL_2: 562 case RT5682_STO_NG2_CTRL_3: 563 case RT5682_STO_NG2_CTRL_4: 564 case RT5682_STO_NG2_CTRL_5: 565 case RT5682_STO_NG2_CTRL_6: 566 case RT5682_STO_NG2_CTRL_7: 567 case RT5682_STO_NG2_CTRL_8: 568 case RT5682_STO_NG2_CTRL_9: 569 case RT5682_STO_NG2_CTRL_10: 570 case RT5682_STO1_DAC_SIL_DET: 571 case RT5682_SIL_PSV_CTRL1: 572 case RT5682_SIL_PSV_CTRL2: 573 case RT5682_SIL_PSV_CTRL3: 574 case RT5682_SIL_PSV_CTRL4: 575 case RT5682_SIL_PSV_CTRL5: 576 case RT5682_HP_IMP_SENS_CTRL_01: 577 case RT5682_HP_IMP_SENS_CTRL_02: 578 case RT5682_HP_IMP_SENS_CTRL_03: 579 case RT5682_HP_IMP_SENS_CTRL_04: 580 case RT5682_HP_IMP_SENS_CTRL_05: 581 case RT5682_HP_IMP_SENS_CTRL_06: 582 case RT5682_HP_IMP_SENS_CTRL_07: 583 case RT5682_HP_IMP_SENS_CTRL_08: 584 case RT5682_HP_IMP_SENS_CTRL_09: 585 case RT5682_HP_IMP_SENS_CTRL_10: 586 case RT5682_HP_IMP_SENS_CTRL_11: 587 case RT5682_HP_IMP_SENS_CTRL_12: 588 case RT5682_HP_IMP_SENS_CTRL_13: 589 case RT5682_HP_IMP_SENS_CTRL_14: 590 case RT5682_HP_IMP_SENS_CTRL_15: 591 case RT5682_HP_IMP_SENS_CTRL_16: 592 case RT5682_HP_IMP_SENS_CTRL_17: 593 case RT5682_HP_IMP_SENS_CTRL_18: 594 case RT5682_HP_IMP_SENS_CTRL_19: 595 case RT5682_HP_IMP_SENS_CTRL_20: 596 case RT5682_HP_IMP_SENS_CTRL_21: 597 case RT5682_HP_IMP_SENS_CTRL_22: 598 case RT5682_HP_IMP_SENS_CTRL_23: 599 case RT5682_HP_IMP_SENS_CTRL_24: 600 case RT5682_HP_IMP_SENS_CTRL_25: 601 case RT5682_HP_IMP_SENS_CTRL_26: 602 case RT5682_HP_IMP_SENS_CTRL_27: 603 case RT5682_HP_IMP_SENS_CTRL_28: 604 case RT5682_HP_IMP_SENS_CTRL_29: 605 case RT5682_HP_IMP_SENS_CTRL_30: 606 case RT5682_HP_IMP_SENS_CTRL_31: 607 case RT5682_HP_IMP_SENS_CTRL_32: 608 case RT5682_HP_IMP_SENS_CTRL_33: 609 case RT5682_HP_IMP_SENS_CTRL_34: 610 case RT5682_HP_IMP_SENS_CTRL_35: 611 case RT5682_HP_IMP_SENS_CTRL_36: 612 case RT5682_HP_IMP_SENS_CTRL_37: 613 case RT5682_HP_IMP_SENS_CTRL_38: 614 case RT5682_HP_IMP_SENS_CTRL_39: 615 case RT5682_HP_IMP_SENS_CTRL_40: 616 case RT5682_HP_IMP_SENS_CTRL_41: 617 case RT5682_HP_IMP_SENS_CTRL_42: 618 case RT5682_HP_IMP_SENS_CTRL_43: 619 case RT5682_HP_LOGIC_CTRL_1: 620 case RT5682_HP_LOGIC_CTRL_2: 621 case RT5682_HP_LOGIC_CTRL_3: 622 case RT5682_HP_CALIB_CTRL_1: 623 case RT5682_HP_CALIB_CTRL_2: 624 case RT5682_HP_CALIB_CTRL_3: 625 case RT5682_HP_CALIB_CTRL_4: 626 case RT5682_HP_CALIB_CTRL_5: 627 case RT5682_HP_CALIB_CTRL_6: 628 case RT5682_HP_CALIB_CTRL_7: 629 case RT5682_HP_CALIB_CTRL_9: 630 case RT5682_HP_CALIB_CTRL_10: 631 case RT5682_HP_CALIB_CTRL_11: 632 case RT5682_HP_CALIB_STA_1: 633 case RT5682_HP_CALIB_STA_2: 634 case RT5682_HP_CALIB_STA_3: 635 case RT5682_HP_CALIB_STA_4: 636 case RT5682_HP_CALIB_STA_5: 637 case RT5682_HP_CALIB_STA_6: 638 case RT5682_HP_CALIB_STA_7: 639 case RT5682_HP_CALIB_STA_8: 640 case RT5682_HP_CALIB_STA_9: 641 case RT5682_HP_CALIB_STA_10: 642 case RT5682_HP_CALIB_STA_11: 643 case RT5682_SAR_IL_CMD_1: 644 case RT5682_SAR_IL_CMD_2: 645 case RT5682_SAR_IL_CMD_3: 646 case RT5682_SAR_IL_CMD_4: 647 case RT5682_SAR_IL_CMD_5: 648 case RT5682_SAR_IL_CMD_6: 649 case RT5682_SAR_IL_CMD_7: 650 case RT5682_SAR_IL_CMD_8: 651 case RT5682_SAR_IL_CMD_9: 652 case RT5682_SAR_IL_CMD_10: 653 case RT5682_SAR_IL_CMD_11: 654 case RT5682_SAR_IL_CMD_12: 655 case RT5682_SAR_IL_CMD_13: 656 case RT5682_EFUSE_CTRL_1: 657 case RT5682_EFUSE_CTRL_2: 658 case RT5682_EFUSE_CTRL_3: 659 case RT5682_EFUSE_CTRL_4: 660 case RT5682_EFUSE_CTRL_5: 661 case RT5682_EFUSE_CTRL_6: 662 case RT5682_EFUSE_CTRL_7: 663 case RT5682_EFUSE_CTRL_8: 664 case RT5682_EFUSE_CTRL_9: 665 case RT5682_EFUSE_CTRL_10: 666 case RT5682_EFUSE_CTRL_11: 667 case RT5682_JD_TOP_VC_VTRL: 668 case RT5682_DRC1_CTRL_0: 669 case RT5682_DRC1_CTRL_1: 670 case RT5682_DRC1_CTRL_2: 671 case RT5682_DRC1_CTRL_3: 672 case RT5682_DRC1_CTRL_4: 673 case RT5682_DRC1_CTRL_5: 674 case RT5682_DRC1_CTRL_6: 675 case RT5682_DRC1_HARD_LMT_CTRL_1: 676 case RT5682_DRC1_HARD_LMT_CTRL_2: 677 case RT5682_DRC1_PRIV_1: 678 case RT5682_DRC1_PRIV_2: 679 case RT5682_DRC1_PRIV_3: 680 case RT5682_DRC1_PRIV_4: 681 case RT5682_DRC1_PRIV_5: 682 case RT5682_DRC1_PRIV_6: 683 case RT5682_DRC1_PRIV_7: 684 case RT5682_DRC1_PRIV_8: 685 case RT5682_EQ_AUTO_RCV_CTRL1: 686 case RT5682_EQ_AUTO_RCV_CTRL2: 687 case RT5682_EQ_AUTO_RCV_CTRL3: 688 case RT5682_EQ_AUTO_RCV_CTRL4: 689 case RT5682_EQ_AUTO_RCV_CTRL5: 690 case RT5682_EQ_AUTO_RCV_CTRL6: 691 case RT5682_EQ_AUTO_RCV_CTRL7: 692 case RT5682_EQ_AUTO_RCV_CTRL8: 693 case RT5682_EQ_AUTO_RCV_CTRL9: 694 case RT5682_EQ_AUTO_RCV_CTRL10: 695 case RT5682_EQ_AUTO_RCV_CTRL11: 696 case RT5682_EQ_AUTO_RCV_CTRL12: 697 case RT5682_EQ_AUTO_RCV_CTRL13: 698 case RT5682_ADC_L_EQ_LPF1_A1: 699 case RT5682_R_EQ_LPF1_A1: 700 case RT5682_L_EQ_LPF1_H0: 701 case RT5682_R_EQ_LPF1_H0: 702 case RT5682_L_EQ_BPF1_A1: 703 case RT5682_R_EQ_BPF1_A1: 704 case RT5682_L_EQ_BPF1_A2: 705 case RT5682_R_EQ_BPF1_A2: 706 case RT5682_L_EQ_BPF1_H0: 707 case RT5682_R_EQ_BPF1_H0: 708 case RT5682_L_EQ_BPF2_A1: 709 case RT5682_R_EQ_BPF2_A1: 710 case RT5682_L_EQ_BPF2_A2: 711 case RT5682_R_EQ_BPF2_A2: 712 case RT5682_L_EQ_BPF2_H0: 713 case RT5682_R_EQ_BPF2_H0: 714 case RT5682_L_EQ_BPF3_A1: 715 case RT5682_R_EQ_BPF3_A1: 716 case RT5682_L_EQ_BPF3_A2: 717 case RT5682_R_EQ_BPF3_A2: 718 case RT5682_L_EQ_BPF3_H0: 719 case RT5682_R_EQ_BPF3_H0: 720 case RT5682_L_EQ_BPF4_A1: 721 case RT5682_R_EQ_BPF4_A1: 722 case RT5682_L_EQ_BPF4_A2: 723 case RT5682_R_EQ_BPF4_A2: 724 case RT5682_L_EQ_BPF4_H0: 725 case RT5682_R_EQ_BPF4_H0: 726 case RT5682_L_EQ_HPF1_A1: 727 case RT5682_R_EQ_HPF1_A1: 728 case RT5682_L_EQ_HPF1_H0: 729 case RT5682_R_EQ_HPF1_H0: 730 case RT5682_L_EQ_PRE_VOL: 731 case RT5682_R_EQ_PRE_VOL: 732 case RT5682_L_EQ_POST_VOL: 733 case RT5682_R_EQ_POST_VOL: 734 case RT5682_I2C_MODE: 735 return true; 736 default: 737 return false; 738 } 739 } 740 EXPORT_SYMBOL_GPL(rt5682_readable_register); 741 742 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 743 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 744 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 745 746 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 747 static const DECLARE_TLV_DB_RANGE(bst_tlv, 748 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 749 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 750 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 751 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 752 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 753 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 754 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 755 ); 756 757 /* Interface data select */ 758 static const char * const rt5682_data_select[] = { 759 "L/R", "R/L", "L/L", "R/R" 760 }; 761 762 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum, 763 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select); 764 765 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum, 766 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select); 767 768 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum, 769 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select); 770 771 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum, 772 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select); 773 774 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum, 775 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select); 776 777 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux = 778 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum); 779 780 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux = 781 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum); 782 783 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux = 784 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum); 785 786 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux = 787 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum); 788 789 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux = 790 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum); 791 792 static const char * const rt5682_dac_select[] = { 793 "IF1", "SOUND" 794 }; 795 796 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum, 797 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select); 798 799 static const struct snd_kcontrol_new rt5682_dac_l_mux = 800 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum); 801 802 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum, 803 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select); 804 805 static const struct snd_kcontrol_new rt5682_dac_r_mux = 806 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum); 807 808 void rt5682_reset(struct rt5682_priv *rt5682) 809 { 810 regmap_write(rt5682->regmap, RT5682_RESET, 0); 811 if (!rt5682->is_sdw) 812 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); 813 } 814 EXPORT_SYMBOL_GPL(rt5682_reset); 815 816 /** 817 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters 818 * @component: SoC audio component device. 819 * @filter_mask: mask of filters. 820 * @clk_src: clock source 821 * 822 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can 823 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 824 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 825 * ASRC function will track i2s clock and generate a corresponding system clock 826 * for codec. This function provides an API to select the clock source for a 827 * set of filters specified by the mask. And the component driver will turn on 828 * ASRC for these filters if ASRC is selected as their clock source. 829 */ 830 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 831 unsigned int filter_mask, unsigned int clk_src) 832 { 833 switch (clk_src) { 834 case RT5682_CLK_SEL_SYS: 835 case RT5682_CLK_SEL_I2S1_ASRC: 836 case RT5682_CLK_SEL_I2S2_ASRC: 837 break; 838 839 default: 840 return -EINVAL; 841 } 842 843 if (filter_mask & RT5682_DA_STEREO1_FILTER) { 844 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2, 845 RT5682_FILTER_CLK_SEL_MASK, 846 clk_src << RT5682_FILTER_CLK_SEL_SFT); 847 } 848 849 if (filter_mask & RT5682_AD_STEREO1_FILTER) { 850 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3, 851 RT5682_FILTER_CLK_SEL_MASK, 852 clk_src << RT5682_FILTER_CLK_SEL_SFT); 853 } 854 855 return 0; 856 } 857 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src); 858 859 static int rt5682_button_detect(struct snd_soc_component *component) 860 { 861 int btn_type, val; 862 863 val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1); 864 btn_type = val & 0xfff0; 865 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); 866 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); 867 snd_soc_component_update_bits(component, 868 RT5682_SAR_IL_CMD_2, 0x10, 0x10); 869 870 return btn_type; 871 } 872 873 static void rt5682_enable_push_button_irq(struct snd_soc_component *component, 874 bool enable) 875 { 876 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 877 878 if (enable) { 879 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 880 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 881 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 882 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 883 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040); 884 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 885 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 886 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 887 if (rt5682->is_sdw) 888 snd_soc_component_update_bits(component, 889 RT5682_IRQ_CTRL_3, 890 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK, 891 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL); 892 else 893 snd_soc_component_update_bits(component, 894 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK, 895 RT5682_IL_IRQ_EN); 896 } else { 897 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 898 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 899 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 900 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 901 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 902 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 903 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 904 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 905 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 906 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 907 } 908 } 909 910 /** 911 * rt5682_headset_detect - Detect headset. 912 * @component: SoC audio component device. 913 * @jack_insert: Jack insert or not. 914 * 915 * Detect whether is headset or not when jack inserted. 916 * 917 * Returns detect status. 918 */ 919 int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert) 920 { 921 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 922 struct snd_soc_dapm_context *dapm = &component->dapm; 923 unsigned int val, count; 924 925 if (jack_insert) { 926 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 927 RT5682_PWR_VREF2 | RT5682_PWR_MB, 928 RT5682_PWR_VREF2 | RT5682_PWR_MB); 929 snd_soc_component_update_bits(component, 930 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 931 usleep_range(15000, 20000); 932 snd_soc_component_update_bits(component, 933 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2); 934 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 935 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 936 snd_soc_component_update_bits(component, 937 RT5682_HP_CHARGE_PUMP_1, 938 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0); 939 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 940 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 941 942 count = 0; 943 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2) 944 & RT5682_JACK_TYPE_MASK; 945 while (val == 0 && count < 50) { 946 usleep_range(10000, 15000); 947 val = snd_soc_component_read(component, 948 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 949 count++; 950 } 951 952 switch (val) { 953 case 0x1: 954 case 0x2: 955 rt5682->jack_type = SND_JACK_HEADSET; 956 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 957 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN); 958 rt5682_enable_push_button_irq(component, true); 959 break; 960 default: 961 rt5682->jack_type = SND_JACK_HEADPHONE; 962 break; 963 } 964 965 snd_soc_component_update_bits(component, 966 RT5682_HP_CHARGE_PUMP_1, 967 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 968 RT5682_OSW_L_EN | RT5682_OSW_R_EN); 969 snd_soc_component_update_bits(component, RT5682_MICBIAS_2, 970 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 971 RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU); 972 } else { 973 rt5682_enable_push_button_irq(component, false); 974 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 975 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 976 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS")) 977 snd_soc_component_update_bits(component, 978 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0); 979 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2")) 980 snd_soc_component_update_bits(component, 981 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 982 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 983 RT5682_PWR_CBJ, 0); 984 snd_soc_component_update_bits(component, RT5682_MICBIAS_2, 985 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 986 RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD); 987 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 988 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS); 989 990 rt5682->jack_type = 0; 991 } 992 993 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); 994 return rt5682->jack_type; 995 } 996 EXPORT_SYMBOL_GPL(rt5682_headset_detect); 997 998 static int rt5682_set_jack_detect(struct snd_soc_component *component, 999 struct snd_soc_jack *hs_jack, void *data) 1000 { 1001 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1002 1003 rt5682->hs_jack = hs_jack; 1004 1005 if (!hs_jack) { 1006 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1007 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1008 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1009 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1010 cancel_delayed_work_sync(&rt5682->jack_detect_work); 1011 1012 return 0; 1013 } 1014 1015 if (!rt5682->is_sdw) { 1016 switch (rt5682->pdata.jd_src) { 1017 case RT5682_JD1: 1018 snd_soc_component_update_bits(component, 1019 RT5682_CBJ_CTRL_5, 0x0700, 0x0600); 1020 snd_soc_component_update_bits(component, 1021 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC, 1022 RT5682_EXT_JD_SRC_MANUAL); 1023 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 1024 0xd142); 1025 snd_soc_component_update_bits(component, 1026 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN, 1027 RT5682_CBJ_IN_BUF_EN); 1028 snd_soc_component_update_bits(component, 1029 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK, 1030 RT5682_SAR_POW_EN); 1031 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 1032 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ); 1033 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1034 RT5682_POW_IRQ | RT5682_POW_JDH | 1035 RT5682_POW_ANA, RT5682_POW_IRQ | 1036 RT5682_POW_JDH | RT5682_POW_ANA); 1037 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 1038 RT5682_PWR_JDH, RT5682_PWR_JDH); 1039 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1040 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK, 1041 RT5682_JD1_EN | RT5682_JD1_POL_NOR); 1042 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4, 1043 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1044 rt5682->pdata.btndet_delay)); 1045 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5, 1046 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1047 rt5682->pdata.btndet_delay)); 1048 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6, 1049 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1050 rt5682->pdata.btndet_delay)); 1051 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7, 1052 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1053 rt5682->pdata.btndet_delay)); 1054 mod_delayed_work(system_power_efficient_wq, 1055 &rt5682->jack_detect_work, 1056 msecs_to_jiffies(250)); 1057 break; 1058 1059 case RT5682_JD_NULL: 1060 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1061 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1062 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1063 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1064 break; 1065 1066 default: 1067 dev_warn(component->dev, "Wrong JD source\n"); 1068 break; 1069 } 1070 } 1071 1072 return 0; 1073 } 1074 1075 void rt5682_jack_detect_handler(struct work_struct *work) 1076 { 1077 struct rt5682_priv *rt5682 = 1078 container_of(work, struct rt5682_priv, jack_detect_work.work); 1079 int val, btn_type; 1080 1081 while (!rt5682->component) 1082 usleep_range(10000, 15000); 1083 1084 while (!rt5682->component->card->instantiated) 1085 usleep_range(10000, 15000); 1086 1087 mutex_lock(&rt5682->calibrate_mutex); 1088 1089 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL) 1090 & RT5682_JDH_RS_MASK; 1091 if (!val) { 1092 /* jack in */ 1093 if (rt5682->jack_type == 0) { 1094 /* jack was out, report jack type */ 1095 rt5682->jack_type = 1096 rt5682_headset_detect(rt5682->component, 1); 1097 } else if ((rt5682->jack_type & SND_JACK_HEADSET) == 1098 SND_JACK_HEADSET) { 1099 /* jack is already in, report button event */ 1100 rt5682->jack_type = SND_JACK_HEADSET; 1101 btn_type = rt5682_button_detect(rt5682->component); 1102 /** 1103 * rt5682 can report three kinds of button behavior, 1104 * one click, double click and hold. However, 1105 * currently we will report button pressed/released 1106 * event. So all the three button behaviors are 1107 * treated as button pressed. 1108 */ 1109 switch (btn_type) { 1110 case 0x8000: 1111 case 0x4000: 1112 case 0x2000: 1113 rt5682->jack_type |= SND_JACK_BTN_0; 1114 break; 1115 case 0x1000: 1116 case 0x0800: 1117 case 0x0400: 1118 rt5682->jack_type |= SND_JACK_BTN_1; 1119 break; 1120 case 0x0200: 1121 case 0x0100: 1122 case 0x0080: 1123 rt5682->jack_type |= SND_JACK_BTN_2; 1124 break; 1125 case 0x0040: 1126 case 0x0020: 1127 case 0x0010: 1128 rt5682->jack_type |= SND_JACK_BTN_3; 1129 break; 1130 case 0x0000: /* unpressed */ 1131 break; 1132 default: 1133 dev_err(rt5682->component->dev, 1134 "Unexpected button code 0x%04x\n", 1135 btn_type); 1136 break; 1137 } 1138 } 1139 } else { 1140 /* jack out */ 1141 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 1142 } 1143 1144 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 1145 SND_JACK_HEADSET | 1146 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1147 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1148 1149 if (!rt5682->is_sdw) { 1150 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1151 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1152 schedule_delayed_work(&rt5682->jd_check_work, 0); 1153 else 1154 cancel_delayed_work_sync(&rt5682->jd_check_work); 1155 } 1156 1157 mutex_unlock(&rt5682->calibrate_mutex); 1158 } 1159 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler); 1160 1161 static const struct snd_kcontrol_new rt5682_snd_controls[] = { 1162 /* DAC Digital Volume */ 1163 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL, 1164 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 1165 1166 /* IN Boost Volume */ 1167 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL, 1168 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv), 1169 1170 /* ADC Digital Volume Control */ 1171 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL, 1172 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1), 1173 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL, 1174 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1175 1176 /* ADC Boost Volume Control */ 1177 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST, 1178 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT, 1179 3, 0, adc_bst_tlv), 1180 }; 1181 1182 static int rt5682_div_sel(struct rt5682_priv *rt5682, 1183 int target, const int div[], int size) 1184 { 1185 int i; 1186 1187 if (rt5682->sysclk < target) { 1188 dev_err(rt5682->component->dev, 1189 "sysclk rate %d is too low\n", rt5682->sysclk); 1190 return 0; 1191 } 1192 1193 for (i = 0; i < size - 1; i++) { 1194 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]); 1195 if (target * div[i] == rt5682->sysclk) 1196 return i; 1197 if (target * div[i + 1] > rt5682->sysclk) { 1198 dev_dbg(rt5682->component->dev, 1199 "can't find div for sysclk %d\n", 1200 rt5682->sysclk); 1201 return i; 1202 } 1203 } 1204 1205 if (target * div[i] < rt5682->sysclk) 1206 dev_err(rt5682->component->dev, 1207 "sysclk rate %d is too high\n", rt5682->sysclk); 1208 1209 return size - 1; 1210 } 1211 1212 /** 1213 * set_dmic_clk - Set parameter of dmic. 1214 * 1215 * @w: DAPM widget. 1216 * @kcontrol: The kcontrol of this widget. 1217 * @event: Event id. 1218 * 1219 * Choose dmic clock between 1MHz and 3MHz. 1220 * It is better for clock to approximate 3MHz. 1221 */ 1222 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1223 struct snd_kcontrol *kcontrol, int event) 1224 { 1225 struct snd_soc_component *component = 1226 snd_soc_dapm_to_component(w->dapm); 1227 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1228 int idx = -EINVAL, dmic_clk_rate = 3072000; 1229 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1230 1231 if (rt5682->pdata.dmic_clk_rate) 1232 dmic_clk_rate = rt5682->pdata.dmic_clk_rate; 1233 1234 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div)); 1235 1236 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1, 1237 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT); 1238 1239 return 0; 1240 } 1241 1242 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1243 struct snd_kcontrol *kcontrol, int event) 1244 { 1245 struct snd_soc_component *component = 1246 snd_soc_dapm_to_component(w->dapm); 1247 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1248 int ref, val, reg, idx = -EINVAL; 1249 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1250 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1251 1252 if (rt5682->is_sdw) 1253 return 0; 1254 1255 val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) & 1256 RT5682_GP4_PIN_MASK; 1257 if (w->shift == RT5682_PWR_ADC_S1F_BIT && 1258 val == RT5682_GP4_PIN_ADCDAT2) 1259 ref = 256 * rt5682->lrck[RT5682_AIF2]; 1260 else 1261 ref = 256 * rt5682->lrck[RT5682_AIF1]; 1262 1263 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f)); 1264 1265 if (w->shift == RT5682_PWR_ADC_S1F_BIT) 1266 reg = RT5682_PLL_TRACK_3; 1267 else 1268 reg = RT5682_PLL_TRACK_2; 1269 1270 snd_soc_component_update_bits(component, reg, 1271 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT); 1272 1273 /* select over sample rate */ 1274 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1275 if (rt5682->sysclk <= 12288000 * div_o[idx]) 1276 break; 1277 } 1278 1279 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 1280 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK, 1281 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT)); 1282 1283 return 0; 1284 } 1285 1286 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1287 struct snd_soc_dapm_widget *sink) 1288 { 1289 unsigned int val; 1290 struct snd_soc_component *component = 1291 snd_soc_dapm_to_component(w->dapm); 1292 1293 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1294 val &= RT5682_SCLK_SRC_MASK; 1295 if (val == RT5682_SCLK_SRC_PLL1) 1296 return 1; 1297 else 1298 return 0; 1299 } 1300 1301 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w, 1302 struct snd_soc_dapm_widget *sink) 1303 { 1304 unsigned int val; 1305 struct snd_soc_component *component = 1306 snd_soc_dapm_to_component(w->dapm); 1307 1308 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1309 val &= RT5682_SCLK_SRC_MASK; 1310 if (val == RT5682_SCLK_SRC_PLL2) 1311 return 1; 1312 else 1313 return 0; 1314 } 1315 1316 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1317 struct snd_soc_dapm_widget *sink) 1318 { 1319 unsigned int reg, shift, val; 1320 struct snd_soc_component *component = 1321 snd_soc_dapm_to_component(w->dapm); 1322 1323 switch (w->shift) { 1324 case RT5682_ADC_STO1_ASRC_SFT: 1325 reg = RT5682_PLL_TRACK_3; 1326 shift = RT5682_FILTER_CLK_SEL_SFT; 1327 break; 1328 case RT5682_DAC_STO1_ASRC_SFT: 1329 reg = RT5682_PLL_TRACK_2; 1330 shift = RT5682_FILTER_CLK_SEL_SFT; 1331 break; 1332 default: 1333 return 0; 1334 } 1335 1336 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 1337 switch (val) { 1338 case RT5682_CLK_SEL_I2S1_ASRC: 1339 case RT5682_CLK_SEL_I2S2_ASRC: 1340 return 1; 1341 default: 1342 return 0; 1343 } 1344 } 1345 1346 /* Digital Mixer */ 1347 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = { 1348 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1349 RT5682_M_STO1_ADC_L1_SFT, 1, 1), 1350 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1351 RT5682_M_STO1_ADC_L2_SFT, 1, 1), 1352 }; 1353 1354 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = { 1355 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1356 RT5682_M_STO1_ADC_R1_SFT, 1, 1), 1357 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1358 RT5682_M_STO1_ADC_R2_SFT, 1, 1), 1359 }; 1360 1361 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = { 1362 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1363 RT5682_M_ADCMIX_L_SFT, 1, 1), 1364 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1365 RT5682_M_DAC1_L_SFT, 1, 1), 1366 }; 1367 1368 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = { 1369 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1370 RT5682_M_ADCMIX_R_SFT, 1, 1), 1371 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1372 RT5682_M_DAC1_R_SFT, 1, 1), 1373 }; 1374 1375 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = { 1376 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1377 RT5682_M_DAC_L1_STO_L_SFT, 1, 1), 1378 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1379 RT5682_M_DAC_R1_STO_L_SFT, 1, 1), 1380 }; 1381 1382 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = { 1383 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1384 RT5682_M_DAC_L1_STO_R_SFT, 1, 1), 1385 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1386 RT5682_M_DAC_R1_STO_R_SFT, 1, 1), 1387 }; 1388 1389 /* Analog Input Mixer */ 1390 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = { 1391 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER, 1392 RT5682_M_CBJ_RM1_L_SFT, 1, 1), 1393 }; 1394 1395 /* STO1 ADC1 Source */ 1396 /* MX-26 [13] [5] */ 1397 static const char * const rt5682_sto1_adc1_src[] = { 1398 "DAC MIX", "ADC" 1399 }; 1400 1401 static SOC_ENUM_SINGLE_DECL( 1402 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER, 1403 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src); 1404 1405 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux = 1406 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum); 1407 1408 static SOC_ENUM_SINGLE_DECL( 1409 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER, 1410 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src); 1411 1412 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux = 1413 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum); 1414 1415 /* STO1 ADC Source */ 1416 /* MX-26 [11:10] [3:2] */ 1417 static const char * const rt5682_sto1_adc_src[] = { 1418 "ADC1 L", "ADC1 R" 1419 }; 1420 1421 static SOC_ENUM_SINGLE_DECL( 1422 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER, 1423 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src); 1424 1425 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux = 1426 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum); 1427 1428 static SOC_ENUM_SINGLE_DECL( 1429 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER, 1430 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src); 1431 1432 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux = 1433 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum); 1434 1435 /* STO1 ADC2 Source */ 1436 /* MX-26 [12] [4] */ 1437 static const char * const rt5682_sto1_adc2_src[] = { 1438 "DAC MIX", "DMIC" 1439 }; 1440 1441 static SOC_ENUM_SINGLE_DECL( 1442 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER, 1443 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src); 1444 1445 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux = 1446 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum); 1447 1448 static SOC_ENUM_SINGLE_DECL( 1449 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER, 1450 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src); 1451 1452 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux = 1453 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum); 1454 1455 /* MX-79 [6:4] I2S1 ADC data location */ 1456 static const unsigned int rt5682_if1_adc_slot_values[] = { 1457 0, 1458 2, 1459 4, 1460 6, 1461 }; 1462 1463 static const char * const rt5682_if1_adc_slot_src[] = { 1464 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1465 }; 1466 1467 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum, 1468 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK, 1469 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values); 1470 1471 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux = 1472 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum); 1473 1474 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1475 /* MX-2B [4], MX-2B [0]*/ 1476 static const char * const rt5682_alg_dac1_src[] = { 1477 "Stereo1 DAC Mixer", "DAC1" 1478 }; 1479 1480 static SOC_ENUM_SINGLE_DECL( 1481 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX, 1482 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src); 1483 1484 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux = 1485 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum); 1486 1487 static SOC_ENUM_SINGLE_DECL( 1488 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX, 1489 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src); 1490 1491 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux = 1492 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum); 1493 1494 /* Out Switch */ 1495 static const struct snd_kcontrol_new hpol_switch = 1496 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1497 RT5682_L_MUTE_SFT, 1, 1); 1498 static const struct snd_kcontrol_new hpor_switch = 1499 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1500 RT5682_R_MUTE_SFT, 1, 1); 1501 1502 static int rt5682_hp_event(struct snd_soc_dapm_widget *w, 1503 struct snd_kcontrol *kcontrol, int event) 1504 { 1505 struct snd_soc_component *component = 1506 snd_soc_dapm_to_component(w->dapm); 1507 1508 switch (event) { 1509 case SND_SOC_DAPM_PRE_PMU: 1510 snd_soc_component_write(component, 1511 RT5682_HP_LOGIC_CTRL_2, 0x0012); 1512 snd_soc_component_write(component, 1513 RT5682_HP_CTRL_2, 0x6000); 1514 snd_soc_component_update_bits(component, 1515 RT5682_DEPOP_1, 0x60, 0x60); 1516 snd_soc_component_update_bits(component, 1517 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080); 1518 break; 1519 1520 case SND_SOC_DAPM_POST_PMD: 1521 snd_soc_component_update_bits(component, 1522 RT5682_DEPOP_1, 0x60, 0x0); 1523 snd_soc_component_write(component, 1524 RT5682_HP_CTRL_2, 0x0000); 1525 snd_soc_component_update_bits(component, 1526 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000); 1527 break; 1528 } 1529 1530 return 0; 1531 } 1532 1533 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1534 struct snd_kcontrol *kcontrol, int event) 1535 { 1536 struct snd_soc_component *component = 1537 snd_soc_dapm_to_component(w->dapm); 1538 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1539 unsigned int delay = 50, val; 1540 1541 if (rt5682->pdata.dmic_delay) 1542 delay = rt5682->pdata.dmic_delay; 1543 1544 switch (event) { 1545 case SND_SOC_DAPM_POST_PMU: 1546 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1547 val &= RT5682_SCLK_SRC_MASK; 1548 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2) 1549 snd_soc_component_update_bits(component, 1550 RT5682_PWR_ANLG_1, 1551 RT5682_PWR_VREF2 | RT5682_PWR_MB, 1552 RT5682_PWR_VREF2 | RT5682_PWR_MB); 1553 1554 /*Add delay to avoid pop noise*/ 1555 msleep(delay); 1556 break; 1557 1558 case SND_SOC_DAPM_POST_PMD: 1559 if (!rt5682->jack_type) { 1560 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS")) 1561 snd_soc_component_update_bits(component, 1562 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0); 1563 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2")) 1564 snd_soc_component_update_bits(component, 1565 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 1566 } 1567 break; 1568 } 1569 1570 return 0; 1571 } 1572 1573 static int rt5682_set_verf(struct snd_soc_dapm_widget *w, 1574 struct snd_kcontrol *kcontrol, int event) 1575 { 1576 struct snd_soc_component *component = 1577 snd_soc_dapm_to_component(w->dapm); 1578 1579 switch (event) { 1580 case SND_SOC_DAPM_PRE_PMU: 1581 switch (w->shift) { 1582 case RT5682_PWR_VREF1_BIT: 1583 snd_soc_component_update_bits(component, 1584 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0); 1585 break; 1586 1587 case RT5682_PWR_VREF2_BIT: 1588 snd_soc_component_update_bits(component, 1589 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1590 break; 1591 } 1592 break; 1593 1594 case SND_SOC_DAPM_POST_PMU: 1595 usleep_range(15000, 20000); 1596 switch (w->shift) { 1597 case RT5682_PWR_VREF1_BIT: 1598 snd_soc_component_update_bits(component, 1599 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 1600 RT5682_PWR_FV1); 1601 break; 1602 1603 case RT5682_PWR_VREF2_BIT: 1604 snd_soc_component_update_bits(component, 1605 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 1606 RT5682_PWR_FV2); 1607 break; 1608 } 1609 break; 1610 } 1611 1612 return 0; 1613 } 1614 1615 static const unsigned int rt5682_adcdat_pin_values[] = { 1616 1, 1617 3, 1618 }; 1619 1620 static const char * const rt5682_adcdat_pin_select[] = { 1621 "ADCDAT1", 1622 "ADCDAT2", 1623 }; 1624 1625 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum, 1626 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK, 1627 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values); 1628 1629 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl = 1630 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum); 1631 1632 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { 1633 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT, 1634 0, NULL, 0), 1635 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT, 1636 0, NULL, 0), 1637 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT, 1638 0, NULL, 0), 1639 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT, 1640 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1641 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0, 1642 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1643 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0), 1644 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0), 1645 1646 /* ASRC */ 1647 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1648 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1649 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1650 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1651 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1, 1652 RT5682_AD_ASRC_SFT, 0, NULL, 0), 1653 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1, 1654 RT5682_DA_ASRC_SFT, 0, NULL, 0), 1655 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1, 1656 RT5682_DMIC_ASRC_SFT, 0, NULL, 0), 1657 1658 /* Input Side */ 1659 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT, 1660 0, NULL, 0), 1661 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT, 1662 0, NULL, 0), 1663 1664 /* Input Lines */ 1665 SND_SOC_DAPM_INPUT("DMIC L1"), 1666 SND_SOC_DAPM_INPUT("DMIC R1"), 1667 1668 SND_SOC_DAPM_INPUT("IN1P"), 1669 1670 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1671 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1672 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1, 1673 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, 1674 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1675 1676 /* Boost */ 1677 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1678 0, 0, NULL, 0), 1679 1680 /* REC Mixer */ 1681 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix, 1682 ARRAY_SIZE(rt5682_rec1_l_mix)), 1683 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2, 1684 RT5682_PWR_RM1_L_BIT, 0, NULL, 0), 1685 1686 /* ADCs */ 1687 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1688 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1689 1690 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1, 1691 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0), 1692 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1, 1693 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0), 1694 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC, 1695 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0), 1696 1697 /* ADC Mux */ 1698 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1699 &rt5682_sto1_adc1l_mux), 1700 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1701 &rt5682_sto1_adc1r_mux), 1702 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1703 &rt5682_sto1_adc2l_mux), 1704 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1705 &rt5682_sto1_adc2r_mux), 1706 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1707 &rt5682_sto1_adcl_mux), 1708 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1709 &rt5682_sto1_adcr_mux), 1710 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1711 &rt5682_if1_adc_slot_mux), 1712 1713 /* ADC Mixer */ 1714 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2, 1715 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1716 SND_SOC_DAPM_PRE_PMU), 1717 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL, 1718 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix, 1719 ARRAY_SIZE(rt5682_sto1_adc_l_mix)), 1720 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL, 1721 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix, 1722 ARRAY_SIZE(rt5682_sto1_adc_r_mix)), 1723 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1, 1724 14, 1, NULL, 0), 1725 1726 /* ADC PGA */ 1727 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1728 1729 /* Digital Interface */ 1730 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT, 1731 0, NULL, 0), 1732 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT, 1733 0, NULL, 0), 1734 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1735 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1736 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1737 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 1738 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 1739 1740 /* Digital Interface Select */ 1741 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1742 &rt5682_if1_01_adc_swap_mux), 1743 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1744 &rt5682_if1_23_adc_swap_mux), 1745 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1746 &rt5682_if1_45_adc_swap_mux), 1747 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1748 &rt5682_if1_67_adc_swap_mux), 1749 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1750 &rt5682_if2_adc_swap_mux), 1751 1752 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1753 &rt5682_adcdat_pin_ctrl), 1754 1755 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, 1756 &rt5682_dac_l_mux), 1757 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, 1758 &rt5682_dac_r_mux), 1759 1760 /* Audio Interface */ 1761 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1762 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1), 1763 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1764 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1), 1765 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1766 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0), 1767 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0), 1768 1769 /* Output Side */ 1770 /* DAC mixer before sound effect */ 1771 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1772 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)), 1773 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1774 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)), 1775 1776 /* DAC channel Mux */ 1777 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1778 &rt5682_alg_dac_l1_mux), 1779 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1780 &rt5682_alg_dac_r1_mux), 1781 1782 /* DAC Mixer */ 1783 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2, 1784 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1785 SND_SOC_DAPM_PRE_PMU), 1786 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1787 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)), 1788 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1789 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)), 1790 1791 /* DACs */ 1792 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1, 1793 RT5682_PWR_DAC_L1_BIT, 0), 1794 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1, 1795 RT5682_PWR_DAC_R1_BIT, 0), 1796 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC, 1797 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0), 1798 1799 /* HPO */ 1800 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event, 1801 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1802 1803 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1, 1804 RT5682_PWR_HA_L_BIT, 0, NULL, 0), 1805 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1, 1806 RT5682_PWR_HA_R_BIT, 0, NULL, 0), 1807 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1, 1808 RT5682_PUMP_EN_SFT, 0, NULL, 0), 1809 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1, 1810 RT5682_CAPLESS_EN_SFT, 0, NULL, 0), 1811 1812 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1813 &hpol_switch), 1814 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1815 &hpor_switch), 1816 1817 /* CLK DET */ 1818 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET, 1819 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0), 1820 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET, 1821 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0), 1822 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET, 1823 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0), 1824 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET, 1825 RT5682_POW_CLK_DET_SFT, 0, NULL, 0), 1826 1827 /* Output Lines */ 1828 SND_SOC_DAPM_OUTPUT("HPOL"), 1829 SND_SOC_DAPM_OUTPUT("HPOR"), 1830 }; 1831 1832 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { 1833 /*PLL*/ 1834 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1835 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1836 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1837 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1838 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1839 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1840 1841 /*ASRC*/ 1842 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1843 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1844 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1845 {"ADC STO1 ASRC", NULL, "DA ASRC"}, 1846 {"ADC STO1 ASRC", NULL, "CLKDET"}, 1847 {"DAC STO1 ASRC", NULL, "AD ASRC"}, 1848 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1849 {"DAC STO1 ASRC", NULL, "CLKDET"}, 1850 1851 /*Vref*/ 1852 {"MICBIAS1", NULL, "Vref1"}, 1853 {"MICBIAS2", NULL, "Vref1"}, 1854 1855 {"CLKDET SYS", NULL, "CLKDET"}, 1856 1857 {"IN1P", NULL, "LDO2"}, 1858 1859 {"BST1 CBJ", NULL, "IN1P"}, 1860 1861 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1862 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1863 1864 {"ADC1 L", NULL, "RECMIX1L"}, 1865 {"ADC1 L", NULL, "ADC1 L Power"}, 1866 {"ADC1 L", NULL, "ADC1 clock"}, 1867 1868 {"DMIC L1", NULL, "DMIC CLK"}, 1869 {"DMIC L1", NULL, "DMIC1 Power"}, 1870 {"DMIC R1", NULL, "DMIC CLK"}, 1871 {"DMIC R1", NULL, "DMIC1 Power"}, 1872 {"DMIC CLK", NULL, "DMIC ASRC"}, 1873 1874 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1875 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1876 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1877 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1878 1879 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1880 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1881 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1882 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1883 1884 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1885 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1886 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1887 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1888 1889 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1890 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1891 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1892 1893 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1894 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1895 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1896 1897 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"}, 1898 1899 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1900 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1901 1902 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1903 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1904 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1905 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1906 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1907 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1908 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1909 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1910 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1911 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1912 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1913 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1914 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1915 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1916 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1917 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1918 1919 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1920 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1921 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1922 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1923 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1924 {"AIF1TX", NULL, "I2S1"}, 1925 {"AIF1TX", NULL, "ADCDAT Mux"}, 1926 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1927 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1928 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1929 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1930 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1931 {"AIF2TX", NULL, "ADCDAT Mux"}, 1932 1933 {"SDWTX", NULL, "PLL2B"}, 1934 {"SDWTX", NULL, "PLL2F"}, 1935 {"SDWTX", NULL, "ADCDAT Mux"}, 1936 1937 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1938 {"IF1 DAC1 L", NULL, "I2S1"}, 1939 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1940 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1941 {"IF1 DAC1 R", NULL, "I2S1"}, 1942 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1943 1944 {"SOUND DAC L", NULL, "SDWRX"}, 1945 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"}, 1946 {"SOUND DAC L", NULL, "PLL2B"}, 1947 {"SOUND DAC L", NULL, "PLL2F"}, 1948 {"SOUND DAC R", NULL, "SDWRX"}, 1949 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"}, 1950 {"SOUND DAC R", NULL, "PLL2B"}, 1951 {"SOUND DAC R", NULL, "PLL2F"}, 1952 1953 {"DAC L Mux", "IF1", "IF1 DAC1 L"}, 1954 {"DAC L Mux", "SOUND", "SOUND DAC L"}, 1955 {"DAC R Mux", "IF1", "IF1 DAC1 R"}, 1956 {"DAC R Mux", "SOUND", "SOUND DAC R"}, 1957 1958 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1959 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"}, 1960 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1961 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"}, 1962 1963 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1964 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1965 1966 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1967 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1968 1969 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1970 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1971 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1972 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1973 1974 {"DAC L1", NULL, "DAC L1 Source"}, 1975 {"DAC R1", NULL, "DAC R1 Source"}, 1976 1977 {"DAC L1", NULL, "DAC 1 Clock"}, 1978 {"DAC R1", NULL, "DAC 1 Clock"}, 1979 1980 {"HP Amp", NULL, "DAC L1"}, 1981 {"HP Amp", NULL, "DAC R1"}, 1982 {"HP Amp", NULL, "HP Amp L"}, 1983 {"HP Amp", NULL, "HP Amp R"}, 1984 {"HP Amp", NULL, "Capless"}, 1985 {"HP Amp", NULL, "Charge Pump"}, 1986 {"HP Amp", NULL, "CLKDET SYS"}, 1987 {"HP Amp", NULL, "Vref1"}, 1988 {"HPOL Playback", "Switch", "HP Amp"}, 1989 {"HPOR Playback", "Switch", "HP Amp"}, 1990 {"HPOL", NULL, "HPOL Playback"}, 1991 {"HPOR", NULL, "HPOR Playback"}, 1992 }; 1993 1994 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1995 unsigned int rx_mask, int slots, int slot_width) 1996 { 1997 struct snd_soc_component *component = dai->component; 1998 unsigned int cl, val = 0; 1999 2000 if (tx_mask || rx_mask) 2001 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 2002 RT5682_TDM_EN, RT5682_TDM_EN); 2003 else 2004 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 2005 RT5682_TDM_EN, 0); 2006 2007 switch (slots) { 2008 case 4: 2009 val |= RT5682_TDM_TX_CH_4; 2010 val |= RT5682_TDM_RX_CH_4; 2011 break; 2012 case 6: 2013 val |= RT5682_TDM_TX_CH_6; 2014 val |= RT5682_TDM_RX_CH_6; 2015 break; 2016 case 8: 2017 val |= RT5682_TDM_TX_CH_8; 2018 val |= RT5682_TDM_RX_CH_8; 2019 break; 2020 case 2: 2021 break; 2022 default: 2023 return -EINVAL; 2024 } 2025 2026 snd_soc_component_update_bits(component, RT5682_TDM_CTRL, 2027 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 2028 2029 switch (slot_width) { 2030 case 8: 2031 if (tx_mask || rx_mask) 2032 return -EINVAL; 2033 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 2034 break; 2035 case 16: 2036 val = RT5682_TDM_CL_16; 2037 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 2038 break; 2039 case 20: 2040 val = RT5682_TDM_CL_20; 2041 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20; 2042 break; 2043 case 24: 2044 val = RT5682_TDM_CL_24; 2045 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24; 2046 break; 2047 case 32: 2048 val = RT5682_TDM_CL_32; 2049 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32; 2050 break; 2051 default: 2052 return -EINVAL; 2053 } 2054 2055 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2056 RT5682_TDM_CL_MASK, val); 2057 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2058 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl); 2059 2060 return 0; 2061 } 2062 2063 static int rt5682_hw_params(struct snd_pcm_substream *substream, 2064 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2065 { 2066 struct snd_soc_component *component = dai->component; 2067 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2068 unsigned int len_1 = 0, len_2 = 0; 2069 int pre_div, frame_size; 2070 2071 rt5682->lrck[dai->id] = params_rate(params); 2072 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); 2073 2074 frame_size = snd_soc_params_to_frame_size(params); 2075 if (frame_size < 0) { 2076 dev_err(component->dev, "Unsupported frame size: %d\n", 2077 frame_size); 2078 return -EINVAL; 2079 } 2080 2081 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 2082 rt5682->lrck[dai->id], pre_div, dai->id); 2083 2084 switch (params_width(params)) { 2085 case 16: 2086 break; 2087 case 20: 2088 len_1 |= RT5682_I2S1_DL_20; 2089 len_2 |= RT5682_I2S2_DL_20; 2090 break; 2091 case 24: 2092 len_1 |= RT5682_I2S1_DL_24; 2093 len_2 |= RT5682_I2S2_DL_24; 2094 break; 2095 case 32: 2096 len_1 |= RT5682_I2S1_DL_32; 2097 len_2 |= RT5682_I2S2_DL_24; 2098 break; 2099 case 8: 2100 len_1 |= RT5682_I2S2_DL_8; 2101 len_2 |= RT5682_I2S2_DL_8; 2102 break; 2103 default: 2104 return -EINVAL; 2105 } 2106 2107 switch (dai->id) { 2108 case RT5682_AIF1: 2109 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2110 RT5682_I2S1_DL_MASK, len_1); 2111 if (rt5682->master[RT5682_AIF1]) { 2112 snd_soc_component_update_bits(component, 2113 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK | 2114 RT5682_I2S_CLK_SRC_MASK, 2115 pre_div << RT5682_I2S_M_DIV_SFT | 2116 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2117 } 2118 if (params_channels(params) == 1) /* mono mode */ 2119 snd_soc_component_update_bits(component, 2120 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2121 RT5682_I2S1_MONO_EN); 2122 else 2123 snd_soc_component_update_bits(component, 2124 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2125 RT5682_I2S1_MONO_DIS); 2126 break; 2127 case RT5682_AIF2: 2128 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2129 RT5682_I2S2_DL_MASK, len_2); 2130 if (rt5682->master[RT5682_AIF2]) { 2131 snd_soc_component_update_bits(component, 2132 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK, 2133 pre_div << RT5682_I2S2_M_PD_SFT); 2134 } 2135 if (params_channels(params) == 1) /* mono mode */ 2136 snd_soc_component_update_bits(component, 2137 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2138 RT5682_I2S2_MONO_EN); 2139 else 2140 snd_soc_component_update_bits(component, 2141 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2142 RT5682_I2S2_MONO_DIS); 2143 break; 2144 default: 2145 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2146 return -EINVAL; 2147 } 2148 2149 return 0; 2150 } 2151 2152 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2153 { 2154 struct snd_soc_component *component = dai->component; 2155 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2156 unsigned int reg_val = 0, tdm_ctrl = 0; 2157 2158 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2159 case SND_SOC_DAIFMT_CBM_CFM: 2160 rt5682->master[dai->id] = 1; 2161 break; 2162 case SND_SOC_DAIFMT_CBS_CFS: 2163 rt5682->master[dai->id] = 0; 2164 break; 2165 default: 2166 return -EINVAL; 2167 } 2168 2169 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2170 case SND_SOC_DAIFMT_NB_NF: 2171 break; 2172 case SND_SOC_DAIFMT_IB_NF: 2173 reg_val |= RT5682_I2S_BP_INV; 2174 tdm_ctrl |= RT5682_TDM_S_BP_INV; 2175 break; 2176 case SND_SOC_DAIFMT_NB_IF: 2177 if (dai->id == RT5682_AIF1) 2178 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV; 2179 else 2180 return -EINVAL; 2181 break; 2182 case SND_SOC_DAIFMT_IB_IF: 2183 if (dai->id == RT5682_AIF1) 2184 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV | 2185 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV; 2186 else 2187 return -EINVAL; 2188 break; 2189 default: 2190 return -EINVAL; 2191 } 2192 2193 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2194 case SND_SOC_DAIFMT_I2S: 2195 break; 2196 case SND_SOC_DAIFMT_LEFT_J: 2197 reg_val |= RT5682_I2S_DF_LEFT; 2198 tdm_ctrl |= RT5682_TDM_DF_LEFT; 2199 break; 2200 case SND_SOC_DAIFMT_DSP_A: 2201 reg_val |= RT5682_I2S_DF_PCM_A; 2202 tdm_ctrl |= RT5682_TDM_DF_PCM_A; 2203 break; 2204 case SND_SOC_DAIFMT_DSP_B: 2205 reg_val |= RT5682_I2S_DF_PCM_B; 2206 tdm_ctrl |= RT5682_TDM_DF_PCM_B; 2207 break; 2208 default: 2209 return -EINVAL; 2210 } 2211 2212 switch (dai->id) { 2213 case RT5682_AIF1: 2214 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2215 RT5682_I2S_DF_MASK, reg_val); 2216 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2217 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK | 2218 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK | 2219 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK, 2220 tdm_ctrl | rt5682->master[dai->id]); 2221 break; 2222 case RT5682_AIF2: 2223 if (rt5682->master[dai->id] == 0) 2224 reg_val |= RT5682_I2S2_MS_S; 2225 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2226 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK | 2227 RT5682_I2S_DF_MASK, reg_val); 2228 break; 2229 default: 2230 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2231 return -EINVAL; 2232 } 2233 return 0; 2234 } 2235 2236 static int rt5682_set_component_sysclk(struct snd_soc_component *component, 2237 int clk_id, int source, unsigned int freq, int dir) 2238 { 2239 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2240 unsigned int reg_val = 0, src = 0; 2241 2242 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) 2243 return 0; 2244 2245 switch (clk_id) { 2246 case RT5682_SCLK_S_MCLK: 2247 reg_val |= RT5682_SCLK_SRC_MCLK; 2248 src = RT5682_CLK_SRC_MCLK; 2249 break; 2250 case RT5682_SCLK_S_PLL1: 2251 reg_val |= RT5682_SCLK_SRC_PLL1; 2252 src = RT5682_CLK_SRC_PLL1; 2253 break; 2254 case RT5682_SCLK_S_PLL2: 2255 reg_val |= RT5682_SCLK_SRC_PLL2; 2256 src = RT5682_CLK_SRC_PLL2; 2257 break; 2258 case RT5682_SCLK_S_RCCLK: 2259 reg_val |= RT5682_SCLK_SRC_RCCLK; 2260 src = RT5682_CLK_SRC_RCCLK; 2261 break; 2262 default: 2263 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2264 return -EINVAL; 2265 } 2266 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2267 RT5682_SCLK_SRC_MASK, reg_val); 2268 2269 if (rt5682->master[RT5682_AIF2]) { 2270 snd_soc_component_update_bits(component, 2271 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK, 2272 src << RT5682_I2S2_SRC_SFT); 2273 } 2274 2275 rt5682->sysclk = freq; 2276 rt5682->sysclk_src = clk_id; 2277 2278 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2279 freq, clk_id); 2280 2281 return 0; 2282 } 2283 2284 static int rt5682_set_component_pll(struct snd_soc_component *component, 2285 int pll_id, int source, unsigned int freq_in, 2286 unsigned int freq_out) 2287 { 2288 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2289 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code; 2290 unsigned int pll2_fout1, pll2_ps_val; 2291 int ret; 2292 2293 if (source == rt5682->pll_src[pll_id] && 2294 freq_in == rt5682->pll_in[pll_id] && 2295 freq_out == rt5682->pll_out[pll_id]) 2296 return 0; 2297 2298 if (!freq_in || !freq_out) { 2299 dev_dbg(component->dev, "PLL disabled\n"); 2300 2301 rt5682->pll_in[pll_id] = 0; 2302 rt5682->pll_out[pll_id] = 0; 2303 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2304 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 2305 return 0; 2306 } 2307 2308 if (pll_id == RT5682_PLL2) { 2309 switch (source) { 2310 case RT5682_PLL2_S_MCLK: 2311 snd_soc_component_update_bits(component, 2312 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK, 2313 RT5682_PLL2_SRC_MCLK); 2314 break; 2315 default: 2316 dev_err(component->dev, "Unknown PLL2 Source %d\n", 2317 source); 2318 return -EINVAL; 2319 } 2320 2321 /** 2322 * PLL2 concatenates 2 PLL units. 2323 * We suggest the Fout of the front PLL is 3.84MHz. 2324 */ 2325 pll2_fout1 = 3840000; 2326 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code); 2327 if (ret < 0) { 2328 dev_err(component->dev, "Unsupport input clock %d\n", 2329 freq_in); 2330 return ret; 2331 } 2332 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2333 freq_in, pll2_fout1, 2334 pll2f_code.m_bp, 2335 (pll2f_code.m_bp ? 0 : pll2f_code.m_code), 2336 pll2f_code.n_code, pll2f_code.k_code); 2337 2338 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code); 2339 if (ret < 0) { 2340 dev_err(component->dev, "Unsupport input clock %d\n", 2341 pll2_fout1); 2342 return ret; 2343 } 2344 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2345 pll2_fout1, freq_out, 2346 pll2b_code.m_bp, 2347 (pll2b_code.m_bp ? 0 : pll2b_code.m_code), 2348 pll2b_code.n_code, pll2b_code.k_code); 2349 2350 snd_soc_component_write(component, RT5682_PLL2_CTRL_1, 2351 pll2f_code.k_code << RT5682_PLL2F_K_SFT | 2352 pll2b_code.k_code << RT5682_PLL2B_K_SFT | 2353 pll2b_code.m_code); 2354 snd_soc_component_write(component, RT5682_PLL2_CTRL_2, 2355 pll2f_code.m_code << RT5682_PLL2F_M_SFT | 2356 pll2b_code.n_code); 2357 snd_soc_component_write(component, RT5682_PLL2_CTRL_3, 2358 pll2f_code.n_code << RT5682_PLL2F_N_SFT); 2359 2360 if (freq_out == 22579200) 2361 pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT; 2362 else 2363 pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT; 2364 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4, 2365 RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK | 2366 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf, 2367 pll2_ps_val | 2368 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT | 2369 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT | 2370 0xf); 2371 } else { 2372 switch (source) { 2373 case RT5682_PLL1_S_MCLK: 2374 snd_soc_component_update_bits(component, 2375 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2376 RT5682_PLL1_SRC_MCLK); 2377 break; 2378 case RT5682_PLL1_S_BCLK1: 2379 snd_soc_component_update_bits(component, 2380 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2381 RT5682_PLL1_SRC_BCLK1); 2382 break; 2383 default: 2384 dev_err(component->dev, "Unknown PLL1 Source %d\n", 2385 source); 2386 return -EINVAL; 2387 } 2388 2389 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2390 if (ret < 0) { 2391 dev_err(component->dev, "Unsupport input clock %d\n", 2392 freq_in); 2393 return ret; 2394 } 2395 2396 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2397 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2398 pll_code.n_code, pll_code.k_code); 2399 2400 snd_soc_component_write(component, RT5682_PLL_CTRL_1, 2401 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code); 2402 snd_soc_component_write(component, RT5682_PLL_CTRL_2, 2403 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT | 2404 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST); 2405 } 2406 2407 rt5682->pll_in[pll_id] = freq_in; 2408 rt5682->pll_out[pll_id] = freq_out; 2409 rt5682->pll_src[pll_id] = source; 2410 2411 return 0; 2412 } 2413 2414 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2415 { 2416 struct snd_soc_component *component = dai->component; 2417 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2418 2419 rt5682->bclk[dai->id] = ratio; 2420 2421 switch (ratio) { 2422 case 256: 2423 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2424 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256); 2425 break; 2426 case 128: 2427 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2428 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128); 2429 break; 2430 case 64: 2431 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2432 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64); 2433 break; 2434 case 32: 2435 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2436 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32); 2437 break; 2438 default: 2439 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); 2440 return -EINVAL; 2441 } 2442 2443 return 0; 2444 } 2445 2446 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2447 { 2448 struct snd_soc_component *component = dai->component; 2449 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2450 2451 rt5682->bclk[dai->id] = ratio; 2452 2453 switch (ratio) { 2454 case 64: 2455 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2456 RT5682_I2S2_BCLK_MS2_MASK, 2457 RT5682_I2S2_BCLK_MS2_64); 2458 break; 2459 case 32: 2460 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2461 RT5682_I2S2_BCLK_MS2_MASK, 2462 RT5682_I2S2_BCLK_MS2_32); 2463 break; 2464 default: 2465 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); 2466 return -EINVAL; 2467 } 2468 2469 return 0; 2470 } 2471 2472 static int rt5682_set_bias_level(struct snd_soc_component *component, 2473 enum snd_soc_bias_level level) 2474 { 2475 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2476 2477 switch (level) { 2478 case SND_SOC_BIAS_PREPARE: 2479 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2480 RT5682_PWR_BG, RT5682_PWR_BG); 2481 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2482 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 2483 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO); 2484 break; 2485 2486 case SND_SOC_BIAS_STANDBY: 2487 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2488 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL); 2489 break; 2490 case SND_SOC_BIAS_OFF: 2491 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2492 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0); 2493 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2494 RT5682_PWR_BG, 0); 2495 break; 2496 case SND_SOC_BIAS_ON: 2497 break; 2498 } 2499 2500 return 0; 2501 } 2502 2503 #ifdef CONFIG_COMMON_CLK 2504 #define CLK_PLL2_FIN 48000000 2505 #define CLK_48 48000 2506 #define CLK_44 44100 2507 2508 static bool rt5682_clk_check(struct rt5682_priv *rt5682) 2509 { 2510 if (!rt5682->master[RT5682_AIF1]) { 2511 dev_dbg(rt5682->component->dev, "sysclk/dai not set correctly\n"); 2512 return false; 2513 } 2514 return true; 2515 } 2516 2517 static int rt5682_wclk_prepare(struct clk_hw *hw) 2518 { 2519 struct rt5682_priv *rt5682 = 2520 container_of(hw, struct rt5682_priv, 2521 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2522 struct snd_soc_component *component = rt5682->component; 2523 struct snd_soc_dapm_context *dapm = 2524 snd_soc_component_get_dapm(component); 2525 2526 if (!rt5682_clk_check(rt5682)) 2527 return -EINVAL; 2528 2529 snd_soc_dapm_mutex_lock(dapm); 2530 2531 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS"); 2532 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2533 RT5682_PWR_MB, RT5682_PWR_MB); 2534 2535 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2"); 2536 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2537 RT5682_PWR_VREF2 | RT5682_PWR_FV2, 2538 RT5682_PWR_VREF2); 2539 usleep_range(55000, 60000); 2540 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2541 RT5682_PWR_FV2, RT5682_PWR_FV2); 2542 2543 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1"); 2544 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F"); 2545 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B"); 2546 snd_soc_dapm_sync_unlocked(dapm); 2547 2548 snd_soc_dapm_mutex_unlock(dapm); 2549 2550 return 0; 2551 } 2552 2553 static void rt5682_wclk_unprepare(struct clk_hw *hw) 2554 { 2555 struct rt5682_priv *rt5682 = 2556 container_of(hw, struct rt5682_priv, 2557 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2558 struct snd_soc_component *component = rt5682->component; 2559 struct snd_soc_dapm_context *dapm = 2560 snd_soc_component_get_dapm(component); 2561 2562 if (!rt5682_clk_check(rt5682)) 2563 return; 2564 2565 snd_soc_dapm_mutex_lock(dapm); 2566 2567 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS"); 2568 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2"); 2569 if (!rt5682->jack_type) 2570 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2571 RT5682_PWR_VREF2 | RT5682_PWR_FV2 | 2572 RT5682_PWR_MB, 0); 2573 2574 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1"); 2575 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F"); 2576 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B"); 2577 snd_soc_dapm_sync_unlocked(dapm); 2578 2579 snd_soc_dapm_mutex_unlock(dapm); 2580 } 2581 2582 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw, 2583 unsigned long parent_rate) 2584 { 2585 struct rt5682_priv *rt5682 = 2586 container_of(hw, struct rt5682_priv, 2587 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2588 struct snd_soc_component *component = rt5682->component; 2589 const char * const clk_name = clk_hw_get_name(hw); 2590 2591 if (!rt5682_clk_check(rt5682)) 2592 return 0; 2593 /* 2594 * Only accept to set wclk rate to 44.1k or 48kHz. 2595 */ 2596 if (rt5682->lrck[RT5682_AIF1] != CLK_48 && 2597 rt5682->lrck[RT5682_AIF1] != CLK_44) { 2598 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", 2599 __func__, clk_name, CLK_44, CLK_48); 2600 return 0; 2601 } 2602 2603 return rt5682->lrck[RT5682_AIF1]; 2604 } 2605 2606 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate, 2607 unsigned long *parent_rate) 2608 { 2609 struct rt5682_priv *rt5682 = 2610 container_of(hw, struct rt5682_priv, 2611 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2612 struct snd_soc_component *component = rt5682->component; 2613 const char * const clk_name = clk_hw_get_name(hw); 2614 2615 if (!rt5682_clk_check(rt5682)) 2616 return -EINVAL; 2617 /* 2618 * Only accept to set wclk rate to 44.1k or 48kHz. 2619 * It will force to 48kHz if not both. 2620 */ 2621 if (rate != CLK_48 && rate != CLK_44) { 2622 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", 2623 __func__, clk_name, CLK_44, CLK_48); 2624 rate = CLK_48; 2625 } 2626 2627 return rate; 2628 } 2629 2630 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, 2631 unsigned long parent_rate) 2632 { 2633 struct rt5682_priv *rt5682 = 2634 container_of(hw, struct rt5682_priv, 2635 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2636 struct snd_soc_component *component = rt5682->component; 2637 struct clk *parent_clk; 2638 const char * const clk_name = clk_hw_get_name(hw); 2639 int pre_div; 2640 unsigned int clk_pll2_out; 2641 2642 if (!rt5682_clk_check(rt5682)) 2643 return -EINVAL; 2644 2645 /* 2646 * Whether the wclk's parent clk (mclk) exists or not, please ensure 2647 * it is fixed or set to 48MHz before setting wclk rate. It's a 2648 * temporary limitation. Only accept 48MHz clk as the clk provider. 2649 * 2650 * It will set the codec anyway by assuming mclk is 48MHz. 2651 */ 2652 parent_clk = clk_get_parent(hw->clk); 2653 if (!parent_clk) 2654 dev_warn(component->dev, 2655 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", 2656 CLK_PLL2_FIN); 2657 2658 if (parent_rate != CLK_PLL2_FIN) 2659 dev_warn(component->dev, "clk %s only support %d Hz input\n", 2660 clk_name, CLK_PLL2_FIN); 2661 2662 /* 2663 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz, 2664 * PLL2 is needed. 2665 */ 2666 clk_pll2_out = rate * 512; 2667 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK, 2668 CLK_PLL2_FIN, clk_pll2_out); 2669 2670 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0, 2671 clk_pll2_out, SND_SOC_CLOCK_IN); 2672 2673 rt5682->lrck[RT5682_AIF1] = rate; 2674 2675 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate); 2676 2677 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 2678 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK, 2679 pre_div << RT5682_I2S_M_DIV_SFT | 2680 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2681 2682 return 0; 2683 } 2684 2685 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw, 2686 unsigned long parent_rate) 2687 { 2688 struct rt5682_priv *rt5682 = 2689 container_of(hw, struct rt5682_priv, 2690 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2691 struct snd_soc_component *component = rt5682->component; 2692 unsigned int bclks_per_wclk; 2693 2694 bclks_per_wclk = snd_soc_component_read(component, RT5682_TDM_TCON_CTRL); 2695 2696 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) { 2697 case RT5682_TDM_BCLK_MS1_256: 2698 return parent_rate * 256; 2699 case RT5682_TDM_BCLK_MS1_128: 2700 return parent_rate * 128; 2701 case RT5682_TDM_BCLK_MS1_64: 2702 return parent_rate * 64; 2703 case RT5682_TDM_BCLK_MS1_32: 2704 return parent_rate * 32; 2705 default: 2706 return 0; 2707 } 2708 } 2709 2710 static unsigned long rt5682_bclk_get_factor(unsigned long rate, 2711 unsigned long parent_rate) 2712 { 2713 unsigned long factor; 2714 2715 factor = rate / parent_rate; 2716 if (factor < 64) 2717 return 32; 2718 else if (factor < 128) 2719 return 64; 2720 else if (factor < 256) 2721 return 128; 2722 else 2723 return 256; 2724 } 2725 2726 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate, 2727 unsigned long *parent_rate) 2728 { 2729 struct rt5682_priv *rt5682 = 2730 container_of(hw, struct rt5682_priv, 2731 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2732 unsigned long factor; 2733 2734 if (!*parent_rate || !rt5682_clk_check(rt5682)) 2735 return -EINVAL; 2736 2737 /* 2738 * BCLK rates are set as a multiplier of WCLK in HW. 2739 * We don't allow changing the parent WCLK. We just do 2740 * some rounding down based on the parent WCLK rate 2741 * and find the appropriate multiplier of BCLK to 2742 * get the rounded down BCLK value. 2743 */ 2744 factor = rt5682_bclk_get_factor(rate, *parent_rate); 2745 2746 return *parent_rate * factor; 2747 } 2748 2749 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate, 2750 unsigned long parent_rate) 2751 { 2752 struct rt5682_priv *rt5682 = 2753 container_of(hw, struct rt5682_priv, 2754 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2755 struct snd_soc_component *component = rt5682->component; 2756 struct snd_soc_dai *dai = NULL; 2757 unsigned long factor; 2758 2759 if (!rt5682_clk_check(rt5682)) 2760 return -EINVAL; 2761 2762 factor = rt5682_bclk_get_factor(rate, parent_rate); 2763 2764 for_each_component_dais(component, dai) 2765 if (dai->id == RT5682_AIF1) 2766 break; 2767 if (!dai) { 2768 dev_err(component->dev, "dai %d not found in component\n", 2769 RT5682_AIF1); 2770 return -ENODEV; 2771 } 2772 2773 return rt5682_set_bclk1_ratio(dai, factor); 2774 } 2775 2776 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = { 2777 [RT5682_DAI_WCLK_IDX] = { 2778 .prepare = rt5682_wclk_prepare, 2779 .unprepare = rt5682_wclk_unprepare, 2780 .recalc_rate = rt5682_wclk_recalc_rate, 2781 .round_rate = rt5682_wclk_round_rate, 2782 .set_rate = rt5682_wclk_set_rate, 2783 }, 2784 [RT5682_DAI_BCLK_IDX] = { 2785 .recalc_rate = rt5682_bclk_recalc_rate, 2786 .round_rate = rt5682_bclk_round_rate, 2787 .set_rate = rt5682_bclk_set_rate, 2788 }, 2789 }; 2790 2791 static int rt5682_register_dai_clks(struct snd_soc_component *component) 2792 { 2793 struct device *dev = component->dev; 2794 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2795 struct rt5682_platform_data *pdata = &rt5682->pdata; 2796 struct clk_hw *dai_clk_hw; 2797 int i, ret; 2798 2799 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) { 2800 struct clk_init_data init = { }; 2801 2802 dai_clk_hw = &rt5682->dai_clks_hw[i]; 2803 2804 switch (i) { 2805 case RT5682_DAI_WCLK_IDX: 2806 /* Make MCLK the parent of WCLK */ 2807 if (rt5682->mclk) { 2808 init.parent_data = &(struct clk_parent_data){ 2809 .fw_name = "mclk", 2810 }; 2811 init.num_parents = 1; 2812 } 2813 break; 2814 case RT5682_DAI_BCLK_IDX: 2815 /* Make WCLK the parent of BCLK */ 2816 init.parent_hws = &(const struct clk_hw *){ 2817 &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX] 2818 }; 2819 init.num_parents = 1; 2820 break; 2821 default: 2822 dev_err(dev, "Invalid clock index\n"); 2823 return -EINVAL; 2824 } 2825 2826 init.name = pdata->dai_clk_names[i]; 2827 init.ops = &rt5682_dai_clk_ops[i]; 2828 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE; 2829 dai_clk_hw->init = &init; 2830 2831 ret = devm_clk_hw_register(dev, dai_clk_hw); 2832 if (ret) { 2833 dev_warn(dev, "Failed to register %s: %d\n", 2834 init.name, ret); 2835 return ret; 2836 } 2837 2838 if (dev->of_node) { 2839 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 2840 dai_clk_hw); 2841 } else { 2842 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw, 2843 init.name, 2844 dev_name(dev)); 2845 if (ret) 2846 return ret; 2847 } 2848 } 2849 2850 return 0; 2851 } 2852 #endif /* CONFIG_COMMON_CLK */ 2853 2854 static int rt5682_probe(struct snd_soc_component *component) 2855 { 2856 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2857 struct sdw_slave *slave; 2858 unsigned long time; 2859 struct snd_soc_dapm_context *dapm = &component->dapm; 2860 2861 #ifdef CONFIG_COMMON_CLK 2862 int ret; 2863 #endif 2864 rt5682->component = component; 2865 2866 if (rt5682->is_sdw) { 2867 slave = rt5682->slave; 2868 time = wait_for_completion_timeout( 2869 &slave->initialization_complete, 2870 msecs_to_jiffies(RT5682_PROBE_TIMEOUT)); 2871 if (!time) { 2872 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 2873 return -ETIMEDOUT; 2874 } 2875 } else { 2876 #ifdef CONFIG_COMMON_CLK 2877 /* Check if MCLK provided */ 2878 rt5682->mclk = devm_clk_get(component->dev, "mclk"); 2879 if (IS_ERR(rt5682->mclk)) { 2880 if (PTR_ERR(rt5682->mclk) != -ENOENT) { 2881 ret = PTR_ERR(rt5682->mclk); 2882 return ret; 2883 } 2884 rt5682->mclk = NULL; 2885 } 2886 2887 /* Register CCF DAI clock control */ 2888 ret = rt5682_register_dai_clks(component); 2889 if (ret) 2890 return ret; 2891 2892 /* Initial setup for CCF */ 2893 rt5682->lrck[RT5682_AIF1] = CLK_48; 2894 #endif 2895 } 2896 2897 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 2898 snd_soc_dapm_disable_pin(dapm, "Vref2"); 2899 snd_soc_dapm_sync(dapm); 2900 return 0; 2901 } 2902 2903 static void rt5682_remove(struct snd_soc_component *component) 2904 { 2905 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2906 2907 rt5682_reset(rt5682); 2908 } 2909 2910 #ifdef CONFIG_PM 2911 static int rt5682_suspend(struct snd_soc_component *component) 2912 { 2913 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2914 2915 regcache_cache_only(rt5682->regmap, true); 2916 regcache_mark_dirty(rt5682->regmap); 2917 return 0; 2918 } 2919 2920 static int rt5682_resume(struct snd_soc_component *component) 2921 { 2922 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2923 2924 regcache_cache_only(rt5682->regmap, false); 2925 regcache_sync(rt5682->regmap); 2926 2927 mod_delayed_work(system_power_efficient_wq, 2928 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 2929 2930 return 0; 2931 } 2932 #else 2933 #define rt5682_suspend NULL 2934 #define rt5682_resume NULL 2935 #endif 2936 2937 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = { 2938 .hw_params = rt5682_hw_params, 2939 .set_fmt = rt5682_set_dai_fmt, 2940 .set_tdm_slot = rt5682_set_tdm_slot, 2941 .set_bclk_ratio = rt5682_set_bclk1_ratio, 2942 }; 2943 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops); 2944 2945 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = { 2946 .hw_params = rt5682_hw_params, 2947 .set_fmt = rt5682_set_dai_fmt, 2948 .set_bclk_ratio = rt5682_set_bclk2_ratio, 2949 }; 2950 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops); 2951 2952 const struct snd_soc_component_driver rt5682_soc_component_dev = { 2953 .probe = rt5682_probe, 2954 .remove = rt5682_remove, 2955 .suspend = rt5682_suspend, 2956 .resume = rt5682_resume, 2957 .set_bias_level = rt5682_set_bias_level, 2958 .controls = rt5682_snd_controls, 2959 .num_controls = ARRAY_SIZE(rt5682_snd_controls), 2960 .dapm_widgets = rt5682_dapm_widgets, 2961 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets), 2962 .dapm_routes = rt5682_dapm_routes, 2963 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes), 2964 .set_sysclk = rt5682_set_component_sysclk, 2965 .set_pll = rt5682_set_component_pll, 2966 .set_jack = rt5682_set_jack_detect, 2967 .use_pmdown_time = 1, 2968 .endianness = 1, 2969 .non_legacy_dai_naming = 1, 2970 }; 2971 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev); 2972 2973 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev) 2974 { 2975 2976 device_property_read_u32(dev, "realtek,dmic1-data-pin", 2977 &rt5682->pdata.dmic1_data_pin); 2978 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 2979 &rt5682->pdata.dmic1_clk_pin); 2980 device_property_read_u32(dev, "realtek,jd-src", 2981 &rt5682->pdata.jd_src); 2982 device_property_read_u32(dev, "realtek,btndet-delay", 2983 &rt5682->pdata.btndet_delay); 2984 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", 2985 &rt5682->pdata.dmic_clk_rate); 2986 device_property_read_u32(dev, "realtek,dmic-delay-ms", 2987 &rt5682->pdata.dmic_delay); 2988 2989 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 2990 "realtek,ldo1-en-gpios", 0); 2991 2992 if (device_property_read_string_array(dev, "clock-output-names", 2993 rt5682->pdata.dai_clk_names, 2994 RT5682_DAI_NUM_CLKS) < 0) 2995 dev_warn(dev, "Using default DAI clk names: %s, %s\n", 2996 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX], 2997 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]); 2998 2999 rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev, 3000 "realtek,dmic-clk-driving-high"); 3001 3002 return 0; 3003 } 3004 EXPORT_SYMBOL_GPL(rt5682_parse_dt); 3005 3006 void rt5682_calibrate(struct rt5682_priv *rt5682) 3007 { 3008 int value, count; 3009 3010 mutex_lock(&rt5682->calibrate_mutex); 3011 3012 rt5682_reset(rt5682); 3013 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f); 3014 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); 3015 usleep_range(15000, 20000); 3016 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); 3017 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); 3018 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); 3019 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); 3020 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); 3021 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); 3022 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); 3023 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); 3024 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); 3025 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); 3026 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); 3027 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3028 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); 3029 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); 3030 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3031 3032 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); 3033 3034 for (count = 0; count < 60; count++) { 3035 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); 3036 if (!(value & 0x8000)) 3037 break; 3038 3039 usleep_range(10000, 10005); 3040 } 3041 3042 if (count >= 60) 3043 dev_err(rt5682->component->dev, "HP Calibration Failure\n"); 3044 3045 /* restore settings */ 3046 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f); 3047 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); 3048 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); 3049 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); 3050 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); 3051 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); 3052 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); 3053 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c); 3054 3055 mutex_unlock(&rt5682->calibrate_mutex); 3056 } 3057 EXPORT_SYMBOL_GPL(rt5682_calibrate); 3058 3059 MODULE_DESCRIPTION("ASoC RT5682 driver"); 3060 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 3061 MODULE_LICENSE("GPL v2"); 3062