xref: /openbmc/linux/sound/soc/codecs/rt5660.h (revision ca04dd8a9b4d350d473675c0f777ff8c213aa0a9)
12b26dd4cSOder Chiou /*
22b26dd4cSOder Chiou  * rt5660.h  --  RT5660 ALSA SoC audio driver
32b26dd4cSOder Chiou  *
42b26dd4cSOder Chiou  * Copyright 2016 Realtek Semiconductor Corp.
52b26dd4cSOder Chiou  * Author: Oder Chiou <oder_chiou@realtek.com>
62b26dd4cSOder Chiou  *
72b26dd4cSOder Chiou  * This program is free software; you can redistribute it and/or modify
82b26dd4cSOder Chiou  * it under the terms of the GNU General Public License version 2 as
92b26dd4cSOder Chiou  * published by the Free Software Foundation.
102b26dd4cSOder Chiou  */
112b26dd4cSOder Chiou 
122b26dd4cSOder Chiou #ifndef _RT5660_H
132b26dd4cSOder Chiou #define _RT5660_H
142b26dd4cSOder Chiou 
152b26dd4cSOder Chiou #include <linux/clk.h>
162b26dd4cSOder Chiou #include <sound/rt5660.h>
172b26dd4cSOder Chiou 
182b26dd4cSOder Chiou /* Info */
192b26dd4cSOder Chiou #define RT5660_RESET				0x00
202b26dd4cSOder Chiou #define RT5660_VENDOR_ID			0xfd
212b26dd4cSOder Chiou #define RT5660_VENDOR_ID1			0xfe
222b26dd4cSOder Chiou #define RT5660_VENDOR_ID2			0xff
232b26dd4cSOder Chiou /*  I/O - Output */
242b26dd4cSOder Chiou #define RT5660_SPK_VOL				0x01
252b26dd4cSOder Chiou #define RT5660_LOUT_VOL				0x02
262b26dd4cSOder Chiou /* I/O - Input */
272b26dd4cSOder Chiou #define RT5660_IN1_IN2				0x0d
282b26dd4cSOder Chiou #define RT5660_IN3_IN4				0x0e
292b26dd4cSOder Chiou /* I/O - ADC/DAC/DMIC */
302b26dd4cSOder Chiou #define RT5660_DAC1_DIG_VOL			0x19
312b26dd4cSOder Chiou #define RT5660_STO1_ADC_DIG_VOL			0x1c
322b26dd4cSOder Chiou #define RT5660_ADC_BST_VOL1			0x1e
332b26dd4cSOder Chiou /* Mixer - D-D */
342b26dd4cSOder Chiou #define RT5660_STO1_ADC_MIXER			0x27
352b26dd4cSOder Chiou #define RT5660_AD_DA_MIXER			0x29
362b26dd4cSOder Chiou #define RT5660_STO_DAC_MIXER			0x2a
372b26dd4cSOder Chiou #define RT5660_DIG_INF1_DATA			0x2f
382b26dd4cSOder Chiou /* Mixer - ADC */
392b26dd4cSOder Chiou #define RT5660_REC_L1_MIXER			0x3b
402b26dd4cSOder Chiou #define RT5660_REC_L2_MIXER			0x3c
412b26dd4cSOder Chiou #define RT5660_REC_R1_MIXER			0x3d
422b26dd4cSOder Chiou #define RT5660_REC_R2_MIXER			0x3e
432b26dd4cSOder Chiou /* Mixer - DAC */
442b26dd4cSOder Chiou #define RT5660_LOUT_MIXER			0x45
452b26dd4cSOder Chiou #define RT5660_SPK_MIXER			0x46
462b26dd4cSOder Chiou #define RT5660_SPO_MIXER			0x48
472b26dd4cSOder Chiou #define RT5660_SPO_CLSD_RATIO			0x4a
482b26dd4cSOder Chiou #define RT5660_OUT_L_GAIN1			0x4d
492b26dd4cSOder Chiou #define RT5660_OUT_L_GAIN2			0x4e
502b26dd4cSOder Chiou #define RT5660_OUT_L1_MIXER			0x4f
512b26dd4cSOder Chiou #define RT5660_OUT_R_GAIN1			0x50
522b26dd4cSOder Chiou #define RT5660_OUT_R_GAIN2			0x51
532b26dd4cSOder Chiou #define RT5660_OUT_R1_MIXER			0x52
542b26dd4cSOder Chiou /* Power */
552b26dd4cSOder Chiou #define RT5660_PWR_DIG1				0x61
562b26dd4cSOder Chiou #define RT5660_PWR_DIG2				0x62
572b26dd4cSOder Chiou #define RT5660_PWR_ANLG1			0x63
582b26dd4cSOder Chiou #define RT5660_PWR_ANLG2			0x64
592b26dd4cSOder Chiou #define RT5660_PWR_MIXER			0x65
602b26dd4cSOder Chiou #define RT5660_PWR_VOL				0x66
612b26dd4cSOder Chiou /* Private Register Control */
622b26dd4cSOder Chiou #define RT5660_PRIV_INDEX			0x6a
632b26dd4cSOder Chiou #define RT5660_PRIV_DATA			0x6c
642b26dd4cSOder Chiou /* Format - ADC/DAC */
652b26dd4cSOder Chiou #define RT5660_I2S1_SDP				0x70
662b26dd4cSOder Chiou #define RT5660_ADDA_CLK1			0x73
672b26dd4cSOder Chiou #define RT5660_ADDA_CLK2			0x74
682b26dd4cSOder Chiou #define RT5660_DMIC_CTRL1			0x75
692b26dd4cSOder Chiou /* Function - Analog */
702b26dd4cSOder Chiou #define RT5660_GLB_CLK				0x80
712b26dd4cSOder Chiou #define RT5660_PLL_CTRL1			0x81
722b26dd4cSOder Chiou #define RT5660_PLL_CTRL2			0x82
732b26dd4cSOder Chiou #define RT5660_CLSD_AMP_OC_CTRL			0x8c
742b26dd4cSOder Chiou #define RT5660_CLSD_AMP_CTRL			0x8d
752b26dd4cSOder Chiou #define RT5660_LOUT_AMP_CTRL			0x8e
762b26dd4cSOder Chiou #define RT5660_SPK_AMP_SPKVDD			0x92
772b26dd4cSOder Chiou #define RT5660_MICBIAS				0x93
782b26dd4cSOder Chiou #define RT5660_CLSD_OUT_CTRL1			0xa1
792b26dd4cSOder Chiou #define RT5660_CLSD_OUT_CTRL2			0xa2
802b26dd4cSOder Chiou #define RT5660_DIPOLE_MIC_CTRL1			0xa3
812b26dd4cSOder Chiou #define RT5660_DIPOLE_MIC_CTRL2			0xa4
822b26dd4cSOder Chiou #define RT5660_DIPOLE_MIC_CTRL3			0xa5
832b26dd4cSOder Chiou #define RT5660_DIPOLE_MIC_CTRL4			0xa6
842b26dd4cSOder Chiou #define RT5660_DIPOLE_MIC_CTRL5			0xa7
852b26dd4cSOder Chiou #define RT5660_DIPOLE_MIC_CTRL6			0xa8
862b26dd4cSOder Chiou #define RT5660_DIPOLE_MIC_CTRL7			0xa9
872b26dd4cSOder Chiou #define RT5660_DIPOLE_MIC_CTRL8			0xaa
882b26dd4cSOder Chiou #define RT5660_DIPOLE_MIC_CTRL9			0xab
892b26dd4cSOder Chiou #define RT5660_DIPOLE_MIC_CTRL10		0xac
902b26dd4cSOder Chiou #define RT5660_DIPOLE_MIC_CTRL11		0xad
912b26dd4cSOder Chiou #define RT5660_DIPOLE_MIC_CTRL12		0xae
922b26dd4cSOder Chiou /* Function - Digital */
932b26dd4cSOder Chiou #define RT5660_EQ_CTRL1				0xb0
942b26dd4cSOder Chiou #define RT5660_EQ_CTRL2				0xb1
952b26dd4cSOder Chiou #define RT5660_DRC_AGC_CTRL1			0xb3
962b26dd4cSOder Chiou #define RT5660_DRC_AGC_CTRL2			0xb4
972b26dd4cSOder Chiou #define RT5660_DRC_AGC_CTRL3			0xb5
982b26dd4cSOder Chiou #define RT5660_DRC_AGC_CTRL4			0xb6
992b26dd4cSOder Chiou #define RT5660_DRC_AGC_CTRL5			0xb7
1002b26dd4cSOder Chiou #define RT5660_JD_CTRL				0xbb
1012b26dd4cSOder Chiou #define RT5660_IRQ_CTRL1			0xbd
1022b26dd4cSOder Chiou #define RT5660_IRQ_CTRL2			0xbe
1032b26dd4cSOder Chiou #define RT5660_INT_IRQ_ST			0xbf
1042b26dd4cSOder Chiou #define RT5660_GPIO_CTRL1			0xc0
1052b26dd4cSOder Chiou #define RT5660_GPIO_CTRL2			0xc2
1062b26dd4cSOder Chiou #define RT5660_WIND_FILTER_CTRL1		0xd3
1072b26dd4cSOder Chiou #define RT5660_SV_ZCD1				0xd9
1082b26dd4cSOder Chiou #define RT5660_SV_ZCD2				0xda
1092b26dd4cSOder Chiou #define RT5660_DRC1_LM_CTRL1			0xe0
1102b26dd4cSOder Chiou #define RT5660_DRC1_LM_CTRL2			0xe1
1112b26dd4cSOder Chiou #define RT5660_DRC2_LM_CTRL1			0xe2
1122b26dd4cSOder Chiou #define RT5660_DRC2_LM_CTRL2			0xe3
1132b26dd4cSOder Chiou #define RT5660_MULTI_DRC_CTRL			0xe4
1142b26dd4cSOder Chiou #define RT5660_DRC2_CTRL1			0xe5
1152b26dd4cSOder Chiou #define RT5660_DRC2_CTRL2			0xe6
1162b26dd4cSOder Chiou #define RT5660_DRC2_CTRL3			0xe7
1172b26dd4cSOder Chiou #define RT5660_DRC2_CTRL4			0xe8
1182b26dd4cSOder Chiou #define RT5660_DRC2_CTRL5			0xe9
1192b26dd4cSOder Chiou #define RT5660_ALC_PGA_CTRL1			0xea
1202b26dd4cSOder Chiou #define RT5660_ALC_PGA_CTRL2			0xeb
1212b26dd4cSOder Chiou #define RT5660_ALC_PGA_CTRL3			0xec
1222b26dd4cSOder Chiou #define RT5660_ALC_PGA_CTRL4			0xed
1232b26dd4cSOder Chiou #define RT5660_ALC_PGA_CTRL5			0xee
1242b26dd4cSOder Chiou #define RT5660_ALC_PGA_CTRL6			0xef
1252b26dd4cSOder Chiou #define RT5660_ALC_PGA_CTRL7			0xf0
1262b26dd4cSOder Chiou 
1272b26dd4cSOder Chiou /* General Control */
1282b26dd4cSOder Chiou #define RT5660_GEN_CTRL1			0xfa
1292b26dd4cSOder Chiou #define RT5660_GEN_CTRL2			0xfb
1302b26dd4cSOder Chiou #define RT5660_GEN_CTRL3			0xfc
1312b26dd4cSOder Chiou 
1322b26dd4cSOder Chiou /* Index of Codec Private Register definition */
1332b26dd4cSOder Chiou #define RT5660_CHOP_DAC_ADC			0x3d
1342b26dd4cSOder Chiou 
1352b26dd4cSOder Chiou /* Global Definition */
1362b26dd4cSOder Chiou #define RT5660_L_MUTE				(0x1 << 15)
1372b26dd4cSOder Chiou #define RT5660_L_MUTE_SFT			15
1382b26dd4cSOder Chiou #define RT5660_VOL_L_MUTE			(0x1 << 14)
1392b26dd4cSOder Chiou #define RT5660_VOL_L_SFT			14
1402b26dd4cSOder Chiou #define RT5660_R_MUTE				(0x1 << 7)
1412b26dd4cSOder Chiou #define RT5660_R_MUTE_SFT			7
1422b26dd4cSOder Chiou #define RT5660_VOL_R_MUTE			(0x1 << 6)
1432b26dd4cSOder Chiou #define RT5660_VOL_R_SFT			6
1442b26dd4cSOder Chiou #define RT5660_L_VOL_MASK			(0x3f << 8)
1452b26dd4cSOder Chiou #define RT5660_L_VOL_SFT			8
1462b26dd4cSOder Chiou #define RT5660_R_VOL_MASK			(0x3f)
1472b26dd4cSOder Chiou #define RT5660_R_VOL_SFT			0
1482b26dd4cSOder Chiou 
1492b26dd4cSOder Chiou /* IN1 and IN2 Control (0x0d) */
1502b26dd4cSOder Chiou #define RT5660_IN_DF1				(0x1 << 15)
1512b26dd4cSOder Chiou #define RT5660_IN_SFT1				15
1522b26dd4cSOder Chiou #define RT5660_BST_MASK1			(0x7f << 8)
1532b26dd4cSOder Chiou #define RT5660_BST_SFT1				8
1542b26dd4cSOder Chiou #define RT5660_IN_DF2				(0x1 << 7)
1552b26dd4cSOder Chiou #define RT5660_IN_SFT2				7
1562b26dd4cSOder Chiou #define RT5660_BST_MASK2			(0x7f << 0)
1572b26dd4cSOder Chiou #define RT5660_BST_SFT2				0
1582b26dd4cSOder Chiou 
1592b26dd4cSOder Chiou /* IN3 and IN4 Control (0x0e) */
1602b26dd4cSOder Chiou #define RT5660_IN_DF3				(0x1 << 15)
1612b26dd4cSOder Chiou #define RT5660_IN_SFT3				15
1622b26dd4cSOder Chiou #define RT5660_BST_MASK3			(0x7f << 8)
1632b26dd4cSOder Chiou #define RT5660_BST_SFT3				8
1642b26dd4cSOder Chiou #define RT5660_IN_DF4				(0x1 << 7)
1652b26dd4cSOder Chiou #define RT5660_IN_SFT4				7
1662b26dd4cSOder Chiou #define RT5660_BST_MASK4			(0x7f << 0)
1672b26dd4cSOder Chiou #define RT5660_BST_SFT4				0
1682b26dd4cSOder Chiou 
1692b26dd4cSOder Chiou /* DAC1 Digital Volume (0x19) */
1702b26dd4cSOder Chiou #define RT5660_DAC_L1_VOL_MASK			(0x7f << 9)
1712b26dd4cSOder Chiou #define RT5660_DAC_L1_VOL_SFT			9
1722b26dd4cSOder Chiou #define RT5660_DAC_R1_VOL_MASK			(0x7f << 1)
1732b26dd4cSOder Chiou #define RT5660_DAC_R1_VOL_SFT			1
1742b26dd4cSOder Chiou 
1752b26dd4cSOder Chiou /* ADC Digital Volume Control (0x1c) */
1762b26dd4cSOder Chiou #define RT5660_ADC_L_VOL_MASK			(0x3f << 9)
1772b26dd4cSOder Chiou #define RT5660_ADC_L_VOL_SFT			9
1782b26dd4cSOder Chiou #define RT5660_ADC_R_VOL_MASK			(0x3f << 1)
1792b26dd4cSOder Chiou #define RT5660_ADC_R_VOL_SFT			1
1802b26dd4cSOder Chiou 
1812b26dd4cSOder Chiou /* ADC Boost Volume Control (0x1e) */
1822b26dd4cSOder Chiou #define RT5660_STO1_ADC_L_BST_MASK		(0x3 << 14)
1832b26dd4cSOder Chiou #define RT5660_STO1_ADC_L_BST_SFT		14
1842b26dd4cSOder Chiou #define RT5660_STO1_ADC_R_BST_MASK		(0x3 << 12)
1852b26dd4cSOder Chiou #define RT5660_STO1_ADC_R_BST_SFT		12
1862b26dd4cSOder Chiou 
1872b26dd4cSOder Chiou /* Stereo ADC Mixer Control (0x27) */
1882b26dd4cSOder Chiou #define RT5660_M_ADC_L1				(0x1 << 14)
1892b26dd4cSOder Chiou #define RT5660_M_ADC_L1_SFT			14
1902b26dd4cSOder Chiou #define RT5660_M_ADC_L2				(0x1 << 13)
1912b26dd4cSOder Chiou #define RT5660_M_ADC_L2_SFT			13
1922b26dd4cSOder Chiou #define RT5660_M_ADC_R1				(0x1 << 6)
1932b26dd4cSOder Chiou #define RT5660_M_ADC_R1_SFT			6
1942b26dd4cSOder Chiou #define RT5660_M_ADC_R2				(0x1 << 5)
1952b26dd4cSOder Chiou #define RT5660_M_ADC_R2_SFT			5
1962b26dd4cSOder Chiou 
1972b26dd4cSOder Chiou /* ADC Mixer to DAC Mixer Control (0x29) */
1982b26dd4cSOder Chiou #define RT5660_M_ADCMIX_L			(0x1 << 15)
1992b26dd4cSOder Chiou #define RT5660_M_ADCMIX_L_SFT			15
2002b26dd4cSOder Chiou #define RT5660_M_DAC1_L				(0x1 << 14)
2012b26dd4cSOder Chiou #define RT5660_M_DAC1_L_SFT			14
2022b26dd4cSOder Chiou #define RT5660_M_ADCMIX_R			(0x1 << 7)
2032b26dd4cSOder Chiou #define RT5660_M_ADCMIX_R_SFT			7
2042b26dd4cSOder Chiou #define RT5660_M_DAC1_R				(0x1 << 6)
2052b26dd4cSOder Chiou #define RT5660_M_DAC1_R_SFT			6
2062b26dd4cSOder Chiou 
2072b26dd4cSOder Chiou /* Stereo DAC Mixer Control (0x2a) */
2082b26dd4cSOder Chiou #define RT5660_M_DAC_L1				(0x1 << 14)
2092b26dd4cSOder Chiou #define RT5660_M_DAC_L1_SFT			14
2102b26dd4cSOder Chiou #define RT5660_DAC_L1_STO_L_VOL_MASK		(0x1 << 13)
2112b26dd4cSOder Chiou #define RT5660_DAC_L1_STO_L_VOL_SFT		13
2122b26dd4cSOder Chiou #define RT5660_M_DAC_R1_STO_L			(0x1 << 9)
2132b26dd4cSOder Chiou #define RT5660_M_DAC_R1_STO_L_SFT		9
2142b26dd4cSOder Chiou #define RT5660_DAC_R1_STO_L_VOL_MASK		(0x1 << 8)
2152b26dd4cSOder Chiou #define RT5660_DAC_R1_STO_L_VOL_SFT		8
2162b26dd4cSOder Chiou #define RT5660_M_DAC_R1				(0x1 << 6)
2172b26dd4cSOder Chiou #define RT5660_M_DAC_R1_SFT			6
2182b26dd4cSOder Chiou #define RT5660_DAC_R1_STO_R_VOL_MASK		(0x1 << 5)
2192b26dd4cSOder Chiou #define RT5660_DAC_R1_STO_R_VOL_SFT		5
2202b26dd4cSOder Chiou #define RT5660_M_DAC_L1_STO_R			(0x1 << 1)
2212b26dd4cSOder Chiou #define RT5660_M_DAC_L1_STO_R_SFT		1
2222b26dd4cSOder Chiou #define RT5660_DAC_L1_STO_R_VOL_MASK		(0x1)
2232b26dd4cSOder Chiou #define RT5660_DAC_L1_STO_R_VOL_SFT		0
2242b26dd4cSOder Chiou 
2252b26dd4cSOder Chiou /* Digital Interface Data Control (0x2f) */
2262b26dd4cSOder Chiou #define RT5660_IF1_DAC_IN_SEL			(0x3 << 14)
2272b26dd4cSOder Chiou #define RT5660_IF1_DAC_IN_SFT			14
2282b26dd4cSOder Chiou #define RT5660_IF1_ADC_IN_SEL			(0x3 << 12)
2292b26dd4cSOder Chiou #define RT5660_IF1_ADC_IN_SFT			12
2302b26dd4cSOder Chiou 
2312b26dd4cSOder Chiou /* REC Left Mixer Control 1 (0x3b) */
2322b26dd4cSOder Chiou #define RT5660_G_BST3_RM_L_MASK			(0x7 << 4)
2332b26dd4cSOder Chiou #define RT5660_G_BST3_RM_L_SFT			4
2342b26dd4cSOder Chiou #define RT5660_G_BST2_RM_L_MASK			(0x7 << 1)
2352b26dd4cSOder Chiou #define RT5660_G_BST2_RM_L_SFT			1
2362b26dd4cSOder Chiou 
2372b26dd4cSOder Chiou /* REC Left Mixer Control 2 (0x3c) */
2382b26dd4cSOder Chiou #define RT5660_G_BST1_RM_L_MASK			(0x7 << 13)
2392b26dd4cSOder Chiou #define RT5660_G_BST1_RM_L_SFT			13
2402b26dd4cSOder Chiou #define RT5660_G_OM_L_RM_L_MASK			(0x7 << 10)
2412b26dd4cSOder Chiou #define RT5660_G_OM_L_RM_L_SFT			10
2422b26dd4cSOder Chiou #define RT5660_M_BST3_RM_L			(0x1 << 3)
2432b26dd4cSOder Chiou #define RT5660_M_BST3_RM_L_SFT			3
2442b26dd4cSOder Chiou #define RT5660_M_BST2_RM_L			(0x1 << 2)
2452b26dd4cSOder Chiou #define RT5660_M_BST2_RM_L_SFT			2
2462b26dd4cSOder Chiou #define RT5660_M_BST1_RM_L			(0x1 << 1)
2472b26dd4cSOder Chiou #define RT5660_M_BST1_RM_L_SFT			1
2482b26dd4cSOder Chiou #define RT5660_M_OM_L_RM_L			(0x1)
2492b26dd4cSOder Chiou #define RT5660_M_OM_L_RM_L_SFT			0
2502b26dd4cSOder Chiou 
2512b26dd4cSOder Chiou /* REC Right Mixer Control 1 (0x3d) */
2522b26dd4cSOder Chiou #define RT5660_G_BST3_RM_R_MASK			(0x7 << 4)
2532b26dd4cSOder Chiou #define RT5660_G_BST3_RM_R_SFT			4
2542b26dd4cSOder Chiou #define RT5660_G_BST2_RM_R_MASK			(0x7 << 1)
2552b26dd4cSOder Chiou #define RT5660_G_BST2_RM_R_SFT			1
2562b26dd4cSOder Chiou 
2572b26dd4cSOder Chiou /* REC Right Mixer Control 2 (0x3e) */
2582b26dd4cSOder Chiou #define RT5660_G_BST1_RM_R_MASK			(0x7 << 13)
2592b26dd4cSOder Chiou #define RT5660_G_BST1_RM_R_SFT			13
2602b26dd4cSOder Chiou #define RT5660_G_OM_R_RM_R_MASK			(0x7 << 10)
2612b26dd4cSOder Chiou #define RT5660_G_OM_R_RM_R_SFT			10
2622b26dd4cSOder Chiou #define RT5660_M_BST3_RM_R			(0x1 << 3)
2632b26dd4cSOder Chiou #define RT5660_M_BST3_RM_R_SFT			3
2642b26dd4cSOder Chiou #define RT5660_M_BST2_RM_R			(0x1 << 2)
2652b26dd4cSOder Chiou #define RT5660_M_BST2_RM_R_SFT			2
2662b26dd4cSOder Chiou #define RT5660_M_BST1_RM_R			(0x1 << 1)
2672b26dd4cSOder Chiou #define RT5660_M_BST1_RM_R_SFT			1
2682b26dd4cSOder Chiou #define RT5660_M_OM_R_RM_R			(0x1)
2692b26dd4cSOder Chiou #define RT5660_M_OM_R_RM_R_SFT			0
2702b26dd4cSOder Chiou 
2712b26dd4cSOder Chiou /* LOUTMIX Control (0x45) */
2722b26dd4cSOder Chiou #define RT5660_M_DAC1_LM			(0x1 << 14)
2732b26dd4cSOder Chiou #define RT5660_M_DAC1_LM_SFT			14
2742b26dd4cSOder Chiou #define RT5660_M_LOVOL_M			(0x1 << 13)
2752b26dd4cSOder Chiou #define RT5660_M_LOVOL_LM_SFT			13
2762b26dd4cSOder Chiou 
2772b26dd4cSOder Chiou /* SPK Mixer Control (0x46) */
2782b26dd4cSOder Chiou #define RT5660_G_BST3_SM_MASK			(0x3 << 14)
2792b26dd4cSOder Chiou #define RT5660_G_BST3_SM_SFT			14
2802b26dd4cSOder Chiou #define RT5660_G_BST1_SM_MASK			(0x3 << 12)
2812b26dd4cSOder Chiou #define RT5660_G_BST1_SM_SFT			12
2822b26dd4cSOder Chiou #define RT5660_G_DACl_SM_MASK			(0x3 << 10)
2832b26dd4cSOder Chiou #define RT5660_G_DACl_SM_SFT			10
2842b26dd4cSOder Chiou #define RT5660_G_DACR_SM_MASK			(0x3 << 8)
2852b26dd4cSOder Chiou #define RT5660_G_DACR_SM_SFT			8
2862b26dd4cSOder Chiou #define RT5660_G_OM_L_SM_MASK			(0x3 << 6)
2872b26dd4cSOder Chiou #define RT5660_G_OM_L_SM_SFT			6
2882b26dd4cSOder Chiou #define RT5660_M_DACR_SM			(0x1 << 5)
2892b26dd4cSOder Chiou #define RT5660_M_DACR_SM_SFT			5
2902b26dd4cSOder Chiou #define RT5660_M_BST1_SM			(0x1 << 4)
2912b26dd4cSOder Chiou #define RT5660_M_BST1_SM_SFT			4
2922b26dd4cSOder Chiou #define RT5660_M_BST3_SM			(0x1 << 3)
2932b26dd4cSOder Chiou #define RT5660_M_BST3_SM_SFT			3
2942b26dd4cSOder Chiou #define RT5660_M_DACL_SM			(0x1 << 2)
2952b26dd4cSOder Chiou #define RT5660_M_DACL_SM_SFT			2
2962b26dd4cSOder Chiou #define RT5660_M_OM_L_SM			(0x1 << 1)
2972b26dd4cSOder Chiou #define RT5660_M_OM_L_SM_SFT			1
2982b26dd4cSOder Chiou 
2992b26dd4cSOder Chiou /* SPOMIX Control (0x48) */
3002b26dd4cSOder Chiou #define RT5660_M_DAC_R_SPM			(0x1 << 14)
3012b26dd4cSOder Chiou #define RT5660_M_DAC_R_SPM_SFT			14
3022b26dd4cSOder Chiou #define RT5660_M_DAC_L_SPM			(0x1 << 13)
3032b26dd4cSOder Chiou #define RT5660_M_DAC_L_SPM_SFT			13
3042b26dd4cSOder Chiou #define RT5660_M_SV_SPM				(0x1 << 12)
3052b26dd4cSOder Chiou #define RT5660_M_SV_SPM_SFT			12
3062b26dd4cSOder Chiou #define RT5660_M_BST1_SPM			(0x1 << 11)
3072b26dd4cSOder Chiou #define RT5660_M_BST1_SPM_SFT			11
3082b26dd4cSOder Chiou 
3092b26dd4cSOder Chiou /* Output Left Mixer Control 1 (0x4d) */
3102b26dd4cSOder Chiou #define RT5660_G_BST3_OM_L_MASK			(0x7 << 13)
3112b26dd4cSOder Chiou #define RT5660_G_BST3_OM_L_SFT			13
3122b26dd4cSOder Chiou #define RT5660_G_BST2_OM_L_MASK			(0x7 << 10)
3132b26dd4cSOder Chiou #define RT5660_G_BST2_OM_L_SFT			10
3142b26dd4cSOder Chiou #define RT5660_G_BST1_OM_L_MASK			(0x7 << 7)
3152b26dd4cSOder Chiou #define RT5660_G_BST1_OM_L_SFT			7
3162b26dd4cSOder Chiou #define RT5660_G_RM_L_OM_L_MASK			(0x7 << 1)
3172b26dd4cSOder Chiou #define RT5660_G_RM_L_OM_L_SFT			1
3182b26dd4cSOder Chiou 
3192b26dd4cSOder Chiou /* Output Left Mixer Control 2 (0x4e) */
3202b26dd4cSOder Chiou #define RT5660_G_DAC_R1_OM_L_MASK		(0x7 << 10)
3212b26dd4cSOder Chiou #define RT5660_G_DAC_R1_OM_L_SFT		10
3222b26dd4cSOder Chiou #define RT5660_G_DAC_L1_OM_L_MASK		(0x7 << 7)
3232b26dd4cSOder Chiou #define RT5660_G_DAC_L1_OM_L_SFT		7
3242b26dd4cSOder Chiou 
3252b26dd4cSOder Chiou /* Output Left Mixer Control 3 (0x4f) */
3262b26dd4cSOder Chiou #define RT5660_M_BST3_OM_L			(0x1 << 5)
3272b26dd4cSOder Chiou #define RT5660_M_BST3_OM_L_SFT			5
3282b26dd4cSOder Chiou #define RT5660_M_BST2_OM_L			(0x1 << 4)
3292b26dd4cSOder Chiou #define RT5660_M_BST2_OM_L_SFT			4
3302b26dd4cSOder Chiou #define RT5660_M_BST1_OM_L			(0x1 << 3)
3312b26dd4cSOder Chiou #define RT5660_M_BST1_OM_L_SFT			3
3322b26dd4cSOder Chiou #define RT5660_M_RM_L_OM_L			(0x1 << 2)
3332b26dd4cSOder Chiou #define RT5660_M_RM_L_OM_L_SFT			2
3342b26dd4cSOder Chiou #define RT5660_M_DAC_R_OM_L			(0x1 << 1)
3352b26dd4cSOder Chiou #define RT5660_M_DAC_R_OM_L_SFT			1
3362b26dd4cSOder Chiou #define RT5660_M_DAC_L_OM_L			(0x1)
3372b26dd4cSOder Chiou #define RT5660_M_DAC_L_OM_L_SFT			0
3382b26dd4cSOder Chiou 
3392b26dd4cSOder Chiou /* Output Right Mixer Control 1 (0x50) */
3402b26dd4cSOder Chiou #define RT5660_G_BST2_OM_R_MASK			(0x7 << 10)
3412b26dd4cSOder Chiou #define RT5660_G_BST2_OM_R_SFT			10
3422b26dd4cSOder Chiou #define RT5660_G_BST1_OM_R_MASK			(0x7 << 7)
3432b26dd4cSOder Chiou #define RT5660_G_BST1_OM_R_SFT			7
3442b26dd4cSOder Chiou #define RT5660_G_RM_R_OM_R_MASK			(0x7 << 1)
3452b26dd4cSOder Chiou #define RT5660_G_RM_R_OM_R_SFT			1
3462b26dd4cSOder Chiou 
3472b26dd4cSOder Chiou /* Output Right Mixer Control 2 (0x51) */
3482b26dd4cSOder Chiou #define RT5660_G_DAC_L_OM_R_MASK		(0x7 << 10)
3492b26dd4cSOder Chiou #define RT5660_G_DAC_L_OM_R_SFT			10
3502b26dd4cSOder Chiou #define RT5660_G_DAC_R_OM_R_MASK		(0x7 << 7)
3512b26dd4cSOder Chiou #define RT5660_G_DAC_R_OM_R_SFT			7
3522b26dd4cSOder Chiou 
3532b26dd4cSOder Chiou /* Output Right Mixer Control 3 (0x52) */
3542b26dd4cSOder Chiou #define RT5660_M_BST2_OM_R			(0x1 << 4)
3552b26dd4cSOder Chiou #define RT5660_M_BST2_OM_R_SFT			4
3562b26dd4cSOder Chiou #define RT5660_M_BST1_OM_R			(0x1 << 3)
3572b26dd4cSOder Chiou #define RT5660_M_BST1_OM_R_SFT			3
3582b26dd4cSOder Chiou #define RT5660_M_RM_R_OM_R			(0x1 << 2)
3592b26dd4cSOder Chiou #define RT5660_M_RM_R_OM_R_SFT			2
3602b26dd4cSOder Chiou #define RT5660_M_DAC_L_OM_R			(0x1 << 1)
3612b26dd4cSOder Chiou #define RT5660_M_DAC_L_OM_R_SFT			1
3622b26dd4cSOder Chiou #define RT5660_M_DAC_R_OM_R			(0x1)
3632b26dd4cSOder Chiou #define RT5660_M_DAC_R_OM_R_SFT			0
3642b26dd4cSOder Chiou 
3652b26dd4cSOder Chiou /* Power Management for Digital 1 (0x61) */
3662b26dd4cSOder Chiou #define RT5660_PWR_I2S1				(0x1 << 15)
3672b26dd4cSOder Chiou #define RT5660_PWR_I2S1_BIT			15
3682b26dd4cSOder Chiou #define RT5660_PWR_DAC_L1			(0x1 << 12)
3692b26dd4cSOder Chiou #define RT5660_PWR_DAC_L1_BIT			12
3702b26dd4cSOder Chiou #define RT5660_PWR_DAC_R1			(0x1 << 11)
3712b26dd4cSOder Chiou #define RT5660_PWR_DAC_R1_BIT			11
3722b26dd4cSOder Chiou #define RT5660_PWR_ADC_L			(0x1 << 2)
3732b26dd4cSOder Chiou #define RT5660_PWR_ADC_L_BIT			2
3742b26dd4cSOder Chiou #define RT5660_PWR_ADC_R			(0x1 << 1)
3752b26dd4cSOder Chiou #define RT5660_PWR_ADC_R_BIT			1
3762b26dd4cSOder Chiou #define RT5660_PWR_CLS_D			(0x1)
3772b26dd4cSOder Chiou #define RT5660_PWR_CLS_D_BIT			0
3782b26dd4cSOder Chiou 
3792b26dd4cSOder Chiou /* Power Management for Digital 2 (0x62) */
3802b26dd4cSOder Chiou #define RT5660_PWR_ADC_S1F			(0x1 << 15)
3812b26dd4cSOder Chiou #define RT5660_PWR_ADC_S1F_BIT			15
3822b26dd4cSOder Chiou #define RT5660_PWR_DAC_S1F			(0x1 << 11)
3832b26dd4cSOder Chiou #define RT5660_PWR_DAC_S1F_BIT			11
3842b26dd4cSOder Chiou 
3852b26dd4cSOder Chiou /* Power Management for Analog 1 (0x63) */
3862b26dd4cSOder Chiou #define RT5660_PWR_VREF1			(0x1 << 15)
3872b26dd4cSOder Chiou #define RT5660_PWR_VREF1_BIT			15
3882b26dd4cSOder Chiou #define RT5660_PWR_FV1				(0x1 << 14)
3892b26dd4cSOder Chiou #define RT5660_PWR_FV1_BIT			14
3902b26dd4cSOder Chiou #define RT5660_PWR_MB				(0x1 << 13)
3912b26dd4cSOder Chiou #define RT5660_PWR_MB_BIT			13
3922b26dd4cSOder Chiou #define RT5660_PWR_BG				(0x1 << 11)
3932b26dd4cSOder Chiou #define RT5660_PWR_BG_BIT			11
3942b26dd4cSOder Chiou #define RT5660_PWR_HP_L				(0x1 << 7)
3952b26dd4cSOder Chiou #define RT5660_PWR_HP_L_BIT			7
3962b26dd4cSOder Chiou #define RT5660_PWR_HP_R				(0x1 << 6)
3972b26dd4cSOder Chiou #define RT5660_PWR_HP_R_BIT			6
3982b26dd4cSOder Chiou #define RT5660_PWR_HA				(0x1 << 5)
3992b26dd4cSOder Chiou #define RT5660_PWR_HA_BIT			5
4002b26dd4cSOder Chiou #define RT5660_PWR_VREF2			(0x1 << 4)
4012b26dd4cSOder Chiou #define RT5660_PWR_VREF2_BIT			4
4022b26dd4cSOder Chiou #define RT5660_PWR_FV2				(0x1 << 3)
4032b26dd4cSOder Chiou #define RT5660_PWR_FV2_BIT			3
4042b26dd4cSOder Chiou #define RT5660_PWR_LDO2				(0x1 << 2)
4052b26dd4cSOder Chiou #define RT5660_PWR_LDO2_BIT			2
4062b26dd4cSOder Chiou 
4072b26dd4cSOder Chiou /* Power Management for Analog 2 (0x64) */
4082b26dd4cSOder Chiou #define RT5660_PWR_BST1				(0x1 << 15)
4092b26dd4cSOder Chiou #define RT5660_PWR_BST1_BIT			15
4102b26dd4cSOder Chiou #define RT5660_PWR_BST2				(0x1 << 14)
4112b26dd4cSOder Chiou #define RT5660_PWR_BST2_BIT			14
4122b26dd4cSOder Chiou #define RT5660_PWR_BST3				(0x1 << 13)
4132b26dd4cSOder Chiou #define RT5660_PWR_BST3_BIT			13
4142b26dd4cSOder Chiou #define RT5660_PWR_MB1				(0x1 << 11)
4152b26dd4cSOder Chiou #define RT5660_PWR_MB1_BIT			11
4162b26dd4cSOder Chiou #define RT5660_PWR_MB2				(0x1 << 10)
4172b26dd4cSOder Chiou #define RT5660_PWR_MB2_BIT			10
4182b26dd4cSOder Chiou #define RT5660_PWR_PLL				(0x1 << 9)
4192b26dd4cSOder Chiou #define RT5660_PWR_PLL_BIT			9
4202b26dd4cSOder Chiou 
4212b26dd4cSOder Chiou /* Power Management for Mixer (0x65) */
4222b26dd4cSOder Chiou #define RT5660_PWR_OM_L				(0x1 << 15)
4232b26dd4cSOder Chiou #define RT5660_PWR_OM_L_BIT			15
4242b26dd4cSOder Chiou #define RT5660_PWR_OM_R				(0x1 << 14)
4252b26dd4cSOder Chiou #define RT5660_PWR_OM_R_BIT			14
4262b26dd4cSOder Chiou #define RT5660_PWR_SM				(0x1 << 13)
4272b26dd4cSOder Chiou #define RT5660_PWR_SM_BIT			13
4282b26dd4cSOder Chiou #define RT5660_PWR_RM_L				(0x1 << 11)
4292b26dd4cSOder Chiou #define RT5660_PWR_RM_L_BIT			11
4302b26dd4cSOder Chiou #define RT5660_PWR_RM_R				(0x1 << 10)
4312b26dd4cSOder Chiou #define RT5660_PWR_RM_R_BIT			10
4322b26dd4cSOder Chiou 
4332b26dd4cSOder Chiou /* Power Management for Volume (0x66) */
4342b26dd4cSOder Chiou #define RT5660_PWR_SV				(0x1 << 15)
4352b26dd4cSOder Chiou #define RT5660_PWR_SV_BIT			15
4362b26dd4cSOder Chiou #define RT5660_PWR_LV_L				(0x1 << 11)
4372b26dd4cSOder Chiou #define RT5660_PWR_LV_L_BIT			11
4382b26dd4cSOder Chiou #define RT5660_PWR_LV_R				(0x1 << 10)
4392b26dd4cSOder Chiou #define RT5660_PWR_LV_R_BIT			10
4402b26dd4cSOder Chiou 
4412b26dd4cSOder Chiou /* I2S1 Audio Serial Data Port Control (0x70) */
4422b26dd4cSOder Chiou #define RT5660_I2S_MS_MASK			(0x1 << 15)
4432b26dd4cSOder Chiou #define RT5660_I2S_MS_SFT			15
4442b26dd4cSOder Chiou #define RT5660_I2S_MS_M				(0x0 << 15)
4452b26dd4cSOder Chiou #define RT5660_I2S_MS_S				(0x1 << 15)
4462b26dd4cSOder Chiou #define RT5660_I2S_O_CP_MASK			(0x3 << 10)
4472b26dd4cSOder Chiou #define RT5660_I2S_O_CP_SFT			10
4482b26dd4cSOder Chiou #define RT5660_I2S_O_CP_OFF			(0x0 << 10)
4492b26dd4cSOder Chiou #define RT5660_I2S_O_CP_U_LAW			(0x1 << 10)
4502b26dd4cSOder Chiou #define RT5660_I2S_O_CP_A_LAW			(0x2 << 10)
4512b26dd4cSOder Chiou #define RT5660_I2S_I_CP_MASK			(0x3 << 8)
4522b26dd4cSOder Chiou #define RT5660_I2S_I_CP_SFT			8
4532b26dd4cSOder Chiou #define RT5660_I2S_I_CP_OFF			(0x0 << 8)
4542b26dd4cSOder Chiou #define RT5660_I2S_I_CP_U_LAW			(0x1 << 8)
4552b26dd4cSOder Chiou #define RT5660_I2S_I_CP_A_LAW			(0x2 << 8)
4562b26dd4cSOder Chiou #define RT5660_I2S_BP_MASK			(0x1 << 7)
4572b26dd4cSOder Chiou #define RT5660_I2S_BP_SFT			7
4582b26dd4cSOder Chiou #define RT5660_I2S_BP_NOR			(0x0 << 7)
4592b26dd4cSOder Chiou #define RT5660_I2S_BP_INV			(0x1 << 7)
4602b26dd4cSOder Chiou #define RT5660_I2S_DL_MASK			(0x3 << 2)
4612b26dd4cSOder Chiou #define RT5660_I2S_DL_SFT			2
4622b26dd4cSOder Chiou #define RT5660_I2S_DL_16			(0x0 << 2)
4632b26dd4cSOder Chiou #define RT5660_I2S_DL_20			(0x1 << 2)
4642b26dd4cSOder Chiou #define RT5660_I2S_DL_24			(0x2 << 2)
4652b26dd4cSOder Chiou #define RT5660_I2S_DL_8				(0x3 << 2)
4662b26dd4cSOder Chiou #define RT5660_I2S_DF_MASK			(0x3)
4672b26dd4cSOder Chiou #define RT5660_I2S_DF_SFT			0
4682b26dd4cSOder Chiou #define RT5660_I2S_DF_I2S			(0x0)
4692b26dd4cSOder Chiou #define RT5660_I2S_DF_LEFT			(0x1)
4702b26dd4cSOder Chiou #define RT5660_I2S_DF_PCM_A			(0x2)
4712b26dd4cSOder Chiou #define RT5660_I2S_DF_PCM_B			(0x3)
4722b26dd4cSOder Chiou 
4732b26dd4cSOder Chiou /* ADC/DAC Clock Control 1 (0x73) */
4742b26dd4cSOder Chiou #define RT5660_I2S_BCLK_MS1_MASK		(0x1 << 15)
4752b26dd4cSOder Chiou #define RT5660_I2S_BCLK_MS1_SFT			15
4762b26dd4cSOder Chiou #define RT5660_I2S_BCLK_MS1_32			(0x0 << 15)
4772b26dd4cSOder Chiou #define RT5660_I2S_BCLK_MS1_64			(0x1 << 15)
4782b26dd4cSOder Chiou #define RT5660_I2S_PD1_MASK			(0x7 << 12)
4792b26dd4cSOder Chiou #define RT5660_I2S_PD1_SFT			12
4802b26dd4cSOder Chiou #define RT5660_I2S_PD1_1			(0x0 << 12)
4812b26dd4cSOder Chiou #define RT5660_I2S_PD1_2			(0x1 << 12)
4822b26dd4cSOder Chiou #define RT5660_I2S_PD1_3			(0x2 << 12)
4832b26dd4cSOder Chiou #define RT5660_I2S_PD1_4			(0x3 << 12)
4842b26dd4cSOder Chiou #define RT5660_I2S_PD1_6			(0x4 << 12)
4852b26dd4cSOder Chiou #define RT5660_I2S_PD1_8			(0x5 << 12)
4862b26dd4cSOder Chiou #define RT5660_I2S_PD1_12			(0x6 << 12)
4872b26dd4cSOder Chiou #define RT5660_I2S_PD1_16			(0x7 << 12)
4882b26dd4cSOder Chiou #define RT5660_DAC_OSR_MASK			(0x3 << 2)
4892b26dd4cSOder Chiou #define RT5660_DAC_OSR_SFT			2
4902b26dd4cSOder Chiou #define RT5660_DAC_OSR_128			(0x0 << 2)
4912b26dd4cSOder Chiou #define RT5660_DAC_OSR_64			(0x1 << 2)
4922b26dd4cSOder Chiou #define RT5660_DAC_OSR_32			(0x2 << 2)
4932b26dd4cSOder Chiou #define RT5660_DAC_OSR_16			(0x3 << 2)
4942b26dd4cSOder Chiou #define RT5660_ADC_OSR_MASK			(0x3)
4952b26dd4cSOder Chiou #define RT5660_ADC_OSR_SFT			0
4962b26dd4cSOder Chiou #define RT5660_ADC_OSR_128			(0x0)
4972b26dd4cSOder Chiou #define RT5660_ADC_OSR_64			(0x1)
4982b26dd4cSOder Chiou #define RT5660_ADC_OSR_32			(0x2)
4992b26dd4cSOder Chiou #define RT5660_ADC_OSR_16			(0x3)
5002b26dd4cSOder Chiou 
5012b26dd4cSOder Chiou /* ADC/DAC Clock Control 2 (0x74) */
5022b26dd4cSOder Chiou #define RT5660_RESET_ADF			(0x1 << 13)
5032b26dd4cSOder Chiou #define RT5660_RESET_ADF_SFT			13
5042b26dd4cSOder Chiou #define RT5660_RESET_DAF			(0x1 << 12)
5052b26dd4cSOder Chiou #define RT5660_RESET_DAF_SFT			12
5062b26dd4cSOder Chiou #define RT5660_DAHPF_EN				(0x1 << 11)
5072b26dd4cSOder Chiou #define RT5660_DAHPF_EN_SFT			11
5082b26dd4cSOder Chiou #define RT5660_ADHPF_EN				(0x1 << 10)
5092b26dd4cSOder Chiou #define RT5660_ADHPF_EN_SFT			10
5102b26dd4cSOder Chiou 
5112b26dd4cSOder Chiou /* Digital Microphone Control (0x75) */
5122b26dd4cSOder Chiou #define RT5660_DMIC_1_EN_MASK			(0x1 << 15)
5132b26dd4cSOder Chiou #define RT5660_DMIC_1_EN_SFT			15
5142b26dd4cSOder Chiou #define RT5660_DMIC_1_DIS			(0x0 << 15)
5152b26dd4cSOder Chiou #define RT5660_DMIC_1_EN			(0x1 << 15)
5162b26dd4cSOder Chiou #define RT5660_DMIC_1L_LH_MASK			(0x1 << 13)
5172b26dd4cSOder Chiou #define RT5660_DMIC_1L_LH_SFT			13
5182b26dd4cSOder Chiou #define RT5660_DMIC_1L_LH_RISING		(0x0 << 13)
5192b26dd4cSOder Chiou #define RT5660_DMIC_1L_LH_FALLING		(0x1 << 13)
5202b26dd4cSOder Chiou #define RT5660_DMIC_1R_LH_MASK			(0x1 << 12)
5212b26dd4cSOder Chiou #define RT5660_DMIC_1R_LH_SFT			12
5222b26dd4cSOder Chiou #define RT5660_DMIC_1R_LH_RISING		(0x0 << 12)
5232b26dd4cSOder Chiou #define RT5660_DMIC_1R_LH_FALLING		(0x1 << 12)
5242b26dd4cSOder Chiou #define RT5660_SEL_DMIC_DATA_MASK		(0x1 << 11)
5252b26dd4cSOder Chiou #define RT5660_SEL_DMIC_DATA_SFT		11
5262b26dd4cSOder Chiou #define RT5660_SEL_DMIC_DATA_GPIO2		(0x0 << 11)
5272b26dd4cSOder Chiou #define RT5660_SEL_DMIC_DATA_IN1P		(0x1 << 11)
5282b26dd4cSOder Chiou #define RT5660_DMIC_CLK_MASK			(0x7 << 5)
5292b26dd4cSOder Chiou #define RT5660_DMIC_CLK_SFT			5
5302b26dd4cSOder Chiou 
5312b26dd4cSOder Chiou /* Global Clock Control (0x80) */
5322b26dd4cSOder Chiou #define RT5660_SCLK_SRC_MASK			(0x3 << 14)
5332b26dd4cSOder Chiou #define RT5660_SCLK_SRC_SFT			14
5342b26dd4cSOder Chiou #define RT5660_SCLK_SRC_MCLK			(0x0 << 14)
5352b26dd4cSOder Chiou #define RT5660_SCLK_SRC_PLL1			(0x1 << 14)
5362b26dd4cSOder Chiou #define RT5660_SCLK_SRC_RCCLK			(0x2 << 14)
5372b26dd4cSOder Chiou #define RT5660_PLL1_SRC_MASK			(0x3 << 12)
5382b26dd4cSOder Chiou #define RT5660_PLL1_SRC_SFT			12
5392b26dd4cSOder Chiou #define RT5660_PLL1_SRC_MCLK			(0x0 << 12)
5402b26dd4cSOder Chiou #define RT5660_PLL1_SRC_BCLK1			(0x1 << 12)
5412b26dd4cSOder Chiou #define RT5660_PLL1_SRC_RCCLK			(0x2 << 12)
5422b26dd4cSOder Chiou #define RT5660_PLL1_PD_MASK			(0x1 << 3)
5432b26dd4cSOder Chiou #define RT5660_PLL1_PD_SFT			3
5442b26dd4cSOder Chiou #define RT5660_PLL1_PD_1			(0x0 << 3)
5452b26dd4cSOder Chiou #define RT5660_PLL1_PD_2			(0x1 << 3)
5462b26dd4cSOder Chiou 
5472b26dd4cSOder Chiou #define RT5660_PLL_INP_MAX			40000000
5482b26dd4cSOder Chiou #define RT5660_PLL_INP_MIN			256000
5492b26dd4cSOder Chiou /* PLL M/N/K Code Control 1 (0x81) */
5502b26dd4cSOder Chiou #define RT5660_PLL_N_MAX			0x1ff
5512b26dd4cSOder Chiou #define RT5660_PLL_N_MASK			(RT5660_PLL_N_MAX << 7)
5522b26dd4cSOder Chiou #define RT5660_PLL_N_SFT			7
5532b26dd4cSOder Chiou #define RT5660_PLL_K_MAX			0x1f
5542b26dd4cSOder Chiou #define RT5660_PLL_K_MASK			(RT5660_PLL_K_MAX)
5552b26dd4cSOder Chiou #define RT5660_PLL_K_SFT			0
5562b26dd4cSOder Chiou 
5572b26dd4cSOder Chiou /* PLL M/N/K Code Control 2 (0x82) */
5582b26dd4cSOder Chiou #define RT5660_PLL_M_MAX			0xf
5592b26dd4cSOder Chiou #define RT5660_PLL_M_MASK			(RT5660_PLL_M_MAX << 12)
5602b26dd4cSOder Chiou #define RT5660_PLL_M_SFT			12
5612b26dd4cSOder Chiou #define RT5660_PLL_M_BP				(0x1 << 11)
5622b26dd4cSOder Chiou #define RT5660_PLL_M_BP_SFT			11
5632b26dd4cSOder Chiou 
5642b26dd4cSOder Chiou /* Class D Over Current Control (0x8c) */
5652b26dd4cSOder Chiou #define RT5660_CLSD_OC_MASK			(0x1 << 9)
5662b26dd4cSOder Chiou #define RT5660_CLSD_OC_SFT			9
5672b26dd4cSOder Chiou #define RT5660_CLSD_OC_PU			(0x0 << 9)
5682b26dd4cSOder Chiou #define RT5660_CLSD_OC_PD			(0x1 << 9)
5692b26dd4cSOder Chiou #define RT5660_AUTO_PD_MASK			(0x1 << 8)
5702b26dd4cSOder Chiou #define RT5660_AUTO_PD_SFT			8
5712b26dd4cSOder Chiou #define RT5660_AUTO_PD_DIS			(0x0 << 8)
5722b26dd4cSOder Chiou #define RT5660_AUTO_PD_EN			(0x1 << 8)
5732b26dd4cSOder Chiou #define RT5660_CLSD_OC_TH_MASK			(0x3f)
5742b26dd4cSOder Chiou #define RT5660_CLSD_OC_TH_SFT			0
5752b26dd4cSOder Chiou 
5762b26dd4cSOder Chiou /* Class D Output Control (0x8d) */
5772b26dd4cSOder Chiou #define RT5660_CLSD_RATIO_MASK			(0xf << 12)
5782b26dd4cSOder Chiou #define RT5660_CLSD_RATIO_SFT			12
5792b26dd4cSOder Chiou 
5802b26dd4cSOder Chiou /* Lout Amp Control 1 (0x8e) */
5812b26dd4cSOder Chiou #define RT5660_LOUT_CO_MASK			(0x1 << 4)
5822b26dd4cSOder Chiou #define RT5660_LOUT_CO_SFT			4
5832b26dd4cSOder Chiou #define RT5660_LOUT_CO_DIS			(0x0 << 4)
5842b26dd4cSOder Chiou #define RT5660_LOUT_CO_EN			(0x1 << 4)
5852b26dd4cSOder Chiou #define RT5660_LOUT_CB_MASK			(0x1)
5862b26dd4cSOder Chiou #define RT5660_LOUT_CB_SFT			0
5872b26dd4cSOder Chiou #define RT5660_LOUT_CB_PD			(0x0)
5882b26dd4cSOder Chiou #define RT5660_LOUT_CB_PU			(0x1)
5892b26dd4cSOder Chiou 
5902b26dd4cSOder Chiou /* SPKVDD detection control (0x92) */
5912b26dd4cSOder Chiou #define RT5660_SPKVDD_DET_MASK			(0x1 << 15)
5922b26dd4cSOder Chiou #define RT5660_SPKVDD_DET_SFT			15
5932b26dd4cSOder Chiou #define RT5660_SPKVDD_DET_DIS			(0x0 << 15)
5942b26dd4cSOder Chiou #define RT5660_SPKVDD_DET_EN			(0x1 << 15)
5952b26dd4cSOder Chiou #define RT5660_SPK_AG_MASK			(0x1 << 14)
5962b26dd4cSOder Chiou #define RT5660_SPK_AG_SFT			14
5972b26dd4cSOder Chiou #define RT5660_SPK_AG_DIS			(0x0 << 14)
5982b26dd4cSOder Chiou #define RT5660_SPK_AG_EN			(0x1 << 14)
5992b26dd4cSOder Chiou 
6002b26dd4cSOder Chiou /* Micbias Control (0x93) */
6012b26dd4cSOder Chiou #define RT5660_MIC1_BS_MASK			(0x1 << 15)
6022b26dd4cSOder Chiou #define RT5660_MIC1_BS_SFT			15
6032b26dd4cSOder Chiou #define RT5660_MIC1_BS_9AV			(0x0 << 15)
6042b26dd4cSOder Chiou #define RT5660_MIC1_BS_75AV			(0x1 << 15)
6052b26dd4cSOder Chiou #define RT5660_MIC2_BS_MASK			(0x1 << 14)
6062b26dd4cSOder Chiou #define RT5660_MIC2_BS_SFT			14
6072b26dd4cSOder Chiou #define RT5660_MIC2_BS_9AV			(0x0 << 14)
6082b26dd4cSOder Chiou #define RT5660_MIC2_BS_75AV			(0x1 << 14)
6092b26dd4cSOder Chiou #define RT5660_MIC1_OVCD_MASK			(0x1 << 11)
6102b26dd4cSOder Chiou #define RT5660_MIC1_OVCD_SFT			11
6112b26dd4cSOder Chiou #define RT5660_MIC1_OVCD_DIS			(0x0 << 11)
6122b26dd4cSOder Chiou #define RT5660_MIC1_OVCD_EN			(0x1 << 11)
6132b26dd4cSOder Chiou #define RT5660_MIC1_OVTH_MASK			(0x3 << 9)
6142b26dd4cSOder Chiou #define RT5660_MIC1_OVTH_SFT			9
6152b26dd4cSOder Chiou #define RT5660_MIC1_OVTH_600UA			(0x0 << 9)
6162b26dd4cSOder Chiou #define RT5660_MIC1_OVTH_1500UA			(0x1 << 9)
6172b26dd4cSOder Chiou #define RT5660_MIC1_OVTH_2000UA			(0x2 << 9)
6182b26dd4cSOder Chiou #define RT5660_MIC2_OVCD_MASK			(0x1 << 8)
6192b26dd4cSOder Chiou #define RT5660_MIC2_OVCD_SFT			8
6202b26dd4cSOder Chiou #define RT5660_MIC2_OVCD_DIS			(0x0 << 8)
6212b26dd4cSOder Chiou #define RT5660_MIC2_OVCD_EN			(0x1 << 8)
6222b26dd4cSOder Chiou #define RT5660_MIC2_OVTH_MASK			(0x3 << 6)
6232b26dd4cSOder Chiou #define RT5660_MIC2_OVTH_SFT			6
6242b26dd4cSOder Chiou #define RT5660_MIC2_OVTH_600UA			(0x0 << 6)
6252b26dd4cSOder Chiou #define RT5660_MIC2_OVTH_1500UA			(0x1 << 6)
6262b26dd4cSOder Chiou #define RT5660_MIC2_OVTH_2000UA			(0x2 << 6)
6272b26dd4cSOder Chiou #define RT5660_PWR_CLK25M_MASK			(0x1 << 4)
6282b26dd4cSOder Chiou #define RT5660_PWR_CLK25M_SFT			4
6292b26dd4cSOder Chiou #define RT5660_PWR_CLK25M_PD			(0x0 << 4)
6302b26dd4cSOder Chiou #define RT5660_PWR_CLK25M_PU			(0x1 << 4)
6312b26dd4cSOder Chiou 
6322b26dd4cSOder Chiou /* EQ Control 1 (0xb0) */
6332b26dd4cSOder Chiou #define RT5660_EQ_SRC_MASK			(0x1 << 15)
6342b26dd4cSOder Chiou #define RT5660_EQ_SRC_SFT			15
6352b26dd4cSOder Chiou #define RT5660_EQ_SRC_DAC			(0x0 << 15)
6362b26dd4cSOder Chiou #define RT5660_EQ_SRC_ADC			(0x1 << 15)
6372b26dd4cSOder Chiou #define RT5660_EQ_UPD				(0x1 << 14)
6382b26dd4cSOder Chiou #define RT5660_EQ_UPD_BIT			14
6392b26dd4cSOder Chiou 
6402b26dd4cSOder Chiou /* Jack Detect Control (0xbb) */
6412b26dd4cSOder Chiou #define RT5660_JD_MASK				(0x3 << 14)
6422b26dd4cSOder Chiou #define RT5660_JD_SFT				14
6432b26dd4cSOder Chiou #define RT5660_JD_DIS				(0x0 << 14)
6442b26dd4cSOder Chiou #define RT5660_JD_GPIO1				(0x1 << 14)
6452b26dd4cSOder Chiou #define RT5660_JD_GPIO2				(0x2 << 14)
6462b26dd4cSOder Chiou #define RT5660_JD_LOUT_MASK			(0x1 << 11)
6472b26dd4cSOder Chiou #define RT5660_JD_LOUT_SFT			11
6482b26dd4cSOder Chiou #define RT5660_JD_LOUT_DIS			(0x0 << 11)
6492b26dd4cSOder Chiou #define RT5660_JD_LOUT_EN			(0x1 << 11)
6502b26dd4cSOder Chiou #define RT5660_JD_LOUT_TRG_MASK			(0x1 << 10)
6512b26dd4cSOder Chiou #define RT5660_JD_LOUT_TRG_SFT			10
6522b26dd4cSOder Chiou #define RT5660_JD_LOUT_TRG_LO			(0x0 << 10)
6532b26dd4cSOder Chiou #define RT5660_JD_LOUT_TRG_HI			(0x1 << 10)
6542b26dd4cSOder Chiou #define RT5660_JD_SPO_MASK			(0x1 << 9)
6552b26dd4cSOder Chiou #define RT5660_JD_SPO_SFT			9
6562b26dd4cSOder Chiou #define RT5660_JD_SPO_DIS			(0x0 << 9)
6572b26dd4cSOder Chiou #define RT5660_JD_SPO_EN			(0x1 << 9)
6582b26dd4cSOder Chiou #define RT5660_JD_SPO_TRG_MASK			(0x1 << 8)
6592b26dd4cSOder Chiou #define RT5660_JD_SPO_TRG_SFT			8
6602b26dd4cSOder Chiou #define RT5660_JD_SPO_TRG_LO			(0x0 << 8)
6612b26dd4cSOder Chiou #define RT5660_JD_SPO_TRG_HI			(0x1 << 8)
6622b26dd4cSOder Chiou 
6632b26dd4cSOder Chiou /* IRQ Control 1 (0xbd) */
6642b26dd4cSOder Chiou #define RT5660_IRQ_JD_MASK			(0x1 << 15)
6652b26dd4cSOder Chiou #define RT5660_IRQ_JD_SFT			15
6662b26dd4cSOder Chiou #define RT5660_IRQ_JD_BP			(0x0 << 15)
6672b26dd4cSOder Chiou #define RT5660_IRQ_JD_NOR			(0x1 << 15)
6682b26dd4cSOder Chiou #define RT5660_IRQ_OT_MASK			(0x1 << 14)
6692b26dd4cSOder Chiou #define RT5660_IRQ_OT_SFT			14
6702b26dd4cSOder Chiou #define RT5660_IRQ_OT_BP			(0x0 << 14)
6712b26dd4cSOder Chiou #define RT5660_IRQ_OT_NOR			(0x1 << 14)
6722b26dd4cSOder Chiou #define RT5660_JD_STKY_MASK			(0x1 << 13)
6732b26dd4cSOder Chiou #define RT5660_JD_STKY_SFT			13
6742b26dd4cSOder Chiou #define RT5660_JD_STKY_DIS			(0x0 << 13)
6752b26dd4cSOder Chiou #define RT5660_JD_STKY_EN			(0x1 << 13)
6762b26dd4cSOder Chiou #define RT5660_OT_STKY_MASK			(0x1 << 12)
6772b26dd4cSOder Chiou #define RT5660_OT_STKY_SFT			12
6782b26dd4cSOder Chiou #define RT5660_OT_STKY_DIS			(0x0 << 12)
6792b26dd4cSOder Chiou #define RT5660_OT_STKY_EN			(0x1 << 12)
6802b26dd4cSOder Chiou #define RT5660_JD_P_MASK			(0x1 << 11)
6812b26dd4cSOder Chiou #define RT5660_JD_P_SFT				11
6822b26dd4cSOder Chiou #define RT5660_JD_P_NOR				(0x0 << 11)
6832b26dd4cSOder Chiou #define RT5660_JD_P_INV				(0x1 << 11)
6842b26dd4cSOder Chiou #define RT5660_OT_P_MASK			(0x1 << 10)
6852b26dd4cSOder Chiou #define RT5660_OT_P_SFT				10
6862b26dd4cSOder Chiou #define RT5660_OT_P_NOR				(0x0 << 10)
6872b26dd4cSOder Chiou #define RT5660_OT_P_INV				(0x1 << 10)
6882b26dd4cSOder Chiou 
6892b26dd4cSOder Chiou /* IRQ Control 2 (0xbe) */
6902b26dd4cSOder Chiou #define RT5660_IRQ_MB1_OC_MASK			(0x1 << 15)
6912b26dd4cSOder Chiou #define RT5660_IRQ_MB1_OC_SFT			15
6922b26dd4cSOder Chiou #define RT5660_IRQ_MB1_OC_BP			(0x0 << 15)
6932b26dd4cSOder Chiou #define RT5660_IRQ_MB1_OC_NOR			(0x1 << 15)
6942b26dd4cSOder Chiou #define RT5660_IRQ_MB2_OC_MASK			(0x1 << 14)
6952b26dd4cSOder Chiou #define RT5660_IRQ_MB2_OC_SFT			14
6962b26dd4cSOder Chiou #define RT5660_IRQ_MB2_OC_BP			(0x0 << 14)
6972b26dd4cSOder Chiou #define RT5660_IRQ_MB2_OC_NOR			(0x1 << 14)
6982b26dd4cSOder Chiou #define RT5660_MB1_OC_STKY_MASK			(0x1 << 11)
6992b26dd4cSOder Chiou #define RT5660_MB1_OC_STKY_SFT			11
7002b26dd4cSOder Chiou #define RT5660_MB1_OC_STKY_DIS			(0x0 << 11)
7012b26dd4cSOder Chiou #define RT5660_MB1_OC_STKY_EN			(0x1 << 11)
7022b26dd4cSOder Chiou #define RT5660_MB2_OC_STKY_MASK			(0x1 << 10)
7032b26dd4cSOder Chiou #define RT5660_MB2_OC_STKY_SFT			10
7042b26dd4cSOder Chiou #define RT5660_MB2_OC_STKY_DIS			(0x0 << 10)
7052b26dd4cSOder Chiou #define RT5660_MB2_OC_STKY_EN			(0x1 << 10)
7062b26dd4cSOder Chiou #define RT5660_MB1_OC_P_MASK			(0x1 << 7)
7072b26dd4cSOder Chiou #define RT5660_MB1_OC_P_SFT			7
7082b26dd4cSOder Chiou #define RT5660_MB1_OC_P_NOR			(0x0 << 7)
7092b26dd4cSOder Chiou #define RT5660_MB1_OC_P_INV			(0x1 << 7)
7102b26dd4cSOder Chiou #define RT5660_MB2_OC_P_MASK			(0x1 << 6)
7112b26dd4cSOder Chiou #define RT5660_MB2_OC_P_SFT			6
7122b26dd4cSOder Chiou #define RT5660_MB2_OC_P_NOR			(0x0 << 6)
7132b26dd4cSOder Chiou #define RT5660_MB2_OC_P_INV			(0x1 << 6)
7142b26dd4cSOder Chiou #define RT5660_MB1_OC_CLR			(0x1 << 3)
7152b26dd4cSOder Chiou #define RT5660_MB1_OC_CLR_SFT			3
7162b26dd4cSOder Chiou #define RT5660_MB2_OC_CLR			(0x1 << 2)
7172b26dd4cSOder Chiou #define RT5660_MB2_OC_CLR_SFT			2
7182b26dd4cSOder Chiou 
7192b26dd4cSOder Chiou /* GPIO Control 1 (0xc0) */
7202b26dd4cSOder Chiou #define RT5660_GP2_PIN_MASK			(0x1 << 14)
7212b26dd4cSOder Chiou #define RT5660_GP2_PIN_SFT			14
7222b26dd4cSOder Chiou #define RT5660_GP2_PIN_GPIO2			(0x0 << 14)
7232b26dd4cSOder Chiou #define RT5660_GP2_PIN_DMIC1_SDA		(0x1 << 14)
7242b26dd4cSOder Chiou #define RT5660_GP1_PIN_MASK			(0x3 << 12)
7252b26dd4cSOder Chiou #define RT5660_GP1_PIN_SFT			12
7262b26dd4cSOder Chiou #define RT5660_GP1_PIN_GPIO1			(0x0 << 12)
7272b26dd4cSOder Chiou #define RT5660_GP1_PIN_DMIC1_SCL		(0x1 << 12)
7282b26dd4cSOder Chiou #define RT5660_GP1_PIN_IRQ			(0x2 << 12)
7292b26dd4cSOder Chiou #define RT5660_GPIO_M_MASK			(0x1 << 9)
7302b26dd4cSOder Chiou #define RT5660_GPIO_M_SFT			9
7312b26dd4cSOder Chiou #define RT5660_GPIO_M_FLT			(0x0 << 9)
7322b26dd4cSOder Chiou #define RT5660_GPIO_M_PH			(0x1 << 9)
7332b26dd4cSOder Chiou 
7342b26dd4cSOder Chiou /* GPIO Control 3 (0xc2) */
7352b26dd4cSOder Chiou #define RT5660_GP2_PF_MASK			(0x1 << 5)
7362b26dd4cSOder Chiou #define RT5660_GP2_PF_SFT			5
7372b26dd4cSOder Chiou #define RT5660_GP2_PF_IN			(0x0 << 5)
7382b26dd4cSOder Chiou #define RT5660_GP2_PF_OUT			(0x1 << 5)
7392b26dd4cSOder Chiou #define RT5660_GP2_OUT_MASK			(0x1 << 4)
7402b26dd4cSOder Chiou #define RT5660_GP2_OUT_SFT			4
7412b26dd4cSOder Chiou #define RT5660_GP2_OUT_LO			(0x0 << 4)
7422b26dd4cSOder Chiou #define RT5660_GP2_OUT_HI			(0x1 << 4)
7432b26dd4cSOder Chiou #define RT5660_GP2_P_MASK			(0x1 << 3)
7442b26dd4cSOder Chiou #define RT5660_GP2_P_SFT			3
7452b26dd4cSOder Chiou #define RT5660_GP2_P_NOR			(0x0 << 3)
7462b26dd4cSOder Chiou #define RT5660_GP2_P_INV			(0x1 << 3)
7472b26dd4cSOder Chiou #define RT5660_GP1_PF_MASK			(0x1 << 2)
7482b26dd4cSOder Chiou #define RT5660_GP1_PF_SFT			2
7492b26dd4cSOder Chiou #define RT5660_GP1_PF_IN			(0x0 << 2)
7502b26dd4cSOder Chiou #define RT5660_GP1_PF_OUT			(0x1 << 2)
7512b26dd4cSOder Chiou #define RT5660_GP1_OUT_MASK			(0x1 << 1)
7522b26dd4cSOder Chiou #define RT5660_GP1_OUT_SFT			1
7532b26dd4cSOder Chiou #define RT5660_GP1_OUT_LO			(0x0 << 1)
7542b26dd4cSOder Chiou #define RT5660_GP1_OUT_HI			(0x1 << 1)
7552b26dd4cSOder Chiou #define RT5660_GP1_P_MASK			(0x1)
7562b26dd4cSOder Chiou #define RT5660_GP1_P_SFT			0
7572b26dd4cSOder Chiou #define RT5660_GP1_P_NOR			(0x0)
7582b26dd4cSOder Chiou #define RT5660_GP1_P_INV			(0x1)
7592b26dd4cSOder Chiou 
7602b26dd4cSOder Chiou /* Soft volume and zero cross control 1 (0xd9) */
7612b26dd4cSOder Chiou #define RT5660_SV_MASK				(0x1 << 15)
7622b26dd4cSOder Chiou #define RT5660_SV_SFT				15
7632b26dd4cSOder Chiou #define RT5660_SV_DIS				(0x0 << 15)
7642b26dd4cSOder Chiou #define RT5660_SV_EN				(0x1 << 15)
7652b26dd4cSOder Chiou #define RT5660_SPO_SV_MASK			(0x1 << 14)
7662b26dd4cSOder Chiou #define RT5660_SPO_SV_SFT			14
7672b26dd4cSOder Chiou #define RT5660_SPO_SV_DIS			(0x0 << 14)
7682b26dd4cSOder Chiou #define RT5660_SPO_SV_EN			(0x1 << 14)
7692b26dd4cSOder Chiou #define RT5660_OUT_SV_MASK			(0x1 << 12)
7702b26dd4cSOder Chiou #define RT5660_OUT_SV_SFT			12
7712b26dd4cSOder Chiou #define RT5660_OUT_SV_DIS			(0x0 << 12)
7722b26dd4cSOder Chiou #define RT5660_OUT_SV_EN			(0x1 << 12)
7732b26dd4cSOder Chiou #define RT5660_ZCD_DIG_MASK			(0x1 << 11)
7742b26dd4cSOder Chiou #define RT5660_ZCD_DIG_SFT			11
7752b26dd4cSOder Chiou #define RT5660_ZCD_DIG_DIS			(0x0 << 11)
7762b26dd4cSOder Chiou #define RT5660_ZCD_DIG_EN			(0x1 << 11)
7772b26dd4cSOder Chiou #define RT5660_ZCD_MASK				(0x1 << 10)
7782b26dd4cSOder Chiou #define RT5660_ZCD_SFT				10
7792b26dd4cSOder Chiou #define RT5660_ZCD_PD				(0x0 << 10)
7802b26dd4cSOder Chiou #define RT5660_ZCD_PU				(0x1 << 10)
7812b26dd4cSOder Chiou #define RT5660_SV_DLY_MASK			(0xf)
7822b26dd4cSOder Chiou #define RT5660_SV_DLY_SFT			0
7832b26dd4cSOder Chiou 
7842b26dd4cSOder Chiou /* Soft volume and zero cross control 2 (0xda) */
7852b26dd4cSOder Chiou #define RT5660_ZCD_SPO_MASK			(0x1 << 15)
7862b26dd4cSOder Chiou #define RT5660_ZCD_SPO_SFT			15
7872b26dd4cSOder Chiou #define RT5660_ZCD_SPO_DIS			(0x0 << 15)
7882b26dd4cSOder Chiou #define RT5660_ZCD_SPO_EN			(0x1 << 15)
7892b26dd4cSOder Chiou #define RT5660_ZCD_OMR_MASK			(0x1 << 8)
7902b26dd4cSOder Chiou #define RT5660_ZCD_OMR_SFT			8
7912b26dd4cSOder Chiou #define RT5660_ZCD_OMR_DIS			(0x0 << 8)
7922b26dd4cSOder Chiou #define RT5660_ZCD_OMR_EN			(0x1 << 8)
7932b26dd4cSOder Chiou #define RT5660_ZCD_OML_MASK			(0x1 << 7)
7942b26dd4cSOder Chiou #define RT5660_ZCD_OML_SFT			7
7952b26dd4cSOder Chiou #define RT5660_ZCD_OML_DIS			(0x0 << 7)
7962b26dd4cSOder Chiou #define RT5660_ZCD_OML_EN			(0x1 << 7)
7972b26dd4cSOder Chiou #define RT5660_ZCD_SPM_MASK			(0x1 << 6)
7982b26dd4cSOder Chiou #define RT5660_ZCD_SPM_SFT			6
7992b26dd4cSOder Chiou #define RT5660_ZCD_SPM_DIS			(0x0 << 6)
8002b26dd4cSOder Chiou #define RT5660_ZCD_SPM_EN			(0x1 << 6)
8012b26dd4cSOder Chiou #define RT5660_ZCD_RMR_MASK			(0x1 << 5)
8022b26dd4cSOder Chiou #define RT5660_ZCD_RMR_SFT			5
8032b26dd4cSOder Chiou #define RT5660_ZCD_RMR_DIS			(0x0 << 5)
8042b26dd4cSOder Chiou #define RT5660_ZCD_RMR_EN			(0x1 << 5)
8052b26dd4cSOder Chiou #define RT5660_ZCD_RML_MASK			(0x1 << 4)
8062b26dd4cSOder Chiou #define RT5660_ZCD_RML_SFT			4
8072b26dd4cSOder Chiou #define RT5660_ZCD_RML_DIS			(0x0 << 4)
8082b26dd4cSOder Chiou #define RT5660_ZCD_RML_EN			(0x1 << 4)
8092b26dd4cSOder Chiou 
8102b26dd4cSOder Chiou /* General Control 1 (0xfa) */
8112b26dd4cSOder Chiou #define RT5660_PWR_VREF_HP			(0x1 << 11)
8122b26dd4cSOder Chiou #define RT5660_PWR_VREF_HP_SFT			11
813d01580c3SBard Liao #define RT5660_AUTO_DIS_AMP			(0x1 << 6)
814d01580c3SBard Liao #define RT5660_MCLK_DET				(0x1 << 5)
815d01580c3SBard Liao #define RT5660_POW_CLKDET			(0x1 << 1)
8162b26dd4cSOder Chiou #define RT5660_DIG_GATE_CTRL			(0x1)
8172b26dd4cSOder Chiou #define RT5660_DIG_GATE_CTRL_SFT		0
8182b26dd4cSOder Chiou 
8192b26dd4cSOder Chiou /* System Clock Source */
8202b26dd4cSOder Chiou #define RT5660_SCLK_S_MCLK			0
8212b26dd4cSOder Chiou #define RT5660_SCLK_S_PLL1			1
8222b26dd4cSOder Chiou #define RT5660_SCLK_S_RCCLK			2
8232b26dd4cSOder Chiou 
8242b26dd4cSOder Chiou /* PLL1 Source */
8252b26dd4cSOder Chiou #define RT5660_PLL1_S_MCLK			0
8262b26dd4cSOder Chiou #define RT5660_PLL1_S_BCLK			1
8272b26dd4cSOder Chiou 
8282b26dd4cSOder Chiou enum {
8292b26dd4cSOder Chiou 	RT5660_AIF1,
8302b26dd4cSOder Chiou 	RT5660_AIFS,
8312b26dd4cSOder Chiou };
8322b26dd4cSOder Chiou 
8332b26dd4cSOder Chiou struct rt5660_priv {
834*ca04dd8aSKuninori Morimoto 	struct snd_soc_component *component;
8352b26dd4cSOder Chiou 	struct rt5660_platform_data pdata;
8362b26dd4cSOder Chiou 	struct regmap *regmap;
8372b26dd4cSOder Chiou 	struct clk *mclk;
8382b26dd4cSOder Chiou 
8392b26dd4cSOder Chiou 	int sysclk;
8402b26dd4cSOder Chiou 	int sysclk_src;
8412b26dd4cSOder Chiou 	int lrck[RT5660_AIFS];
8422b26dd4cSOder Chiou 	int bclk[RT5660_AIFS];
8432b26dd4cSOder Chiou 	int master[RT5660_AIFS];
8442b26dd4cSOder Chiou 
8452b26dd4cSOder Chiou 	int pll_src;
8462b26dd4cSOder Chiou 	int pll_in;
8472b26dd4cSOder Chiou 	int pll_out;
8482b26dd4cSOder Chiou };
8492b26dd4cSOder Chiou 
8502b26dd4cSOder Chiou #endif
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