12b26dd4cSOder Chiou /* 22b26dd4cSOder Chiou * rt5660.c -- RT5660 ALSA SoC audio codec driver 32b26dd4cSOder Chiou * 42b26dd4cSOder Chiou * Copyright 2016 Realtek Semiconductor Corp. 52b26dd4cSOder Chiou * Author: Oder Chiou <oder_chiou@realtek.com> 62b26dd4cSOder Chiou * 72b26dd4cSOder Chiou * This program is free software; you can redistribute it and/or modify 82b26dd4cSOder Chiou * it under the terms of the GNU General Public License version 2 as 92b26dd4cSOder Chiou * published by the Free Software Foundation. 102b26dd4cSOder Chiou */ 112b26dd4cSOder Chiou 122b26dd4cSOder Chiou #include <linux/module.h> 132b26dd4cSOder Chiou #include <linux/moduleparam.h> 142b26dd4cSOder Chiou #include <linux/init.h> 152b26dd4cSOder Chiou #include <linux/delay.h> 162b26dd4cSOder Chiou #include <linux/pm.h> 172b26dd4cSOder Chiou #include <linux/gpio.h> 182b26dd4cSOder Chiou #include <linux/i2c.h> 192b26dd4cSOder Chiou #include <linux/regmap.h> 202b26dd4cSOder Chiou #include <linux/of.h> 212b26dd4cSOder Chiou #include <linux/of_gpio.h> 222b26dd4cSOder Chiou #include <linux/platform_device.h> 232b26dd4cSOder Chiou #include <linux/spi/spi.h> 242b26dd4cSOder Chiou #include <linux/acpi.h> 252b26dd4cSOder Chiou #include <sound/core.h> 262b26dd4cSOder Chiou #include <sound/pcm.h> 272b26dd4cSOder Chiou #include <sound/pcm_params.h> 282b26dd4cSOder Chiou #include <sound/soc.h> 292b26dd4cSOder Chiou #include <sound/soc-dapm.h> 302b26dd4cSOder Chiou #include <sound/initval.h> 312b26dd4cSOder Chiou #include <sound/tlv.h> 322b26dd4cSOder Chiou 332b26dd4cSOder Chiou #include "rl6231.h" 342b26dd4cSOder Chiou #include "rt5660.h" 352b26dd4cSOder Chiou 362b26dd4cSOder Chiou #define RT5660_DEVICE_ID 0x6338 372b26dd4cSOder Chiou 382b26dd4cSOder Chiou #define RT5660_PR_RANGE_BASE (0xff + 1) 392b26dd4cSOder Chiou #define RT5660_PR_SPACING 0x100 402b26dd4cSOder Chiou 412b26dd4cSOder Chiou #define RT5660_PR_BASE (RT5660_PR_RANGE_BASE + (0 * RT5660_PR_SPACING)) 422b26dd4cSOder Chiou 432b26dd4cSOder Chiou static const struct regmap_range_cfg rt5660_ranges[] = { 442b26dd4cSOder Chiou { .name = "PR", .range_min = RT5660_PR_BASE, 452b26dd4cSOder Chiou .range_max = RT5660_PR_BASE + 0xf3, 462b26dd4cSOder Chiou .selector_reg = RT5660_PRIV_INDEX, 472b26dd4cSOder Chiou .selector_mask = 0xff, 482b26dd4cSOder Chiou .selector_shift = 0x0, 492b26dd4cSOder Chiou .window_start = RT5660_PRIV_DATA, 502b26dd4cSOder Chiou .window_len = 0x1, }, 512b26dd4cSOder Chiou }; 522b26dd4cSOder Chiou 532b26dd4cSOder Chiou static const struct reg_sequence rt5660_patch[] = { 542b26dd4cSOder Chiou { RT5660_ALC_PGA_CTRL2, 0x44c3 }, 552b26dd4cSOder Chiou { RT5660_PR_BASE + 0x3d, 0x2600 }, 562b26dd4cSOder Chiou }; 572b26dd4cSOder Chiou 582b26dd4cSOder Chiou static const struct reg_default rt5660_reg[] = { 592b26dd4cSOder Chiou { 0x00, 0x0000 }, 602b26dd4cSOder Chiou { 0x01, 0xc800 }, 612b26dd4cSOder Chiou { 0x02, 0xc8c8 }, 622b26dd4cSOder Chiou { 0x0d, 0x1010 }, 632b26dd4cSOder Chiou { 0x0e, 0x1010 }, 642b26dd4cSOder Chiou { 0x19, 0xafaf }, 652b26dd4cSOder Chiou { 0x1c, 0x2f2f }, 662b26dd4cSOder Chiou { 0x1e, 0x0000 }, 672b26dd4cSOder Chiou { 0x27, 0x6060 }, 682b26dd4cSOder Chiou { 0x29, 0x8080 }, 692b26dd4cSOder Chiou { 0x2a, 0x4242 }, 702b26dd4cSOder Chiou { 0x2f, 0x0000 }, 712b26dd4cSOder Chiou { 0x3b, 0x0000 }, 722b26dd4cSOder Chiou { 0x3c, 0x007f }, 732b26dd4cSOder Chiou { 0x3d, 0x0000 }, 742b26dd4cSOder Chiou { 0x3e, 0x007f }, 752b26dd4cSOder Chiou { 0x45, 0xe000 }, 762b26dd4cSOder Chiou { 0x46, 0x003e }, 772b26dd4cSOder Chiou { 0x48, 0xf800 }, 782b26dd4cSOder Chiou { 0x4a, 0x0004 }, 792b26dd4cSOder Chiou { 0x4d, 0x0000 }, 802b26dd4cSOder Chiou { 0x4e, 0x0000 }, 812b26dd4cSOder Chiou { 0x4f, 0x01ff }, 822b26dd4cSOder Chiou { 0x50, 0x0000 }, 832b26dd4cSOder Chiou { 0x51, 0x0000 }, 842b26dd4cSOder Chiou { 0x52, 0x01ff }, 852b26dd4cSOder Chiou { 0x61, 0x0000 }, 862b26dd4cSOder Chiou { 0x62, 0x0000 }, 872b26dd4cSOder Chiou { 0x63, 0x00c0 }, 882b26dd4cSOder Chiou { 0x64, 0x0000 }, 892b26dd4cSOder Chiou { 0x65, 0x0000 }, 902b26dd4cSOder Chiou { 0x66, 0x0000 }, 912b26dd4cSOder Chiou { 0x70, 0x8000 }, 922b26dd4cSOder Chiou { 0x73, 0x7000 }, 932b26dd4cSOder Chiou { 0x74, 0x3c00 }, 942b26dd4cSOder Chiou { 0x75, 0x2800 }, 952b26dd4cSOder Chiou { 0x80, 0x0000 }, 962b26dd4cSOder Chiou { 0x81, 0x0000 }, 972b26dd4cSOder Chiou { 0x82, 0x0000 }, 982b26dd4cSOder Chiou { 0x8c, 0x0228 }, 992b26dd4cSOder Chiou { 0x8d, 0xa000 }, 1002b26dd4cSOder Chiou { 0x8e, 0x0000 }, 1012b26dd4cSOder Chiou { 0x92, 0x0000 }, 1022b26dd4cSOder Chiou { 0x93, 0x3000 }, 1032b26dd4cSOder Chiou { 0xa1, 0x0059 }, 1042b26dd4cSOder Chiou { 0xa2, 0x0001 }, 1052b26dd4cSOder Chiou { 0xa3, 0x5c80 }, 1062b26dd4cSOder Chiou { 0xa4, 0x0146 }, 1072b26dd4cSOder Chiou { 0xa5, 0x1f1f }, 1082b26dd4cSOder Chiou { 0xa6, 0x78c6 }, 1092b26dd4cSOder Chiou { 0xa7, 0xe5ec }, 1102b26dd4cSOder Chiou { 0xa8, 0xba61 }, 1112b26dd4cSOder Chiou { 0xa9, 0x3c78 }, 1122b26dd4cSOder Chiou { 0xaa, 0x8ae2 }, 1132b26dd4cSOder Chiou { 0xab, 0xe5ec }, 1142b26dd4cSOder Chiou { 0xac, 0xc600 }, 1152b26dd4cSOder Chiou { 0xad, 0xba61 }, 1162b26dd4cSOder Chiou { 0xae, 0x17ed }, 1172b26dd4cSOder Chiou { 0xb0, 0x2080 }, 1182b26dd4cSOder Chiou { 0xb1, 0x0000 }, 1192b26dd4cSOder Chiou { 0xb3, 0x001f }, 1202b26dd4cSOder Chiou { 0xb4, 0x020c }, 1212b26dd4cSOder Chiou { 0xb5, 0x1f00 }, 1222b26dd4cSOder Chiou { 0xb6, 0x0000 }, 1232b26dd4cSOder Chiou { 0xb7, 0x4000 }, 1242b26dd4cSOder Chiou { 0xbb, 0x0000 }, 1252b26dd4cSOder Chiou { 0xbd, 0x0000 }, 1262b26dd4cSOder Chiou { 0xbe, 0x0000 }, 1272b26dd4cSOder Chiou { 0xbf, 0x0100 }, 1282b26dd4cSOder Chiou { 0xc0, 0x0000 }, 1292b26dd4cSOder Chiou { 0xc2, 0x0000 }, 1302b26dd4cSOder Chiou { 0xd3, 0xa220 }, 1312b26dd4cSOder Chiou { 0xd9, 0x0809 }, 1322b26dd4cSOder Chiou { 0xda, 0x0000 }, 1332b26dd4cSOder Chiou { 0xe0, 0x8000 }, 1342b26dd4cSOder Chiou { 0xe1, 0x0200 }, 1352b26dd4cSOder Chiou { 0xe2, 0x8000 }, 1362b26dd4cSOder Chiou { 0xe3, 0x0200 }, 1372b26dd4cSOder Chiou { 0xe4, 0x0f20 }, 1382b26dd4cSOder Chiou { 0xe5, 0x001f }, 1392b26dd4cSOder Chiou { 0xe6, 0x020c }, 1402b26dd4cSOder Chiou { 0xe7, 0x1f00 }, 1412b26dd4cSOder Chiou { 0xe8, 0x0000 }, 1422b26dd4cSOder Chiou { 0xe9, 0x4000 }, 1432b26dd4cSOder Chiou { 0xea, 0x00a6 }, 1442b26dd4cSOder Chiou { 0xeb, 0x04c3 }, 1452b26dd4cSOder Chiou { 0xec, 0x27c8 }, 1462b26dd4cSOder Chiou { 0xed, 0x7418 }, 1472b26dd4cSOder Chiou { 0xee, 0xbf50 }, 1482b26dd4cSOder Chiou { 0xef, 0x0045 }, 1492b26dd4cSOder Chiou { 0xf0, 0x0007 }, 1502b26dd4cSOder Chiou { 0xfa, 0x0000 }, 1512b26dd4cSOder Chiou { 0xfd, 0x0000 }, 1522b26dd4cSOder Chiou { 0xfe, 0x10ec }, 1532b26dd4cSOder Chiou { 0xff, 0x6338 }, 1542b26dd4cSOder Chiou }; 1552b26dd4cSOder Chiou 1562b26dd4cSOder Chiou static bool rt5660_volatile_register(struct device *dev, unsigned int reg) 1572b26dd4cSOder Chiou { 1582b26dd4cSOder Chiou int i; 1592b26dd4cSOder Chiou 1602b26dd4cSOder Chiou for (i = 0; i < ARRAY_SIZE(rt5660_ranges); i++) 1612b26dd4cSOder Chiou if ((reg >= rt5660_ranges[i].window_start && 1622b26dd4cSOder Chiou reg <= rt5660_ranges[i].window_start + 1632b26dd4cSOder Chiou rt5660_ranges[i].window_len) || 1642b26dd4cSOder Chiou (reg >= rt5660_ranges[i].range_min && 1652b26dd4cSOder Chiou reg <= rt5660_ranges[i].range_max)) 1662b26dd4cSOder Chiou return true; 1672b26dd4cSOder Chiou 1682b26dd4cSOder Chiou switch (reg) { 1692b26dd4cSOder Chiou case RT5660_RESET: 1702b26dd4cSOder Chiou case RT5660_PRIV_DATA: 1712b26dd4cSOder Chiou case RT5660_EQ_CTRL1: 1722b26dd4cSOder Chiou case RT5660_IRQ_CTRL2: 1732b26dd4cSOder Chiou case RT5660_INT_IRQ_ST: 1742b26dd4cSOder Chiou case RT5660_VENDOR_ID: 1752b26dd4cSOder Chiou case RT5660_VENDOR_ID1: 1762b26dd4cSOder Chiou case RT5660_VENDOR_ID2: 1772b26dd4cSOder Chiou return true; 1782b26dd4cSOder Chiou default: 1792b26dd4cSOder Chiou return false; 1802b26dd4cSOder Chiou } 1812b26dd4cSOder Chiou } 1822b26dd4cSOder Chiou 1832b26dd4cSOder Chiou static bool rt5660_readable_register(struct device *dev, unsigned int reg) 1842b26dd4cSOder Chiou { 1852b26dd4cSOder Chiou int i; 1862b26dd4cSOder Chiou 1872b26dd4cSOder Chiou for (i = 0; i < ARRAY_SIZE(rt5660_ranges); i++) 1882b26dd4cSOder Chiou if ((reg >= rt5660_ranges[i].window_start && 1892b26dd4cSOder Chiou reg <= rt5660_ranges[i].window_start + 1902b26dd4cSOder Chiou rt5660_ranges[i].window_len) || 1912b26dd4cSOder Chiou (reg >= rt5660_ranges[i].range_min && 1922b26dd4cSOder Chiou reg <= rt5660_ranges[i].range_max)) 1932b26dd4cSOder Chiou return true; 1942b26dd4cSOder Chiou 1952b26dd4cSOder Chiou switch (reg) { 1962b26dd4cSOder Chiou case RT5660_RESET: 1972b26dd4cSOder Chiou case RT5660_SPK_VOL: 1982b26dd4cSOder Chiou case RT5660_LOUT_VOL: 1992b26dd4cSOder Chiou case RT5660_IN1_IN2: 2002b26dd4cSOder Chiou case RT5660_IN3_IN4: 2012b26dd4cSOder Chiou case RT5660_DAC1_DIG_VOL: 2022b26dd4cSOder Chiou case RT5660_STO1_ADC_DIG_VOL: 2032b26dd4cSOder Chiou case RT5660_ADC_BST_VOL1: 2042b26dd4cSOder Chiou case RT5660_STO1_ADC_MIXER: 2052b26dd4cSOder Chiou case RT5660_AD_DA_MIXER: 2062b26dd4cSOder Chiou case RT5660_STO_DAC_MIXER: 2072b26dd4cSOder Chiou case RT5660_DIG_INF1_DATA: 2082b26dd4cSOder Chiou case RT5660_REC_L1_MIXER: 2092b26dd4cSOder Chiou case RT5660_REC_L2_MIXER: 2102b26dd4cSOder Chiou case RT5660_REC_R1_MIXER: 2112b26dd4cSOder Chiou case RT5660_REC_R2_MIXER: 2122b26dd4cSOder Chiou case RT5660_LOUT_MIXER: 2132b26dd4cSOder Chiou case RT5660_SPK_MIXER: 2142b26dd4cSOder Chiou case RT5660_SPO_MIXER: 2152b26dd4cSOder Chiou case RT5660_SPO_CLSD_RATIO: 2162b26dd4cSOder Chiou case RT5660_OUT_L_GAIN1: 2172b26dd4cSOder Chiou case RT5660_OUT_L_GAIN2: 2182b26dd4cSOder Chiou case RT5660_OUT_L1_MIXER: 2192b26dd4cSOder Chiou case RT5660_OUT_R_GAIN1: 2202b26dd4cSOder Chiou case RT5660_OUT_R_GAIN2: 2212b26dd4cSOder Chiou case RT5660_OUT_R1_MIXER: 2222b26dd4cSOder Chiou case RT5660_PWR_DIG1: 2232b26dd4cSOder Chiou case RT5660_PWR_DIG2: 2242b26dd4cSOder Chiou case RT5660_PWR_ANLG1: 2252b26dd4cSOder Chiou case RT5660_PWR_ANLG2: 2262b26dd4cSOder Chiou case RT5660_PWR_MIXER: 2272b26dd4cSOder Chiou case RT5660_PWR_VOL: 2282b26dd4cSOder Chiou case RT5660_PRIV_INDEX: 2292b26dd4cSOder Chiou case RT5660_PRIV_DATA: 2302b26dd4cSOder Chiou case RT5660_I2S1_SDP: 2312b26dd4cSOder Chiou case RT5660_ADDA_CLK1: 2322b26dd4cSOder Chiou case RT5660_ADDA_CLK2: 2332b26dd4cSOder Chiou case RT5660_DMIC_CTRL1: 2342b26dd4cSOder Chiou case RT5660_GLB_CLK: 2352b26dd4cSOder Chiou case RT5660_PLL_CTRL1: 2362b26dd4cSOder Chiou case RT5660_PLL_CTRL2: 2372b26dd4cSOder Chiou case RT5660_CLSD_AMP_OC_CTRL: 2382b26dd4cSOder Chiou case RT5660_CLSD_AMP_CTRL: 2392b26dd4cSOder Chiou case RT5660_LOUT_AMP_CTRL: 2402b26dd4cSOder Chiou case RT5660_SPK_AMP_SPKVDD: 2412b26dd4cSOder Chiou case RT5660_MICBIAS: 2422b26dd4cSOder Chiou case RT5660_CLSD_OUT_CTRL1: 2432b26dd4cSOder Chiou case RT5660_CLSD_OUT_CTRL2: 2442b26dd4cSOder Chiou case RT5660_DIPOLE_MIC_CTRL1: 2452b26dd4cSOder Chiou case RT5660_DIPOLE_MIC_CTRL2: 2462b26dd4cSOder Chiou case RT5660_DIPOLE_MIC_CTRL3: 2472b26dd4cSOder Chiou case RT5660_DIPOLE_MIC_CTRL4: 2482b26dd4cSOder Chiou case RT5660_DIPOLE_MIC_CTRL5: 2492b26dd4cSOder Chiou case RT5660_DIPOLE_MIC_CTRL6: 2502b26dd4cSOder Chiou case RT5660_DIPOLE_MIC_CTRL7: 2512b26dd4cSOder Chiou case RT5660_DIPOLE_MIC_CTRL8: 2522b26dd4cSOder Chiou case RT5660_DIPOLE_MIC_CTRL9: 2532b26dd4cSOder Chiou case RT5660_DIPOLE_MIC_CTRL10: 2542b26dd4cSOder Chiou case RT5660_DIPOLE_MIC_CTRL11: 2552b26dd4cSOder Chiou case RT5660_DIPOLE_MIC_CTRL12: 2562b26dd4cSOder Chiou case RT5660_EQ_CTRL1: 2572b26dd4cSOder Chiou case RT5660_EQ_CTRL2: 2582b26dd4cSOder Chiou case RT5660_DRC_AGC_CTRL1: 2592b26dd4cSOder Chiou case RT5660_DRC_AGC_CTRL2: 2602b26dd4cSOder Chiou case RT5660_DRC_AGC_CTRL3: 2612b26dd4cSOder Chiou case RT5660_DRC_AGC_CTRL4: 2622b26dd4cSOder Chiou case RT5660_DRC_AGC_CTRL5: 2632b26dd4cSOder Chiou case RT5660_JD_CTRL: 2642b26dd4cSOder Chiou case RT5660_IRQ_CTRL1: 2652b26dd4cSOder Chiou case RT5660_IRQ_CTRL2: 2662b26dd4cSOder Chiou case RT5660_INT_IRQ_ST: 2672b26dd4cSOder Chiou case RT5660_GPIO_CTRL1: 2682b26dd4cSOder Chiou case RT5660_GPIO_CTRL2: 2692b26dd4cSOder Chiou case RT5660_WIND_FILTER_CTRL1: 2702b26dd4cSOder Chiou case RT5660_SV_ZCD1: 2712b26dd4cSOder Chiou case RT5660_SV_ZCD2: 2722b26dd4cSOder Chiou case RT5660_DRC1_LM_CTRL1: 2732b26dd4cSOder Chiou case RT5660_DRC1_LM_CTRL2: 2742b26dd4cSOder Chiou case RT5660_DRC2_LM_CTRL1: 2752b26dd4cSOder Chiou case RT5660_DRC2_LM_CTRL2: 2762b26dd4cSOder Chiou case RT5660_MULTI_DRC_CTRL: 2772b26dd4cSOder Chiou case RT5660_DRC2_CTRL1: 2782b26dd4cSOder Chiou case RT5660_DRC2_CTRL2: 2792b26dd4cSOder Chiou case RT5660_DRC2_CTRL3: 2802b26dd4cSOder Chiou case RT5660_DRC2_CTRL4: 2812b26dd4cSOder Chiou case RT5660_DRC2_CTRL5: 2822b26dd4cSOder Chiou case RT5660_ALC_PGA_CTRL1: 2832b26dd4cSOder Chiou case RT5660_ALC_PGA_CTRL2: 2842b26dd4cSOder Chiou case RT5660_ALC_PGA_CTRL3: 2852b26dd4cSOder Chiou case RT5660_ALC_PGA_CTRL4: 2862b26dd4cSOder Chiou case RT5660_ALC_PGA_CTRL5: 2872b26dd4cSOder Chiou case RT5660_ALC_PGA_CTRL6: 2882b26dd4cSOder Chiou case RT5660_ALC_PGA_CTRL7: 2892b26dd4cSOder Chiou case RT5660_GEN_CTRL1: 2902b26dd4cSOder Chiou case RT5660_GEN_CTRL2: 2912b26dd4cSOder Chiou case RT5660_GEN_CTRL3: 2922b26dd4cSOder Chiou case RT5660_VENDOR_ID: 2932b26dd4cSOder Chiou case RT5660_VENDOR_ID1: 2942b26dd4cSOder Chiou case RT5660_VENDOR_ID2: 2952b26dd4cSOder Chiou return true; 2962b26dd4cSOder Chiou default: 2972b26dd4cSOder Chiou return false; 2982b26dd4cSOder Chiou } 2992b26dd4cSOder Chiou } 3002b26dd4cSOder Chiou 3012b26dd4cSOder Chiou static const DECLARE_TLV_DB_SCALE(rt5660_out_vol_tlv, -4650, 150, 0); 3022b26dd4cSOder Chiou static const DECLARE_TLV_DB_SCALE(rt5660_dac_vol_tlv, -6525, 75, 0); 3032b26dd4cSOder Chiou static const DECLARE_TLV_DB_SCALE(rt5660_adc_vol_tlv, -1725, 75, 0); 3042b26dd4cSOder Chiou static const DECLARE_TLV_DB_SCALE(rt5660_adc_bst_tlv, 0, 1200, 0); 3052b26dd4cSOder Chiou static const DECLARE_TLV_DB_SCALE(rt5660_bst_tlv, -1200, 75, 0); 3062b26dd4cSOder Chiou 3072b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_snd_controls[] = { 3082b26dd4cSOder Chiou /* Speaker Output Volume */ 3092b26dd4cSOder Chiou SOC_SINGLE("Speaker Playback Switch", RT5660_SPK_VOL, RT5660_L_MUTE_SFT, 3102b26dd4cSOder Chiou 1, 1), 3112b26dd4cSOder Chiou SOC_SINGLE_TLV("Speaker Playback Volume", RT5660_SPK_VOL, 3122b26dd4cSOder Chiou RT5660_L_VOL_SFT, 39, 1, rt5660_out_vol_tlv), 3132b26dd4cSOder Chiou 3142b26dd4cSOder Chiou /* OUTPUT Control */ 3152b26dd4cSOder Chiou SOC_DOUBLE("OUT Playback Switch", RT5660_LOUT_VOL, RT5660_L_MUTE_SFT, 3162b26dd4cSOder Chiou RT5660_R_MUTE_SFT, 1, 1), 3172b26dd4cSOder Chiou SOC_DOUBLE_TLV("OUT Playback Volume", RT5660_LOUT_VOL, RT5660_L_VOL_SFT, 3182b26dd4cSOder Chiou RT5660_R_VOL_SFT, 39, 1, rt5660_out_vol_tlv), 3192b26dd4cSOder Chiou 3202b26dd4cSOder Chiou /* DAC Digital Volume */ 3212b26dd4cSOder Chiou SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5660_DAC1_DIG_VOL, 3222b26dd4cSOder Chiou RT5660_DAC_L1_VOL_SFT, RT5660_DAC_R1_VOL_SFT, 87, 0, 3232b26dd4cSOder Chiou rt5660_dac_vol_tlv), 3242b26dd4cSOder Chiou 3252b26dd4cSOder Chiou /* IN1/IN2/IN3 Control */ 3262b26dd4cSOder Chiou SOC_SINGLE_TLV("IN1 Boost Volume", RT5660_IN1_IN2, RT5660_BST_SFT1, 69, 3272b26dd4cSOder Chiou 0, rt5660_bst_tlv), 3282b26dd4cSOder Chiou SOC_SINGLE_TLV("IN2 Boost Volume", RT5660_IN1_IN2, RT5660_BST_SFT2, 69, 3292b26dd4cSOder Chiou 0, rt5660_bst_tlv), 3302b26dd4cSOder Chiou SOC_SINGLE_TLV("IN3 Boost Volume", RT5660_IN3_IN4, RT5660_BST_SFT3, 69, 3312b26dd4cSOder Chiou 0, rt5660_bst_tlv), 3322b26dd4cSOder Chiou 3332b26dd4cSOder Chiou /* ADC Digital Volume Control */ 3342b26dd4cSOder Chiou SOC_DOUBLE("ADC Capture Switch", RT5660_STO1_ADC_DIG_VOL, 3352b26dd4cSOder Chiou RT5660_L_MUTE_SFT, RT5660_R_MUTE_SFT, 1, 1), 3362b26dd4cSOder Chiou SOC_DOUBLE_TLV("ADC Capture Volume", RT5660_STO1_ADC_DIG_VOL, 3372b26dd4cSOder Chiou RT5660_ADC_L_VOL_SFT, RT5660_ADC_R_VOL_SFT, 63, 0, 3382b26dd4cSOder Chiou rt5660_adc_vol_tlv), 3392b26dd4cSOder Chiou 3402b26dd4cSOder Chiou /* ADC Boost Volume Control */ 3412b26dd4cSOder Chiou SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5660_ADC_BST_VOL1, 3422b26dd4cSOder Chiou RT5660_STO1_ADC_L_BST_SFT, RT5660_STO1_ADC_R_BST_SFT, 3, 0, 3432b26dd4cSOder Chiou rt5660_adc_bst_tlv), 3442b26dd4cSOder Chiou }; 3452b26dd4cSOder Chiou 3462b26dd4cSOder Chiou /** 3472b26dd4cSOder Chiou * rt5660_set_dmic_clk - Set parameter of dmic. 3482b26dd4cSOder Chiou * 3492b26dd4cSOder Chiou * @w: DAPM widget. 3502b26dd4cSOder Chiou * @kcontrol: The kcontrol of this widget. 3512b26dd4cSOder Chiou * @event: Event id. 3522b26dd4cSOder Chiou * 3532b26dd4cSOder Chiou */ 3542b26dd4cSOder Chiou static int rt5660_set_dmic_clk(struct snd_soc_dapm_widget *w, 3552b26dd4cSOder Chiou struct snd_kcontrol *kcontrol, int event) 3562b26dd4cSOder Chiou { 3572b26dd4cSOder Chiou struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 3582b26dd4cSOder Chiou struct rt5660_priv *rt5660 = snd_soc_codec_get_drvdata(codec); 3592b26dd4cSOder Chiou int idx, rate; 3602b26dd4cSOder Chiou 3612b26dd4cSOder Chiou rate = rt5660->sysclk / rl6231_get_pre_div(rt5660->regmap, 3622b26dd4cSOder Chiou RT5660_ADDA_CLK1, RT5660_I2S_PD1_SFT); 3632b26dd4cSOder Chiou idx = rl6231_calc_dmic_clk(rate); 3642b26dd4cSOder Chiou if (idx < 0) 3652b26dd4cSOder Chiou dev_err(codec->dev, "Failed to set DMIC clock\n"); 3662b26dd4cSOder Chiou else 3672b26dd4cSOder Chiou snd_soc_update_bits(codec, RT5660_DMIC_CTRL1, 3682b26dd4cSOder Chiou RT5660_DMIC_CLK_MASK, idx << RT5660_DMIC_CLK_SFT); 3692b26dd4cSOder Chiou 3702b26dd4cSOder Chiou return idx; 3712b26dd4cSOder Chiou } 3722b26dd4cSOder Chiou 3732b26dd4cSOder Chiou static int rt5660_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 3742b26dd4cSOder Chiou struct snd_soc_dapm_widget *sink) 3752b26dd4cSOder Chiou { 3762b26dd4cSOder Chiou struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 3772b26dd4cSOder Chiou unsigned int val; 3782b26dd4cSOder Chiou 3792b26dd4cSOder Chiou val = snd_soc_read(codec, RT5660_GLB_CLK); 3802b26dd4cSOder Chiou val &= RT5660_SCLK_SRC_MASK; 3812b26dd4cSOder Chiou if (val == RT5660_SCLK_SRC_PLL1) 3822b26dd4cSOder Chiou return 1; 3832b26dd4cSOder Chiou else 3842b26dd4cSOder Chiou return 0; 3852b26dd4cSOder Chiou } 3862b26dd4cSOder Chiou 3872b26dd4cSOder Chiou /* Digital Mixer */ 3882b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_sto1_adc_l_mix[] = { 3892b26dd4cSOder Chiou SOC_DAPM_SINGLE("ADC1 Switch", RT5660_STO1_ADC_MIXER, 3902b26dd4cSOder Chiou RT5660_M_ADC_L1_SFT, 1, 1), 3912b26dd4cSOder Chiou SOC_DAPM_SINGLE("ADC2 Switch", RT5660_STO1_ADC_MIXER, 3922b26dd4cSOder Chiou RT5660_M_ADC_L2_SFT, 1, 1), 3932b26dd4cSOder Chiou }; 3942b26dd4cSOder Chiou 3952b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_sto1_adc_r_mix[] = { 3962b26dd4cSOder Chiou SOC_DAPM_SINGLE("ADC1 Switch", RT5660_STO1_ADC_MIXER, 3972b26dd4cSOder Chiou RT5660_M_ADC_R1_SFT, 1, 1), 3982b26dd4cSOder Chiou SOC_DAPM_SINGLE("ADC2 Switch", RT5660_STO1_ADC_MIXER, 3992b26dd4cSOder Chiou RT5660_M_ADC_R2_SFT, 1, 1), 4002b26dd4cSOder Chiou }; 4012b26dd4cSOder Chiou 4022b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_dac_l_mix[] = { 4032b26dd4cSOder Chiou SOC_DAPM_SINGLE("Stereo ADC Switch", RT5660_AD_DA_MIXER, 4042b26dd4cSOder Chiou RT5660_M_ADCMIX_L_SFT, 1, 1), 4052b26dd4cSOder Chiou SOC_DAPM_SINGLE("DAC1 Switch", RT5660_AD_DA_MIXER, 4062b26dd4cSOder Chiou RT5660_M_DAC1_L_SFT, 1, 1), 4072b26dd4cSOder Chiou }; 4082b26dd4cSOder Chiou 4092b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_dac_r_mix[] = { 4102b26dd4cSOder Chiou SOC_DAPM_SINGLE("Stereo ADC Switch", RT5660_AD_DA_MIXER, 4112b26dd4cSOder Chiou RT5660_M_ADCMIX_R_SFT, 1, 1), 4122b26dd4cSOder Chiou SOC_DAPM_SINGLE("DAC1 Switch", RT5660_AD_DA_MIXER, 4132b26dd4cSOder Chiou RT5660_M_DAC1_R_SFT, 1, 1), 4142b26dd4cSOder Chiou }; 4152b26dd4cSOder Chiou 4162b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_sto_dac_l_mix[] = { 4172b26dd4cSOder Chiou SOC_DAPM_SINGLE("DAC L1 Switch", RT5660_STO_DAC_MIXER, 4182b26dd4cSOder Chiou RT5660_M_DAC_L1_SFT, 1, 1), 4192b26dd4cSOder Chiou SOC_DAPM_SINGLE("DAC R1 Switch", RT5660_STO_DAC_MIXER, 4202b26dd4cSOder Chiou RT5660_M_DAC_R1_STO_L_SFT, 1, 1), 4212b26dd4cSOder Chiou }; 4222b26dd4cSOder Chiou 4232b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_sto_dac_r_mix[] = { 4242b26dd4cSOder Chiou SOC_DAPM_SINGLE("DAC R1 Switch", RT5660_STO_DAC_MIXER, 4252b26dd4cSOder Chiou RT5660_M_DAC_R1_SFT, 1, 1), 4262b26dd4cSOder Chiou SOC_DAPM_SINGLE("DAC L1 Switch", RT5660_STO_DAC_MIXER, 4272b26dd4cSOder Chiou RT5660_M_DAC_L1_STO_R_SFT, 1, 1), 4282b26dd4cSOder Chiou }; 4292b26dd4cSOder Chiou 4302b26dd4cSOder Chiou /* Analog Input Mixer */ 4312b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_rec_l_mix[] = { 4322b26dd4cSOder Chiou SOC_DAPM_SINGLE("BST3 Switch", RT5660_REC_L2_MIXER, 4332b26dd4cSOder Chiou RT5660_M_BST3_RM_L_SFT, 1, 1), 4342b26dd4cSOder Chiou SOC_DAPM_SINGLE("BST2 Switch", RT5660_REC_L2_MIXER, 4352b26dd4cSOder Chiou RT5660_M_BST2_RM_L_SFT, 1, 1), 4362b26dd4cSOder Chiou SOC_DAPM_SINGLE("BST1 Switch", RT5660_REC_L2_MIXER, 4372b26dd4cSOder Chiou RT5660_M_BST1_RM_L_SFT, 1, 1), 4382b26dd4cSOder Chiou SOC_DAPM_SINGLE("OUT MIXL Switch", RT5660_REC_L2_MIXER, 4392b26dd4cSOder Chiou RT5660_M_OM_L_RM_L_SFT, 1, 1), 4402b26dd4cSOder Chiou }; 4412b26dd4cSOder Chiou 4422b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_rec_r_mix[] = { 4432b26dd4cSOder Chiou SOC_DAPM_SINGLE("BST3 Switch", RT5660_REC_R2_MIXER, 4442b26dd4cSOder Chiou RT5660_M_BST3_RM_R_SFT, 1, 1), 4452b26dd4cSOder Chiou SOC_DAPM_SINGLE("BST2 Switch", RT5660_REC_R2_MIXER, 4462b26dd4cSOder Chiou RT5660_M_BST2_RM_R_SFT, 1, 1), 4472b26dd4cSOder Chiou SOC_DAPM_SINGLE("BST1 Switch", RT5660_REC_R2_MIXER, 4482b26dd4cSOder Chiou RT5660_M_BST1_RM_R_SFT, 1, 1), 4492b26dd4cSOder Chiou SOC_DAPM_SINGLE("OUT MIXR Switch", RT5660_REC_R2_MIXER, 4502b26dd4cSOder Chiou RT5660_M_OM_R_RM_R_SFT, 1, 1), 4512b26dd4cSOder Chiou }; 4522b26dd4cSOder Chiou 4532b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_spk_mix[] = { 4542b26dd4cSOder Chiou SOC_DAPM_SINGLE("BST3 Switch", RT5660_SPK_MIXER, 4552b26dd4cSOder Chiou RT5660_M_BST3_SM_SFT, 1, 1), 4562b26dd4cSOder Chiou SOC_DAPM_SINGLE("BST1 Switch", RT5660_SPK_MIXER, 4572b26dd4cSOder Chiou RT5660_M_BST1_SM_SFT, 1, 1), 4582b26dd4cSOder Chiou SOC_DAPM_SINGLE("DACL Switch", RT5660_SPK_MIXER, 4592b26dd4cSOder Chiou RT5660_M_DACL_SM_SFT, 1, 1), 4602b26dd4cSOder Chiou SOC_DAPM_SINGLE("DACR Switch", RT5660_SPK_MIXER, 4612b26dd4cSOder Chiou RT5660_M_DACR_SM_SFT, 1, 1), 4622b26dd4cSOder Chiou SOC_DAPM_SINGLE("OUTMIXL Switch", RT5660_SPK_MIXER, 4632b26dd4cSOder Chiou RT5660_M_OM_L_SM_SFT, 1, 1), 4642b26dd4cSOder Chiou }; 4652b26dd4cSOder Chiou 4662b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_out_l_mix[] = { 4672b26dd4cSOder Chiou SOC_DAPM_SINGLE("BST3 Switch", RT5660_OUT_L1_MIXER, 4682b26dd4cSOder Chiou RT5660_M_BST3_OM_L_SFT, 1, 1), 4692b26dd4cSOder Chiou SOC_DAPM_SINGLE("BST2 Switch", RT5660_OUT_L1_MIXER, 4702b26dd4cSOder Chiou RT5660_M_BST2_OM_L_SFT, 1, 1), 4712b26dd4cSOder Chiou SOC_DAPM_SINGLE("BST1 Switch", RT5660_OUT_L1_MIXER, 4722b26dd4cSOder Chiou RT5660_M_BST1_OM_L_SFT, 1, 1), 4732b26dd4cSOder Chiou SOC_DAPM_SINGLE("RECMIXL Switch", RT5660_OUT_L1_MIXER, 4742b26dd4cSOder Chiou RT5660_M_RM_L_OM_L_SFT, 1, 1), 4752b26dd4cSOder Chiou SOC_DAPM_SINGLE("DACR Switch", RT5660_OUT_L1_MIXER, 4762b26dd4cSOder Chiou RT5660_M_DAC_R_OM_L_SFT, 1, 1), 4772b26dd4cSOder Chiou SOC_DAPM_SINGLE("DACL Switch", RT5660_OUT_L1_MIXER, 4782b26dd4cSOder Chiou RT5660_M_DAC_L_OM_L_SFT, 1, 1), 4792b26dd4cSOder Chiou }; 4802b26dd4cSOder Chiou 4812b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_out_r_mix[] = { 4822b26dd4cSOder Chiou SOC_DAPM_SINGLE("BST2 Switch", RT5660_OUT_R1_MIXER, 4832b26dd4cSOder Chiou RT5660_M_BST2_OM_R_SFT, 1, 1), 4842b26dd4cSOder Chiou SOC_DAPM_SINGLE("BST1 Switch", RT5660_OUT_R1_MIXER, 4852b26dd4cSOder Chiou RT5660_M_BST1_OM_R_SFT, 1, 1), 4862b26dd4cSOder Chiou SOC_DAPM_SINGLE("RECMIXR Switch", RT5660_OUT_R1_MIXER, 4872b26dd4cSOder Chiou RT5660_M_RM_R_OM_R_SFT, 1, 1), 4882b26dd4cSOder Chiou SOC_DAPM_SINGLE("DACR Switch", RT5660_OUT_R1_MIXER, 4892b26dd4cSOder Chiou RT5660_M_DAC_R_OM_R_SFT, 1, 1), 4902b26dd4cSOder Chiou SOC_DAPM_SINGLE("DACL Switch", RT5660_OUT_R1_MIXER, 4912b26dd4cSOder Chiou RT5660_M_DAC_L_OM_R_SFT, 1, 1), 4922b26dd4cSOder Chiou }; 4932b26dd4cSOder Chiou 4942b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_spo_mix[] = { 4952b26dd4cSOder Chiou SOC_DAPM_SINGLE("DACR Switch", RT5660_SPO_MIXER, 4962b26dd4cSOder Chiou RT5660_M_DAC_R_SPM_SFT, 1, 1), 4972b26dd4cSOder Chiou SOC_DAPM_SINGLE("DACL Switch", RT5660_SPO_MIXER, 4982b26dd4cSOder Chiou RT5660_M_DAC_L_SPM_SFT, 1, 1), 4992b26dd4cSOder Chiou SOC_DAPM_SINGLE("SPKVOL Switch", RT5660_SPO_MIXER, 5002b26dd4cSOder Chiou RT5660_M_SV_SPM_SFT, 1, 1), 5012b26dd4cSOder Chiou SOC_DAPM_SINGLE("BST1 Switch", RT5660_SPO_MIXER, 5022b26dd4cSOder Chiou RT5660_M_BST1_SPM_SFT, 1, 1), 5032b26dd4cSOder Chiou }; 5042b26dd4cSOder Chiou 5052b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_lout_mix[] = { 5062b26dd4cSOder Chiou SOC_DAPM_SINGLE("DAC Switch", RT5660_LOUT_MIXER, 5072b26dd4cSOder Chiou RT5660_M_DAC1_LM_SFT, 1, 1), 5082b26dd4cSOder Chiou SOC_DAPM_SINGLE("OUTMIX Switch", RT5660_LOUT_MIXER, 5092b26dd4cSOder Chiou RT5660_M_LOVOL_LM_SFT, 1, 1), 5102b26dd4cSOder Chiou }; 5112b26dd4cSOder Chiou 5122b26dd4cSOder Chiou static const struct snd_kcontrol_new spk_vol_control = 5132b26dd4cSOder Chiou SOC_DAPM_SINGLE("Switch", RT5660_SPK_VOL, 5142b26dd4cSOder Chiou RT5660_VOL_L_SFT, 1, 1); 5152b26dd4cSOder Chiou 5162b26dd4cSOder Chiou static const struct snd_kcontrol_new lout_l_vol_control = 5172b26dd4cSOder Chiou SOC_DAPM_SINGLE("Switch", RT5660_LOUT_VOL, 5182b26dd4cSOder Chiou RT5660_VOL_L_SFT, 1, 1); 5192b26dd4cSOder Chiou 5202b26dd4cSOder Chiou static const struct snd_kcontrol_new lout_r_vol_control = 5212b26dd4cSOder Chiou SOC_DAPM_SINGLE("Switch", RT5660_LOUT_VOL, 5222b26dd4cSOder Chiou RT5660_VOL_R_SFT, 1, 1); 5232b26dd4cSOder Chiou 5242b26dd4cSOder Chiou /* Interface data select */ 5252b26dd4cSOder Chiou static const char * const rt5660_data_select[] = { 5262b26dd4cSOder Chiou "L/R", "R/L", "L/L", "R/R" 5272b26dd4cSOder Chiou }; 5282b26dd4cSOder Chiou 5292b26dd4cSOder Chiou static const SOC_ENUM_SINGLE_DECL(rt5660_if1_dac_enum, 5302b26dd4cSOder Chiou RT5660_DIG_INF1_DATA, RT5660_IF1_DAC_IN_SFT, rt5660_data_select); 5312b26dd4cSOder Chiou 5322b26dd4cSOder Chiou static const SOC_ENUM_SINGLE_DECL(rt5660_if1_adc_enum, 5332b26dd4cSOder Chiou RT5660_DIG_INF1_DATA, RT5660_IF1_ADC_IN_SFT, rt5660_data_select); 5342b26dd4cSOder Chiou 5352b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_if1_dac_swap_mux = 5362b26dd4cSOder Chiou SOC_DAPM_ENUM("IF1 DAC Swap Source", rt5660_if1_dac_enum); 5372b26dd4cSOder Chiou 5382b26dd4cSOder Chiou static const struct snd_kcontrol_new rt5660_if1_adc_swap_mux = 5392b26dd4cSOder Chiou SOC_DAPM_ENUM("IF1 ADC Swap Source", rt5660_if1_adc_enum); 5402b26dd4cSOder Chiou 5412b26dd4cSOder Chiou static int rt5660_lout_event(struct snd_soc_dapm_widget *w, 5422b26dd4cSOder Chiou struct snd_kcontrol *kcontrol, int event) 5432b26dd4cSOder Chiou { 5442b26dd4cSOder Chiou struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 5452b26dd4cSOder Chiou 5462b26dd4cSOder Chiou switch (event) { 5472b26dd4cSOder Chiou case SND_SOC_DAPM_POST_PMU: 5482b26dd4cSOder Chiou snd_soc_update_bits(codec, RT5660_LOUT_AMP_CTRL, 5492b26dd4cSOder Chiou RT5660_LOUT_CO_MASK | RT5660_LOUT_CB_MASK, 5502b26dd4cSOder Chiou RT5660_LOUT_CO_EN | RT5660_LOUT_CB_PU); 5512b26dd4cSOder Chiou break; 5522b26dd4cSOder Chiou 5532b26dd4cSOder Chiou case SND_SOC_DAPM_PRE_PMD: 5542b26dd4cSOder Chiou snd_soc_update_bits(codec, RT5660_LOUT_AMP_CTRL, 5552b26dd4cSOder Chiou RT5660_LOUT_CO_MASK | RT5660_LOUT_CB_MASK, 5562b26dd4cSOder Chiou RT5660_LOUT_CO_DIS | RT5660_LOUT_CB_PD); 5572b26dd4cSOder Chiou break; 5582b26dd4cSOder Chiou 5592b26dd4cSOder Chiou default: 5602b26dd4cSOder Chiou return 0; 5612b26dd4cSOder Chiou } 5622b26dd4cSOder Chiou 5632b26dd4cSOder Chiou return 0; 5642b26dd4cSOder Chiou } 5652b26dd4cSOder Chiou 5662b26dd4cSOder Chiou static const struct snd_soc_dapm_widget rt5660_dapm_widgets[] = { 5672b26dd4cSOder Chiou SND_SOC_DAPM_SUPPLY("LDO2", RT5660_PWR_ANLG1, 5682b26dd4cSOder Chiou RT5660_PWR_LDO2_BIT, 0, NULL, 0), 5692b26dd4cSOder Chiou SND_SOC_DAPM_SUPPLY("PLL1", RT5660_PWR_ANLG2, 5702b26dd4cSOder Chiou RT5660_PWR_PLL_BIT, 0, NULL, 0), 5712b26dd4cSOder Chiou 5722b26dd4cSOder Chiou /* MICBIAS */ 5732b26dd4cSOder Chiou SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5660_PWR_ANLG2, 5742b26dd4cSOder Chiou RT5660_PWR_MB1_BIT, 0, NULL, 0), 5752b26dd4cSOder Chiou SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5660_PWR_ANLG2, 5762b26dd4cSOder Chiou RT5660_PWR_MB2_BIT, 0, NULL, 0), 5772b26dd4cSOder Chiou 5782b26dd4cSOder Chiou /* Input Side */ 5792b26dd4cSOder Chiou /* Input Lines */ 5802b26dd4cSOder Chiou SND_SOC_DAPM_INPUT("DMIC L1"), 5812b26dd4cSOder Chiou SND_SOC_DAPM_INPUT("DMIC R1"), 5822b26dd4cSOder Chiou 5832b26dd4cSOder Chiou SND_SOC_DAPM_INPUT("IN1P"), 5842b26dd4cSOder Chiou SND_SOC_DAPM_INPUT("IN1N"), 5852b26dd4cSOder Chiou SND_SOC_DAPM_INPUT("IN2P"), 5862b26dd4cSOder Chiou SND_SOC_DAPM_INPUT("IN3P"), 5872b26dd4cSOder Chiou SND_SOC_DAPM_INPUT("IN3N"), 5882b26dd4cSOder Chiou 5892b26dd4cSOder Chiou SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 5902b26dd4cSOder Chiou rt5660_set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 5912b26dd4cSOder Chiou SND_SOC_DAPM_SUPPLY("DMIC Power", RT5660_DMIC_CTRL1, 5922b26dd4cSOder Chiou RT5660_DMIC_1_EN_SFT, 0, NULL, 0), 5932b26dd4cSOder Chiou 5942b26dd4cSOder Chiou /* Boost */ 5952b26dd4cSOder Chiou SND_SOC_DAPM_PGA("BST1", RT5660_PWR_ANLG2, RT5660_PWR_BST1_BIT, 0, 5962b26dd4cSOder Chiou NULL, 0), 5972b26dd4cSOder Chiou SND_SOC_DAPM_PGA("BST2", RT5660_PWR_ANLG2, RT5660_PWR_BST2_BIT, 0, 5982b26dd4cSOder Chiou NULL, 0), 5992b26dd4cSOder Chiou SND_SOC_DAPM_PGA("BST3", RT5660_PWR_ANLG2, RT5660_PWR_BST3_BIT, 0, 6002b26dd4cSOder Chiou NULL, 0), 6012b26dd4cSOder Chiou 6022b26dd4cSOder Chiou /* REC Mixer */ 6032b26dd4cSOder Chiou SND_SOC_DAPM_MIXER("RECMIXL", RT5660_PWR_MIXER, RT5660_PWR_RM_L_BIT, 6042b26dd4cSOder Chiou 0, rt5660_rec_l_mix, ARRAY_SIZE(rt5660_rec_l_mix)), 6052b26dd4cSOder Chiou SND_SOC_DAPM_MIXER("RECMIXR", RT5660_PWR_MIXER, RT5660_PWR_RM_R_BIT, 6062b26dd4cSOder Chiou 0, rt5660_rec_r_mix, ARRAY_SIZE(rt5660_rec_r_mix)), 6072b26dd4cSOder Chiou 6082b26dd4cSOder Chiou /* ADCs */ 6092b26dd4cSOder Chiou SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 6102b26dd4cSOder Chiou SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 6112b26dd4cSOder Chiou 6122b26dd4cSOder Chiou SND_SOC_DAPM_SUPPLY("ADC L power", RT5660_PWR_DIG1, 6132b26dd4cSOder Chiou RT5660_PWR_ADC_L_BIT, 0, NULL, 0), 6142b26dd4cSOder Chiou SND_SOC_DAPM_SUPPLY("ADC R power", RT5660_PWR_DIG1, 6152b26dd4cSOder Chiou RT5660_PWR_ADC_R_BIT, 0, NULL, 0), 6162b26dd4cSOder Chiou SND_SOC_DAPM_SUPPLY("ADC clock", RT5660_PR_BASE + RT5660_CHOP_DAC_ADC, 6172b26dd4cSOder Chiou 12, 0, NULL, 0), 6182b26dd4cSOder Chiou 6192b26dd4cSOder Chiou /* ADC Mixer */ 6202b26dd4cSOder Chiou SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5660_PWR_DIG2, 6212b26dd4cSOder Chiou RT5660_PWR_ADC_S1F_BIT, 0, NULL, 0), 6222b26dd4cSOder Chiou SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 6232b26dd4cSOder Chiou rt5660_sto1_adc_l_mix, ARRAY_SIZE(rt5660_sto1_adc_l_mix)), 6242b26dd4cSOder Chiou SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 6252b26dd4cSOder Chiou rt5660_sto1_adc_r_mix, ARRAY_SIZE(rt5660_sto1_adc_r_mix)), 6262b26dd4cSOder Chiou 6272b26dd4cSOder Chiou /* ADC */ 6282b26dd4cSOder Chiou SND_SOC_DAPM_ADC("Stereo1 ADC MIXL", NULL, RT5660_STO1_ADC_DIG_VOL, 6292b26dd4cSOder Chiou RT5660_L_MUTE_SFT, 1), 6302b26dd4cSOder Chiou SND_SOC_DAPM_ADC("Stereo1 ADC MIXR", NULL, RT5660_STO1_ADC_DIG_VOL, 6312b26dd4cSOder Chiou RT5660_R_MUTE_SFT, 1), 6322b26dd4cSOder Chiou 6332b26dd4cSOder Chiou /* Digital Interface */ 6342b26dd4cSOder Chiou SND_SOC_DAPM_SUPPLY("I2S1", RT5660_PWR_DIG1, RT5660_PWR_I2S1_BIT, 0, 6352b26dd4cSOder Chiou NULL, 0), 6362b26dd4cSOder Chiou SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 6372b26dd4cSOder Chiou SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 6382b26dd4cSOder Chiou SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 6392b26dd4cSOder Chiou SND_SOC_DAPM_MUX("IF1 DAC Swap Mux", SND_SOC_NOPM, 0, 0, 6402b26dd4cSOder Chiou &rt5660_if1_dac_swap_mux), 6412b26dd4cSOder Chiou SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 6422b26dd4cSOder Chiou SND_SOC_DAPM_MUX("IF1 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 6432b26dd4cSOder Chiou &rt5660_if1_adc_swap_mux), 6442b26dd4cSOder Chiou 6452b26dd4cSOder Chiou /* Audio Interface */ 6462b26dd4cSOder Chiou SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 6472b26dd4cSOder Chiou SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 6482b26dd4cSOder Chiou 6492b26dd4cSOder Chiou /* Output Side */ 6502b26dd4cSOder Chiou /* DAC mixer before sound effect */ 6512b26dd4cSOder Chiou SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, rt5660_dac_l_mix, 6522b26dd4cSOder Chiou ARRAY_SIZE(rt5660_dac_l_mix)), 6532b26dd4cSOder Chiou SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, rt5660_dac_r_mix, 6542b26dd4cSOder Chiou ARRAY_SIZE(rt5660_dac_r_mix)), 6552b26dd4cSOder Chiou 6562b26dd4cSOder Chiou /* DAC Mixer */ 6572b26dd4cSOder Chiou SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5660_PWR_DIG2, 6582b26dd4cSOder Chiou RT5660_PWR_DAC_S1F_BIT, 0, NULL, 0), 6592b26dd4cSOder Chiou SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 6602b26dd4cSOder Chiou rt5660_sto_dac_l_mix, ARRAY_SIZE(rt5660_sto_dac_l_mix)), 6612b26dd4cSOder Chiou SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 6622b26dd4cSOder Chiou rt5660_sto_dac_r_mix, ARRAY_SIZE(rt5660_sto_dac_r_mix)), 6632b26dd4cSOder Chiou 6642b26dd4cSOder Chiou /* DACs */ 6652b26dd4cSOder Chiou SND_SOC_DAPM_DAC("DAC L1", NULL, RT5660_PWR_DIG1, 6662b26dd4cSOder Chiou RT5660_PWR_DAC_L1_BIT, 0), 6672b26dd4cSOder Chiou SND_SOC_DAPM_DAC("DAC R1", NULL, RT5660_PWR_DIG1, 6682b26dd4cSOder Chiou RT5660_PWR_DAC_R1_BIT, 0), 6692b26dd4cSOder Chiou 6702b26dd4cSOder Chiou /* OUT Mixer */ 6712b26dd4cSOder Chiou SND_SOC_DAPM_MIXER("SPK MIX", RT5660_PWR_MIXER, RT5660_PWR_SM_BIT, 6722b26dd4cSOder Chiou 0, rt5660_spk_mix, ARRAY_SIZE(rt5660_spk_mix)), 6732b26dd4cSOder Chiou SND_SOC_DAPM_MIXER("OUT MIXL", RT5660_PWR_MIXER, RT5660_PWR_OM_L_BIT, 6742b26dd4cSOder Chiou 0, rt5660_out_l_mix, ARRAY_SIZE(rt5660_out_l_mix)), 6752b26dd4cSOder Chiou SND_SOC_DAPM_MIXER("OUT MIXR", RT5660_PWR_MIXER, RT5660_PWR_OM_R_BIT, 6762b26dd4cSOder Chiou 0, rt5660_out_r_mix, ARRAY_SIZE(rt5660_out_r_mix)), 6772b26dd4cSOder Chiou 6782b26dd4cSOder Chiou /* Output Volume */ 6792b26dd4cSOder Chiou SND_SOC_DAPM_SWITCH("SPKVOL", RT5660_PWR_VOL, 6802b26dd4cSOder Chiou RT5660_PWR_SV_BIT, 0, &spk_vol_control), 6812b26dd4cSOder Chiou SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 6822b26dd4cSOder Chiou 0, 0, NULL, 0), 6832b26dd4cSOder Chiou SND_SOC_DAPM_PGA("LOUTVOL", SND_SOC_NOPM, 6842b26dd4cSOder Chiou 0, 0, NULL, 0), 6852b26dd4cSOder Chiou SND_SOC_DAPM_SWITCH("LOUTVOL L", SND_SOC_NOPM, 6862b26dd4cSOder Chiou RT5660_PWR_LV_L_BIT, 0, &lout_l_vol_control), 6872b26dd4cSOder Chiou SND_SOC_DAPM_SWITCH("LOUTVOL R", SND_SOC_NOPM, 6882b26dd4cSOder Chiou RT5660_PWR_LV_R_BIT, 0, &lout_r_vol_control), 6892b26dd4cSOder Chiou 6902b26dd4cSOder Chiou /* HPO/LOUT/Mono Mixer */ 6912b26dd4cSOder Chiou SND_SOC_DAPM_MIXER("SPO MIX", SND_SOC_NOPM, 0, 6922b26dd4cSOder Chiou 0, rt5660_spo_mix, ARRAY_SIZE(rt5660_spo_mix)), 6932b26dd4cSOder Chiou SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, 6942b26dd4cSOder Chiou rt5660_lout_mix, ARRAY_SIZE(rt5660_lout_mix)), 6952b26dd4cSOder Chiou SND_SOC_DAPM_SUPPLY("VREF HP", RT5660_GEN_CTRL1, 6962b26dd4cSOder Chiou RT5660_PWR_VREF_HP_SFT, 0, NULL, 0), 6972b26dd4cSOder Chiou SND_SOC_DAPM_PGA_S("LOUT amp", 1, RT5660_PWR_ANLG1, 6982b26dd4cSOder Chiou RT5660_PWR_HA_BIT, 0, rt5660_lout_event, 6992b26dd4cSOder Chiou SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 7002b26dd4cSOder Chiou SND_SOC_DAPM_PGA_S("SPK amp", 1, RT5660_PWR_DIG1, 7012b26dd4cSOder Chiou RT5660_PWR_CLS_D_BIT, 0, NULL, 0), 7022b26dd4cSOder Chiou 7032b26dd4cSOder Chiou /* Output Lines */ 7042b26dd4cSOder Chiou SND_SOC_DAPM_OUTPUT("LOUTL"), 7052b26dd4cSOder Chiou SND_SOC_DAPM_OUTPUT("LOUTR"), 7062b26dd4cSOder Chiou SND_SOC_DAPM_OUTPUT("SPO"), 7072b26dd4cSOder Chiou }; 7082b26dd4cSOder Chiou 7092b26dd4cSOder Chiou static const struct snd_soc_dapm_route rt5660_dapm_routes[] = { 7102b26dd4cSOder Chiou { "MICBIAS1", NULL, "LDO2" }, 7112b26dd4cSOder Chiou { "MICBIAS2", NULL, "LDO2" }, 7122b26dd4cSOder Chiou 7132b26dd4cSOder Chiou { "BST1", NULL, "IN1P" }, 7142b26dd4cSOder Chiou { "BST1", NULL, "IN1N" }, 7152b26dd4cSOder Chiou { "BST2", NULL, "IN2P" }, 7162b26dd4cSOder Chiou { "BST3", NULL, "IN3P" }, 7172b26dd4cSOder Chiou { "BST3", NULL, "IN3N" }, 7182b26dd4cSOder Chiou 7192b26dd4cSOder Chiou { "RECMIXL", "BST3 Switch", "BST3" }, 7202b26dd4cSOder Chiou { "RECMIXL", "BST2 Switch", "BST2" }, 7212b26dd4cSOder Chiou { "RECMIXL", "BST1 Switch", "BST1" }, 7222b26dd4cSOder Chiou { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" }, 7232b26dd4cSOder Chiou 7242b26dd4cSOder Chiou { "RECMIXR", "BST3 Switch", "BST3" }, 7252b26dd4cSOder Chiou { "RECMIXR", "BST2 Switch", "BST2" }, 7262b26dd4cSOder Chiou { "RECMIXR", "BST1 Switch", "BST1" }, 7272b26dd4cSOder Chiou { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" }, 7282b26dd4cSOder Chiou 7292b26dd4cSOder Chiou { "ADC L", NULL, "RECMIXL" }, 7302b26dd4cSOder Chiou { "ADC L", NULL, "ADC L power" }, 7312b26dd4cSOder Chiou { "ADC L", NULL, "ADC clock" }, 7322b26dd4cSOder Chiou { "ADC R", NULL, "RECMIXR" }, 7332b26dd4cSOder Chiou { "ADC R", NULL, "ADC R power" }, 7342b26dd4cSOder Chiou { "ADC R", NULL, "ADC clock" }, 7352b26dd4cSOder Chiou 7362b26dd4cSOder Chiou {"DMIC L1", NULL, "DMIC CLK"}, 7372b26dd4cSOder Chiou {"DMIC L1", NULL, "DMIC Power"}, 7382b26dd4cSOder Chiou {"DMIC R1", NULL, "DMIC CLK"}, 7392b26dd4cSOder Chiou {"DMIC R1", NULL, "DMIC Power"}, 7402b26dd4cSOder Chiou 7412b26dd4cSOder Chiou { "Sto1 ADC MIXL", "ADC1 Switch", "ADC L" }, 7422b26dd4cSOder Chiou { "Sto1 ADC MIXL", "ADC2 Switch", "DMIC L1" }, 7432b26dd4cSOder Chiou { "Sto1 ADC MIXR", "ADC1 Switch", "ADC R" }, 7442b26dd4cSOder Chiou { "Sto1 ADC MIXR", "ADC2 Switch", "DMIC R1" }, 7452b26dd4cSOder Chiou 7462b26dd4cSOder Chiou { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 7472b26dd4cSOder Chiou { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 7482b26dd4cSOder Chiou { "adc stereo1 filter", NULL, "PLL1", rt5660_is_sys_clk_from_pll }, 7492b26dd4cSOder Chiou 7502b26dd4cSOder Chiou { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 7512b26dd4cSOder Chiou { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 7522b26dd4cSOder Chiou { "adc stereo1 filter", NULL, "PLL1", rt5660_is_sys_clk_from_pll }, 7532b26dd4cSOder Chiou 7542b26dd4cSOder Chiou { "IF1 ADC", NULL, "Stereo1 ADC MIXL" }, 7552b26dd4cSOder Chiou { "IF1 ADC", NULL, "Stereo1 ADC MIXR" }, 7562b26dd4cSOder Chiou { "IF1 ADC", NULL, "I2S1" }, 7572b26dd4cSOder Chiou 7582b26dd4cSOder Chiou { "IF1 ADC Swap Mux", "L/R", "IF1 ADC" }, 7592b26dd4cSOder Chiou { "IF1 ADC Swap Mux", "R/L", "IF1 ADC" }, 7602b26dd4cSOder Chiou { "IF1 ADC Swap Mux", "L/L", "IF1 ADC" }, 7612b26dd4cSOder Chiou { "IF1 ADC Swap Mux", "R/R", "IF1 ADC" }, 7622b26dd4cSOder Chiou { "AIF1TX", NULL, "IF1 ADC Swap Mux" }, 7632b26dd4cSOder Chiou 7642b26dd4cSOder Chiou { "IF1 DAC", NULL, "AIF1RX" }, 7652b26dd4cSOder Chiou { "IF1 DAC", NULL, "I2S1" }, 7662b26dd4cSOder Chiou 7672b26dd4cSOder Chiou { "IF1 DAC Swap Mux", "L/R", "IF1 DAC" }, 7682b26dd4cSOder Chiou { "IF1 DAC Swap Mux", "R/L", "IF1 DAC" }, 7692b26dd4cSOder Chiou { "IF1 DAC Swap Mux", "L/L", "IF1 DAC" }, 7702b26dd4cSOder Chiou { "IF1 DAC Swap Mux", "R/R", "IF1 DAC" }, 7712b26dd4cSOder Chiou 7722b26dd4cSOder Chiou { "IF1 DAC L", NULL, "IF1 DAC Swap Mux" }, 7732b26dd4cSOder Chiou { "IF1 DAC R", NULL, "IF1 DAC Swap Mux" }, 7742b26dd4cSOder Chiou 7752b26dd4cSOder Chiou { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" }, 7762b26dd4cSOder Chiou { "DAC1 MIXL", "DAC1 Switch", "IF1 DAC L" }, 7772b26dd4cSOder Chiou { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" }, 7782b26dd4cSOder Chiou { "DAC1 MIXR", "DAC1 Switch", "IF1 DAC R" }, 7792b26dd4cSOder Chiou 7802b26dd4cSOder Chiou { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 7812b26dd4cSOder Chiou { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" }, 7822b26dd4cSOder Chiou { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 7832b26dd4cSOder Chiou { "dac stereo1 filter", NULL, "PLL1", rt5660_is_sys_clk_from_pll }, 7842b26dd4cSOder Chiou { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 7852b26dd4cSOder Chiou { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" }, 7862b26dd4cSOder Chiou { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 7872b26dd4cSOder Chiou { "dac stereo1 filter", NULL, "PLL1", rt5660_is_sys_clk_from_pll }, 7882b26dd4cSOder Chiou 7892b26dd4cSOder Chiou { "DAC L1", NULL, "Stereo DAC MIXL" }, 7902b26dd4cSOder Chiou { "DAC R1", NULL, "Stereo DAC MIXR" }, 7912b26dd4cSOder Chiou 7922b26dd4cSOder Chiou { "SPK MIX", "BST3 Switch", "BST3" }, 7932b26dd4cSOder Chiou { "SPK MIX", "BST1 Switch", "BST1" }, 7942b26dd4cSOder Chiou { "SPK MIX", "DACL Switch", "DAC L1" }, 7952b26dd4cSOder Chiou { "SPK MIX", "DACR Switch", "DAC R1" }, 7962b26dd4cSOder Chiou { "SPK MIX", "OUTMIXL Switch", "OUT MIXL" }, 7972b26dd4cSOder Chiou 7982b26dd4cSOder Chiou { "OUT MIXL", "BST3 Switch", "BST3" }, 7992b26dd4cSOder Chiou { "OUT MIXL", "BST2 Switch", "BST2" }, 8002b26dd4cSOder Chiou { "OUT MIXL", "BST1 Switch", "BST1" }, 8012b26dd4cSOder Chiou { "OUT MIXL", "RECMIXL Switch", "RECMIXL" }, 8022b26dd4cSOder Chiou { "OUT MIXL", "DACR Switch", "DAC R1" }, 8032b26dd4cSOder Chiou { "OUT MIXL", "DACL Switch", "DAC L1" }, 8042b26dd4cSOder Chiou 8052b26dd4cSOder Chiou { "OUT MIXR", "BST2 Switch", "BST2" }, 8062b26dd4cSOder Chiou { "OUT MIXR", "BST1 Switch", "BST1" }, 8072b26dd4cSOder Chiou { "OUT MIXR", "RECMIXR Switch", "RECMIXR" }, 8082b26dd4cSOder Chiou { "OUT MIXR", "DACR Switch", "DAC R1" }, 8092b26dd4cSOder Chiou { "OUT MIXR", "DACL Switch", "DAC L1" }, 8102b26dd4cSOder Chiou 8112b26dd4cSOder Chiou { "SPO MIX", "DACR Switch", "DAC R1" }, 8122b26dd4cSOder Chiou { "SPO MIX", "DACL Switch", "DAC L1" }, 8132b26dd4cSOder Chiou { "SPO MIX", "SPKVOL Switch", "SPKVOL" }, 8142b26dd4cSOder Chiou { "SPO MIX", "BST1 Switch", "BST1" }, 8152b26dd4cSOder Chiou 8162b26dd4cSOder Chiou { "SPKVOL", "Switch", "SPK MIX" }, 8172b26dd4cSOder Chiou { "LOUTVOL L", "Switch", "OUT MIXL" }, 8182b26dd4cSOder Chiou { "LOUTVOL R", "Switch", "OUT MIXR" }, 8192b26dd4cSOder Chiou 8202b26dd4cSOder Chiou { "LOUTVOL", NULL, "LOUTVOL L" }, 8212b26dd4cSOder Chiou { "LOUTVOL", NULL, "LOUTVOL R" }, 8222b26dd4cSOder Chiou 8232b26dd4cSOder Chiou { "DAC 1", NULL, "DAC L1" }, 8242b26dd4cSOder Chiou { "DAC 1", NULL, "DAC R1" }, 8252b26dd4cSOder Chiou 8262b26dd4cSOder Chiou { "LOUT MIX", "DAC Switch", "DAC 1" }, 8272b26dd4cSOder Chiou { "LOUT MIX", "OUTMIX Switch", "LOUTVOL" }, 8282b26dd4cSOder Chiou 8292b26dd4cSOder Chiou { "LOUT amp", NULL, "LOUT MIX" }, 8302b26dd4cSOder Chiou { "LOUT amp", NULL, "VREF HP" }, 8312b26dd4cSOder Chiou { "LOUTL", NULL, "LOUT amp" }, 8322b26dd4cSOder Chiou { "LOUTR", NULL, "LOUT amp" }, 8332b26dd4cSOder Chiou 8342b26dd4cSOder Chiou { "SPK amp", NULL, "SPO MIX" }, 8352b26dd4cSOder Chiou { "SPO", NULL, "SPK amp" }, 8362b26dd4cSOder Chiou }; 8372b26dd4cSOder Chiou 8382b26dd4cSOder Chiou static int rt5660_hw_params(struct snd_pcm_substream *substream, 8392b26dd4cSOder Chiou struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 8402b26dd4cSOder Chiou { 8412b26dd4cSOder Chiou struct snd_soc_codec *codec = dai->codec; 8422b26dd4cSOder Chiou struct rt5660_priv *rt5660 = snd_soc_codec_get_drvdata(codec); 8432b26dd4cSOder Chiou unsigned int val_len = 0, val_clk, mask_clk; 8442b26dd4cSOder Chiou int pre_div, bclk_ms, frame_size; 8452b26dd4cSOder Chiou 8462b26dd4cSOder Chiou rt5660->lrck[dai->id] = params_rate(params); 8472b26dd4cSOder Chiou pre_div = rl6231_get_clk_info(rt5660->sysclk, rt5660->lrck[dai->id]); 8482b26dd4cSOder Chiou if (pre_div < 0) { 8492b26dd4cSOder Chiou dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n", 8502b26dd4cSOder Chiou rt5660->lrck[dai->id], dai->id); 8512b26dd4cSOder Chiou return -EINVAL; 8522b26dd4cSOder Chiou } 8532b26dd4cSOder Chiou 8542b26dd4cSOder Chiou frame_size = snd_soc_params_to_frame_size(params); 8552b26dd4cSOder Chiou if (frame_size < 0) { 8562b26dd4cSOder Chiou dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); 8572b26dd4cSOder Chiou return frame_size; 8582b26dd4cSOder Chiou } 8592b26dd4cSOder Chiou 8602b26dd4cSOder Chiou if (frame_size > 32) 8612b26dd4cSOder Chiou bclk_ms = 1; 8622b26dd4cSOder Chiou else 8632b26dd4cSOder Chiou bclk_ms = 0; 8642b26dd4cSOder Chiou 8652b26dd4cSOder Chiou rt5660->bclk[dai->id] = rt5660->lrck[dai->id] * (32 << bclk_ms); 8662b26dd4cSOder Chiou 8672b26dd4cSOder Chiou dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 8682b26dd4cSOder Chiou rt5660->bclk[dai->id], rt5660->lrck[dai->id]); 8692b26dd4cSOder Chiou dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 8702b26dd4cSOder Chiou bclk_ms, pre_div, dai->id); 8712b26dd4cSOder Chiou 8722b26dd4cSOder Chiou switch (params_width(params)) { 8732b26dd4cSOder Chiou case 16: 8742b26dd4cSOder Chiou break; 8752b26dd4cSOder Chiou case 20: 8762b26dd4cSOder Chiou val_len |= RT5660_I2S_DL_20; 8772b26dd4cSOder Chiou break; 8782b26dd4cSOder Chiou case 24: 8792b26dd4cSOder Chiou val_len |= RT5660_I2S_DL_24; 8802b26dd4cSOder Chiou break; 8812b26dd4cSOder Chiou case 8: 8822b26dd4cSOder Chiou val_len |= RT5660_I2S_DL_8; 8832b26dd4cSOder Chiou break; 8842b26dd4cSOder Chiou default: 8852b26dd4cSOder Chiou return -EINVAL; 8862b26dd4cSOder Chiou } 8872b26dd4cSOder Chiou 8882b26dd4cSOder Chiou switch (dai->id) { 8892b26dd4cSOder Chiou case RT5660_AIF1: 8902b26dd4cSOder Chiou mask_clk = RT5660_I2S_BCLK_MS1_MASK | RT5660_I2S_PD1_MASK; 8912b26dd4cSOder Chiou val_clk = bclk_ms << RT5660_I2S_BCLK_MS1_SFT | 8922b26dd4cSOder Chiou pre_div << RT5660_I2S_PD1_SFT; 8932b26dd4cSOder Chiou snd_soc_update_bits(codec, RT5660_I2S1_SDP, RT5660_I2S_DL_MASK, 8942b26dd4cSOder Chiou val_len); 8952b26dd4cSOder Chiou snd_soc_update_bits(codec, RT5660_ADDA_CLK1, mask_clk, val_clk); 8962b26dd4cSOder Chiou break; 8972b26dd4cSOder Chiou 8982b26dd4cSOder Chiou default: 8992b26dd4cSOder Chiou dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id); 9002b26dd4cSOder Chiou return -EINVAL; 9012b26dd4cSOder Chiou } 9022b26dd4cSOder Chiou 9032b26dd4cSOder Chiou return 0; 9042b26dd4cSOder Chiou } 9052b26dd4cSOder Chiou 9062b26dd4cSOder Chiou static int rt5660_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 9072b26dd4cSOder Chiou { 9082b26dd4cSOder Chiou struct snd_soc_codec *codec = dai->codec; 9092b26dd4cSOder Chiou struct rt5660_priv *rt5660 = snd_soc_codec_get_drvdata(codec); 9102b26dd4cSOder Chiou unsigned int reg_val = 0; 9112b26dd4cSOder Chiou 9122b26dd4cSOder Chiou switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 9132b26dd4cSOder Chiou case SND_SOC_DAIFMT_CBM_CFM: 9142b26dd4cSOder Chiou rt5660->master[dai->id] = 1; 9152b26dd4cSOder Chiou break; 9162b26dd4cSOder Chiou 9172b26dd4cSOder Chiou case SND_SOC_DAIFMT_CBS_CFS: 9182b26dd4cSOder Chiou reg_val |= RT5660_I2S_MS_S; 9192b26dd4cSOder Chiou rt5660->master[dai->id] = 0; 9202b26dd4cSOder Chiou break; 9212b26dd4cSOder Chiou 9222b26dd4cSOder Chiou default: 9232b26dd4cSOder Chiou return -EINVAL; 9242b26dd4cSOder Chiou } 9252b26dd4cSOder Chiou 9262b26dd4cSOder Chiou switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 9272b26dd4cSOder Chiou case SND_SOC_DAIFMT_NB_NF: 9282b26dd4cSOder Chiou break; 9292b26dd4cSOder Chiou 9302b26dd4cSOder Chiou case SND_SOC_DAIFMT_IB_NF: 9312b26dd4cSOder Chiou reg_val |= RT5660_I2S_BP_INV; 9322b26dd4cSOder Chiou break; 9332b26dd4cSOder Chiou 9342b26dd4cSOder Chiou default: 9352b26dd4cSOder Chiou return -EINVAL; 9362b26dd4cSOder Chiou } 9372b26dd4cSOder Chiou 9382b26dd4cSOder Chiou switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 9392b26dd4cSOder Chiou case SND_SOC_DAIFMT_I2S: 9402b26dd4cSOder Chiou break; 9412b26dd4cSOder Chiou 9422b26dd4cSOder Chiou case SND_SOC_DAIFMT_LEFT_J: 9432b26dd4cSOder Chiou reg_val |= RT5660_I2S_DF_LEFT; 9442b26dd4cSOder Chiou break; 9452b26dd4cSOder Chiou 9462b26dd4cSOder Chiou case SND_SOC_DAIFMT_DSP_A: 9472b26dd4cSOder Chiou reg_val |= RT5660_I2S_DF_PCM_A; 9482b26dd4cSOder Chiou break; 9492b26dd4cSOder Chiou 9502b26dd4cSOder Chiou case SND_SOC_DAIFMT_DSP_B: 9512b26dd4cSOder Chiou reg_val |= RT5660_I2S_DF_PCM_B; 9522b26dd4cSOder Chiou break; 9532b26dd4cSOder Chiou 9542b26dd4cSOder Chiou default: 9552b26dd4cSOder Chiou return -EINVAL; 9562b26dd4cSOder Chiou } 9572b26dd4cSOder Chiou 9582b26dd4cSOder Chiou switch (dai->id) { 9592b26dd4cSOder Chiou case RT5660_AIF1: 9602b26dd4cSOder Chiou snd_soc_update_bits(codec, RT5660_I2S1_SDP, 9612b26dd4cSOder Chiou RT5660_I2S_MS_MASK | RT5660_I2S_BP_MASK | 9622b26dd4cSOder Chiou RT5660_I2S_DF_MASK, reg_val); 9632b26dd4cSOder Chiou break; 9642b26dd4cSOder Chiou 9652b26dd4cSOder Chiou default: 9662b26dd4cSOder Chiou dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id); 9672b26dd4cSOder Chiou return -EINVAL; 9682b26dd4cSOder Chiou } 9692b26dd4cSOder Chiou 9702b26dd4cSOder Chiou return 0; 9712b26dd4cSOder Chiou } 9722b26dd4cSOder Chiou 9732b26dd4cSOder Chiou static int rt5660_set_dai_sysclk(struct snd_soc_dai *dai, 9742b26dd4cSOder Chiou int clk_id, unsigned int freq, int dir) 9752b26dd4cSOder Chiou { 9762b26dd4cSOder Chiou struct snd_soc_codec *codec = dai->codec; 9772b26dd4cSOder Chiou struct rt5660_priv *rt5660 = snd_soc_codec_get_drvdata(codec); 9782b26dd4cSOder Chiou unsigned int reg_val = 0; 9792b26dd4cSOder Chiou 9802b26dd4cSOder Chiou if (freq == rt5660->sysclk && clk_id == rt5660->sysclk_src) 9812b26dd4cSOder Chiou return 0; 9822b26dd4cSOder Chiou 9832b26dd4cSOder Chiou switch (clk_id) { 9842b26dd4cSOder Chiou case RT5660_SCLK_S_MCLK: 9852b26dd4cSOder Chiou reg_val |= RT5660_SCLK_SRC_MCLK; 9862b26dd4cSOder Chiou break; 9872b26dd4cSOder Chiou 9882b26dd4cSOder Chiou case RT5660_SCLK_S_PLL1: 9892b26dd4cSOder Chiou reg_val |= RT5660_SCLK_SRC_PLL1; 9902b26dd4cSOder Chiou break; 9912b26dd4cSOder Chiou 9922b26dd4cSOder Chiou case RT5660_SCLK_S_RCCLK: 9932b26dd4cSOder Chiou reg_val |= RT5660_SCLK_SRC_RCCLK; 9942b26dd4cSOder Chiou break; 9952b26dd4cSOder Chiou 9962b26dd4cSOder Chiou default: 9972b26dd4cSOder Chiou dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); 9982b26dd4cSOder Chiou return -EINVAL; 9992b26dd4cSOder Chiou } 10002b26dd4cSOder Chiou 10012b26dd4cSOder Chiou snd_soc_update_bits(codec, RT5660_GLB_CLK, RT5660_SCLK_SRC_MASK, 10022b26dd4cSOder Chiou reg_val); 10032b26dd4cSOder Chiou 10042b26dd4cSOder Chiou rt5660->sysclk = freq; 10052b26dd4cSOder Chiou rt5660->sysclk_src = clk_id; 10062b26dd4cSOder Chiou 10072b26dd4cSOder Chiou dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 10082b26dd4cSOder Chiou 10092b26dd4cSOder Chiou return 0; 10102b26dd4cSOder Chiou } 10112b26dd4cSOder Chiou 10122b26dd4cSOder Chiou static int rt5660_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 10132b26dd4cSOder Chiou unsigned int freq_in, unsigned int freq_out) 10142b26dd4cSOder Chiou { 10152b26dd4cSOder Chiou struct snd_soc_codec *codec = dai->codec; 10162b26dd4cSOder Chiou struct rt5660_priv *rt5660 = snd_soc_codec_get_drvdata(codec); 10172b26dd4cSOder Chiou struct rl6231_pll_code pll_code; 10182b26dd4cSOder Chiou int ret; 10192b26dd4cSOder Chiou 10202b26dd4cSOder Chiou if (source == rt5660->pll_src && freq_in == rt5660->pll_in && 10212b26dd4cSOder Chiou freq_out == rt5660->pll_out) 10222b26dd4cSOder Chiou return 0; 10232b26dd4cSOder Chiou 10242b26dd4cSOder Chiou if (!freq_in || !freq_out) { 10252b26dd4cSOder Chiou dev_dbg(codec->dev, "PLL disabled\n"); 10262b26dd4cSOder Chiou 10272b26dd4cSOder Chiou rt5660->pll_in = 0; 10282b26dd4cSOder Chiou rt5660->pll_out = 0; 10292b26dd4cSOder Chiou snd_soc_update_bits(codec, RT5660_GLB_CLK, 10302b26dd4cSOder Chiou RT5660_SCLK_SRC_MASK, RT5660_SCLK_SRC_MCLK); 10312b26dd4cSOder Chiou return 0; 10322b26dd4cSOder Chiou } 10332b26dd4cSOder Chiou 10342b26dd4cSOder Chiou switch (source) { 10352b26dd4cSOder Chiou case RT5660_PLL1_S_MCLK: 10362b26dd4cSOder Chiou snd_soc_update_bits(codec, RT5660_GLB_CLK, 10372b26dd4cSOder Chiou RT5660_PLL1_SRC_MASK, RT5660_PLL1_SRC_MCLK); 10382b26dd4cSOder Chiou break; 10392b26dd4cSOder Chiou 10402b26dd4cSOder Chiou case RT5660_PLL1_S_BCLK: 10412b26dd4cSOder Chiou snd_soc_update_bits(codec, RT5660_GLB_CLK, 10422b26dd4cSOder Chiou RT5660_PLL1_SRC_MASK, RT5660_PLL1_SRC_BCLK1); 10432b26dd4cSOder Chiou break; 10442b26dd4cSOder Chiou 10452b26dd4cSOder Chiou default: 10462b26dd4cSOder Chiou dev_err(codec->dev, "Unknown PLL source %d\n", source); 10472b26dd4cSOder Chiou return -EINVAL; 10482b26dd4cSOder Chiou } 10492b26dd4cSOder Chiou 10502b26dd4cSOder Chiou ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 10512b26dd4cSOder Chiou if (ret < 0) { 10522b26dd4cSOder Chiou dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); 10532b26dd4cSOder Chiou return ret; 10542b26dd4cSOder Chiou } 10552b26dd4cSOder Chiou 10562b26dd4cSOder Chiou dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", 10572b26dd4cSOder Chiou pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 10582b26dd4cSOder Chiou pll_code.n_code, pll_code.k_code); 10592b26dd4cSOder Chiou 10602b26dd4cSOder Chiou snd_soc_write(codec, RT5660_PLL_CTRL1, 10612b26dd4cSOder Chiou pll_code.n_code << RT5660_PLL_N_SFT | pll_code.k_code); 10622b26dd4cSOder Chiou snd_soc_write(codec, RT5660_PLL_CTRL2, 10632b26dd4cSOder Chiou (pll_code.m_bp ? 0 : pll_code.m_code) << RT5660_PLL_M_SFT | 10642b26dd4cSOder Chiou pll_code.m_bp << RT5660_PLL_M_BP_SFT); 10652b26dd4cSOder Chiou 10662b26dd4cSOder Chiou rt5660->pll_in = freq_in; 10672b26dd4cSOder Chiou rt5660->pll_out = freq_out; 10682b26dd4cSOder Chiou rt5660->pll_src = source; 10692b26dd4cSOder Chiou 10702b26dd4cSOder Chiou return 0; 10712b26dd4cSOder Chiou } 10722b26dd4cSOder Chiou 10732b26dd4cSOder Chiou static int rt5660_set_bias_level(struct snd_soc_codec *codec, 10742b26dd4cSOder Chiou enum snd_soc_bias_level level) 10752b26dd4cSOder Chiou { 10762b26dd4cSOder Chiou struct rt5660_priv *rt5660 = snd_soc_codec_get_drvdata(codec); 10772b26dd4cSOder Chiou int ret; 10782b26dd4cSOder Chiou 10792b26dd4cSOder Chiou switch (level) { 10802b26dd4cSOder Chiou case SND_SOC_BIAS_ON: 10812b26dd4cSOder Chiou break; 10822b26dd4cSOder Chiou 10832b26dd4cSOder Chiou case SND_SOC_BIAS_PREPARE: 10842b26dd4cSOder Chiou snd_soc_update_bits(codec, RT5660_GEN_CTRL1, 10852b26dd4cSOder Chiou RT5660_DIG_GATE_CTRL, RT5660_DIG_GATE_CTRL); 10862b26dd4cSOder Chiou 10872b26dd4cSOder Chiou if (IS_ERR(rt5660->mclk)) 10882b26dd4cSOder Chiou break; 10892b26dd4cSOder Chiou 10902b26dd4cSOder Chiou if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON) { 10912b26dd4cSOder Chiou clk_disable_unprepare(rt5660->mclk); 10922b26dd4cSOder Chiou } else { 10932b26dd4cSOder Chiou ret = clk_prepare_enable(rt5660->mclk); 10942b26dd4cSOder Chiou if (ret) 10952b26dd4cSOder Chiou return ret; 10962b26dd4cSOder Chiou } 10972b26dd4cSOder Chiou break; 10982b26dd4cSOder Chiou 10992b26dd4cSOder Chiou case SND_SOC_BIAS_STANDBY: 11002b26dd4cSOder Chiou if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { 11012b26dd4cSOder Chiou snd_soc_update_bits(codec, RT5660_PWR_ANLG1, 11022b26dd4cSOder Chiou RT5660_PWR_VREF1 | RT5660_PWR_MB | 11032b26dd4cSOder Chiou RT5660_PWR_BG | RT5660_PWR_VREF2, 11042b26dd4cSOder Chiou RT5660_PWR_VREF1 | RT5660_PWR_MB | 11052b26dd4cSOder Chiou RT5660_PWR_BG | RT5660_PWR_VREF2); 11062b26dd4cSOder Chiou usleep_range(10000, 15000); 11072b26dd4cSOder Chiou snd_soc_update_bits(codec, RT5660_PWR_ANLG1, 11082b26dd4cSOder Chiou RT5660_PWR_FV1 | RT5660_PWR_FV2, 11092b26dd4cSOder Chiou RT5660_PWR_FV1 | RT5660_PWR_FV2); 11102b26dd4cSOder Chiou } 11112b26dd4cSOder Chiou break; 11122b26dd4cSOder Chiou 11132b26dd4cSOder Chiou case SND_SOC_BIAS_OFF: 11142b26dd4cSOder Chiou snd_soc_update_bits(codec, RT5660_GEN_CTRL1, 11152b26dd4cSOder Chiou RT5660_DIG_GATE_CTRL, 0); 11162b26dd4cSOder Chiou break; 11172b26dd4cSOder Chiou 11182b26dd4cSOder Chiou default: 11192b26dd4cSOder Chiou break; 11202b26dd4cSOder Chiou } 11212b26dd4cSOder Chiou 11222b26dd4cSOder Chiou return 0; 11232b26dd4cSOder Chiou } 11242b26dd4cSOder Chiou 11252b26dd4cSOder Chiou static int rt5660_probe(struct snd_soc_codec *codec) 11262b26dd4cSOder Chiou { 11272b26dd4cSOder Chiou struct rt5660_priv *rt5660 = snd_soc_codec_get_drvdata(codec); 11282b26dd4cSOder Chiou 11292b26dd4cSOder Chiou rt5660->codec = codec; 11302b26dd4cSOder Chiou 11312b26dd4cSOder Chiou return 0; 11322b26dd4cSOder Chiou } 11332b26dd4cSOder Chiou 11342b26dd4cSOder Chiou static int rt5660_remove(struct snd_soc_codec *codec) 11352b26dd4cSOder Chiou { 11362b26dd4cSOder Chiou return snd_soc_write(codec, RT5660_RESET, 0); 11372b26dd4cSOder Chiou } 11382b26dd4cSOder Chiou 11392b26dd4cSOder Chiou #ifdef CONFIG_PM 11402b26dd4cSOder Chiou static int rt5660_suspend(struct snd_soc_codec *codec) 11412b26dd4cSOder Chiou { 11422b26dd4cSOder Chiou struct rt5660_priv *rt5660 = snd_soc_codec_get_drvdata(codec); 11432b26dd4cSOder Chiou 11442b26dd4cSOder Chiou regcache_cache_only(rt5660->regmap, true); 11452b26dd4cSOder Chiou regcache_mark_dirty(rt5660->regmap); 11462b26dd4cSOder Chiou 11472b26dd4cSOder Chiou return 0; 11482b26dd4cSOder Chiou } 11492b26dd4cSOder Chiou 11502b26dd4cSOder Chiou static int rt5660_resume(struct snd_soc_codec *codec) 11512b26dd4cSOder Chiou { 11522b26dd4cSOder Chiou struct rt5660_priv *rt5660 = snd_soc_codec_get_drvdata(codec); 11532b26dd4cSOder Chiou 11542b26dd4cSOder Chiou if (rt5660->pdata.poweroff_codec_in_suspend) 11552b26dd4cSOder Chiou usleep_range(350000, 400000); 11562b26dd4cSOder Chiou 11572b26dd4cSOder Chiou regcache_cache_only(rt5660->regmap, false); 11582b26dd4cSOder Chiou regcache_sync(rt5660->regmap); 11592b26dd4cSOder Chiou 11602b26dd4cSOder Chiou return 0; 11612b26dd4cSOder Chiou } 11622b26dd4cSOder Chiou #else 11632b26dd4cSOder Chiou #define rt5660_suspend NULL 11642b26dd4cSOder Chiou #define rt5660_resume NULL 11652b26dd4cSOder Chiou #endif 11662b26dd4cSOder Chiou 11672b26dd4cSOder Chiou #define RT5660_STEREO_RATES SNDRV_PCM_RATE_8000_192000 11682b26dd4cSOder Chiou #define RT5660_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 11692b26dd4cSOder Chiou SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 11702b26dd4cSOder Chiou 11712b26dd4cSOder Chiou static const struct snd_soc_dai_ops rt5660_aif_dai_ops = { 11722b26dd4cSOder Chiou .hw_params = rt5660_hw_params, 11732b26dd4cSOder Chiou .set_fmt = rt5660_set_dai_fmt, 11742b26dd4cSOder Chiou .set_sysclk = rt5660_set_dai_sysclk, 11752b26dd4cSOder Chiou .set_pll = rt5660_set_dai_pll, 11762b26dd4cSOder Chiou }; 11772b26dd4cSOder Chiou 11782b26dd4cSOder Chiou static struct snd_soc_dai_driver rt5660_dai[] = { 11792b26dd4cSOder Chiou { 11802b26dd4cSOder Chiou .name = "rt5660-aif1", 11812b26dd4cSOder Chiou .id = RT5660_AIF1, 11822b26dd4cSOder Chiou .playback = { 11832b26dd4cSOder Chiou .stream_name = "AIF1 Playback", 11842b26dd4cSOder Chiou .channels_min = 1, 11852b26dd4cSOder Chiou .channels_max = 2, 11862b26dd4cSOder Chiou .rates = RT5660_STEREO_RATES, 11872b26dd4cSOder Chiou .formats = RT5660_FORMATS, 11882b26dd4cSOder Chiou }, 11892b26dd4cSOder Chiou .capture = { 11902b26dd4cSOder Chiou .stream_name = "AIF1 Capture", 11912b26dd4cSOder Chiou .channels_min = 1, 11922b26dd4cSOder Chiou .channels_max = 2, 11932b26dd4cSOder Chiou .rates = RT5660_STEREO_RATES, 11942b26dd4cSOder Chiou .formats = RT5660_FORMATS, 11952b26dd4cSOder Chiou }, 11962b26dd4cSOder Chiou .ops = &rt5660_aif_dai_ops, 11972b26dd4cSOder Chiou }, 11982b26dd4cSOder Chiou }; 11992b26dd4cSOder Chiou 12002b26dd4cSOder Chiou static struct snd_soc_codec_driver soc_codec_dev_rt5660 = { 12012b26dd4cSOder Chiou .probe = rt5660_probe, 12022b26dd4cSOder Chiou .remove = rt5660_remove, 12032b26dd4cSOder Chiou .suspend = rt5660_suspend, 12042b26dd4cSOder Chiou .resume = rt5660_resume, 12052b26dd4cSOder Chiou .set_bias_level = rt5660_set_bias_level, 12062b26dd4cSOder Chiou .idle_bias_off = true, 12072b26dd4cSOder Chiou .component_driver = { 12082b26dd4cSOder Chiou .controls = rt5660_snd_controls, 12092b26dd4cSOder Chiou .num_controls = ARRAY_SIZE(rt5660_snd_controls), 12102b26dd4cSOder Chiou .dapm_widgets = rt5660_dapm_widgets, 12112b26dd4cSOder Chiou .num_dapm_widgets = ARRAY_SIZE(rt5660_dapm_widgets), 12122b26dd4cSOder Chiou .dapm_routes = rt5660_dapm_routes, 12132b26dd4cSOder Chiou .num_dapm_routes = ARRAY_SIZE(rt5660_dapm_routes), 12142b26dd4cSOder Chiou }, 12152b26dd4cSOder Chiou }; 12162b26dd4cSOder Chiou 12172b26dd4cSOder Chiou static const struct regmap_config rt5660_regmap = { 12182b26dd4cSOder Chiou .reg_bits = 8, 12192b26dd4cSOder Chiou .val_bits = 16, 12202b26dd4cSOder Chiou .use_single_rw = true, 12212b26dd4cSOder Chiou 12222b26dd4cSOder Chiou .max_register = RT5660_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5660_ranges) * 12232b26dd4cSOder Chiou RT5660_PR_SPACING), 12242b26dd4cSOder Chiou .volatile_reg = rt5660_volatile_register, 12252b26dd4cSOder Chiou .readable_reg = rt5660_readable_register, 12262b26dd4cSOder Chiou 12272b26dd4cSOder Chiou .cache_type = REGCACHE_RBTREE, 12282b26dd4cSOder Chiou .reg_defaults = rt5660_reg, 12292b26dd4cSOder Chiou .num_reg_defaults = ARRAY_SIZE(rt5660_reg), 12302b26dd4cSOder Chiou .ranges = rt5660_ranges, 12312b26dd4cSOder Chiou .num_ranges = ARRAY_SIZE(rt5660_ranges), 12322b26dd4cSOder Chiou }; 12332b26dd4cSOder Chiou 12342b26dd4cSOder Chiou static const struct i2c_device_id rt5660_i2c_id[] = { 12352b26dd4cSOder Chiou { "rt5660", 0 }, 12362b26dd4cSOder Chiou { } 12372b26dd4cSOder Chiou }; 12382b26dd4cSOder Chiou MODULE_DEVICE_TABLE(i2c, rt5660_i2c_id); 12392b26dd4cSOder Chiou 12402b26dd4cSOder Chiou static const struct of_device_id rt5660_of_match[] = { 12412b26dd4cSOder Chiou { .compatible = "realtek,rt5660", }, 12422b26dd4cSOder Chiou {}, 12432b26dd4cSOder Chiou }; 12442b26dd4cSOder Chiou MODULE_DEVICE_TABLE(of, rt5660_of_match); 12452b26dd4cSOder Chiou 12462b26dd4cSOder Chiou static const struct acpi_device_id rt5660_acpi_match[] = { 12472b26dd4cSOder Chiou { "10EC5660", 0 }, 12482b26dd4cSOder Chiou { }, 12492b26dd4cSOder Chiou }; 12502b26dd4cSOder Chiou MODULE_DEVICE_TABLE(acpi, rt5660_acpi_match); 12512b26dd4cSOder Chiou 12522b26dd4cSOder Chiou static int rt5660_parse_dt(struct rt5660_priv *rt5660, struct device *dev) 12532b26dd4cSOder Chiou { 12542b26dd4cSOder Chiou rt5660->pdata.in1_diff = device_property_read_bool(dev, 12552b26dd4cSOder Chiou "realtek,in1-differential"); 12562b26dd4cSOder Chiou rt5660->pdata.in3_diff = device_property_read_bool(dev, 12572b26dd4cSOder Chiou "realtek,in3-differential"); 12582b26dd4cSOder Chiou rt5660->pdata.poweroff_codec_in_suspend = device_property_read_bool(dev, 12592b26dd4cSOder Chiou "realtek,poweroff-in-suspend"); 12602b26dd4cSOder Chiou device_property_read_u32(dev, "realtek,dmic1-data-pin", 12612b26dd4cSOder Chiou &rt5660->pdata.dmic1_data_pin); 12622b26dd4cSOder Chiou 12632b26dd4cSOder Chiou return 0; 12642b26dd4cSOder Chiou } 12652b26dd4cSOder Chiou 12662b26dd4cSOder Chiou static int rt5660_i2c_probe(struct i2c_client *i2c, 12672b26dd4cSOder Chiou const struct i2c_device_id *id) 12682b26dd4cSOder Chiou { 12692b26dd4cSOder Chiou struct rt5660_platform_data *pdata = dev_get_platdata(&i2c->dev); 12702b26dd4cSOder Chiou struct rt5660_priv *rt5660; 12712b26dd4cSOder Chiou int ret; 12722b26dd4cSOder Chiou unsigned int val; 12732b26dd4cSOder Chiou 12742b26dd4cSOder Chiou rt5660 = devm_kzalloc(&i2c->dev, sizeof(struct rt5660_priv), 12752b26dd4cSOder Chiou GFP_KERNEL); 12762b26dd4cSOder Chiou 12772b26dd4cSOder Chiou if (rt5660 == NULL) 12782b26dd4cSOder Chiou return -ENOMEM; 12792b26dd4cSOder Chiou 12802b26dd4cSOder Chiou /* Check if MCLK provided */ 12812b26dd4cSOder Chiou rt5660->mclk = devm_clk_get(&i2c->dev, "mclk"); 12822b26dd4cSOder Chiou if (PTR_ERR(rt5660->mclk) == -EPROBE_DEFER) 12832b26dd4cSOder Chiou return -EPROBE_DEFER; 12842b26dd4cSOder Chiou 12852b26dd4cSOder Chiou i2c_set_clientdata(i2c, rt5660); 12862b26dd4cSOder Chiou 12872b26dd4cSOder Chiou if (pdata) 12882b26dd4cSOder Chiou rt5660->pdata = *pdata; 12892b26dd4cSOder Chiou else if (i2c->dev.of_node) 12902b26dd4cSOder Chiou rt5660_parse_dt(rt5660, &i2c->dev); 12912b26dd4cSOder Chiou 12922b26dd4cSOder Chiou rt5660->regmap = devm_regmap_init_i2c(i2c, &rt5660_regmap); 12932b26dd4cSOder Chiou if (IS_ERR(rt5660->regmap)) { 12942b26dd4cSOder Chiou ret = PTR_ERR(rt5660->regmap); 12952b26dd4cSOder Chiou dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 12962b26dd4cSOder Chiou ret); 12972b26dd4cSOder Chiou return ret; 12982b26dd4cSOder Chiou } 12992b26dd4cSOder Chiou 13002b26dd4cSOder Chiou regmap_read(rt5660->regmap, RT5660_VENDOR_ID2, &val); 13012b26dd4cSOder Chiou if (val != RT5660_DEVICE_ID) { 13022b26dd4cSOder Chiou dev_err(&i2c->dev, 13032b26dd4cSOder Chiou "Device with ID register %#x is not rt5660\n", val); 13042b26dd4cSOder Chiou return -ENODEV; 13052b26dd4cSOder Chiou } 13062b26dd4cSOder Chiou 13072b26dd4cSOder Chiou regmap_write(rt5660->regmap, RT5660_RESET, 0); 13082b26dd4cSOder Chiou 13092b26dd4cSOder Chiou ret = regmap_register_patch(rt5660->regmap, rt5660_patch, 13102b26dd4cSOder Chiou ARRAY_SIZE(rt5660_patch)); 13112b26dd4cSOder Chiou if (ret != 0) 13122b26dd4cSOder Chiou dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 13132b26dd4cSOder Chiou 1314*d01580c3SBard Liao regmap_update_bits(rt5660->regmap, RT5660_GEN_CTRL1, 1315*d01580c3SBard Liao RT5660_AUTO_DIS_AMP | RT5660_MCLK_DET | RT5660_POW_CLKDET, 1316*d01580c3SBard Liao RT5660_AUTO_DIS_AMP | RT5660_MCLK_DET | RT5660_POW_CLKDET); 1317*d01580c3SBard Liao 13182b26dd4cSOder Chiou if (rt5660->pdata.dmic1_data_pin) { 13192b26dd4cSOder Chiou regmap_update_bits(rt5660->regmap, RT5660_GPIO_CTRL1, 13202b26dd4cSOder Chiou RT5660_GP1_PIN_MASK, RT5660_GP1_PIN_DMIC1_SCL); 13212b26dd4cSOder Chiou 13222b26dd4cSOder Chiou if (rt5660->pdata.dmic1_data_pin == RT5660_DMIC1_DATA_GPIO2) 13232b26dd4cSOder Chiou regmap_update_bits(rt5660->regmap, RT5660_DMIC_CTRL1, 13242b26dd4cSOder Chiou RT5660_SEL_DMIC_DATA_MASK, 13252b26dd4cSOder Chiou RT5660_SEL_DMIC_DATA_GPIO2); 13262b26dd4cSOder Chiou else if (rt5660->pdata.dmic1_data_pin == RT5660_DMIC1_DATA_IN1P) 13272b26dd4cSOder Chiou regmap_update_bits(rt5660->regmap, RT5660_DMIC_CTRL1, 13282b26dd4cSOder Chiou RT5660_SEL_DMIC_DATA_MASK, 13292b26dd4cSOder Chiou RT5660_SEL_DMIC_DATA_IN1P); 13302b26dd4cSOder Chiou } 13312b26dd4cSOder Chiou 13322b26dd4cSOder Chiou return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5660, 13332b26dd4cSOder Chiou rt5660_dai, ARRAY_SIZE(rt5660_dai)); 13342b26dd4cSOder Chiou } 13352b26dd4cSOder Chiou 13362b26dd4cSOder Chiou static int rt5660_i2c_remove(struct i2c_client *i2c) 13372b26dd4cSOder Chiou { 13382b26dd4cSOder Chiou snd_soc_unregister_codec(&i2c->dev); 13392b26dd4cSOder Chiou 13402b26dd4cSOder Chiou return 0; 13412b26dd4cSOder Chiou } 13422b26dd4cSOder Chiou 13432b26dd4cSOder Chiou static struct i2c_driver rt5660_i2c_driver = { 13442b26dd4cSOder Chiou .driver = { 13452b26dd4cSOder Chiou .name = "rt5660", 13462b26dd4cSOder Chiou .acpi_match_table = ACPI_PTR(rt5660_acpi_match), 13472b26dd4cSOder Chiou .of_match_table = of_match_ptr(rt5660_of_match), 13482b26dd4cSOder Chiou }, 13492b26dd4cSOder Chiou .probe = rt5660_i2c_probe, 13502b26dd4cSOder Chiou .remove = rt5660_i2c_remove, 13512b26dd4cSOder Chiou .id_table = rt5660_i2c_id, 13522b26dd4cSOder Chiou }; 13532b26dd4cSOder Chiou module_i2c_driver(rt5660_i2c_driver); 13542b26dd4cSOder Chiou 13552b26dd4cSOder Chiou MODULE_DESCRIPTION("ASoC RT5660 driver"); 13562b26dd4cSOder Chiou MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 13572b26dd4cSOder Chiou MODULE_LICENSE("GPL v2"); 1358