1 /* 2 * rt5645.c -- RT5645 ALSA SoC audio codec driver 3 * 4 * Copyright 2013 Realtek Semiconductor Corp. 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/platform_device.h> 19 #include <linux/spi/spi.h> 20 #include <linux/gpio.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/acpi.h> 23 #include <linux/dmi.h> 24 #include <linux/regulator/consumer.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/jack.h> 29 #include <sound/soc.h> 30 #include <sound/soc-dapm.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 34 #include "rl6231.h" 35 #include "rt5645.h" 36 37 #define RT5645_DEVICE_ID 0x6308 38 #define RT5650_DEVICE_ID 0x6419 39 40 #define RT5645_PR_RANGE_BASE (0xff + 1) 41 #define RT5645_PR_SPACING 0x100 42 43 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING)) 44 45 #define RT5645_HWEQ_NUM 57 46 47 static const struct regmap_range_cfg rt5645_ranges[] = { 48 { 49 .name = "PR", 50 .range_min = RT5645_PR_BASE, 51 .range_max = RT5645_PR_BASE + 0xf8, 52 .selector_reg = RT5645_PRIV_INDEX, 53 .selector_mask = 0xff, 54 .selector_shift = 0x0, 55 .window_start = RT5645_PRIV_DATA, 56 .window_len = 0x1, 57 }, 58 }; 59 60 static const struct reg_sequence init_list[] = { 61 {RT5645_PR_BASE + 0x3d, 0x3600}, 62 {RT5645_PR_BASE + 0x1c, 0xfd20}, 63 {RT5645_PR_BASE + 0x20, 0x611f}, 64 {RT5645_PR_BASE + 0x21, 0x4040}, 65 {RT5645_PR_BASE + 0x23, 0x0004}, 66 }; 67 #define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list) 68 69 static const struct reg_sequence rt5650_init_list[] = { 70 {0xf6, 0x0100}, 71 }; 72 73 static const struct reg_default rt5645_reg[] = { 74 { 0x00, 0x0000 }, 75 { 0x01, 0xc8c8 }, 76 { 0x02, 0xc8c8 }, 77 { 0x03, 0xc8c8 }, 78 { 0x0a, 0x0002 }, 79 { 0x0b, 0x2827 }, 80 { 0x0c, 0xe000 }, 81 { 0x0d, 0x0000 }, 82 { 0x0e, 0x0000 }, 83 { 0x0f, 0x0808 }, 84 { 0x14, 0x3333 }, 85 { 0x16, 0x4b00 }, 86 { 0x18, 0x018b }, 87 { 0x19, 0xafaf }, 88 { 0x1a, 0xafaf }, 89 { 0x1b, 0x0001 }, 90 { 0x1c, 0x2f2f }, 91 { 0x1d, 0x2f2f }, 92 { 0x1e, 0x0000 }, 93 { 0x20, 0x0000 }, 94 { 0x27, 0x7060 }, 95 { 0x28, 0x7070 }, 96 { 0x29, 0x8080 }, 97 { 0x2a, 0x5656 }, 98 { 0x2b, 0x5454 }, 99 { 0x2c, 0xaaa0 }, 100 { 0x2d, 0x0000 }, 101 { 0x2f, 0x1002 }, 102 { 0x31, 0x5000 }, 103 { 0x32, 0x0000 }, 104 { 0x33, 0x0000 }, 105 { 0x34, 0x0000 }, 106 { 0x35, 0x0000 }, 107 { 0x3b, 0x0000 }, 108 { 0x3c, 0x007f }, 109 { 0x3d, 0x0000 }, 110 { 0x3e, 0x007f }, 111 { 0x3f, 0x0000 }, 112 { 0x40, 0x001f }, 113 { 0x41, 0x0000 }, 114 { 0x42, 0x001f }, 115 { 0x45, 0x6000 }, 116 { 0x46, 0x003e }, 117 { 0x47, 0x003e }, 118 { 0x48, 0xf807 }, 119 { 0x4a, 0x0004 }, 120 { 0x4d, 0x0000 }, 121 { 0x4e, 0x0000 }, 122 { 0x4f, 0x01ff }, 123 { 0x50, 0x0000 }, 124 { 0x51, 0x0000 }, 125 { 0x52, 0x01ff }, 126 { 0x53, 0xf000 }, 127 { 0x56, 0x0111 }, 128 { 0x57, 0x0064 }, 129 { 0x58, 0xef0e }, 130 { 0x59, 0xf0f0 }, 131 { 0x5a, 0xef0e }, 132 { 0x5b, 0xf0f0 }, 133 { 0x5c, 0xef0e }, 134 { 0x5d, 0xf0f0 }, 135 { 0x5e, 0xf000 }, 136 { 0x5f, 0x0000 }, 137 { 0x61, 0x0300 }, 138 { 0x62, 0x0000 }, 139 { 0x63, 0x00c2 }, 140 { 0x64, 0x0000 }, 141 { 0x65, 0x0000 }, 142 { 0x66, 0x0000 }, 143 { 0x6a, 0x0000 }, 144 { 0x6c, 0x0aaa }, 145 { 0x70, 0x8000 }, 146 { 0x71, 0x8000 }, 147 { 0x72, 0x8000 }, 148 { 0x73, 0x7770 }, 149 { 0x74, 0x3e00 }, 150 { 0x75, 0x2409 }, 151 { 0x76, 0x000a }, 152 { 0x77, 0x0c00 }, 153 { 0x78, 0x0000 }, 154 { 0x79, 0x0123 }, 155 { 0x80, 0x0000 }, 156 { 0x81, 0x0000 }, 157 { 0x82, 0x0000 }, 158 { 0x83, 0x0000 }, 159 { 0x84, 0x0000 }, 160 { 0x85, 0x0000 }, 161 { 0x8a, 0x0000 }, 162 { 0x8e, 0x0004 }, 163 { 0x8f, 0x1100 }, 164 { 0x90, 0x0646 }, 165 { 0x91, 0x0c06 }, 166 { 0x93, 0x0000 }, 167 { 0x94, 0x0200 }, 168 { 0x95, 0x0000 }, 169 { 0x9a, 0x2184 }, 170 { 0x9b, 0x010a }, 171 { 0x9c, 0x0aea }, 172 { 0x9d, 0x000c }, 173 { 0x9e, 0x0400 }, 174 { 0xa0, 0xa0a8 }, 175 { 0xa1, 0x0059 }, 176 { 0xa2, 0x0001 }, 177 { 0xae, 0x6000 }, 178 { 0xaf, 0x0000 }, 179 { 0xb0, 0x6000 }, 180 { 0xb1, 0x0000 }, 181 { 0xb2, 0x0000 }, 182 { 0xb3, 0x001f }, 183 { 0xb4, 0x020c }, 184 { 0xb5, 0x1f00 }, 185 { 0xb6, 0x0000 }, 186 { 0xbb, 0x0000 }, 187 { 0xbc, 0x0000 }, 188 { 0xbd, 0x0000 }, 189 { 0xbe, 0x0000 }, 190 { 0xbf, 0x3100 }, 191 { 0xc0, 0x0000 }, 192 { 0xc1, 0x0000 }, 193 { 0xc2, 0x0000 }, 194 { 0xc3, 0x2000 }, 195 { 0xcd, 0x0000 }, 196 { 0xce, 0x0000 }, 197 { 0xcf, 0x1813 }, 198 { 0xd0, 0x0690 }, 199 { 0xd1, 0x1c17 }, 200 { 0xd3, 0xb320 }, 201 { 0xd4, 0x0000 }, 202 { 0xd6, 0x0400 }, 203 { 0xd9, 0x0809 }, 204 { 0xda, 0x0000 }, 205 { 0xdb, 0x0003 }, 206 { 0xdc, 0x0049 }, 207 { 0xdd, 0x001b }, 208 { 0xdf, 0x0008 }, 209 { 0xe0, 0x4000 }, 210 { 0xe6, 0x8000 }, 211 { 0xe7, 0x0200 }, 212 { 0xec, 0xb300 }, 213 { 0xed, 0x0000 }, 214 { 0xf0, 0x001f }, 215 { 0xf1, 0x020c }, 216 { 0xf2, 0x1f00 }, 217 { 0xf3, 0x0000 }, 218 { 0xf4, 0x4000 }, 219 { 0xf8, 0x0000 }, 220 { 0xf9, 0x0000 }, 221 { 0xfa, 0x2060 }, 222 { 0xfb, 0x4040 }, 223 { 0xfc, 0x0000 }, 224 { 0xfd, 0x0002 }, 225 { 0xfe, 0x10ec }, 226 { 0xff, 0x6308 }, 227 }; 228 229 struct rt5645_eq_param_s { 230 unsigned short reg; 231 unsigned short val; 232 }; 233 234 static const char *const rt5645_supply_names[] = { 235 "avdd", 236 "cpvdd", 237 }; 238 239 struct rt5645_priv { 240 struct snd_soc_codec *codec; 241 struct rt5645_platform_data pdata; 242 struct regmap *regmap; 243 struct i2c_client *i2c; 244 struct gpio_desc *gpiod_hp_det; 245 struct snd_soc_jack *hp_jack; 246 struct snd_soc_jack *mic_jack; 247 struct snd_soc_jack *btn_jack; 248 struct delayed_work jack_detect_work; 249 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)]; 250 struct rt5645_eq_param_s *eq_param; 251 252 int codec_type; 253 int sysclk; 254 int sysclk_src; 255 int lrck[RT5645_AIFS]; 256 int bclk[RT5645_AIFS]; 257 int master[RT5645_AIFS]; 258 259 int pll_src; 260 int pll_in; 261 int pll_out; 262 263 int jack_type; 264 bool en_button_func; 265 bool hp_on; 266 }; 267 268 static int rt5645_reset(struct snd_soc_codec *codec) 269 { 270 return snd_soc_write(codec, RT5645_RESET, 0); 271 } 272 273 static bool rt5645_volatile_register(struct device *dev, unsigned int reg) 274 { 275 int i; 276 277 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { 278 if (reg >= rt5645_ranges[i].range_min && 279 reg <= rt5645_ranges[i].range_max) { 280 return true; 281 } 282 } 283 284 switch (reg) { 285 case RT5645_RESET: 286 case RT5645_PRIV_DATA: 287 case RT5645_IN1_CTRL1: 288 case RT5645_IN1_CTRL2: 289 case RT5645_IN1_CTRL3: 290 case RT5645_A_JD_CTRL1: 291 case RT5645_ADC_EQ_CTRL1: 292 case RT5645_EQ_CTRL1: 293 case RT5645_ALC_CTRL_1: 294 case RT5645_IRQ_CTRL2: 295 case RT5645_IRQ_CTRL3: 296 case RT5645_INT_IRQ_ST: 297 case RT5645_IL_CMD: 298 case RT5650_4BTN_IL_CMD1: 299 case RT5645_VENDOR_ID: 300 case RT5645_VENDOR_ID1: 301 case RT5645_VENDOR_ID2: 302 return true; 303 default: 304 return false; 305 } 306 } 307 308 static bool rt5645_readable_register(struct device *dev, unsigned int reg) 309 { 310 int i; 311 312 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { 313 if (reg >= rt5645_ranges[i].range_min && 314 reg <= rt5645_ranges[i].range_max) { 315 return true; 316 } 317 } 318 319 switch (reg) { 320 case RT5645_RESET: 321 case RT5645_SPK_VOL: 322 case RT5645_HP_VOL: 323 case RT5645_LOUT1: 324 case RT5645_IN1_CTRL1: 325 case RT5645_IN1_CTRL2: 326 case RT5645_IN1_CTRL3: 327 case RT5645_IN2_CTRL: 328 case RT5645_INL1_INR1_VOL: 329 case RT5645_SPK_FUNC_LIM: 330 case RT5645_ADJ_HPF_CTRL: 331 case RT5645_DAC1_DIG_VOL: 332 case RT5645_DAC2_DIG_VOL: 333 case RT5645_DAC_CTRL: 334 case RT5645_STO1_ADC_DIG_VOL: 335 case RT5645_MONO_ADC_DIG_VOL: 336 case RT5645_ADC_BST_VOL1: 337 case RT5645_ADC_BST_VOL2: 338 case RT5645_STO1_ADC_MIXER: 339 case RT5645_MONO_ADC_MIXER: 340 case RT5645_AD_DA_MIXER: 341 case RT5645_STO_DAC_MIXER: 342 case RT5645_MONO_DAC_MIXER: 343 case RT5645_DIG_MIXER: 344 case RT5650_A_DAC_SOUR: 345 case RT5645_DIG_INF1_DATA: 346 case RT5645_PDM_OUT_CTRL: 347 case RT5645_REC_L1_MIXER: 348 case RT5645_REC_L2_MIXER: 349 case RT5645_REC_R1_MIXER: 350 case RT5645_REC_R2_MIXER: 351 case RT5645_HPMIXL_CTRL: 352 case RT5645_HPOMIXL_CTRL: 353 case RT5645_HPMIXR_CTRL: 354 case RT5645_HPOMIXR_CTRL: 355 case RT5645_HPO_MIXER: 356 case RT5645_SPK_L_MIXER: 357 case RT5645_SPK_R_MIXER: 358 case RT5645_SPO_MIXER: 359 case RT5645_SPO_CLSD_RATIO: 360 case RT5645_OUT_L1_MIXER: 361 case RT5645_OUT_R1_MIXER: 362 case RT5645_OUT_L_GAIN1: 363 case RT5645_OUT_L_GAIN2: 364 case RT5645_OUT_R_GAIN1: 365 case RT5645_OUT_R_GAIN2: 366 case RT5645_LOUT_MIXER: 367 case RT5645_HAPTIC_CTRL1: 368 case RT5645_HAPTIC_CTRL2: 369 case RT5645_HAPTIC_CTRL3: 370 case RT5645_HAPTIC_CTRL4: 371 case RT5645_HAPTIC_CTRL5: 372 case RT5645_HAPTIC_CTRL6: 373 case RT5645_HAPTIC_CTRL7: 374 case RT5645_HAPTIC_CTRL8: 375 case RT5645_HAPTIC_CTRL9: 376 case RT5645_HAPTIC_CTRL10: 377 case RT5645_PWR_DIG1: 378 case RT5645_PWR_DIG2: 379 case RT5645_PWR_ANLG1: 380 case RT5645_PWR_ANLG2: 381 case RT5645_PWR_MIXER: 382 case RT5645_PWR_VOL: 383 case RT5645_PRIV_INDEX: 384 case RT5645_PRIV_DATA: 385 case RT5645_I2S1_SDP: 386 case RT5645_I2S2_SDP: 387 case RT5645_ADDA_CLK1: 388 case RT5645_ADDA_CLK2: 389 case RT5645_DMIC_CTRL1: 390 case RT5645_DMIC_CTRL2: 391 case RT5645_TDM_CTRL_1: 392 case RT5645_TDM_CTRL_2: 393 case RT5645_TDM_CTRL_3: 394 case RT5650_TDM_CTRL_4: 395 case RT5645_GLB_CLK: 396 case RT5645_PLL_CTRL1: 397 case RT5645_PLL_CTRL2: 398 case RT5645_ASRC_1: 399 case RT5645_ASRC_2: 400 case RT5645_ASRC_3: 401 case RT5645_ASRC_4: 402 case RT5645_DEPOP_M1: 403 case RT5645_DEPOP_M2: 404 case RT5645_DEPOP_M3: 405 case RT5645_CHARGE_PUMP: 406 case RT5645_MICBIAS: 407 case RT5645_A_JD_CTRL1: 408 case RT5645_VAD_CTRL4: 409 case RT5645_CLSD_OUT_CTRL: 410 case RT5645_ADC_EQ_CTRL1: 411 case RT5645_ADC_EQ_CTRL2: 412 case RT5645_EQ_CTRL1: 413 case RT5645_EQ_CTRL2: 414 case RT5645_ALC_CTRL_1: 415 case RT5645_ALC_CTRL_2: 416 case RT5645_ALC_CTRL_3: 417 case RT5645_ALC_CTRL_4: 418 case RT5645_ALC_CTRL_5: 419 case RT5645_JD_CTRL: 420 case RT5645_IRQ_CTRL1: 421 case RT5645_IRQ_CTRL2: 422 case RT5645_IRQ_CTRL3: 423 case RT5645_INT_IRQ_ST: 424 case RT5645_GPIO_CTRL1: 425 case RT5645_GPIO_CTRL2: 426 case RT5645_GPIO_CTRL3: 427 case RT5645_BASS_BACK: 428 case RT5645_MP3_PLUS1: 429 case RT5645_MP3_PLUS2: 430 case RT5645_ADJ_HPF1: 431 case RT5645_ADJ_HPF2: 432 case RT5645_HP_CALIB_AMP_DET: 433 case RT5645_SV_ZCD1: 434 case RT5645_SV_ZCD2: 435 case RT5645_IL_CMD: 436 case RT5645_IL_CMD2: 437 case RT5645_IL_CMD3: 438 case RT5650_4BTN_IL_CMD1: 439 case RT5650_4BTN_IL_CMD2: 440 case RT5645_DRC1_HL_CTRL1: 441 case RT5645_DRC2_HL_CTRL1: 442 case RT5645_ADC_MONO_HP_CTRL1: 443 case RT5645_ADC_MONO_HP_CTRL2: 444 case RT5645_DRC2_CTRL1: 445 case RT5645_DRC2_CTRL2: 446 case RT5645_DRC2_CTRL3: 447 case RT5645_DRC2_CTRL4: 448 case RT5645_DRC2_CTRL5: 449 case RT5645_JD_CTRL3: 450 case RT5645_JD_CTRL4: 451 case RT5645_GEN_CTRL1: 452 case RT5645_GEN_CTRL2: 453 case RT5645_GEN_CTRL3: 454 case RT5645_VENDOR_ID: 455 case RT5645_VENDOR_ID1: 456 case RT5645_VENDOR_ID2: 457 return true; 458 default: 459 return false; 460 } 461 } 462 463 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 464 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 465 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 466 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 467 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 468 469 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 470 static const DECLARE_TLV_DB_RANGE(bst_tlv, 471 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 472 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 473 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 474 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 475 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 476 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 477 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 478 ); 479 480 /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */ 481 static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv, 482 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0), 483 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0), 484 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0), 485 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0) 486 ); 487 488 static int rt5645_hweq_info(struct snd_kcontrol *kcontrol, 489 struct snd_ctl_elem_info *uinfo) 490 { 491 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 492 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s); 493 494 return 0; 495 } 496 497 static int rt5645_hweq_get(struct snd_kcontrol *kcontrol, 498 struct snd_ctl_elem_value *ucontrol) 499 { 500 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 501 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 502 struct rt5645_eq_param_s *eq_param = 503 (struct rt5645_eq_param_s *)ucontrol->value.bytes.data; 504 int i; 505 506 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 507 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg); 508 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val); 509 } 510 511 return 0; 512 } 513 514 static bool rt5645_validate_hweq(unsigned short reg) 515 { 516 if ((reg >= 0x1a4 && reg <= 0x1cd) | (reg >= 0x1e5 && reg <= 0x1f8) | 517 (reg == RT5645_EQ_CTRL2)) 518 return true; 519 520 return false; 521 } 522 523 static int rt5645_hweq_put(struct snd_kcontrol *kcontrol, 524 struct snd_ctl_elem_value *ucontrol) 525 { 526 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 527 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 528 struct rt5645_eq_param_s *eq_param = 529 (struct rt5645_eq_param_s *)ucontrol->value.bytes.data; 530 int i; 531 532 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 533 eq_param[i].reg = be16_to_cpu(eq_param[i].reg); 534 eq_param[i].val = be16_to_cpu(eq_param[i].val); 535 } 536 537 /* The final setting of the table should be RT5645_EQ_CTRL2 */ 538 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) { 539 if (eq_param[i].reg == 0) 540 continue; 541 else if (eq_param[i].reg != RT5645_EQ_CTRL2) 542 return 0; 543 else 544 break; 545 } 546 547 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 548 if (!rt5645_validate_hweq(eq_param[i].reg) && 549 eq_param[i].reg != 0) 550 return 0; 551 else if (eq_param[i].reg == 0) 552 break; 553 } 554 555 memcpy(rt5645->eq_param, eq_param, 556 RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s)); 557 558 return 0; 559 } 560 561 #define RT5645_HWEQ(xname) \ 562 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 563 .info = rt5645_hweq_info, \ 564 .get = rt5645_hweq_get, \ 565 .put = rt5645_hweq_put \ 566 } 567 568 static const struct snd_kcontrol_new rt5645_snd_controls[] = { 569 /* Speaker Output Volume */ 570 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL, 571 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 572 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL, 573 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 574 575 /* ClassD modulator Speaker Gain Ratio */ 576 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO, 577 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv), 578 579 /* Headphone Output Volume */ 580 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL, 581 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 582 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL, 583 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 584 585 /* OUTPUT Control */ 586 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1, 587 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 588 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1, 589 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 590 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1, 591 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 592 593 /* DAC Digital Volume */ 594 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL, 595 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1), 596 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL, 597 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 598 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL, 599 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 600 601 /* IN1/IN2 Control */ 602 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1, 603 RT5645_BST_SFT1, 8, 0, bst_tlv), 604 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL, 605 RT5645_BST_SFT2, 8, 0, bst_tlv), 606 607 /* INL/INR Volume Control */ 608 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL, 609 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv), 610 611 /* ADC Digital Volume Control */ 612 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL, 613 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 614 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL, 615 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 616 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL, 617 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 618 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL, 619 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 620 621 /* ADC Boost Volume Control */ 622 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1, 623 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0, 624 adc_bst_tlv), 625 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2, 626 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0, 627 adc_bst_tlv), 628 629 /* I2S2 function select */ 630 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT, 631 1, 1), 632 RT5645_HWEQ("Speaker HWEQ"), 633 }; 634 635 /** 636 * set_dmic_clk - Set parameter of dmic. 637 * 638 * @w: DAPM widget. 639 * @kcontrol: The kcontrol of this widget. 640 * @event: Event id. 641 * 642 */ 643 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 644 struct snd_kcontrol *kcontrol, int event) 645 { 646 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 647 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 648 int idx, rate; 649 650 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap, 651 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT); 652 idx = rl6231_calc_dmic_clk(rate); 653 if (idx < 0) 654 dev_err(codec->dev, "Failed to set DMIC clock\n"); 655 else 656 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1, 657 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT); 658 return idx; 659 } 660 661 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 662 struct snd_soc_dapm_widget *sink) 663 { 664 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 665 unsigned int val; 666 667 val = snd_soc_read(codec, RT5645_GLB_CLK); 668 val &= RT5645_SCLK_SRC_MASK; 669 if (val == RT5645_SCLK_SRC_PLL1) 670 return 1; 671 else 672 return 0; 673 } 674 675 static int is_using_asrc(struct snd_soc_dapm_widget *source, 676 struct snd_soc_dapm_widget *sink) 677 { 678 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 679 unsigned int reg, shift, val; 680 681 switch (source->shift) { 682 case 0: 683 reg = RT5645_ASRC_3; 684 shift = 0; 685 break; 686 case 1: 687 reg = RT5645_ASRC_3; 688 shift = 4; 689 break; 690 case 3: 691 reg = RT5645_ASRC_2; 692 shift = 0; 693 break; 694 case 8: 695 reg = RT5645_ASRC_2; 696 shift = 4; 697 break; 698 case 9: 699 reg = RT5645_ASRC_2; 700 shift = 8; 701 break; 702 case 10: 703 reg = RT5645_ASRC_2; 704 shift = 12; 705 break; 706 default: 707 return 0; 708 } 709 710 val = (snd_soc_read(codec, reg) >> shift) & 0xf; 711 switch (val) { 712 case 1: 713 case 2: 714 case 3: 715 case 4: 716 return 1; 717 default: 718 return 0; 719 } 720 721 } 722 723 static int rt5645_enable_hweq(struct snd_soc_codec *codec) 724 { 725 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 726 int i; 727 728 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 729 if (rt5645_validate_hweq(rt5645->eq_param[i].reg)) 730 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg, 731 rt5645->eq_param[i].val); 732 else 733 break; 734 } 735 736 return 0; 737 } 738 739 /** 740 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters 741 * @codec: SoC audio codec device. 742 * @filter_mask: mask of filters. 743 * @clk_src: clock source 744 * 745 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can 746 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 747 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 748 * ASRC function will track i2s clock and generate a corresponding system clock 749 * for codec. This function provides an API to select the clock source for a 750 * set of filters specified by the mask. And the codec driver will turn on ASRC 751 * for these filters if ASRC is selected as their clock source. 752 */ 753 int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec, 754 unsigned int filter_mask, unsigned int clk_src) 755 { 756 unsigned int asrc2_mask = 0; 757 unsigned int asrc2_value = 0; 758 unsigned int asrc3_mask = 0; 759 unsigned int asrc3_value = 0; 760 761 switch (clk_src) { 762 case RT5645_CLK_SEL_SYS: 763 case RT5645_CLK_SEL_I2S1_ASRC: 764 case RT5645_CLK_SEL_I2S2_ASRC: 765 case RT5645_CLK_SEL_SYS2: 766 break; 767 768 default: 769 return -EINVAL; 770 } 771 772 if (filter_mask & RT5645_DA_STEREO_FILTER) { 773 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK; 774 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK) 775 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT); 776 } 777 778 if (filter_mask & RT5645_DA_MONO_L_FILTER) { 779 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK; 780 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK) 781 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT); 782 } 783 784 if (filter_mask & RT5645_DA_MONO_R_FILTER) { 785 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK; 786 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK) 787 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT); 788 } 789 790 if (filter_mask & RT5645_AD_STEREO_FILTER) { 791 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK; 792 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK) 793 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT); 794 } 795 796 if (filter_mask & RT5645_AD_MONO_L_FILTER) { 797 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK; 798 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK) 799 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT); 800 } 801 802 if (filter_mask & RT5645_AD_MONO_R_FILTER) { 803 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK; 804 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK) 805 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT); 806 } 807 808 if (asrc2_mask) 809 snd_soc_update_bits(codec, RT5645_ASRC_2, 810 asrc2_mask, asrc2_value); 811 812 if (asrc3_mask) 813 snd_soc_update_bits(codec, RT5645_ASRC_3, 814 asrc3_mask, asrc3_value); 815 816 return 0; 817 } 818 EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src); 819 820 /* Digital Mixer */ 821 static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = { 822 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, 823 RT5645_M_ADC_L1_SFT, 1, 1), 824 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, 825 RT5645_M_ADC_L2_SFT, 1, 1), 826 }; 827 828 static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = { 829 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, 830 RT5645_M_ADC_R1_SFT, 1, 1), 831 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, 832 RT5645_M_ADC_R2_SFT, 1, 1), 833 }; 834 835 static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = { 836 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, 837 RT5645_M_MONO_ADC_L1_SFT, 1, 1), 838 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, 839 RT5645_M_MONO_ADC_L2_SFT, 1, 1), 840 }; 841 842 static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = { 843 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, 844 RT5645_M_MONO_ADC_R1_SFT, 1, 1), 845 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, 846 RT5645_M_MONO_ADC_R2_SFT, 1, 1), 847 }; 848 849 static const struct snd_kcontrol_new rt5645_dac_l_mix[] = { 850 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, 851 RT5645_M_ADCMIX_L_SFT, 1, 1), 852 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, 853 RT5645_M_DAC1_L_SFT, 1, 1), 854 }; 855 856 static const struct snd_kcontrol_new rt5645_dac_r_mix[] = { 857 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, 858 RT5645_M_ADCMIX_R_SFT, 1, 1), 859 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, 860 RT5645_M_DAC1_R_SFT, 1, 1), 861 }; 862 863 static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = { 864 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, 865 RT5645_M_DAC_L1_SFT, 1, 1), 866 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER, 867 RT5645_M_DAC_L2_SFT, 1, 1), 868 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, 869 RT5645_M_DAC_R1_STO_L_SFT, 1, 1), 870 }; 871 872 static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = { 873 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, 874 RT5645_M_DAC_R1_SFT, 1, 1), 875 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER, 876 RT5645_M_DAC_R2_SFT, 1, 1), 877 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, 878 RT5645_M_DAC_L1_STO_R_SFT, 1, 1), 879 }; 880 881 static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = { 882 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER, 883 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1), 884 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, 885 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1), 886 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, 887 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1), 888 }; 889 890 static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = { 891 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER, 892 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1), 893 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, 894 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1), 895 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, 896 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1), 897 }; 898 899 static const struct snd_kcontrol_new rt5645_dig_l_mix[] = { 900 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER, 901 RT5645_M_STO_L_DAC_L_SFT, 1, 1), 902 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, 903 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1), 904 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, 905 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1), 906 }; 907 908 static const struct snd_kcontrol_new rt5645_dig_r_mix[] = { 909 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER, 910 RT5645_M_STO_R_DAC_R_SFT, 1, 1), 911 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, 912 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1), 913 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, 914 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1), 915 }; 916 917 /* Analog Input Mixer */ 918 static const struct snd_kcontrol_new rt5645_rec_l_mix[] = { 919 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER, 920 RT5645_M_HP_L_RM_L_SFT, 1, 1), 921 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER, 922 RT5645_M_IN_L_RM_L_SFT, 1, 1), 923 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER, 924 RT5645_M_BST2_RM_L_SFT, 1, 1), 925 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER, 926 RT5645_M_BST1_RM_L_SFT, 1, 1), 927 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER, 928 RT5645_M_OM_L_RM_L_SFT, 1, 1), 929 }; 930 931 static const struct snd_kcontrol_new rt5645_rec_r_mix[] = { 932 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER, 933 RT5645_M_HP_R_RM_R_SFT, 1, 1), 934 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER, 935 RT5645_M_IN_R_RM_R_SFT, 1, 1), 936 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER, 937 RT5645_M_BST2_RM_R_SFT, 1, 1), 938 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER, 939 RT5645_M_BST1_RM_R_SFT, 1, 1), 940 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER, 941 RT5645_M_OM_R_RM_R_SFT, 1, 1), 942 }; 943 944 static const struct snd_kcontrol_new rt5645_spk_l_mix[] = { 945 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER, 946 RT5645_M_DAC_L1_SM_L_SFT, 1, 1), 947 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER, 948 RT5645_M_DAC_L2_SM_L_SFT, 1, 1), 949 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER, 950 RT5645_M_IN_L_SM_L_SFT, 1, 1), 951 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER, 952 RT5645_M_BST1_L_SM_L_SFT, 1, 1), 953 }; 954 955 static const struct snd_kcontrol_new rt5645_spk_r_mix[] = { 956 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER, 957 RT5645_M_DAC_R1_SM_R_SFT, 1, 1), 958 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER, 959 RT5645_M_DAC_R2_SM_R_SFT, 1, 1), 960 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER, 961 RT5645_M_IN_R_SM_R_SFT, 1, 1), 962 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER, 963 RT5645_M_BST2_R_SM_R_SFT, 1, 1), 964 }; 965 966 static const struct snd_kcontrol_new rt5645_out_l_mix[] = { 967 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER, 968 RT5645_M_BST1_OM_L_SFT, 1, 1), 969 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER, 970 RT5645_M_IN_L_OM_L_SFT, 1, 1), 971 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER, 972 RT5645_M_DAC_L2_OM_L_SFT, 1, 1), 973 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER, 974 RT5645_M_DAC_L1_OM_L_SFT, 1, 1), 975 }; 976 977 static const struct snd_kcontrol_new rt5645_out_r_mix[] = { 978 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER, 979 RT5645_M_BST2_OM_R_SFT, 1, 1), 980 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER, 981 RT5645_M_IN_R_OM_R_SFT, 1, 1), 982 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER, 983 RT5645_M_DAC_R2_OM_R_SFT, 1, 1), 984 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER, 985 RT5645_M_DAC_R1_OM_R_SFT, 1, 1), 986 }; 987 988 static const struct snd_kcontrol_new rt5645_spo_l_mix[] = { 989 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, 990 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1), 991 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER, 992 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1), 993 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, 994 RT5645_M_SV_R_SPM_L_SFT, 1, 1), 995 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER, 996 RT5645_M_SV_L_SPM_L_SFT, 1, 1), 997 }; 998 999 static const struct snd_kcontrol_new rt5645_spo_r_mix[] = { 1000 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, 1001 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1), 1002 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, 1003 RT5645_M_SV_R_SPM_R_SFT, 1, 1), 1004 }; 1005 1006 static const struct snd_kcontrol_new rt5645_hpo_mix[] = { 1007 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER, 1008 RT5645_M_DAC1_HM_SFT, 1, 1), 1009 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER, 1010 RT5645_M_HPVOL_HM_SFT, 1, 1), 1011 }; 1012 1013 static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = { 1014 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL, 1015 RT5645_M_DAC1_HV_SFT, 1, 1), 1016 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL, 1017 RT5645_M_DAC2_HV_SFT, 1, 1), 1018 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL, 1019 RT5645_M_IN_HV_SFT, 1, 1), 1020 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL, 1021 RT5645_M_BST1_HV_SFT, 1, 1), 1022 }; 1023 1024 static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = { 1025 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL, 1026 RT5645_M_DAC1_HV_SFT, 1, 1), 1027 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL, 1028 RT5645_M_DAC2_HV_SFT, 1, 1), 1029 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL, 1030 RT5645_M_IN_HV_SFT, 1, 1), 1031 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL, 1032 RT5645_M_BST2_HV_SFT, 1, 1), 1033 }; 1034 1035 static const struct snd_kcontrol_new rt5645_lout_mix[] = { 1036 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER, 1037 RT5645_M_DAC_L1_LM_SFT, 1, 1), 1038 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER, 1039 RT5645_M_DAC_R1_LM_SFT, 1, 1), 1040 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER, 1041 RT5645_M_OV_L_LM_SFT, 1, 1), 1042 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER, 1043 RT5645_M_OV_R_LM_SFT, 1, 1), 1044 }; 1045 1046 /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */ 1047 static const char * const rt5645_dac1_src[] = { 1048 "IF1 DAC", "IF2 DAC", "IF3 DAC" 1049 }; 1050 1051 static SOC_ENUM_SINGLE_DECL( 1052 rt5645_dac1l_enum, RT5645_AD_DA_MIXER, 1053 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src); 1054 1055 static const struct snd_kcontrol_new rt5645_dac1l_mux = 1056 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum); 1057 1058 static SOC_ENUM_SINGLE_DECL( 1059 rt5645_dac1r_enum, RT5645_AD_DA_MIXER, 1060 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src); 1061 1062 static const struct snd_kcontrol_new rt5645_dac1r_mux = 1063 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum); 1064 1065 /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */ 1066 static const char * const rt5645_dac12_src[] = { 1067 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC" 1068 }; 1069 1070 static SOC_ENUM_SINGLE_DECL( 1071 rt5645_dac2l_enum, RT5645_DAC_CTRL, 1072 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src); 1073 1074 static const struct snd_kcontrol_new rt5645_dac_l2_mux = 1075 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum); 1076 1077 static const char * const rt5645_dacr2_src[] = { 1078 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic" 1079 }; 1080 1081 static SOC_ENUM_SINGLE_DECL( 1082 rt5645_dac2r_enum, RT5645_DAC_CTRL, 1083 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src); 1084 1085 static const struct snd_kcontrol_new rt5645_dac_r2_mux = 1086 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum); 1087 1088 1089 /* INL/R source */ 1090 static const char * const rt5645_inl_src[] = { 1091 "IN2P", "MonoP" 1092 }; 1093 1094 static SOC_ENUM_SINGLE_DECL( 1095 rt5645_inl_enum, RT5645_INL1_INR1_VOL, 1096 RT5645_INL_SEL_SFT, rt5645_inl_src); 1097 1098 static const struct snd_kcontrol_new rt5645_inl_mux = 1099 SOC_DAPM_ENUM("INL source", rt5645_inl_enum); 1100 1101 static const char * const rt5645_inr_src[] = { 1102 "IN2N", "MonoN" 1103 }; 1104 1105 static SOC_ENUM_SINGLE_DECL( 1106 rt5645_inr_enum, RT5645_INL1_INR1_VOL, 1107 RT5645_INR_SEL_SFT, rt5645_inr_src); 1108 1109 static const struct snd_kcontrol_new rt5645_inr_mux = 1110 SOC_DAPM_ENUM("INR source", rt5645_inr_enum); 1111 1112 /* Stereo1 ADC source */ 1113 /* MX-27 [12] */ 1114 static const char * const rt5645_stereo_adc1_src[] = { 1115 "DAC MIX", "ADC" 1116 }; 1117 1118 static SOC_ENUM_SINGLE_DECL( 1119 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER, 1120 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src); 1121 1122 static const struct snd_kcontrol_new rt5645_sto_adc1_mux = 1123 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum); 1124 1125 /* MX-27 [11] */ 1126 static const char * const rt5645_stereo_adc2_src[] = { 1127 "DAC MIX", "DMIC" 1128 }; 1129 1130 static SOC_ENUM_SINGLE_DECL( 1131 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER, 1132 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src); 1133 1134 static const struct snd_kcontrol_new rt5645_sto_adc2_mux = 1135 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum); 1136 1137 /* MX-27 [8] */ 1138 static const char * const rt5645_stereo_dmic_src[] = { 1139 "DMIC1", "DMIC2" 1140 }; 1141 1142 static SOC_ENUM_SINGLE_DECL( 1143 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER, 1144 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src); 1145 1146 static const struct snd_kcontrol_new rt5645_sto1_dmic_mux = 1147 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum); 1148 1149 /* Mono ADC source */ 1150 /* MX-28 [12] */ 1151 static const char * const rt5645_mono_adc_l1_src[] = { 1152 "Mono DAC MIXL", "ADC" 1153 }; 1154 1155 static SOC_ENUM_SINGLE_DECL( 1156 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER, 1157 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src); 1158 1159 static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux = 1160 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum); 1161 /* MX-28 [11] */ 1162 static const char * const rt5645_mono_adc_l2_src[] = { 1163 "Mono DAC MIXL", "DMIC" 1164 }; 1165 1166 static SOC_ENUM_SINGLE_DECL( 1167 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER, 1168 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src); 1169 1170 static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux = 1171 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum); 1172 1173 /* MX-28 [8] */ 1174 static const char * const rt5645_mono_dmic_src[] = { 1175 "DMIC1", "DMIC2" 1176 }; 1177 1178 static SOC_ENUM_SINGLE_DECL( 1179 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER, 1180 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src); 1181 1182 static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux = 1183 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum); 1184 /* MX-28 [1:0] */ 1185 static SOC_ENUM_SINGLE_DECL( 1186 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER, 1187 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src); 1188 1189 static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux = 1190 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum); 1191 /* MX-28 [4] */ 1192 static const char * const rt5645_mono_adc_r1_src[] = { 1193 "Mono DAC MIXR", "ADC" 1194 }; 1195 1196 static SOC_ENUM_SINGLE_DECL( 1197 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER, 1198 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src); 1199 1200 static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux = 1201 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum); 1202 /* MX-28 [3] */ 1203 static const char * const rt5645_mono_adc_r2_src[] = { 1204 "Mono DAC MIXR", "DMIC" 1205 }; 1206 1207 static SOC_ENUM_SINGLE_DECL( 1208 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER, 1209 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src); 1210 1211 static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux = 1212 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum); 1213 1214 /* MX-77 [9:8] */ 1215 static const char * const rt5645_if1_adc_in_src[] = { 1216 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC", 1217 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1" 1218 }; 1219 1220 static SOC_ENUM_SINGLE_DECL( 1221 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1, 1222 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src); 1223 1224 static const struct snd_kcontrol_new rt5645_if1_adc_in_mux = 1225 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum); 1226 1227 /* MX-78 [4:0] */ 1228 static const char * const rt5650_if1_adc_in_src[] = { 1229 "IF_ADC1/IF_ADC2/DAC_REF/Null", 1230 "IF_ADC1/IF_ADC2/Null/DAC_REF", 1231 "IF_ADC1/DAC_REF/IF_ADC2/Null", 1232 "IF_ADC1/DAC_REF/Null/IF_ADC2", 1233 "IF_ADC1/Null/DAC_REF/IF_ADC2", 1234 "IF_ADC1/Null/IF_ADC2/DAC_REF", 1235 1236 "IF_ADC2/IF_ADC1/DAC_REF/Null", 1237 "IF_ADC2/IF_ADC1/Null/DAC_REF", 1238 "IF_ADC2/DAC_REF/IF_ADC1/Null", 1239 "IF_ADC2/DAC_REF/Null/IF_ADC1", 1240 "IF_ADC2/Null/DAC_REF/IF_ADC1", 1241 "IF_ADC2/Null/IF_ADC1/DAC_REF", 1242 1243 "DAC_REF/IF_ADC1/IF_ADC2/Null", 1244 "DAC_REF/IF_ADC1/Null/IF_ADC2", 1245 "DAC_REF/IF_ADC2/IF_ADC1/Null", 1246 "DAC_REF/IF_ADC2/Null/IF_ADC1", 1247 "DAC_REF/Null/IF_ADC1/IF_ADC2", 1248 "DAC_REF/Null/IF_ADC2/IF_ADC1", 1249 1250 "Null/IF_ADC1/IF_ADC2/DAC_REF", 1251 "Null/IF_ADC1/DAC_REF/IF_ADC2", 1252 "Null/IF_ADC2/IF_ADC1/DAC_REF", 1253 "Null/IF_ADC2/DAC_REF/IF_ADC1", 1254 "Null/DAC_REF/IF_ADC1/IF_ADC2", 1255 "Null/DAC_REF/IF_ADC2/IF_ADC1", 1256 }; 1257 1258 static SOC_ENUM_SINGLE_DECL( 1259 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2, 1260 0, rt5650_if1_adc_in_src); 1261 1262 static const struct snd_kcontrol_new rt5650_if1_adc_in_mux = 1263 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum); 1264 1265 /* MX-78 [15:14][13:12][11:10] */ 1266 static const char * const rt5645_tdm_adc_swap_select[] = { 1267 "L/R", "R/L", "L/L", "R/R" 1268 }; 1269 1270 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum, 1271 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select); 1272 1273 static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux = 1274 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum); 1275 1276 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum, 1277 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select); 1278 1279 static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux = 1280 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum); 1281 1282 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum, 1283 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select); 1284 1285 static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux = 1286 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum); 1287 1288 /* MX-77 [7:6][5:4][3:2] */ 1289 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum, 1290 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select); 1291 1292 static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux = 1293 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum); 1294 1295 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum, 1296 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select); 1297 1298 static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux = 1299 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum); 1300 1301 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum, 1302 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select); 1303 1304 static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux = 1305 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum); 1306 1307 /* MX-79 [14:12][10:8][6:4][2:0] */ 1308 static const char * const rt5645_tdm_dac_swap_select[] = { 1309 "Slot0", "Slot1", "Slot2", "Slot3" 1310 }; 1311 1312 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum, 1313 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select); 1314 1315 static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux = 1316 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum); 1317 1318 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum, 1319 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select); 1320 1321 static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux = 1322 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum); 1323 1324 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum, 1325 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select); 1326 1327 static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux = 1328 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum); 1329 1330 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum, 1331 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select); 1332 1333 static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux = 1334 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum); 1335 1336 /* MX-7a [14:12][10:8][6:4][2:0] */ 1337 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum, 1338 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select); 1339 1340 static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux = 1341 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum); 1342 1343 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum, 1344 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select); 1345 1346 static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux = 1347 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum); 1348 1349 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum, 1350 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select); 1351 1352 static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux = 1353 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum); 1354 1355 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum, 1356 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select); 1357 1358 static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux = 1359 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum); 1360 1361 /* MX-2d [3] [2] */ 1362 static const char * const rt5650_a_dac1_src[] = { 1363 "DAC1", "Stereo DAC Mixer" 1364 }; 1365 1366 static SOC_ENUM_SINGLE_DECL( 1367 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR, 1368 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src); 1369 1370 static const struct snd_kcontrol_new rt5650_a_dac1_l_mux = 1371 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum); 1372 1373 static SOC_ENUM_SINGLE_DECL( 1374 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR, 1375 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src); 1376 1377 static const struct snd_kcontrol_new rt5650_a_dac1_r_mux = 1378 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum); 1379 1380 /* MX-2d [1] [0] */ 1381 static const char * const rt5650_a_dac2_src[] = { 1382 "Stereo DAC Mixer", "Mono DAC Mixer" 1383 }; 1384 1385 static SOC_ENUM_SINGLE_DECL( 1386 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR, 1387 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src); 1388 1389 static const struct snd_kcontrol_new rt5650_a_dac2_l_mux = 1390 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum); 1391 1392 static SOC_ENUM_SINGLE_DECL( 1393 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR, 1394 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src); 1395 1396 static const struct snd_kcontrol_new rt5650_a_dac2_r_mux = 1397 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum); 1398 1399 /* MX-2F [13:12] */ 1400 static const char * const rt5645_if2_adc_in_src[] = { 1401 "IF_ADC1", "IF_ADC2", "VAD_ADC" 1402 }; 1403 1404 static SOC_ENUM_SINGLE_DECL( 1405 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA, 1406 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src); 1407 1408 static const struct snd_kcontrol_new rt5645_if2_adc_in_mux = 1409 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum); 1410 1411 /* MX-2F [1:0] */ 1412 static const char * const rt5645_if3_adc_in_src[] = { 1413 "IF_ADC1", "IF_ADC2", "VAD_ADC" 1414 }; 1415 1416 static SOC_ENUM_SINGLE_DECL( 1417 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA, 1418 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src); 1419 1420 static const struct snd_kcontrol_new rt5645_if3_adc_in_mux = 1421 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum); 1422 1423 /* MX-31 [15] [13] [11] [9] */ 1424 static const char * const rt5645_pdm_src[] = { 1425 "Mono DAC", "Stereo DAC" 1426 }; 1427 1428 static SOC_ENUM_SINGLE_DECL( 1429 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL, 1430 RT5645_PDM1_L_SFT, rt5645_pdm_src); 1431 1432 static const struct snd_kcontrol_new rt5645_pdm1_l_mux = 1433 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum); 1434 1435 static SOC_ENUM_SINGLE_DECL( 1436 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL, 1437 RT5645_PDM1_R_SFT, rt5645_pdm_src); 1438 1439 static const struct snd_kcontrol_new rt5645_pdm1_r_mux = 1440 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum); 1441 1442 /* MX-9D [9:8] */ 1443 static const char * const rt5645_vad_adc_src[] = { 1444 "Sto1 ADC L", "Mono ADC L", "Mono ADC R" 1445 }; 1446 1447 static SOC_ENUM_SINGLE_DECL( 1448 rt5645_vad_adc_enum, RT5645_VAD_CTRL4, 1449 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src); 1450 1451 static const struct snd_kcontrol_new rt5645_vad_adc_mux = 1452 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum); 1453 1454 static const struct snd_kcontrol_new spk_l_vol_control = 1455 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, 1456 RT5645_L_MUTE_SFT, 1, 1); 1457 1458 static const struct snd_kcontrol_new spk_r_vol_control = 1459 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, 1460 RT5645_R_MUTE_SFT, 1, 1); 1461 1462 static const struct snd_kcontrol_new hp_l_vol_control = 1463 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, 1464 RT5645_L_MUTE_SFT, 1, 1); 1465 1466 static const struct snd_kcontrol_new hp_r_vol_control = 1467 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, 1468 RT5645_R_MUTE_SFT, 1, 1); 1469 1470 static const struct snd_kcontrol_new pdm1_l_vol_control = 1471 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, 1472 RT5645_M_PDM1_L, 1, 1); 1473 1474 static const struct snd_kcontrol_new pdm1_r_vol_control = 1475 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, 1476 RT5645_M_PDM1_R, 1, 1); 1477 1478 static void hp_amp_power(struct snd_soc_codec *codec, int on) 1479 { 1480 static int hp_amp_power_count; 1481 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 1482 1483 if (on) { 1484 if (hp_amp_power_count <= 0) { 1485 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1486 snd_soc_write(codec, RT5645_DEPOP_M2, 0x3100); 1487 snd_soc_write(codec, RT5645_CHARGE_PUMP, 1488 0x0e06); 1489 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d); 1490 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1491 RT5645_HP_DCC_INT1, 0x9f01); 1492 msleep(20); 1493 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1494 RT5645_HP_CO_MASK, RT5645_HP_CO_EN); 1495 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1496 0x3e, 0x7400); 1497 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737); 1498 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1499 RT5645_MAMP_INT_REG2, 0xfc00); 1500 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140); 1501 msleep(40); 1502 rt5645->hp_on = true; 1503 } else { 1504 /* depop parameters */ 1505 snd_soc_update_bits(codec, RT5645_DEPOP_M2, 1506 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN); 1507 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d); 1508 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1509 RT5645_HP_DCC_INT1, 0x9f01); 1510 mdelay(150); 1511 /* headphone amp power on */ 1512 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1513 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0); 1514 snd_soc_update_bits(codec, RT5645_PWR_VOL, 1515 RT5645_PWR_HV_L | RT5645_PWR_HV_R, 1516 RT5645_PWR_HV_L | RT5645_PWR_HV_R); 1517 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1518 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1519 RT5645_PWR_HA, 1520 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1521 RT5645_PWR_HA); 1522 mdelay(5); 1523 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1524 RT5645_PWR_FV1 | RT5645_PWR_FV2, 1525 RT5645_PWR_FV1 | RT5645_PWR_FV2); 1526 1527 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1528 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK, 1529 RT5645_HP_CO_EN | RT5645_HP_SG_EN); 1530 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1531 0x14, 0x1aaa); 1532 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1533 0x24, 0x0430); 1534 } 1535 } 1536 hp_amp_power_count++; 1537 } else { 1538 hp_amp_power_count--; 1539 if (hp_amp_power_count <= 0) { 1540 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1541 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1542 0x3e, 0x7400); 1543 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737); 1544 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1545 RT5645_MAMP_INT_REG2, 0xfc00); 1546 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140); 1547 msleep(100); 1548 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001); 1549 1550 } else { 1551 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1552 RT5645_HP_SG_MASK | 1553 RT5645_HP_L_SMT_MASK | 1554 RT5645_HP_R_SMT_MASK, 1555 RT5645_HP_SG_DIS | 1556 RT5645_HP_L_SMT_DIS | 1557 RT5645_HP_R_SMT_DIS); 1558 /* headphone amp power down */ 1559 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000); 1560 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1561 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1562 RT5645_PWR_HA, 0); 1563 snd_soc_update_bits(codec, RT5645_DEPOP_M2, 1564 RT5645_DEPOP_MASK, 0); 1565 } 1566 } 1567 } 1568 } 1569 1570 static int rt5645_hp_event(struct snd_soc_dapm_widget *w, 1571 struct snd_kcontrol *kcontrol, int event) 1572 { 1573 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1574 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 1575 1576 switch (event) { 1577 case SND_SOC_DAPM_POST_PMU: 1578 hp_amp_power(codec, 1); 1579 /* headphone unmute sequence */ 1580 if (rt5645->codec_type == CODEC_TYPE_RT5645) { 1581 snd_soc_update_bits(codec, RT5645_DEPOP_M3, 1582 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1583 RT5645_CP_FQ3_MASK, 1584 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) | 1585 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1586 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT)); 1587 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1588 RT5645_MAMP_INT_REG2, 0xfc00); 1589 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1590 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN); 1591 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1592 RT5645_RSTN_MASK, RT5645_RSTN_EN); 1593 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1594 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK | 1595 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS | 1596 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); 1597 msleep(40); 1598 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1599 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK | 1600 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS | 1601 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS); 1602 } 1603 break; 1604 1605 case SND_SOC_DAPM_PRE_PMD: 1606 /* headphone mute sequence */ 1607 if (rt5645->codec_type == CODEC_TYPE_RT5645) { 1608 snd_soc_update_bits(codec, RT5645_DEPOP_M3, 1609 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1610 RT5645_CP_FQ3_MASK, 1611 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) | 1612 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1613 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT)); 1614 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1615 RT5645_MAMP_INT_REG2, 0xfc00); 1616 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1617 RT5645_HP_SG_MASK, RT5645_HP_SG_EN); 1618 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1619 RT5645_RSTP_MASK, RT5645_RSTP_EN); 1620 snd_soc_update_bits(codec, RT5645_DEPOP_M1, 1621 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK | 1622 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS | 1623 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); 1624 msleep(30); 1625 } 1626 hp_amp_power(codec, 0); 1627 break; 1628 1629 default: 1630 return 0; 1631 } 1632 1633 return 0; 1634 } 1635 1636 static int rt5645_spk_event(struct snd_soc_dapm_widget *w, 1637 struct snd_kcontrol *kcontrol, int event) 1638 { 1639 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1640 1641 switch (event) { 1642 case SND_SOC_DAPM_POST_PMU: 1643 rt5645_enable_hweq(codec); 1644 snd_soc_update_bits(codec, RT5645_PWR_DIG1, 1645 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1646 RT5645_PWR_CLS_D_L, 1647 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1648 RT5645_PWR_CLS_D_L); 1649 snd_soc_update_bits(codec, RT5645_GEN_CTRL3, 1650 RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1); 1651 break; 1652 1653 case SND_SOC_DAPM_PRE_PMD: 1654 snd_soc_update_bits(codec, RT5645_GEN_CTRL3, 1655 RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS); 1656 snd_soc_write(codec, RT5645_EQ_CTRL2, 0); 1657 snd_soc_update_bits(codec, RT5645_PWR_DIG1, 1658 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1659 RT5645_PWR_CLS_D_L, 0); 1660 break; 1661 1662 default: 1663 return 0; 1664 } 1665 1666 return 0; 1667 } 1668 1669 static int rt5645_lout_event(struct snd_soc_dapm_widget *w, 1670 struct snd_kcontrol *kcontrol, int event) 1671 { 1672 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1673 1674 switch (event) { 1675 case SND_SOC_DAPM_POST_PMU: 1676 hp_amp_power(codec, 1); 1677 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1678 RT5645_PWR_LM, RT5645_PWR_LM); 1679 snd_soc_update_bits(codec, RT5645_LOUT1, 1680 RT5645_L_MUTE | RT5645_R_MUTE, 0); 1681 break; 1682 1683 case SND_SOC_DAPM_PRE_PMD: 1684 snd_soc_update_bits(codec, RT5645_LOUT1, 1685 RT5645_L_MUTE | RT5645_R_MUTE, 1686 RT5645_L_MUTE | RT5645_R_MUTE); 1687 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 1688 RT5645_PWR_LM, 0); 1689 hp_amp_power(codec, 0); 1690 break; 1691 1692 default: 1693 return 0; 1694 } 1695 1696 return 0; 1697 } 1698 1699 static int rt5645_bst2_event(struct snd_soc_dapm_widget *w, 1700 struct snd_kcontrol *kcontrol, int event) 1701 { 1702 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1703 1704 switch (event) { 1705 case SND_SOC_DAPM_POST_PMU: 1706 snd_soc_update_bits(codec, RT5645_PWR_ANLG2, 1707 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P); 1708 break; 1709 1710 case SND_SOC_DAPM_PRE_PMD: 1711 snd_soc_update_bits(codec, RT5645_PWR_ANLG2, 1712 RT5645_PWR_BST2_P, 0); 1713 break; 1714 1715 default: 1716 return 0; 1717 } 1718 1719 return 0; 1720 } 1721 1722 static int rt5650_hp_event(struct snd_soc_dapm_widget *w, 1723 struct snd_kcontrol *k, int event) 1724 { 1725 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1726 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 1727 1728 switch (event) { 1729 case SND_SOC_DAPM_POST_PMU: 1730 if (rt5645->hp_on) { 1731 msleep(100); 1732 rt5645->hp_on = false; 1733 } 1734 break; 1735 1736 default: 1737 return 0; 1738 } 1739 1740 return 0; 1741 } 1742 1743 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = { 1744 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER, 1745 RT5645_PWR_LDO2_BIT, 0, NULL, 0), 1746 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2, 1747 RT5645_PWR_PLL_BIT, 0, NULL, 0), 1748 1749 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2, 1750 RT5645_PWR_JD1_BIT, 0, NULL, 0), 1751 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL, 1752 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0), 1753 1754 /* ASRC */ 1755 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1, 1756 11, 0, NULL, 0), 1757 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1, 1758 12, 0, NULL, 0), 1759 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1, 1760 10, 0, NULL, 0), 1761 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1, 1762 9, 0, NULL, 0), 1763 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1, 1764 8, 0, NULL, 0), 1765 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1, 1766 7, 0, NULL, 0), 1767 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1, 1768 5, 0, NULL, 0), 1769 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1, 1770 4, 0, NULL, 0), 1771 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1, 1772 3, 0, NULL, 0), 1773 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1, 1774 1, 0, NULL, 0), 1775 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1, 1776 0, 0, NULL, 0), 1777 1778 /* Input Side */ 1779 /* micbias */ 1780 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2, 1781 RT5645_PWR_MB1_BIT, 0), 1782 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2, 1783 RT5645_PWR_MB2_BIT, 0), 1784 /* Input Lines */ 1785 SND_SOC_DAPM_INPUT("DMIC L1"), 1786 SND_SOC_DAPM_INPUT("DMIC R1"), 1787 SND_SOC_DAPM_INPUT("DMIC L2"), 1788 SND_SOC_DAPM_INPUT("DMIC R2"), 1789 1790 SND_SOC_DAPM_INPUT("IN1P"), 1791 SND_SOC_DAPM_INPUT("IN1N"), 1792 SND_SOC_DAPM_INPUT("IN2P"), 1793 SND_SOC_DAPM_INPUT("IN2N"), 1794 1795 SND_SOC_DAPM_INPUT("Haptic Generator"), 1796 1797 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1798 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 1799 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1800 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1801 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1, 1802 RT5645_DMIC_1_EN_SFT, 0, NULL, 0), 1803 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1, 1804 RT5645_DMIC_2_EN_SFT, 0, NULL, 0), 1805 /* Boost */ 1806 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2, 1807 RT5645_PWR_BST1_BIT, 0, NULL, 0), 1808 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2, 1809 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event, 1810 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 1811 /* Input Volume */ 1812 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL, 1813 RT5645_PWR_IN_L_BIT, 0, NULL, 0), 1814 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL, 1815 RT5645_PWR_IN_R_BIT, 0, NULL, 0), 1816 /* REC Mixer */ 1817 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT, 1818 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)), 1819 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT, 1820 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)), 1821 /* ADCs */ 1822 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 1823 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 1824 1825 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1, 1826 RT5645_PWR_ADC_L_BIT, 0, NULL, 0), 1827 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1, 1828 RT5645_PWR_ADC_R_BIT, 0, NULL, 0), 1829 1830 /* ADC Mux */ 1831 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 1832 &rt5645_sto1_dmic_mux), 1833 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1834 &rt5645_sto_adc2_mux), 1835 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1836 &rt5645_sto_adc2_mux), 1837 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1838 &rt5645_sto_adc1_mux), 1839 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1840 &rt5645_sto_adc1_mux), 1841 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 1842 &rt5645_mono_dmic_l_mux), 1843 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 1844 &rt5645_mono_dmic_r_mux), 1845 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1846 &rt5645_mono_adc_l2_mux), 1847 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1848 &rt5645_mono_adc_l1_mux), 1849 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1850 &rt5645_mono_adc_r1_mux), 1851 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1852 &rt5645_mono_adc_r2_mux), 1853 /* ADC Mixer */ 1854 1855 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2, 1856 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0), 1857 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 1858 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix), 1859 NULL, 0), 1860 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 1861 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix), 1862 NULL, 0), 1863 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2, 1864 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0), 1865 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, 1866 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix), 1867 NULL, 0), 1868 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2, 1869 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0), 1870 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, 1871 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix), 1872 NULL, 0), 1873 1874 /* ADC PGA */ 1875 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 1876 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 1877 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1878 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 1879 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1880 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 1881 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1882 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 1883 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 1884 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 1885 1886 /* IF1 2 Mux */ 1887 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 1888 0, 0, &rt5645_if2_adc_in_mux), 1889 1890 /* Digital Interface */ 1891 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1, 1892 RT5645_PWR_I2S1_BIT, 0, NULL, 0), 1893 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 1894 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1895 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 1896 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 1897 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 1898 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 1899 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 1900 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1, 1901 RT5645_PWR_I2S2_BIT, 0, NULL, 0), 1902 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 1903 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 1904 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 1905 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 1906 1907 /* Digital Interface Select */ 1908 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 1909 0, 0, &rt5645_vad_adc_mux), 1910 1911 /* Audio Interface */ 1912 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1913 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 1914 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 1915 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 1916 1917 /* Output Side */ 1918 /* DAC mixer before sound effect */ 1919 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1920 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)), 1921 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1922 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)), 1923 1924 /* DAC2 channel Mux */ 1925 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux), 1926 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux), 1927 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1, 1928 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0), 1929 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1, 1930 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0), 1931 1932 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux), 1933 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux), 1934 1935 /* DAC Mixer */ 1936 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2, 1937 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0), 1938 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2, 1939 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0), 1940 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2, 1941 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0), 1942 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 1943 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)), 1944 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 1945 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)), 1946 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 1947 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)), 1948 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 1949 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)), 1950 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0, 1951 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)), 1952 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0, 1953 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)), 1954 1955 /* DACs */ 1956 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT, 1957 0), 1958 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT, 1959 0), 1960 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT, 1961 0), 1962 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT, 1963 0), 1964 /* OUT Mixer */ 1965 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT, 1966 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)), 1967 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT, 1968 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)), 1969 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT, 1970 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)), 1971 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT, 1972 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)), 1973 /* Ouput Volume */ 1974 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0, 1975 &spk_l_vol_control), 1976 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0, 1977 &spk_r_vol_control), 1978 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT, 1979 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)), 1980 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT, 1981 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)), 1982 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER, 1983 RT5645_PWR_HM_L_BIT, 0, NULL, 0), 1984 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER, 1985 RT5645_PWR_HM_R_BIT, 0, NULL, 0), 1986 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0), 1987 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0), 1988 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0), 1989 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control), 1990 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control), 1991 1992 /* HPO/LOUT/Mono Mixer */ 1993 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix, 1994 ARRAY_SIZE(rt5645_spo_l_mix)), 1995 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix, 1996 ARRAY_SIZE(rt5645_spo_r_mix)), 1997 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix, 1998 ARRAY_SIZE(rt5645_hpo_mix)), 1999 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix, 2000 ARRAY_SIZE(rt5645_lout_mix)), 2001 2002 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event, 2003 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2004 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event, 2005 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2006 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event, 2007 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2008 2009 /* PDM */ 2010 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT, 2011 0, NULL, 0), 2012 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux), 2013 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux), 2014 2015 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control), 2016 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control), 2017 2018 /* Output Lines */ 2019 SND_SOC_DAPM_OUTPUT("HPOL"), 2020 SND_SOC_DAPM_OUTPUT("HPOR"), 2021 SND_SOC_DAPM_OUTPUT("LOUTL"), 2022 SND_SOC_DAPM_OUTPUT("LOUTR"), 2023 SND_SOC_DAPM_OUTPUT("PDM1L"), 2024 SND_SOC_DAPM_OUTPUT("PDM1R"), 2025 SND_SOC_DAPM_OUTPUT("SPOL"), 2026 SND_SOC_DAPM_OUTPUT("SPOR"), 2027 SND_SOC_DAPM_POST("DAPM_POST", rt5650_hp_event), 2028 }; 2029 2030 static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = { 2031 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, 2032 &rt5645_if1_dac0_tdm_sel_mux), 2033 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, 2034 &rt5645_if1_dac1_tdm_sel_mux), 2035 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2036 &rt5645_if1_dac2_tdm_sel_mux), 2037 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2038 &rt5645_if1_dac3_tdm_sel_mux), 2039 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM, 2040 0, 0, &rt5645_if1_adc_in_mux), 2041 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM, 2042 0, 0, &rt5645_if1_adc1_in_mux), 2043 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM, 2044 0, 0, &rt5645_if1_adc2_in_mux), 2045 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM, 2046 0, 0, &rt5645_if1_adc3_in_mux), 2047 }; 2048 2049 static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = { 2050 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM, 2051 0, 0, &rt5650_a_dac1_l_mux), 2052 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM, 2053 0, 0, &rt5650_a_dac1_r_mux), 2054 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM, 2055 0, 0, &rt5650_a_dac2_l_mux), 2056 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM, 2057 0, 0, &rt5650_a_dac2_r_mux), 2058 2059 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM, 2060 0, 0, &rt5650_if1_adc1_in_mux), 2061 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM, 2062 0, 0, &rt5650_if1_adc2_in_mux), 2063 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM, 2064 0, 0, &rt5650_if1_adc3_in_mux), 2065 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM, 2066 0, 0, &rt5650_if1_adc_in_mux), 2067 2068 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, 2069 &rt5650_if1_dac0_tdm_sel_mux), 2070 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, 2071 &rt5650_if1_dac1_tdm_sel_mux), 2072 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2073 &rt5650_if1_dac2_tdm_sel_mux), 2074 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2075 &rt5650_if1_dac3_tdm_sel_mux), 2076 }; 2077 2078 static const struct snd_soc_dapm_route rt5645_dapm_routes[] = { 2079 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, 2080 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, 2081 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, 2082 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc }, 2083 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc }, 2084 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, 2085 2086 { "I2S1", NULL, "I2S1 ASRC" }, 2087 { "I2S2", NULL, "I2S2 ASRC" }, 2088 2089 { "IN1P", NULL, "LDO2" }, 2090 { "IN2P", NULL, "LDO2" }, 2091 2092 { "DMIC1", NULL, "DMIC L1" }, 2093 { "DMIC1", NULL, "DMIC R1" }, 2094 { "DMIC2", NULL, "DMIC L2" }, 2095 { "DMIC2", NULL, "DMIC R2" }, 2096 2097 { "BST1", NULL, "IN1P" }, 2098 { "BST1", NULL, "IN1N" }, 2099 { "BST1", NULL, "JD Power" }, 2100 { "BST1", NULL, "Mic Det Power" }, 2101 { "BST2", NULL, "IN2P" }, 2102 { "BST2", NULL, "IN2N" }, 2103 2104 { "INL VOL", NULL, "IN2P" }, 2105 { "INR VOL", NULL, "IN2N" }, 2106 2107 { "RECMIXL", "HPOL Switch", "HPOL" }, 2108 { "RECMIXL", "INL Switch", "INL VOL" }, 2109 { "RECMIXL", "BST2 Switch", "BST2" }, 2110 { "RECMIXL", "BST1 Switch", "BST1" }, 2111 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" }, 2112 2113 { "RECMIXR", "HPOR Switch", "HPOR" }, 2114 { "RECMIXR", "INR Switch", "INR VOL" }, 2115 { "RECMIXR", "BST2 Switch", "BST2" }, 2116 { "RECMIXR", "BST1 Switch", "BST1" }, 2117 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" }, 2118 2119 { "ADC L", NULL, "RECMIXL" }, 2120 { "ADC L", NULL, "ADC L power" }, 2121 { "ADC R", NULL, "RECMIXR" }, 2122 { "ADC R", NULL, "ADC R power" }, 2123 2124 {"DMIC L1", NULL, "DMIC CLK"}, 2125 {"DMIC L1", NULL, "DMIC1 Power"}, 2126 {"DMIC R1", NULL, "DMIC CLK"}, 2127 {"DMIC R1", NULL, "DMIC1 Power"}, 2128 {"DMIC L2", NULL, "DMIC CLK"}, 2129 {"DMIC L2", NULL, "DMIC2 Power"}, 2130 {"DMIC R2", NULL, "DMIC CLK"}, 2131 {"DMIC R2", NULL, "DMIC2 Power"}, 2132 2133 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 2134 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 2135 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" }, 2136 2137 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" }, 2138 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" }, 2139 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" }, 2140 2141 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" }, 2142 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" }, 2143 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" }, 2144 2145 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2146 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" }, 2147 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" }, 2148 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" }, 2149 2150 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" }, 2151 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" }, 2152 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2153 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" }, 2154 2155 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" }, 2156 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2157 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2158 { "Mono ADC L1 Mux", "ADC", "ADC L" }, 2159 2160 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2161 { "Mono ADC R1 Mux", "ADC", "ADC R" }, 2162 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" }, 2163 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2164 2165 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" }, 2166 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" }, 2167 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" }, 2168 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" }, 2169 2170 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 2171 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 2172 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2173 2174 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 2175 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 2176 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2177 2178 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" }, 2179 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" }, 2180 { "Mono ADC MIXL", NULL, "adc mono left filter" }, 2181 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, 2182 2183 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" }, 2184 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" }, 2185 { "Mono ADC MIXR", NULL, "adc mono right filter" }, 2186 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, 2187 2188 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" }, 2189 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" }, 2190 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" }, 2191 2192 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" }, 2193 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" }, 2194 { "IF_ADC2", NULL, "Mono ADC MIXL" }, 2195 { "IF_ADC2", NULL, "Mono ADC MIXR" }, 2196 { "VAD_ADC", NULL, "VAD ADC Mux" }, 2197 2198 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" }, 2199 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" }, 2200 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" }, 2201 2202 { "IF1 ADC", NULL, "I2S1" }, 2203 { "IF2 ADC", NULL, "I2S2" }, 2204 { "IF2 ADC", NULL, "IF2 ADC Mux" }, 2205 2206 { "AIF2TX", NULL, "IF2 ADC" }, 2207 2208 { "IF1 DAC0", NULL, "AIF1RX" }, 2209 { "IF1 DAC1", NULL, "AIF1RX" }, 2210 { "IF1 DAC2", NULL, "AIF1RX" }, 2211 { "IF1 DAC3", NULL, "AIF1RX" }, 2212 { "IF2 DAC", NULL, "AIF2RX" }, 2213 2214 { "IF1 DAC0", NULL, "I2S1" }, 2215 { "IF1 DAC1", NULL, "I2S1" }, 2216 { "IF1 DAC2", NULL, "I2S1" }, 2217 { "IF1 DAC3", NULL, "I2S1" }, 2218 { "IF2 DAC", NULL, "I2S2" }, 2219 2220 { "IF2 DAC L", NULL, "IF2 DAC" }, 2221 { "IF2 DAC R", NULL, "IF2 DAC" }, 2222 2223 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" }, 2224 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" }, 2225 2226 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" }, 2227 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" }, 2228 { "DAC1 MIXL", NULL, "dac stereo1 filter" }, 2229 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" }, 2230 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" }, 2231 { "DAC1 MIXR", NULL, "dac stereo1 filter" }, 2232 2233 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" }, 2234 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" }, 2235 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" }, 2236 { "DAC L2 Volume", NULL, "DAC L2 Mux" }, 2237 { "DAC L2 Volume", NULL, "dac mono left filter" }, 2238 2239 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" }, 2240 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" }, 2241 { "DAC R2 Mux", "Haptic", "Haptic Generator" }, 2242 { "DAC R2 Volume", NULL, "DAC R2 Mux" }, 2243 { "DAC R2 Volume", NULL, "dac mono right filter" }, 2244 2245 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 2246 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" }, 2247 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2248 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 2249 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 2250 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" }, 2251 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2252 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 2253 2254 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 2255 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2256 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, 2257 { "Mono DAC MIXL", NULL, "dac mono left filter" }, 2258 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 2259 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2260 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, 2261 { "Mono DAC MIXR", NULL, "dac mono right filter" }, 2262 2263 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 2264 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2265 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, 2266 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 2267 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2268 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, 2269 2270 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll }, 2271 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll }, 2272 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll }, 2273 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll }, 2274 2275 { "SPK MIXL", "BST1 Switch", "BST1" }, 2276 { "SPK MIXL", "INL Switch", "INL VOL" }, 2277 { "SPK MIXL", "DAC L1 Switch", "DAC L1" }, 2278 { "SPK MIXL", "DAC L2 Switch", "DAC L2" }, 2279 { "SPK MIXR", "BST2 Switch", "BST2" }, 2280 { "SPK MIXR", "INR Switch", "INR VOL" }, 2281 { "SPK MIXR", "DAC R1 Switch", "DAC R1" }, 2282 { "SPK MIXR", "DAC R2 Switch", "DAC R2" }, 2283 2284 { "OUT MIXL", "BST1 Switch", "BST1" }, 2285 { "OUT MIXL", "INL Switch", "INL VOL" }, 2286 { "OUT MIXL", "DAC L2 Switch", "DAC L2" }, 2287 { "OUT MIXL", "DAC L1 Switch", "DAC L1" }, 2288 2289 { "OUT MIXR", "BST2 Switch", "BST2" }, 2290 { "OUT MIXR", "INR Switch", "INR VOL" }, 2291 { "OUT MIXR", "DAC R2 Switch", "DAC R2" }, 2292 { "OUT MIXR", "DAC R1 Switch", "DAC R1" }, 2293 2294 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" }, 2295 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" }, 2296 { "HPOVOL MIXL", "INL Switch", "INL VOL" }, 2297 { "HPOVOL MIXL", "BST1 Switch", "BST1" }, 2298 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" }, 2299 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" }, 2300 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" }, 2301 { "HPOVOL MIXR", "INR Switch", "INR VOL" }, 2302 { "HPOVOL MIXR", "BST2 Switch", "BST2" }, 2303 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" }, 2304 2305 { "DAC 2", NULL, "DAC L2" }, 2306 { "DAC 2", NULL, "DAC R2" }, 2307 { "DAC 1", NULL, "DAC L1" }, 2308 { "DAC 1", NULL, "DAC R1" }, 2309 { "HPOVOL L", "Switch", "HPOVOL MIXL" }, 2310 { "HPOVOL R", "Switch", "HPOVOL MIXR" }, 2311 { "HPOVOL", NULL, "HPOVOL L" }, 2312 { "HPOVOL", NULL, "HPOVOL R" }, 2313 { "HPO MIX", "DAC1 Switch", "DAC 1" }, 2314 { "HPO MIX", "HPVOL Switch", "HPOVOL" }, 2315 2316 { "SPKVOL L", "Switch", "SPK MIXL" }, 2317 { "SPKVOL R", "Switch", "SPK MIXR" }, 2318 2319 { "SPOL MIX", "DAC R1 Switch", "DAC R1" }, 2320 { "SPOL MIX", "DAC L1 Switch", "DAC L1" }, 2321 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" }, 2322 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" }, 2323 { "SPOR MIX", "DAC R1 Switch", "DAC R1" }, 2324 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" }, 2325 2326 { "LOUT MIX", "DAC L1 Switch", "DAC L1" }, 2327 { "LOUT MIX", "DAC R1 Switch", "DAC R1" }, 2328 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" }, 2329 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" }, 2330 2331 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" }, 2332 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" }, 2333 { "PDM1 L Mux", NULL, "PDM1 Power" }, 2334 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" }, 2335 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" }, 2336 { "PDM1 R Mux", NULL, "PDM1 Power" }, 2337 2338 { "HP amp", NULL, "HPO MIX" }, 2339 { "HP amp", NULL, "JD Power" }, 2340 { "HP amp", NULL, "Mic Det Power" }, 2341 { "HP amp", NULL, "LDO2" }, 2342 { "HPOL", NULL, "HP amp" }, 2343 { "HPOR", NULL, "HP amp" }, 2344 2345 { "LOUT amp", NULL, "LOUT MIX" }, 2346 { "LOUTL", NULL, "LOUT amp" }, 2347 { "LOUTR", NULL, "LOUT amp" }, 2348 2349 { "PDM1 L", "Switch", "PDM1 L Mux" }, 2350 { "PDM1 R", "Switch", "PDM1 R Mux" }, 2351 2352 { "PDM1L", NULL, "PDM1 L" }, 2353 { "PDM1R", NULL, "PDM1 R" }, 2354 2355 { "SPK amp", NULL, "SPOL MIX" }, 2356 { "SPK amp", NULL, "SPOR MIX" }, 2357 { "SPOL", NULL, "SPK amp" }, 2358 { "SPOR", NULL, "SPK amp" }, 2359 }; 2360 2361 static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = { 2362 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"}, 2363 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, 2364 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"}, 2365 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, 2366 2367 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, 2368 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"}, 2369 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, 2370 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"}, 2371 2372 { "DAC L1", NULL, "A DAC1 L Mux" }, 2373 { "DAC R1", NULL, "A DAC1 R Mux" }, 2374 { "DAC L2", NULL, "A DAC2 L Mux" }, 2375 { "DAC R2", NULL, "A DAC2 R Mux" }, 2376 2377 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, 2378 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, 2379 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, 2380 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, 2381 2382 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, 2383 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, 2384 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, 2385 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, 2386 2387 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, 2388 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, 2389 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, 2390 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, 2391 2392 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" }, 2393 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" }, 2394 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" }, 2395 2396 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" }, 2397 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" }, 2398 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" }, 2399 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" }, 2400 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" }, 2401 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" }, 2402 2403 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" }, 2404 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" }, 2405 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" }, 2406 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" }, 2407 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" }, 2408 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" }, 2409 2410 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" }, 2411 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" }, 2412 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" }, 2413 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" }, 2414 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2415 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2416 2417 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" }, 2418 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" }, 2419 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" }, 2420 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" }, 2421 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2422 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2423 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" }, 2424 2425 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, 2426 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, 2427 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, 2428 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, 2429 2430 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, 2431 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, 2432 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, 2433 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, 2434 2435 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, 2436 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, 2437 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, 2438 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, 2439 2440 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, 2441 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, 2442 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, 2443 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, 2444 2445 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" }, 2446 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" }, 2447 2448 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" }, 2449 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" }, 2450 }; 2451 2452 static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = { 2453 { "DAC L1", NULL, "Stereo DAC MIXL" }, 2454 { "DAC R1", NULL, "Stereo DAC MIXR" }, 2455 { "DAC L2", NULL, "Mono DAC MIXL" }, 2456 { "DAC R2", NULL, "Mono DAC MIXR" }, 2457 2458 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, 2459 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, 2460 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, 2461 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, 2462 2463 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, 2464 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, 2465 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, 2466 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, 2467 2468 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, 2469 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, 2470 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, 2471 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, 2472 2473 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" }, 2474 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" }, 2475 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" }, 2476 2477 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" }, 2478 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" }, 2479 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2480 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2481 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" }, 2482 2483 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, 2484 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, 2485 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, 2486 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, 2487 2488 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, 2489 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, 2490 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, 2491 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, 2492 2493 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, 2494 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, 2495 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, 2496 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, 2497 2498 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, 2499 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, 2500 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, 2501 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, 2502 2503 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" }, 2504 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" }, 2505 2506 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" }, 2507 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" }, 2508 }; 2509 2510 static int rt5645_hw_params(struct snd_pcm_substream *substream, 2511 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2512 { 2513 struct snd_soc_codec *codec = dai->codec; 2514 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2515 unsigned int val_len = 0, val_clk, mask_clk, dl_sft; 2516 int pre_div, bclk_ms, frame_size; 2517 2518 rt5645->lrck[dai->id] = params_rate(params); 2519 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]); 2520 if (pre_div < 0) { 2521 dev_err(codec->dev, "Unsupported clock setting\n"); 2522 return -EINVAL; 2523 } 2524 frame_size = snd_soc_params_to_frame_size(params); 2525 if (frame_size < 0) { 2526 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); 2527 return -EINVAL; 2528 } 2529 2530 switch (rt5645->codec_type) { 2531 case CODEC_TYPE_RT5650: 2532 dl_sft = 4; 2533 break; 2534 default: 2535 dl_sft = 2; 2536 break; 2537 } 2538 2539 bclk_ms = frame_size > 32; 2540 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms); 2541 2542 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 2543 rt5645->bclk[dai->id], rt5645->lrck[dai->id]); 2544 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 2545 bclk_ms, pre_div, dai->id); 2546 2547 switch (params_width(params)) { 2548 case 16: 2549 break; 2550 case 20: 2551 val_len = 0x1; 2552 break; 2553 case 24: 2554 val_len = 0x2; 2555 break; 2556 case 8: 2557 val_len = 0x3; 2558 break; 2559 default: 2560 return -EINVAL; 2561 } 2562 2563 switch (dai->id) { 2564 case RT5645_AIF1: 2565 mask_clk = RT5645_I2S_PD1_MASK; 2566 val_clk = pre_div << RT5645_I2S_PD1_SFT; 2567 snd_soc_update_bits(codec, RT5645_I2S1_SDP, 2568 (0x3 << dl_sft), (val_len << dl_sft)); 2569 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk); 2570 break; 2571 case RT5645_AIF2: 2572 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK; 2573 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT | 2574 pre_div << RT5645_I2S_PD2_SFT; 2575 snd_soc_update_bits(codec, RT5645_I2S2_SDP, 2576 (0x3 << dl_sft), (val_len << dl_sft)); 2577 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk); 2578 break; 2579 default: 2580 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id); 2581 return -EINVAL; 2582 } 2583 2584 return 0; 2585 } 2586 2587 static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2588 { 2589 struct snd_soc_codec *codec = dai->codec; 2590 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2591 unsigned int reg_val = 0, pol_sft; 2592 2593 switch (rt5645->codec_type) { 2594 case CODEC_TYPE_RT5650: 2595 pol_sft = 8; 2596 break; 2597 default: 2598 pol_sft = 7; 2599 break; 2600 } 2601 2602 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2603 case SND_SOC_DAIFMT_CBM_CFM: 2604 rt5645->master[dai->id] = 1; 2605 break; 2606 case SND_SOC_DAIFMT_CBS_CFS: 2607 reg_val |= RT5645_I2S_MS_S; 2608 rt5645->master[dai->id] = 0; 2609 break; 2610 default: 2611 return -EINVAL; 2612 } 2613 2614 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2615 case SND_SOC_DAIFMT_NB_NF: 2616 break; 2617 case SND_SOC_DAIFMT_IB_NF: 2618 reg_val |= (1 << pol_sft); 2619 break; 2620 default: 2621 return -EINVAL; 2622 } 2623 2624 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2625 case SND_SOC_DAIFMT_I2S: 2626 break; 2627 case SND_SOC_DAIFMT_LEFT_J: 2628 reg_val |= RT5645_I2S_DF_LEFT; 2629 break; 2630 case SND_SOC_DAIFMT_DSP_A: 2631 reg_val |= RT5645_I2S_DF_PCM_A; 2632 break; 2633 case SND_SOC_DAIFMT_DSP_B: 2634 reg_val |= RT5645_I2S_DF_PCM_B; 2635 break; 2636 default: 2637 return -EINVAL; 2638 } 2639 switch (dai->id) { 2640 case RT5645_AIF1: 2641 snd_soc_update_bits(codec, RT5645_I2S1_SDP, 2642 RT5645_I2S_MS_MASK | (1 << pol_sft) | 2643 RT5645_I2S_DF_MASK, reg_val); 2644 break; 2645 case RT5645_AIF2: 2646 snd_soc_update_bits(codec, RT5645_I2S2_SDP, 2647 RT5645_I2S_MS_MASK | (1 << pol_sft) | 2648 RT5645_I2S_DF_MASK, reg_val); 2649 break; 2650 default: 2651 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id); 2652 return -EINVAL; 2653 } 2654 return 0; 2655 } 2656 2657 static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai, 2658 int clk_id, unsigned int freq, int dir) 2659 { 2660 struct snd_soc_codec *codec = dai->codec; 2661 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2662 unsigned int reg_val = 0; 2663 2664 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src) 2665 return 0; 2666 2667 switch (clk_id) { 2668 case RT5645_SCLK_S_MCLK: 2669 reg_val |= RT5645_SCLK_SRC_MCLK; 2670 break; 2671 case RT5645_SCLK_S_PLL1: 2672 reg_val |= RT5645_SCLK_SRC_PLL1; 2673 break; 2674 case RT5645_SCLK_S_RCCLK: 2675 reg_val |= RT5645_SCLK_SRC_RCCLK; 2676 break; 2677 default: 2678 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); 2679 return -EINVAL; 2680 } 2681 snd_soc_update_bits(codec, RT5645_GLB_CLK, 2682 RT5645_SCLK_SRC_MASK, reg_val); 2683 rt5645->sysclk = freq; 2684 rt5645->sysclk_src = clk_id; 2685 2686 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 2687 2688 return 0; 2689 } 2690 2691 static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 2692 unsigned int freq_in, unsigned int freq_out) 2693 { 2694 struct snd_soc_codec *codec = dai->codec; 2695 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2696 struct rl6231_pll_code pll_code; 2697 int ret; 2698 2699 if (source == rt5645->pll_src && freq_in == rt5645->pll_in && 2700 freq_out == rt5645->pll_out) 2701 return 0; 2702 2703 if (!freq_in || !freq_out) { 2704 dev_dbg(codec->dev, "PLL disabled\n"); 2705 2706 rt5645->pll_in = 0; 2707 rt5645->pll_out = 0; 2708 snd_soc_update_bits(codec, RT5645_GLB_CLK, 2709 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK); 2710 return 0; 2711 } 2712 2713 switch (source) { 2714 case RT5645_PLL1_S_MCLK: 2715 snd_soc_update_bits(codec, RT5645_GLB_CLK, 2716 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK); 2717 break; 2718 case RT5645_PLL1_S_BCLK1: 2719 case RT5645_PLL1_S_BCLK2: 2720 switch (dai->id) { 2721 case RT5645_AIF1: 2722 snd_soc_update_bits(codec, RT5645_GLB_CLK, 2723 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1); 2724 break; 2725 case RT5645_AIF2: 2726 snd_soc_update_bits(codec, RT5645_GLB_CLK, 2727 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2); 2728 break; 2729 default: 2730 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id); 2731 return -EINVAL; 2732 } 2733 break; 2734 default: 2735 dev_err(codec->dev, "Unknown PLL source %d\n", source); 2736 return -EINVAL; 2737 } 2738 2739 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2740 if (ret < 0) { 2741 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); 2742 return ret; 2743 } 2744 2745 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", 2746 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2747 pll_code.n_code, pll_code.k_code); 2748 2749 snd_soc_write(codec, RT5645_PLL_CTRL1, 2750 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code); 2751 snd_soc_write(codec, RT5645_PLL_CTRL2, 2752 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT | 2753 pll_code.m_bp << RT5645_PLL_M_BP_SFT); 2754 2755 rt5645->pll_in = freq_in; 2756 rt5645->pll_out = freq_out; 2757 rt5645->pll_src = source; 2758 2759 return 0; 2760 } 2761 2762 static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2763 unsigned int rx_mask, int slots, int slot_width) 2764 { 2765 struct snd_soc_codec *codec = dai->codec; 2766 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2767 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft; 2768 unsigned int mask, val = 0; 2769 2770 switch (rt5645->codec_type) { 2771 case CODEC_TYPE_RT5650: 2772 en_sft = 15; 2773 i_slot_sft = 10; 2774 o_slot_sft = 8; 2775 i_width_sht = 6; 2776 o_width_sht = 4; 2777 mask = 0x8ff0; 2778 break; 2779 default: 2780 en_sft = 14; 2781 i_slot_sft = o_slot_sft = 12; 2782 i_width_sht = o_width_sht = 10; 2783 mask = 0x7c00; 2784 break; 2785 } 2786 if (rx_mask || tx_mask) { 2787 val |= (1 << en_sft); 2788 if (rt5645->codec_type == CODEC_TYPE_RT5645) 2789 snd_soc_update_bits(codec, RT5645_BASS_BACK, 2790 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB); 2791 } 2792 2793 switch (slots) { 2794 case 4: 2795 val |= (1 << i_slot_sft) | (1 << o_slot_sft); 2796 break; 2797 case 6: 2798 val |= (2 << i_slot_sft) | (2 << o_slot_sft); 2799 break; 2800 case 8: 2801 val |= (3 << i_slot_sft) | (3 << o_slot_sft); 2802 break; 2803 case 2: 2804 default: 2805 break; 2806 } 2807 2808 switch (slot_width) { 2809 case 20: 2810 val |= (1 << i_width_sht) | (1 << o_width_sht); 2811 break; 2812 case 24: 2813 val |= (2 << i_width_sht) | (2 << o_width_sht); 2814 break; 2815 case 32: 2816 val |= (3 << i_width_sht) | (3 << o_width_sht); 2817 break; 2818 case 16: 2819 default: 2820 break; 2821 } 2822 2823 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, mask, val); 2824 2825 return 0; 2826 } 2827 2828 static int rt5645_set_bias_level(struct snd_soc_codec *codec, 2829 enum snd_soc_bias_level level) 2830 { 2831 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2832 2833 switch (level) { 2834 case SND_SOC_BIAS_PREPARE: 2835 if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) { 2836 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 2837 RT5645_PWR_VREF1 | RT5645_PWR_MB | 2838 RT5645_PWR_BG | RT5645_PWR_VREF2, 2839 RT5645_PWR_VREF1 | RT5645_PWR_MB | 2840 RT5645_PWR_BG | RT5645_PWR_VREF2); 2841 mdelay(10); 2842 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 2843 RT5645_PWR_FV1 | RT5645_PWR_FV2, 2844 RT5645_PWR_FV1 | RT5645_PWR_FV2); 2845 snd_soc_update_bits(codec, RT5645_GEN_CTRL1, 2846 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); 2847 } 2848 break; 2849 2850 case SND_SOC_BIAS_STANDBY: 2851 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 2852 RT5645_PWR_VREF1 | RT5645_PWR_MB | 2853 RT5645_PWR_BG | RT5645_PWR_VREF2, 2854 RT5645_PWR_VREF1 | RT5645_PWR_MB | 2855 RT5645_PWR_BG | RT5645_PWR_VREF2); 2856 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 2857 RT5645_PWR_FV1 | RT5645_PWR_FV2, 2858 RT5645_PWR_FV1 | RT5645_PWR_FV2); 2859 if (rt5645->en_button_func && 2860 snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) 2861 queue_delayed_work(system_power_efficient_wq, 2862 &rt5645->jack_detect_work, msecs_to_jiffies(0)); 2863 break; 2864 2865 case SND_SOC_BIAS_OFF: 2866 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100); 2867 if (!rt5645->en_button_func) 2868 snd_soc_update_bits(codec, RT5645_GEN_CTRL1, 2869 RT5645_DIG_GATE_CTRL, 0); 2870 snd_soc_update_bits(codec, RT5645_PWR_ANLG1, 2871 RT5645_PWR_VREF1 | RT5645_PWR_MB | 2872 RT5645_PWR_BG | RT5645_PWR_VREF2 | 2873 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0); 2874 break; 2875 2876 default: 2877 break; 2878 } 2879 2880 return 0; 2881 } 2882 2883 static void rt5645_enable_push_button_irq(struct snd_soc_codec *codec, 2884 bool enable) 2885 { 2886 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 2887 2888 if (enable) { 2889 snd_soc_dapm_force_enable_pin(dapm, "ADC L power"); 2890 snd_soc_dapm_force_enable_pin(dapm, "ADC R power"); 2891 snd_soc_dapm_sync(dapm); 2892 2893 snd_soc_update_bits(codec, 2894 RT5645_INT_IRQ_ST, 0x8, 0x8); 2895 snd_soc_update_bits(codec, 2896 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000); 2897 snd_soc_read(codec, RT5650_4BTN_IL_CMD1); 2898 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1, 2899 snd_soc_read(codec, RT5650_4BTN_IL_CMD1)); 2900 } else { 2901 snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD2, 0x8000, 0x0); 2902 snd_soc_update_bits(codec, RT5645_INT_IRQ_ST, 0x8, 0x0); 2903 2904 snd_soc_dapm_disable_pin(dapm, "ADC L power"); 2905 snd_soc_dapm_disable_pin(dapm, "ADC R power"); 2906 snd_soc_dapm_sync(dapm); 2907 } 2908 } 2909 2910 static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert) 2911 { 2912 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 2913 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 2914 unsigned int val; 2915 2916 if (jack_insert) { 2917 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006); 2918 2919 /* for jack type detect */ 2920 snd_soc_dapm_force_enable_pin(dapm, "LDO2"); 2921 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power"); 2922 snd_soc_dapm_sync(dapm); 2923 if (!dapm->card->instantiated) { 2924 /* Power up necessary bits for JD if dapm is 2925 not ready yet */ 2926 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1, 2927 RT5645_PWR_MB | RT5645_PWR_VREF2, 2928 RT5645_PWR_MB | RT5645_PWR_VREF2); 2929 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER, 2930 RT5645_PWR_LDO2, RT5645_PWR_LDO2); 2931 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL, 2932 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET); 2933 } 2934 2935 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0); 2936 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 2937 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 2938 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 2939 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN); 2940 msleep(100); 2941 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 2942 RT5645_CBJ_MN_JD, 0); 2943 2944 msleep(600); 2945 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val); 2946 val &= 0x7; 2947 dev_dbg(codec->dev, "val = %d\n", val); 2948 2949 if (val == 1 || val == 2) { 2950 rt5645->jack_type = SND_JACK_HEADSET; 2951 if (rt5645->en_button_func) { 2952 rt5645_enable_push_button_irq(codec, true); 2953 } 2954 } else { 2955 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 2956 snd_soc_dapm_sync(dapm); 2957 rt5645->jack_type = SND_JACK_HEADPHONE; 2958 } 2959 if (rt5645->pdata.jd_invert) 2960 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 2961 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 2962 } else { /* jack out */ 2963 rt5645->jack_type = 0; 2964 2965 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL, 2966 RT5645_L_MUTE | RT5645_R_MUTE, 2967 RT5645_L_MUTE | RT5645_R_MUTE); 2968 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 2969 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 2970 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 2971 RT5645_CBJ_BST1_EN, 0); 2972 2973 if (rt5645->en_button_func) 2974 rt5645_enable_push_button_irq(codec, false); 2975 2976 if (rt5645->pdata.jd_mode == 0) 2977 snd_soc_dapm_disable_pin(dapm, "LDO2"); 2978 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 2979 snd_soc_dapm_sync(dapm); 2980 if (rt5645->pdata.jd_invert) 2981 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 2982 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR); 2983 } 2984 2985 return rt5645->jack_type; 2986 } 2987 2988 static int rt5645_button_detect(struct snd_soc_codec *codec) 2989 { 2990 int btn_type, val; 2991 2992 val = snd_soc_read(codec, RT5650_4BTN_IL_CMD1); 2993 pr_debug("val=0x%x\n", val); 2994 btn_type = val & 0xfff0; 2995 snd_soc_write(codec, RT5650_4BTN_IL_CMD1, val); 2996 2997 return btn_type; 2998 } 2999 3000 static irqreturn_t rt5645_irq(int irq, void *data); 3001 3002 int rt5645_set_jack_detect(struct snd_soc_codec *codec, 3003 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack, 3004 struct snd_soc_jack *btn_jack) 3005 { 3006 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 3007 3008 rt5645->hp_jack = hp_jack; 3009 rt5645->mic_jack = mic_jack; 3010 rt5645->btn_jack = btn_jack; 3011 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) { 3012 rt5645->en_button_func = true; 3013 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3014 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); 3015 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1, 3016 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); 3017 } 3018 rt5645_irq(0, rt5645); 3019 3020 return 0; 3021 } 3022 EXPORT_SYMBOL_GPL(rt5645_set_jack_detect); 3023 3024 static void rt5645_jack_detect_work(struct work_struct *work) 3025 { 3026 struct rt5645_priv *rt5645 = 3027 container_of(work, struct rt5645_priv, jack_detect_work.work); 3028 int val, btn_type, gpio_state = 0, report = 0; 3029 3030 if (!rt5645->codec) 3031 return; 3032 3033 switch (rt5645->pdata.jd_mode) { 3034 case 0: /* Not using rt5645 JD */ 3035 if (rt5645->gpiod_hp_det) { 3036 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det); 3037 dev_dbg(rt5645->codec->dev, "gpio_state = %d\n", 3038 gpio_state); 3039 report = rt5645_jack_detect(rt5645->codec, gpio_state); 3040 } 3041 snd_soc_jack_report(rt5645->hp_jack, 3042 report, SND_JACK_HEADPHONE); 3043 snd_soc_jack_report(rt5645->mic_jack, 3044 report, SND_JACK_MICROPHONE); 3045 return; 3046 case 1: /* 2 port */ 3047 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0070; 3048 break; 3049 default: /* 1 port */ 3050 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0020; 3051 break; 3052 3053 } 3054 3055 switch (val) { 3056 /* jack in */ 3057 case 0x30: /* 2 port */ 3058 case 0x0: /* 1 port or 2 port */ 3059 if (rt5645->jack_type == 0) { 3060 report = rt5645_jack_detect(rt5645->codec, 1); 3061 /* for push button and jack out */ 3062 break; 3063 } 3064 btn_type = 0; 3065 if (snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x4) { 3066 /* button pressed */ 3067 report = SND_JACK_HEADSET; 3068 btn_type = rt5645_button_detect(rt5645->codec); 3069 /* rt5650 can report three kinds of button behavior, 3070 one click, double click and hold. However, 3071 currently we will report button pressed/released 3072 event. So all the three button behaviors are 3073 treated as button pressed. */ 3074 switch (btn_type) { 3075 case 0x8000: 3076 case 0x4000: 3077 case 0x2000: 3078 report |= SND_JACK_BTN_0; 3079 break; 3080 case 0x1000: 3081 case 0x0800: 3082 case 0x0400: 3083 report |= SND_JACK_BTN_1; 3084 break; 3085 case 0x0200: 3086 case 0x0100: 3087 case 0x0080: 3088 report |= SND_JACK_BTN_2; 3089 break; 3090 case 0x0040: 3091 case 0x0020: 3092 case 0x0010: 3093 report |= SND_JACK_BTN_3; 3094 break; 3095 case 0x0000: /* unpressed */ 3096 break; 3097 default: 3098 dev_err(rt5645->codec->dev, 3099 "Unexpected button code 0x%04x\n", 3100 btn_type); 3101 break; 3102 } 3103 } 3104 if (btn_type == 0)/* button release */ 3105 report = rt5645->jack_type; 3106 3107 break; 3108 /* jack out */ 3109 case 0x70: /* 2 port */ 3110 case 0x10: /* 2 port */ 3111 case 0x20: /* 1 port */ 3112 report = 0; 3113 snd_soc_update_bits(rt5645->codec, 3114 RT5645_INT_IRQ_ST, 0x1, 0x0); 3115 rt5645_jack_detect(rt5645->codec, 0); 3116 break; 3117 default: 3118 break; 3119 } 3120 3121 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE); 3122 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE); 3123 if (rt5645->en_button_func) 3124 snd_soc_jack_report(rt5645->btn_jack, 3125 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3126 SND_JACK_BTN_2 | SND_JACK_BTN_3); 3127 } 3128 3129 static irqreturn_t rt5645_irq(int irq, void *data) 3130 { 3131 struct rt5645_priv *rt5645 = data; 3132 3133 queue_delayed_work(system_power_efficient_wq, 3134 &rt5645->jack_detect_work, msecs_to_jiffies(250)); 3135 3136 return IRQ_HANDLED; 3137 } 3138 3139 static int rt5645_probe(struct snd_soc_codec *codec) 3140 { 3141 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 3142 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 3143 3144 rt5645->codec = codec; 3145 3146 switch (rt5645->codec_type) { 3147 case CODEC_TYPE_RT5645: 3148 snd_soc_dapm_new_controls(dapm, 3149 rt5645_specific_dapm_widgets, 3150 ARRAY_SIZE(rt5645_specific_dapm_widgets)); 3151 snd_soc_dapm_add_routes(dapm, 3152 rt5645_specific_dapm_routes, 3153 ARRAY_SIZE(rt5645_specific_dapm_routes)); 3154 break; 3155 case CODEC_TYPE_RT5650: 3156 snd_soc_dapm_new_controls(dapm, 3157 rt5650_specific_dapm_widgets, 3158 ARRAY_SIZE(rt5650_specific_dapm_widgets)); 3159 snd_soc_dapm_add_routes(dapm, 3160 rt5650_specific_dapm_routes, 3161 ARRAY_SIZE(rt5650_specific_dapm_routes)); 3162 break; 3163 } 3164 3165 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF); 3166 3167 /* for JD function */ 3168 if (rt5645->pdata.jd_mode) { 3169 snd_soc_dapm_force_enable_pin(dapm, "JD Power"); 3170 snd_soc_dapm_force_enable_pin(dapm, "LDO2"); 3171 snd_soc_dapm_sync(dapm); 3172 } 3173 3174 rt5645->eq_param = devm_kzalloc(codec->dev, 3175 RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s), GFP_KERNEL); 3176 3177 return 0; 3178 } 3179 3180 static int rt5645_remove(struct snd_soc_codec *codec) 3181 { 3182 rt5645_reset(codec); 3183 return 0; 3184 } 3185 3186 #ifdef CONFIG_PM 3187 static int rt5645_suspend(struct snd_soc_codec *codec) 3188 { 3189 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 3190 3191 regcache_cache_only(rt5645->regmap, true); 3192 regcache_mark_dirty(rt5645->regmap); 3193 3194 return 0; 3195 } 3196 3197 static int rt5645_resume(struct snd_soc_codec *codec) 3198 { 3199 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 3200 3201 regcache_cache_only(rt5645->regmap, false); 3202 regcache_sync(rt5645->regmap); 3203 3204 return 0; 3205 } 3206 #else 3207 #define rt5645_suspend NULL 3208 #define rt5645_resume NULL 3209 #endif 3210 3211 #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000 3212 #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 3213 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 3214 3215 static const struct snd_soc_dai_ops rt5645_aif_dai_ops = { 3216 .hw_params = rt5645_hw_params, 3217 .set_fmt = rt5645_set_dai_fmt, 3218 .set_sysclk = rt5645_set_dai_sysclk, 3219 .set_tdm_slot = rt5645_set_tdm_slot, 3220 .set_pll = rt5645_set_dai_pll, 3221 }; 3222 3223 static struct snd_soc_dai_driver rt5645_dai[] = { 3224 { 3225 .name = "rt5645-aif1", 3226 .id = RT5645_AIF1, 3227 .playback = { 3228 .stream_name = "AIF1 Playback", 3229 .channels_min = 1, 3230 .channels_max = 2, 3231 .rates = RT5645_STEREO_RATES, 3232 .formats = RT5645_FORMATS, 3233 }, 3234 .capture = { 3235 .stream_name = "AIF1 Capture", 3236 .channels_min = 1, 3237 .channels_max = 4, 3238 .rates = RT5645_STEREO_RATES, 3239 .formats = RT5645_FORMATS, 3240 }, 3241 .ops = &rt5645_aif_dai_ops, 3242 }, 3243 { 3244 .name = "rt5645-aif2", 3245 .id = RT5645_AIF2, 3246 .playback = { 3247 .stream_name = "AIF2 Playback", 3248 .channels_min = 1, 3249 .channels_max = 2, 3250 .rates = RT5645_STEREO_RATES, 3251 .formats = RT5645_FORMATS, 3252 }, 3253 .capture = { 3254 .stream_name = "AIF2 Capture", 3255 .channels_min = 1, 3256 .channels_max = 2, 3257 .rates = RT5645_STEREO_RATES, 3258 .formats = RT5645_FORMATS, 3259 }, 3260 .ops = &rt5645_aif_dai_ops, 3261 }, 3262 }; 3263 3264 static struct snd_soc_codec_driver soc_codec_dev_rt5645 = { 3265 .probe = rt5645_probe, 3266 .remove = rt5645_remove, 3267 .suspend = rt5645_suspend, 3268 .resume = rt5645_resume, 3269 .set_bias_level = rt5645_set_bias_level, 3270 .idle_bias_off = true, 3271 .controls = rt5645_snd_controls, 3272 .num_controls = ARRAY_SIZE(rt5645_snd_controls), 3273 .dapm_widgets = rt5645_dapm_widgets, 3274 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets), 3275 .dapm_routes = rt5645_dapm_routes, 3276 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes), 3277 }; 3278 3279 static const struct regmap_config rt5645_regmap = { 3280 .reg_bits = 8, 3281 .val_bits = 16, 3282 .use_single_rw = true, 3283 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * 3284 RT5645_PR_SPACING), 3285 .volatile_reg = rt5645_volatile_register, 3286 .readable_reg = rt5645_readable_register, 3287 3288 .cache_type = REGCACHE_RBTREE, 3289 .reg_defaults = rt5645_reg, 3290 .num_reg_defaults = ARRAY_SIZE(rt5645_reg), 3291 .ranges = rt5645_ranges, 3292 .num_ranges = ARRAY_SIZE(rt5645_ranges), 3293 }; 3294 3295 static const struct i2c_device_id rt5645_i2c_id[] = { 3296 { "rt5645", 0 }, 3297 { "rt5650", 0 }, 3298 { } 3299 }; 3300 MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id); 3301 3302 #ifdef CONFIG_ACPI 3303 static struct acpi_device_id rt5645_acpi_match[] = { 3304 { "10EC5645", 0 }, 3305 { "10EC5650", 0 }, 3306 {}, 3307 }; 3308 MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match); 3309 #endif 3310 3311 static struct rt5645_platform_data *rt5645_pdata; 3312 3313 static struct rt5645_platform_data strago_platform_data = { 3314 .dmic1_data_pin = RT5645_DMIC1_DISABLE, 3315 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3316 .jd_mode = 3, 3317 }; 3318 3319 static int strago_quirk_cb(const struct dmi_system_id *id) 3320 { 3321 rt5645_pdata = &strago_platform_data; 3322 3323 return 1; 3324 } 3325 3326 static const struct dmi_system_id dmi_platform_intel_braswell[] = { 3327 { 3328 .ident = "Intel Strago", 3329 .callback = strago_quirk_cb, 3330 .matches = { 3331 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"), 3332 }, 3333 }, 3334 { 3335 .ident = "Google Celes", 3336 .callback = strago_quirk_cb, 3337 .matches = { 3338 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"), 3339 }, 3340 }, 3341 { 3342 .ident = "Google Ultima", 3343 .callback = strago_quirk_cb, 3344 .matches = { 3345 DMI_MATCH(DMI_PRODUCT_NAME, "Ultima"), 3346 }, 3347 }, 3348 { 3349 .ident = "Google Reks", 3350 .callback = strago_quirk_cb, 3351 .matches = { 3352 DMI_MATCH(DMI_PRODUCT_NAME, "Reks"), 3353 }, 3354 }, 3355 { } 3356 }; 3357 3358 static struct rt5645_platform_data buddy_platform_data = { 3359 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, 3360 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3361 .jd_mode = 3, 3362 .jd_invert = true, 3363 }; 3364 3365 static int buddy_quirk_cb(const struct dmi_system_id *id) 3366 { 3367 rt5645_pdata = &buddy_platform_data; 3368 3369 return 1; 3370 } 3371 3372 static struct dmi_system_id dmi_platform_intel_broadwell[] = { 3373 { 3374 .ident = "Chrome Buddy", 3375 .callback = buddy_quirk_cb, 3376 .matches = { 3377 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"), 3378 }, 3379 }, 3380 { } 3381 }; 3382 3383 3384 static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev) 3385 { 3386 rt5645->pdata.in2_diff = device_property_read_bool(dev, 3387 "realtek,in2-differential"); 3388 device_property_read_u32(dev, 3389 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin); 3390 device_property_read_u32(dev, 3391 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin); 3392 device_property_read_u32(dev, 3393 "realtek,jd-mode", &rt5645->pdata.jd_mode); 3394 3395 return 0; 3396 } 3397 3398 static int rt5645_i2c_probe(struct i2c_client *i2c, 3399 const struct i2c_device_id *id) 3400 { 3401 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev); 3402 struct rt5645_priv *rt5645; 3403 int ret, i; 3404 unsigned int val; 3405 3406 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv), 3407 GFP_KERNEL); 3408 if (rt5645 == NULL) 3409 return -ENOMEM; 3410 3411 rt5645->i2c = i2c; 3412 i2c_set_clientdata(i2c, rt5645); 3413 3414 if (pdata) 3415 rt5645->pdata = *pdata; 3416 else if (dmi_check_system(dmi_platform_intel_braswell) || 3417 dmi_check_system(dmi_platform_intel_broadwell)) 3418 rt5645->pdata = *rt5645_pdata; 3419 else 3420 rt5645_parse_dt(rt5645, &i2c->dev); 3421 3422 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect", 3423 GPIOD_IN); 3424 3425 if (IS_ERR(rt5645->gpiod_hp_det)) { 3426 dev_err(&i2c->dev, "failed to initialize gpiod\n"); 3427 return PTR_ERR(rt5645->gpiod_hp_det); 3428 } 3429 3430 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap); 3431 if (IS_ERR(rt5645->regmap)) { 3432 ret = PTR_ERR(rt5645->regmap); 3433 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 3434 ret); 3435 return ret; 3436 } 3437 3438 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++) 3439 rt5645->supplies[i].supply = rt5645_supply_names[i]; 3440 3441 ret = devm_regulator_bulk_get(&i2c->dev, 3442 ARRAY_SIZE(rt5645->supplies), 3443 rt5645->supplies); 3444 if (ret) { 3445 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 3446 return ret; 3447 } 3448 3449 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies), 3450 rt5645->supplies); 3451 if (ret) { 3452 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 3453 return ret; 3454 } 3455 3456 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val); 3457 3458 switch (val) { 3459 case RT5645_DEVICE_ID: 3460 rt5645->codec_type = CODEC_TYPE_RT5645; 3461 break; 3462 case RT5650_DEVICE_ID: 3463 rt5645->codec_type = CODEC_TYPE_RT5650; 3464 break; 3465 default: 3466 dev_err(&i2c->dev, 3467 "Device with ID register %#x is not rt5645 or rt5650\n", 3468 val); 3469 ret = -ENODEV; 3470 goto err_enable; 3471 } 3472 3473 regmap_write(rt5645->regmap, RT5645_RESET, 0); 3474 3475 ret = regmap_register_patch(rt5645->regmap, init_list, 3476 ARRAY_SIZE(init_list)); 3477 if (ret != 0) 3478 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 3479 3480 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 3481 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list, 3482 ARRAY_SIZE(rt5650_init_list)); 3483 if (ret != 0) 3484 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n", 3485 ret); 3486 } 3487 3488 if (rt5645->pdata.in2_diff) 3489 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL, 3490 RT5645_IN_DF2, RT5645_IN_DF2); 3491 3492 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) { 3493 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3494 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL); 3495 } 3496 switch (rt5645->pdata.dmic1_data_pin) { 3497 case RT5645_DMIC_DATA_IN2N: 3498 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3499 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N); 3500 break; 3501 3502 case RT5645_DMIC_DATA_GPIO5: 3503 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3504 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO); 3505 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3506 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5); 3507 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3508 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA); 3509 break; 3510 3511 case RT5645_DMIC_DATA_GPIO11: 3512 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3513 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11); 3514 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3515 RT5645_GP11_PIN_MASK, 3516 RT5645_GP11_PIN_DMIC1_SDA); 3517 break; 3518 3519 default: 3520 break; 3521 } 3522 3523 switch (rt5645->pdata.dmic2_data_pin) { 3524 case RT5645_DMIC_DATA_IN2P: 3525 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3526 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P); 3527 break; 3528 3529 case RT5645_DMIC_DATA_GPIO6: 3530 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3531 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6); 3532 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3533 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA); 3534 break; 3535 3536 case RT5645_DMIC_DATA_GPIO10: 3537 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3538 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10); 3539 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3540 RT5645_GP10_PIN_MASK, 3541 RT5645_GP10_PIN_DMIC2_SDA); 3542 break; 3543 3544 case RT5645_DMIC_DATA_GPIO12: 3545 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3546 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12); 3547 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3548 RT5645_GP12_PIN_MASK, 3549 RT5645_GP12_PIN_DMIC2_SDA); 3550 break; 3551 3552 default: 3553 break; 3554 } 3555 3556 if (rt5645->pdata.jd_mode) { 3557 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 3558 RT5645_IRQ_CLK_GATE_CTRL, 3559 RT5645_IRQ_CLK_GATE_CTRL); 3560 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 3561 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT); 3562 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 3563 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN); 3564 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 3565 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE); 3566 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER, 3567 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE); 3568 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 3569 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN); 3570 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3571 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); 3572 switch (rt5645->pdata.jd_mode) { 3573 case 1: 3574 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 3575 RT5645_JD1_MODE_MASK, 3576 RT5645_JD1_MODE_0); 3577 break; 3578 case 2: 3579 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 3580 RT5645_JD1_MODE_MASK, 3581 RT5645_JD1_MODE_1); 3582 break; 3583 case 3: 3584 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 3585 RT5645_JD1_MODE_MASK, 3586 RT5645_JD1_MODE_2); 3587 break; 3588 default: 3589 break; 3590 } 3591 } 3592 3593 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work); 3594 3595 if (rt5645->i2c->irq) { 3596 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq, 3597 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 3598 | IRQF_ONESHOT, "rt5645", rt5645); 3599 if (ret) { 3600 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 3601 goto err_enable; 3602 } 3603 } 3604 3605 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645, 3606 rt5645_dai, ARRAY_SIZE(rt5645_dai)); 3607 if (ret) 3608 goto err_irq; 3609 3610 return 0; 3611 3612 err_irq: 3613 if (rt5645->i2c->irq) 3614 free_irq(rt5645->i2c->irq, rt5645); 3615 err_enable: 3616 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); 3617 return ret; 3618 } 3619 3620 static int rt5645_i2c_remove(struct i2c_client *i2c) 3621 { 3622 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); 3623 3624 if (i2c->irq) 3625 free_irq(i2c->irq, rt5645); 3626 3627 cancel_delayed_work_sync(&rt5645->jack_detect_work); 3628 3629 snd_soc_unregister_codec(&i2c->dev); 3630 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); 3631 3632 return 0; 3633 } 3634 3635 static void rt5645_i2c_shutdown(struct i2c_client *i2c) 3636 { 3637 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); 3638 3639 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 3640 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND); 3641 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD, 3642 RT5645_CBJ_MN_JD); 3643 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN, 3644 0); 3645 msleep(20); 3646 regmap_write(rt5645->regmap, RT5645_RESET, 0); 3647 } 3648 3649 static struct i2c_driver rt5645_i2c_driver = { 3650 .driver = { 3651 .name = "rt5645", 3652 .acpi_match_table = ACPI_PTR(rt5645_acpi_match), 3653 }, 3654 .probe = rt5645_i2c_probe, 3655 .remove = rt5645_i2c_remove, 3656 .shutdown = rt5645_i2c_shutdown, 3657 .id_table = rt5645_i2c_id, 3658 }; 3659 module_i2c_driver(rt5645_i2c_driver); 3660 3661 MODULE_DESCRIPTION("ASoC RT5645 driver"); 3662 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 3663 MODULE_LICENSE("GPL v2"); 3664