1*f289e55cSJeff Chang /* SPDX-License-Identifier: GPL-2.0 */ 2*f289e55cSJeff Chang /* 3*f289e55cSJeff Chang * Copyright (c) 2019 MediaTek Inc. 4*f289e55cSJeff Chang */ 5*f289e55cSJeff Chang 6*f289e55cSJeff Chang #ifndef __SND_SOC_MT6660_H 7*f289e55cSJeff Chang #define __SND_SOC_MT6660_H 8*f289e55cSJeff Chang 9*f289e55cSJeff Chang #include <linux/mutex.h> 10*f289e55cSJeff Chang #include <linux/regmap.h> 11*f289e55cSJeff Chang 12*f289e55cSJeff Chang #pragma pack(push, 1) 13*f289e55cSJeff Chang struct mt6660_platform_data { 14*f289e55cSJeff Chang u8 init_setting_num; 15*f289e55cSJeff Chang u32 *init_setting_addr; 16*f289e55cSJeff Chang u32 *init_setting_mask; 17*f289e55cSJeff Chang u32 *init_setting_val; 18*f289e55cSJeff Chang }; 19*f289e55cSJeff Chang 20*f289e55cSJeff Chang struct mt6660_chip { 21*f289e55cSJeff Chang struct i2c_client *i2c; 22*f289e55cSJeff Chang struct device *dev; 23*f289e55cSJeff Chang struct platform_device *param_dev; 24*f289e55cSJeff Chang struct mt6660_platform_data plat_data; 25*f289e55cSJeff Chang struct mutex io_lock; 26*f289e55cSJeff Chang struct regmap *regmap; 27*f289e55cSJeff Chang u16 chip_rev; 28*f289e55cSJeff Chang }; 29*f289e55cSJeff Chang #pragma pack(pop) 30*f289e55cSJeff Chang 31*f289e55cSJeff Chang #define MT6660_REG_DEVID (0x00) 32*f289e55cSJeff Chang #define MT6660_REG_SYSTEM_CTRL (0x03) 33*f289e55cSJeff Chang #define MT6660_REG_IRQ_STATUS1 (0x05) 34*f289e55cSJeff Chang #define MT6660_REG_ADDA_CLOCK (0x07) 35*f289e55cSJeff Chang #define MT6660_REG_SERIAL_CFG1 (0x10) 36*f289e55cSJeff Chang #define MT6660_REG_DATAO_SEL (0x12) 37*f289e55cSJeff Chang #define MT6660_REG_TDM_CFG3 (0x15) 38*f289e55cSJeff Chang #define MT6660_REG_HPF_CTRL (0x18) 39*f289e55cSJeff Chang #define MT6660_REG_HPF1_COEF (0x1A) 40*f289e55cSJeff Chang #define MT6660_REG_HPF2_COEF (0x1B) 41*f289e55cSJeff Chang #define MT6660_REG_PATH_BYPASS (0x1E) 42*f289e55cSJeff Chang #define MT6660_REG_WDT_CTRL (0x20) 43*f289e55cSJeff Chang #define MT6660_REG_HCLIP_CTRL (0x24) 44*f289e55cSJeff Chang #define MT6660_REG_VOL_CTRL (0x29) 45*f289e55cSJeff Chang #define MT6660_REG_SPS_CTRL (0x30) 46*f289e55cSJeff Chang #define MT6660_REG_SIGMAX (0x33) 47*f289e55cSJeff Chang #define MT6660_REG_CALI_T0 (0x3F) 48*f289e55cSJeff Chang #define MT6660_REG_BST_CTRL (0x40) 49*f289e55cSJeff Chang #define MT6660_REG_PROTECTION_CFG (0x46) 50*f289e55cSJeff Chang #define MT6660_REG_DA_GAIN (0x4c) 51*f289e55cSJeff Chang #define MT6660_REG_AUDIO_IN2_SEL (0x50) 52*f289e55cSJeff Chang #define MT6660_REG_SIG_GAIN (0x51) 53*f289e55cSJeff Chang #define MT6660_REG_PLL_CFG1 (0x60) 54*f289e55cSJeff Chang #define MT6660_REG_DRE_CTRL (0x68) 55*f289e55cSJeff Chang #define MT6660_REG_DRE_THDMODE (0x69) 56*f289e55cSJeff Chang #define MT6660_REG_DRE_CORASE (0x6B) 57*f289e55cSJeff Chang #define MT6660_REG_PWM_CTRL (0x70) 58*f289e55cSJeff Chang #define MT6660_REG_DC_PROTECT_CTRL (0x74) 59*f289e55cSJeff Chang #define MT6660_REG_ADC_USB_MODE (0x7c) 60*f289e55cSJeff Chang #define MT6660_REG_INTERNAL_CFG (0x88) 61*f289e55cSJeff Chang #define MT6660_REG_RESV0 (0x98) 62*f289e55cSJeff Chang #define MT6660_REG_RESV1 (0x99) 63*f289e55cSJeff Chang #define MT6660_REG_RESV2 (0x9A) 64*f289e55cSJeff Chang #define MT6660_REG_RESV3 (0x9B) 65*f289e55cSJeff Chang #define MT6660_REG_RESV6 (0xA2) 66*f289e55cSJeff Chang #define MT6660_REG_RESV7 (0xA3) 67*f289e55cSJeff Chang #define MT6660_REG_RESV10 (0xB0) 68*f289e55cSJeff Chang #define MT6660_REG_RESV11 (0xB1) 69*f289e55cSJeff Chang #define MT6660_REG_RESV16 (0xB6) 70*f289e55cSJeff Chang #define MT6660_REG_RESV17 (0xB7) 71*f289e55cSJeff Chang #define MT6660_REG_RESV19 (0xB9) 72*f289e55cSJeff Chang #define MT6660_REG_RESV21 (0xBB) 73*f289e55cSJeff Chang #define MT6660_REG_RESV23 (0xBD) 74*f289e55cSJeff Chang #define MT6660_REG_RESV31 (0xD3) 75*f289e55cSJeff Chang #define MT6660_REG_RESV40 (0xE0) 76*f289e55cSJeff Chang 77*f289e55cSJeff Chang #endif /* __SND_SOC_MT6660_H */ 78