1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24c5d1469SSylwester Nawrocki /* 34c5d1469SSylwester Nawrocki * MAX98504 ALSA SoC Audio driver 44c5d1469SSylwester Nawrocki * 54c5d1469SSylwester Nawrocki * Copyright 2011 - 2012 Maxim Integrated Products 64c5d1469SSylwester Nawrocki * Copyright 2016 Samsung Electronics Co., Ltd. 74c5d1469SSylwester Nawrocki */ 84c5d1469SSylwester Nawrocki #ifndef MAX98504_H_ 94c5d1469SSylwester Nawrocki #define MAX98504_H_ 104c5d1469SSylwester Nawrocki 114c5d1469SSylwester Nawrocki /* 124c5d1469SSylwester Nawrocki * MAX98504 Register Definitions 134c5d1469SSylwester Nawrocki */ 144c5d1469SSylwester Nawrocki #define MAX98504_INTERRUPT_STATUS 0x01 154c5d1469SSylwester Nawrocki #define MAX98504_INTERRUPT_FLAGS 0x02 164c5d1469SSylwester Nawrocki #define MAX98504_INTERRUPT_ENABLE 0x03 174c5d1469SSylwester Nawrocki #define MAX98504_INTERRUPT_FLAG_CLEARS 0x04 184c5d1469SSylwester Nawrocki #define MAX98504_GPIO_ENABLE 0x10 194c5d1469SSylwester Nawrocki #define MAX98504_GPIO_CONFIG 0x11 204c5d1469SSylwester Nawrocki #define MAX98504_WATCHDOG_ENABLE 0x12 214c5d1469SSylwester Nawrocki #define MAX98504_WATCHDOG_CONFIG 0x13 224c5d1469SSylwester Nawrocki #define MAX98504_WATCHDOG_CLEAR 0x14 234c5d1469SSylwester Nawrocki #define MAX98504_CLOCK_MONITOR_ENABLE 0x15 244c5d1469SSylwester Nawrocki #define MAX98504_PVDD_BROWNOUT_ENABLE 0x16 254c5d1469SSylwester Nawrocki #define MAX98504_PVDD_BROWNOUT_CONFIG_1 0x17 264c5d1469SSylwester Nawrocki #define MAX98504_PVDD_BROWNOUT_CONFIG_2 0x18 274c5d1469SSylwester Nawrocki #define MAX98504_PVDD_BROWNOUT_CONFIG_3 0x19 284c5d1469SSylwester Nawrocki #define MAX98504_PVDD_BROWNOUT_CONFIG_4 0x1a 294c5d1469SSylwester Nawrocki #define MAX98504_PCM_RX_ENABLE 0x20 304c5d1469SSylwester Nawrocki #define MAX98504_PCM_TX_ENABLE 0x21 314c5d1469SSylwester Nawrocki #define MAX98504_PCM_TX_HIZ_CONTROL 0x22 324c5d1469SSylwester Nawrocki #define MAX98504_PCM_TX_CHANNEL_SOURCES 0x23 334c5d1469SSylwester Nawrocki #define MAX98504_PCM_MODE_CONFIG 0x24 344c5d1469SSylwester Nawrocki #define MAX98504_PCM_DSP_CONFIG 0x25 354c5d1469SSylwester Nawrocki #define MAX98504_PCM_CLOCK_SETUP 0x26 364c5d1469SSylwester Nawrocki #define MAX98504_PCM_SAMPLE_RATE_SETUP 0x27 374c5d1469SSylwester Nawrocki #define MAX98504_PCM_TO_SPEAKER_MONOMIX 0x28 384c5d1469SSylwester Nawrocki #define MAX98504_PDM_TX_ENABLE 0x30 394c5d1469SSylwester Nawrocki #define MAX98504_PDM_TX_HIZ_CONTROL 0x31 404c5d1469SSylwester Nawrocki #define MAX98504_PDM_TX_CONTROL 0x32 414c5d1469SSylwester Nawrocki #define MAX98504_PDM_RX_ENABLE 0x33 424c5d1469SSylwester Nawrocki #define MAX98504_SPEAKER_ENABLE 0x34 434c5d1469SSylwester Nawrocki #define MAX98504_SPEAKER_SOURCE_SELECT 0x35 444c5d1469SSylwester Nawrocki #define MAX98504_MEASUREMENT_ENABLE 0x36 454c5d1469SSylwester Nawrocki #define MAX98504_ANALOGUE_INPUT_GAIN 0x37 464c5d1469SSylwester Nawrocki #define MAX98504_TEMPERATURE_LIMIT_CONFIG 0x38 474c5d1469SSylwester Nawrocki #define MAX98504_GLOBAL_ENABLE 0x40 484c5d1469SSylwester Nawrocki #define MAX98504_SOFTWARE_RESET 0x41 494c5d1469SSylwester Nawrocki #define MAX98504_REV_ID 0x7fff 504c5d1469SSylwester Nawrocki 514c5d1469SSylwester Nawrocki #define MAX98504_MAX_REGISTER 0x7fff 524c5d1469SSylwester Nawrocki 534c5d1469SSylwester Nawrocki #define MAX98504_DAI_ID_PCM 1 544c5d1469SSylwester Nawrocki #define MAX98504_DAI_ID_PDM 2 554c5d1469SSylwester Nawrocki 564c5d1469SSylwester Nawrocki #endif /* MAX98504_H_ */ 57