10c516b4fSNicolin Chen /* 20c516b4fSNicolin Chen * Cirrus Logic CS42448/CS42888 Audio CODEC Digital Audio Interface (DAI) driver 30c516b4fSNicolin Chen * 40c516b4fSNicolin Chen * Copyright (C) 2014 Freescale Semiconductor, Inc. 50c516b4fSNicolin Chen * 60c516b4fSNicolin Chen * Author: Nicolin Chen <Guangyu.Chen@freescale.com> 70c516b4fSNicolin Chen * 80c516b4fSNicolin Chen * This file is licensed under the terms of the GNU General Public License 90c516b4fSNicolin Chen * version 2. This program is licensed "as is" without any warranty of any 100c516b4fSNicolin Chen * kind, whether express or implied. 110c516b4fSNicolin Chen */ 120c516b4fSNicolin Chen 130c516b4fSNicolin Chen #include <linux/clk.h> 140c516b4fSNicolin Chen #include <linux/delay.h> 150c516b4fSNicolin Chen #include <linux/module.h> 160c516b4fSNicolin Chen #include <linux/of_device.h> 170c516b4fSNicolin Chen #include <linux/pm_runtime.h> 180c516b4fSNicolin Chen #include <linux/regulator/consumer.h> 190c516b4fSNicolin Chen #include <sound/pcm_params.h> 200c516b4fSNicolin Chen #include <sound/soc.h> 210c516b4fSNicolin Chen #include <sound/tlv.h> 220c516b4fSNicolin Chen 230c516b4fSNicolin Chen #include "cs42xx8.h" 240c516b4fSNicolin Chen 250c516b4fSNicolin Chen #define CS42XX8_NUM_SUPPLIES 4 260c516b4fSNicolin Chen static const char *const cs42xx8_supply_names[CS42XX8_NUM_SUPPLIES] = { 270c516b4fSNicolin Chen "VA", 280c516b4fSNicolin Chen "VD", 290c516b4fSNicolin Chen "VLS", 300c516b4fSNicolin Chen "VLC", 310c516b4fSNicolin Chen }; 320c516b4fSNicolin Chen 330c516b4fSNicolin Chen #define CS42XX8_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 340c516b4fSNicolin Chen SNDRV_PCM_FMTBIT_S20_3LE | \ 350c516b4fSNicolin Chen SNDRV_PCM_FMTBIT_S24_LE | \ 360c516b4fSNicolin Chen SNDRV_PCM_FMTBIT_S32_LE) 370c516b4fSNicolin Chen 380c516b4fSNicolin Chen /* codec private data */ 390c516b4fSNicolin Chen struct cs42xx8_priv { 400c516b4fSNicolin Chen struct regulator_bulk_data supplies[CS42XX8_NUM_SUPPLIES]; 410c516b4fSNicolin Chen const struct cs42xx8_driver_data *drvdata; 420c516b4fSNicolin Chen struct regmap *regmap; 430c516b4fSNicolin Chen struct clk *clk; 440c516b4fSNicolin Chen 450c516b4fSNicolin Chen bool slave_mode; 460c516b4fSNicolin Chen unsigned long sysclk; 470c516b4fSNicolin Chen }; 480c516b4fSNicolin Chen 490c516b4fSNicolin Chen /* -127.5dB to 0dB with step of 0.5dB */ 500c516b4fSNicolin Chen static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1); 510c516b4fSNicolin Chen /* -64dB to 24dB with step of 0.5dB */ 520c516b4fSNicolin Chen static const DECLARE_TLV_DB_SCALE(adc_tlv, -6400, 50, 0); 530c516b4fSNicolin Chen 540c516b4fSNicolin Chen static const char *const cs42xx8_adc_single[] = { "Differential", "Single-Ended" }; 550c516b4fSNicolin Chen static const char *const cs42xx8_szc[] = { "Immediate Change", "Zero Cross", 560c516b4fSNicolin Chen "Soft Ramp", "Soft Ramp on Zero Cross" }; 570c516b4fSNicolin Chen 580c516b4fSNicolin Chen static const struct soc_enum adc1_single_enum = 590c516b4fSNicolin Chen SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 4, 2, cs42xx8_adc_single); 600c516b4fSNicolin Chen static const struct soc_enum adc2_single_enum = 610c516b4fSNicolin Chen SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 3, 2, cs42xx8_adc_single); 620c516b4fSNicolin Chen static const struct soc_enum adc3_single_enum = 630c516b4fSNicolin Chen SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 2, 2, cs42xx8_adc_single); 640c516b4fSNicolin Chen static const struct soc_enum dac_szc_enum = 650c516b4fSNicolin Chen SOC_ENUM_SINGLE(CS42XX8_TXCTL, 5, 4, cs42xx8_szc); 660c516b4fSNicolin Chen static const struct soc_enum adc_szc_enum = 670c516b4fSNicolin Chen SOC_ENUM_SINGLE(CS42XX8_TXCTL, 0, 4, cs42xx8_szc); 680c516b4fSNicolin Chen 690c516b4fSNicolin Chen static const struct snd_kcontrol_new cs42xx8_snd_controls[] = { 700c516b4fSNicolin Chen SOC_DOUBLE_R_TLV("DAC1 Playback Volume", CS42XX8_VOLAOUT1, 710c516b4fSNicolin Chen CS42XX8_VOLAOUT2, 0, 0xff, 1, dac_tlv), 720c516b4fSNicolin Chen SOC_DOUBLE_R_TLV("DAC2 Playback Volume", CS42XX8_VOLAOUT3, 730c516b4fSNicolin Chen CS42XX8_VOLAOUT4, 0, 0xff, 1, dac_tlv), 740c516b4fSNicolin Chen SOC_DOUBLE_R_TLV("DAC3 Playback Volume", CS42XX8_VOLAOUT5, 750c516b4fSNicolin Chen CS42XX8_VOLAOUT6, 0, 0xff, 1, dac_tlv), 760c516b4fSNicolin Chen SOC_DOUBLE_R_TLV("DAC4 Playback Volume", CS42XX8_VOLAOUT7, 770c516b4fSNicolin Chen CS42XX8_VOLAOUT8, 0, 0xff, 1, dac_tlv), 780c516b4fSNicolin Chen SOC_DOUBLE_R_S_TLV("ADC1 Capture Volume", CS42XX8_VOLAIN1, 790c516b4fSNicolin Chen CS42XX8_VOLAIN2, 0, -0x80, 0x30, 7, 0, adc_tlv), 800c516b4fSNicolin Chen SOC_DOUBLE_R_S_TLV("ADC2 Capture Volume", CS42XX8_VOLAIN3, 810c516b4fSNicolin Chen CS42XX8_VOLAIN4, 0, -0x80, 0x30, 7, 0, adc_tlv), 820c516b4fSNicolin Chen SOC_DOUBLE("DAC1 Invert Switch", CS42XX8_DACINV, 0, 1, 1, 0), 830c516b4fSNicolin Chen SOC_DOUBLE("DAC2 Invert Switch", CS42XX8_DACINV, 2, 3, 1, 0), 840c516b4fSNicolin Chen SOC_DOUBLE("DAC3 Invert Switch", CS42XX8_DACINV, 4, 5, 1, 0), 850c516b4fSNicolin Chen SOC_DOUBLE("DAC4 Invert Switch", CS42XX8_DACINV, 6, 7, 1, 0), 860c516b4fSNicolin Chen SOC_DOUBLE("ADC1 Invert Switch", CS42XX8_ADCINV, 0, 1, 1, 0), 870c516b4fSNicolin Chen SOC_DOUBLE("ADC2 Invert Switch", CS42XX8_ADCINV, 2, 3, 1, 0), 880c516b4fSNicolin Chen SOC_SINGLE("ADC High-Pass Filter Switch", CS42XX8_ADCCTL, 7, 1, 1), 890c516b4fSNicolin Chen SOC_SINGLE("DAC De-emphasis Switch", CS42XX8_ADCCTL, 5, 1, 0), 900c516b4fSNicolin Chen SOC_ENUM("ADC1 Single Ended Mode Switch", adc1_single_enum), 910c516b4fSNicolin Chen SOC_ENUM("ADC2 Single Ended Mode Switch", adc2_single_enum), 920c516b4fSNicolin Chen SOC_SINGLE("DAC Single Volume Control Switch", CS42XX8_TXCTL, 7, 1, 0), 930c516b4fSNicolin Chen SOC_ENUM("DAC Soft Ramp & Zero Cross Control Switch", dac_szc_enum), 940c516b4fSNicolin Chen SOC_SINGLE("DAC Auto Mute Switch", CS42XX8_TXCTL, 4, 1, 0), 950c516b4fSNicolin Chen SOC_SINGLE("Mute ADC Serial Port Switch", CS42XX8_TXCTL, 3, 1, 0), 960c516b4fSNicolin Chen SOC_SINGLE("ADC Single Volume Control Switch", CS42XX8_TXCTL, 2, 1, 0), 970c516b4fSNicolin Chen SOC_ENUM("ADC Soft Ramp & Zero Cross Control Switch", adc_szc_enum), 980c516b4fSNicolin Chen }; 990c516b4fSNicolin Chen 1000c516b4fSNicolin Chen static const struct snd_kcontrol_new cs42xx8_adc3_snd_controls[] = { 1010c516b4fSNicolin Chen SOC_DOUBLE_R_S_TLV("ADC3 Capture Volume", CS42XX8_VOLAIN5, 1020c516b4fSNicolin Chen CS42XX8_VOLAIN6, 0, -0x80, 0x30, 7, 0, adc_tlv), 1030c516b4fSNicolin Chen SOC_DOUBLE("ADC3 Invert Switch", CS42XX8_ADCINV, 4, 5, 1, 0), 1040c516b4fSNicolin Chen SOC_ENUM("ADC3 Single Ended Mode Switch", adc3_single_enum), 1050c516b4fSNicolin Chen }; 1060c516b4fSNicolin Chen 1070c516b4fSNicolin Chen static const struct snd_soc_dapm_widget cs42xx8_dapm_widgets[] = { 1080c516b4fSNicolin Chen SND_SOC_DAPM_DAC("DAC1", "Playback", CS42XX8_PWRCTL, 1, 1), 1090c516b4fSNicolin Chen SND_SOC_DAPM_DAC("DAC2", "Playback", CS42XX8_PWRCTL, 2, 1), 1100c516b4fSNicolin Chen SND_SOC_DAPM_DAC("DAC3", "Playback", CS42XX8_PWRCTL, 3, 1), 1110c516b4fSNicolin Chen SND_SOC_DAPM_DAC("DAC4", "Playback", CS42XX8_PWRCTL, 4, 1), 1120c516b4fSNicolin Chen 1130c516b4fSNicolin Chen SND_SOC_DAPM_OUTPUT("AOUT1L"), 1140c516b4fSNicolin Chen SND_SOC_DAPM_OUTPUT("AOUT1R"), 1150c516b4fSNicolin Chen SND_SOC_DAPM_OUTPUT("AOUT2L"), 1160c516b4fSNicolin Chen SND_SOC_DAPM_OUTPUT("AOUT2R"), 1170c516b4fSNicolin Chen SND_SOC_DAPM_OUTPUT("AOUT3L"), 1180c516b4fSNicolin Chen SND_SOC_DAPM_OUTPUT("AOUT3R"), 1190c516b4fSNicolin Chen SND_SOC_DAPM_OUTPUT("AOUT4L"), 1200c516b4fSNicolin Chen SND_SOC_DAPM_OUTPUT("AOUT4R"), 1210c516b4fSNicolin Chen 1220c516b4fSNicolin Chen SND_SOC_DAPM_ADC("ADC1", "Capture", CS42XX8_PWRCTL, 5, 1), 1230c516b4fSNicolin Chen SND_SOC_DAPM_ADC("ADC2", "Capture", CS42XX8_PWRCTL, 6, 1), 1240c516b4fSNicolin Chen 1250c516b4fSNicolin Chen SND_SOC_DAPM_INPUT("AIN1L"), 1260c516b4fSNicolin Chen SND_SOC_DAPM_INPUT("AIN1R"), 1270c516b4fSNicolin Chen SND_SOC_DAPM_INPUT("AIN2L"), 1280c516b4fSNicolin Chen SND_SOC_DAPM_INPUT("AIN2R"), 1290c516b4fSNicolin Chen 1300c516b4fSNicolin Chen SND_SOC_DAPM_SUPPLY("PWR", CS42XX8_PWRCTL, 0, 1, NULL, 0), 1310c516b4fSNicolin Chen }; 1320c516b4fSNicolin Chen 1330c516b4fSNicolin Chen static const struct snd_soc_dapm_widget cs42xx8_adc3_dapm_widgets[] = { 1340c516b4fSNicolin Chen SND_SOC_DAPM_ADC("ADC3", "Capture", CS42XX8_PWRCTL, 7, 1), 1350c516b4fSNicolin Chen 1360c516b4fSNicolin Chen SND_SOC_DAPM_INPUT("AIN3L"), 1370c516b4fSNicolin Chen SND_SOC_DAPM_INPUT("AIN3R"), 1380c516b4fSNicolin Chen }; 1390c516b4fSNicolin Chen 1400c516b4fSNicolin Chen static const struct snd_soc_dapm_route cs42xx8_dapm_routes[] = { 1410c516b4fSNicolin Chen /* Playback */ 1420c516b4fSNicolin Chen { "AOUT1L", NULL, "DAC1" }, 1430c516b4fSNicolin Chen { "AOUT1R", NULL, "DAC1" }, 1440c516b4fSNicolin Chen { "DAC1", NULL, "PWR" }, 1450c516b4fSNicolin Chen 1460c516b4fSNicolin Chen { "AOUT2L", NULL, "DAC2" }, 1470c516b4fSNicolin Chen { "AOUT2R", NULL, "DAC2" }, 1480c516b4fSNicolin Chen { "DAC2", NULL, "PWR" }, 1490c516b4fSNicolin Chen 1500c516b4fSNicolin Chen { "AOUT3L", NULL, "DAC3" }, 1510c516b4fSNicolin Chen { "AOUT3R", NULL, "DAC3" }, 1520c516b4fSNicolin Chen { "DAC3", NULL, "PWR" }, 1530c516b4fSNicolin Chen 1540c516b4fSNicolin Chen { "AOUT4L", NULL, "DAC4" }, 1550c516b4fSNicolin Chen { "AOUT4R", NULL, "DAC4" }, 1560c516b4fSNicolin Chen { "DAC4", NULL, "PWR" }, 1570c516b4fSNicolin Chen 1580c516b4fSNicolin Chen /* Capture */ 1590c516b4fSNicolin Chen { "ADC1", NULL, "AIN1L" }, 1600c516b4fSNicolin Chen { "ADC1", NULL, "AIN1R" }, 1610c516b4fSNicolin Chen { "ADC1", NULL, "PWR" }, 1620c516b4fSNicolin Chen 1630c516b4fSNicolin Chen { "ADC2", NULL, "AIN2L" }, 1640c516b4fSNicolin Chen { "ADC2", NULL, "AIN2R" }, 1650c516b4fSNicolin Chen { "ADC2", NULL, "PWR" }, 1660c516b4fSNicolin Chen }; 1670c516b4fSNicolin Chen 1680c516b4fSNicolin Chen static const struct snd_soc_dapm_route cs42xx8_adc3_dapm_routes[] = { 1690c516b4fSNicolin Chen /* Capture */ 1700c516b4fSNicolin Chen { "ADC3", NULL, "AIN3L" }, 1710c516b4fSNicolin Chen { "ADC3", NULL, "AIN3R" }, 1720c516b4fSNicolin Chen { "ADC3", NULL, "PWR" }, 1730c516b4fSNicolin Chen }; 1740c516b4fSNicolin Chen 1750c516b4fSNicolin Chen struct cs42xx8_ratios { 1760c516b4fSNicolin Chen unsigned int ratio; 1770c516b4fSNicolin Chen unsigned char speed; 1780c516b4fSNicolin Chen unsigned char mclk; 1790c516b4fSNicolin Chen }; 1800c516b4fSNicolin Chen 1810c516b4fSNicolin Chen static const struct cs42xx8_ratios cs42xx8_ratios[] = { 1820c516b4fSNicolin Chen { 64, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_256(4) }, 1830c516b4fSNicolin Chen { 96, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_384(4) }, 1840c516b4fSNicolin Chen { 128, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_512(4) }, 1850c516b4fSNicolin Chen { 192, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_768(4) }, 1860c516b4fSNicolin Chen { 256, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_256(1) }, 1870c516b4fSNicolin Chen { 384, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_384(1) }, 1880c516b4fSNicolin Chen { 512, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_512(1) }, 1890c516b4fSNicolin Chen { 768, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_768(1) }, 1900c516b4fSNicolin Chen { 1024, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_1024(1) } 1910c516b4fSNicolin Chen }; 1920c516b4fSNicolin Chen 1930c516b4fSNicolin Chen static int cs42xx8_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1940c516b4fSNicolin Chen int clk_id, unsigned int freq, int dir) 1950c516b4fSNicolin Chen { 1960c516b4fSNicolin Chen struct snd_soc_codec *codec = codec_dai->codec; 1970c516b4fSNicolin Chen struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 1980c516b4fSNicolin Chen 1990c516b4fSNicolin Chen cs42xx8->sysclk = freq; 2000c516b4fSNicolin Chen 2010c516b4fSNicolin Chen return 0; 2020c516b4fSNicolin Chen } 2030c516b4fSNicolin Chen 2040c516b4fSNicolin Chen static int cs42xx8_set_dai_fmt(struct snd_soc_dai *codec_dai, 2050c516b4fSNicolin Chen unsigned int format) 2060c516b4fSNicolin Chen { 2070c516b4fSNicolin Chen struct snd_soc_codec *codec = codec_dai->codec; 2080c516b4fSNicolin Chen struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 2090c516b4fSNicolin Chen u32 val; 2100c516b4fSNicolin Chen 2110c516b4fSNicolin Chen /* Set DAI format */ 2120c516b4fSNicolin Chen switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 2130c516b4fSNicolin Chen case SND_SOC_DAIFMT_LEFT_J: 2140c516b4fSNicolin Chen val = CS42XX8_INTF_DAC_DIF_LEFTJ | CS42XX8_INTF_ADC_DIF_LEFTJ; 2150c516b4fSNicolin Chen break; 2160c516b4fSNicolin Chen case SND_SOC_DAIFMT_I2S: 2170c516b4fSNicolin Chen val = CS42XX8_INTF_DAC_DIF_I2S | CS42XX8_INTF_ADC_DIF_I2S; 2180c516b4fSNicolin Chen break; 2190c516b4fSNicolin Chen case SND_SOC_DAIFMT_RIGHT_J: 2200c516b4fSNicolin Chen val = CS42XX8_INTF_DAC_DIF_RIGHTJ | CS42XX8_INTF_ADC_DIF_RIGHTJ; 2210c516b4fSNicolin Chen break; 222689dc643SShengjiu Wang case SND_SOC_DAIFMT_DSP_A: 223689dc643SShengjiu Wang val = CS42XX8_INTF_DAC_DIF_TDM | CS42XX8_INTF_ADC_DIF_TDM; 224689dc643SShengjiu Wang break; 2250c516b4fSNicolin Chen default: 2260c516b4fSNicolin Chen dev_err(codec->dev, "unsupported dai format\n"); 2270c516b4fSNicolin Chen return -EINVAL; 2280c516b4fSNicolin Chen } 2290c516b4fSNicolin Chen 2300c516b4fSNicolin Chen regmap_update_bits(cs42xx8->regmap, CS42XX8_INTF, 2310c516b4fSNicolin Chen CS42XX8_INTF_DAC_DIF_MASK | 2320c516b4fSNicolin Chen CS42XX8_INTF_ADC_DIF_MASK, val); 2330c516b4fSNicolin Chen 2340c516b4fSNicolin Chen /* Set master/slave audio interface */ 2350c516b4fSNicolin Chen switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 2360c516b4fSNicolin Chen case SND_SOC_DAIFMT_CBS_CFS: 2370c516b4fSNicolin Chen cs42xx8->slave_mode = true; 2380c516b4fSNicolin Chen break; 2390c516b4fSNicolin Chen case SND_SOC_DAIFMT_CBM_CFM: 2400c516b4fSNicolin Chen cs42xx8->slave_mode = false; 2410c516b4fSNicolin Chen break; 2420c516b4fSNicolin Chen default: 2430c516b4fSNicolin Chen dev_err(codec->dev, "unsupported master/slave mode\n"); 2440c516b4fSNicolin Chen return -EINVAL; 2450c516b4fSNicolin Chen } 2460c516b4fSNicolin Chen 2470c516b4fSNicolin Chen return 0; 2480c516b4fSNicolin Chen } 2490c516b4fSNicolin Chen 2500c516b4fSNicolin Chen static int cs42xx8_hw_params(struct snd_pcm_substream *substream, 2510c516b4fSNicolin Chen struct snd_pcm_hw_params *params, 2520c516b4fSNicolin Chen struct snd_soc_dai *dai) 2530c516b4fSNicolin Chen { 2545958de23SLars-Peter Clausen struct snd_soc_codec *codec = dai->codec; 2550c516b4fSNicolin Chen struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 2560c516b4fSNicolin Chen bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 2570c516b4fSNicolin Chen u32 ratio = cs42xx8->sysclk / params_rate(params); 2580c516b4fSNicolin Chen u32 i, fm, val, mask; 2590c516b4fSNicolin Chen 2600c516b4fSNicolin Chen for (i = 0; i < ARRAY_SIZE(cs42xx8_ratios); i++) { 2610c516b4fSNicolin Chen if (cs42xx8_ratios[i].ratio == ratio) 2620c516b4fSNicolin Chen break; 2630c516b4fSNicolin Chen } 2640c516b4fSNicolin Chen 2650c516b4fSNicolin Chen if (i == ARRAY_SIZE(cs42xx8_ratios)) { 2660c516b4fSNicolin Chen dev_err(codec->dev, "unsupported sysclk ratio\n"); 2670c516b4fSNicolin Chen return -EINVAL; 2680c516b4fSNicolin Chen } 2690c516b4fSNicolin Chen 2700c516b4fSNicolin Chen mask = CS42XX8_FUNCMOD_MFREQ_MASK; 2710c516b4fSNicolin Chen val = cs42xx8_ratios[i].mclk; 2720c516b4fSNicolin Chen 2730c516b4fSNicolin Chen fm = cs42xx8->slave_mode ? CS42XX8_FM_AUTO : cs42xx8_ratios[i].speed; 2740c516b4fSNicolin Chen 2750c516b4fSNicolin Chen regmap_update_bits(cs42xx8->regmap, CS42XX8_FUNCMOD, 2760c516b4fSNicolin Chen CS42XX8_FUNCMOD_xC_FM_MASK(tx) | mask, 2770c516b4fSNicolin Chen CS42XX8_FUNCMOD_xC_FM(tx, fm) | val); 2780c516b4fSNicolin Chen 2790c516b4fSNicolin Chen return 0; 2800c516b4fSNicolin Chen } 2810c516b4fSNicolin Chen 2820c516b4fSNicolin Chen static int cs42xx8_digital_mute(struct snd_soc_dai *dai, int mute) 2830c516b4fSNicolin Chen { 2840c516b4fSNicolin Chen struct snd_soc_codec *codec = dai->codec; 2850c516b4fSNicolin Chen struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 2860c516b4fSNicolin Chen 2870c516b4fSNicolin Chen regmap_update_bits(cs42xx8->regmap, CS42XX8_DACMUTE, 2880c516b4fSNicolin Chen CS42XX8_DACMUTE_ALL, mute ? CS42XX8_DACMUTE_ALL : 0); 2890c516b4fSNicolin Chen 2900c516b4fSNicolin Chen return 0; 2910c516b4fSNicolin Chen } 2920c516b4fSNicolin Chen 2930c516b4fSNicolin Chen static const struct snd_soc_dai_ops cs42xx8_dai_ops = { 2940c516b4fSNicolin Chen .set_fmt = cs42xx8_set_dai_fmt, 2950c516b4fSNicolin Chen .set_sysclk = cs42xx8_set_dai_sysclk, 2960c516b4fSNicolin Chen .hw_params = cs42xx8_hw_params, 2970c516b4fSNicolin Chen .digital_mute = cs42xx8_digital_mute, 2980c516b4fSNicolin Chen }; 2990c516b4fSNicolin Chen 3000c516b4fSNicolin Chen static struct snd_soc_dai_driver cs42xx8_dai = { 3010c516b4fSNicolin Chen .playback = { 3020c516b4fSNicolin Chen .stream_name = "Playback", 3030c516b4fSNicolin Chen .channels_min = 1, 3040c516b4fSNicolin Chen .channels_max = 8, 3050c516b4fSNicolin Chen .rates = SNDRV_PCM_RATE_8000_192000, 3060c516b4fSNicolin Chen .formats = CS42XX8_FORMATS, 3070c516b4fSNicolin Chen }, 3080c516b4fSNicolin Chen .capture = { 3090c516b4fSNicolin Chen .stream_name = "Capture", 3100c516b4fSNicolin Chen .channels_min = 1, 3110c516b4fSNicolin Chen .rates = SNDRV_PCM_RATE_8000_192000, 3120c516b4fSNicolin Chen .formats = CS42XX8_FORMATS, 3130c516b4fSNicolin Chen }, 3140c516b4fSNicolin Chen .ops = &cs42xx8_dai_ops, 3150c516b4fSNicolin Chen }; 3160c516b4fSNicolin Chen 3170c516b4fSNicolin Chen static const struct reg_default cs42xx8_reg[] = { 3180c516b4fSNicolin Chen { 0x01, 0x01 }, /* Chip I.D. and Revision Register */ 3190c516b4fSNicolin Chen { 0x02, 0x00 }, /* Power Control */ 3200c516b4fSNicolin Chen { 0x03, 0xF0 }, /* Functional Mode */ 3210c516b4fSNicolin Chen { 0x04, 0x46 }, /* Interface Formats */ 3220c516b4fSNicolin Chen { 0x05, 0x00 }, /* ADC Control & DAC De-Emphasis */ 3230c516b4fSNicolin Chen { 0x06, 0x10 }, /* Transition Control */ 3240c516b4fSNicolin Chen { 0x07, 0x00 }, /* DAC Channel Mute */ 3250c516b4fSNicolin Chen { 0x08, 0x00 }, /* Volume Control AOUT1 */ 3260c516b4fSNicolin Chen { 0x09, 0x00 }, /* Volume Control AOUT2 */ 3270c516b4fSNicolin Chen { 0x0a, 0x00 }, /* Volume Control AOUT3 */ 3280c516b4fSNicolin Chen { 0x0b, 0x00 }, /* Volume Control AOUT4 */ 3290c516b4fSNicolin Chen { 0x0c, 0x00 }, /* Volume Control AOUT5 */ 3300c516b4fSNicolin Chen { 0x0d, 0x00 }, /* Volume Control AOUT6 */ 3310c516b4fSNicolin Chen { 0x0e, 0x00 }, /* Volume Control AOUT7 */ 3320c516b4fSNicolin Chen { 0x0f, 0x00 }, /* Volume Control AOUT8 */ 3330c516b4fSNicolin Chen { 0x10, 0x00 }, /* DAC Channel Invert */ 3340c516b4fSNicolin Chen { 0x11, 0x00 }, /* Volume Control AIN1 */ 3350c516b4fSNicolin Chen { 0x12, 0x00 }, /* Volume Control AIN2 */ 3360c516b4fSNicolin Chen { 0x13, 0x00 }, /* Volume Control AIN3 */ 3370c516b4fSNicolin Chen { 0x14, 0x00 }, /* Volume Control AIN4 */ 3380c516b4fSNicolin Chen { 0x15, 0x00 }, /* Volume Control AIN5 */ 3390c516b4fSNicolin Chen { 0x16, 0x00 }, /* Volume Control AIN6 */ 3400c516b4fSNicolin Chen { 0x17, 0x00 }, /* ADC Channel Invert */ 3410c516b4fSNicolin Chen { 0x18, 0x00 }, /* Status Control */ 3420c516b4fSNicolin Chen { 0x1a, 0x00 }, /* Status Mask */ 3430c516b4fSNicolin Chen { 0x1b, 0x00 }, /* MUTEC Pin Control */ 3440c516b4fSNicolin Chen }; 3450c516b4fSNicolin Chen 3460c516b4fSNicolin Chen static bool cs42xx8_volatile_register(struct device *dev, unsigned int reg) 3470c516b4fSNicolin Chen { 3480c516b4fSNicolin Chen switch (reg) { 3490c516b4fSNicolin Chen case CS42XX8_STATUS: 3500c516b4fSNicolin Chen return true; 3510c516b4fSNicolin Chen default: 3520c516b4fSNicolin Chen return false; 3530c516b4fSNicolin Chen } 3540c516b4fSNicolin Chen } 3550c516b4fSNicolin Chen 3560c516b4fSNicolin Chen static bool cs42xx8_writeable_register(struct device *dev, unsigned int reg) 3570c516b4fSNicolin Chen { 3580c516b4fSNicolin Chen switch (reg) { 3590c516b4fSNicolin Chen case CS42XX8_CHIPID: 3600c516b4fSNicolin Chen case CS42XX8_STATUS: 3610c516b4fSNicolin Chen return false; 3620c516b4fSNicolin Chen default: 3630c516b4fSNicolin Chen return true; 3640c516b4fSNicolin Chen } 3650c516b4fSNicolin Chen } 3660c516b4fSNicolin Chen 3670c516b4fSNicolin Chen const struct regmap_config cs42xx8_regmap_config = { 3680c516b4fSNicolin Chen .reg_bits = 8, 3690c516b4fSNicolin Chen .val_bits = 8, 3700c516b4fSNicolin Chen 3710c516b4fSNicolin Chen .max_register = CS42XX8_LASTREG, 3720c516b4fSNicolin Chen .reg_defaults = cs42xx8_reg, 3730c516b4fSNicolin Chen .num_reg_defaults = ARRAY_SIZE(cs42xx8_reg), 3740c516b4fSNicolin Chen .volatile_reg = cs42xx8_volatile_register, 3750c516b4fSNicolin Chen .writeable_reg = cs42xx8_writeable_register, 3760c516b4fSNicolin Chen .cache_type = REGCACHE_RBTREE, 3770c516b4fSNicolin Chen }; 3780c516b4fSNicolin Chen EXPORT_SYMBOL_GPL(cs42xx8_regmap_config); 3790c516b4fSNicolin Chen 3800c516b4fSNicolin Chen static int cs42xx8_codec_probe(struct snd_soc_codec *codec) 3810c516b4fSNicolin Chen { 3820c516b4fSNicolin Chen struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 3830c516b4fSNicolin Chen struct snd_soc_dapm_context *dapm = &codec->dapm; 3840c516b4fSNicolin Chen 3850c516b4fSNicolin Chen switch (cs42xx8->drvdata->num_adcs) { 3860c516b4fSNicolin Chen case 3: 3870c516b4fSNicolin Chen snd_soc_add_codec_controls(codec, cs42xx8_adc3_snd_controls, 3880c516b4fSNicolin Chen ARRAY_SIZE(cs42xx8_adc3_snd_controls)); 3890c516b4fSNicolin Chen snd_soc_dapm_new_controls(dapm, cs42xx8_adc3_dapm_widgets, 3900c516b4fSNicolin Chen ARRAY_SIZE(cs42xx8_adc3_dapm_widgets)); 3910c516b4fSNicolin Chen snd_soc_dapm_add_routes(dapm, cs42xx8_adc3_dapm_routes, 3920c516b4fSNicolin Chen ARRAY_SIZE(cs42xx8_adc3_dapm_routes)); 3930c516b4fSNicolin Chen break; 3940c516b4fSNicolin Chen default: 3950c516b4fSNicolin Chen break; 3960c516b4fSNicolin Chen } 3970c516b4fSNicolin Chen 3980c516b4fSNicolin Chen /* Mute all DAC channels */ 3990c516b4fSNicolin Chen regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE, CS42XX8_DACMUTE_ALL); 4000c516b4fSNicolin Chen 4010c516b4fSNicolin Chen return 0; 4020c516b4fSNicolin Chen } 4030c516b4fSNicolin Chen 4040c516b4fSNicolin Chen static const struct snd_soc_codec_driver cs42xx8_driver = { 4050c516b4fSNicolin Chen .probe = cs42xx8_codec_probe, 4060c516b4fSNicolin Chen .idle_bias_off = true, 4070c516b4fSNicolin Chen 4080c516b4fSNicolin Chen .controls = cs42xx8_snd_controls, 4090c516b4fSNicolin Chen .num_controls = ARRAY_SIZE(cs42xx8_snd_controls), 4100c516b4fSNicolin Chen .dapm_widgets = cs42xx8_dapm_widgets, 4110c516b4fSNicolin Chen .num_dapm_widgets = ARRAY_SIZE(cs42xx8_dapm_widgets), 4120c516b4fSNicolin Chen .dapm_routes = cs42xx8_dapm_routes, 4130c516b4fSNicolin Chen .num_dapm_routes = ARRAY_SIZE(cs42xx8_dapm_routes), 4140c516b4fSNicolin Chen }; 4150c516b4fSNicolin Chen 4160c516b4fSNicolin Chen const struct cs42xx8_driver_data cs42448_data = { 4170c516b4fSNicolin Chen .name = "cs42448", 4180c516b4fSNicolin Chen .num_adcs = 3, 4190c516b4fSNicolin Chen }; 4200c516b4fSNicolin Chen EXPORT_SYMBOL_GPL(cs42448_data); 4210c516b4fSNicolin Chen 4220c516b4fSNicolin Chen const struct cs42xx8_driver_data cs42888_data = { 4230c516b4fSNicolin Chen .name = "cs42888", 4240c516b4fSNicolin Chen .num_adcs = 2, 4250c516b4fSNicolin Chen }; 4260c516b4fSNicolin Chen EXPORT_SYMBOL_GPL(cs42888_data); 4270c516b4fSNicolin Chen 428afb7bb45SLars-Peter Clausen static const struct of_device_id cs42xx8_of_match[] = { 4290c516b4fSNicolin Chen { .compatible = "cirrus,cs42448", .data = &cs42448_data, }, 4300c516b4fSNicolin Chen { .compatible = "cirrus,cs42888", .data = &cs42888_data, }, 4310c516b4fSNicolin Chen { /* sentinel */ } 4320c516b4fSNicolin Chen }; 4330c516b4fSNicolin Chen MODULE_DEVICE_TABLE(of, cs42xx8_of_match); 4340c516b4fSNicolin Chen EXPORT_SYMBOL_GPL(cs42xx8_of_match); 4350c516b4fSNicolin Chen 4360c516b4fSNicolin Chen int cs42xx8_probe(struct device *dev, struct regmap *regmap) 4370c516b4fSNicolin Chen { 4380c516b4fSNicolin Chen const struct of_device_id *of_id = of_match_device(cs42xx8_of_match, dev); 4390c516b4fSNicolin Chen struct cs42xx8_priv *cs42xx8; 4400c516b4fSNicolin Chen int ret, val, i; 4410c516b4fSNicolin Chen 4420c516b4fSNicolin Chen cs42xx8 = devm_kzalloc(dev, sizeof(*cs42xx8), GFP_KERNEL); 4430c516b4fSNicolin Chen if (cs42xx8 == NULL) 4440c516b4fSNicolin Chen return -ENOMEM; 4450c516b4fSNicolin Chen 4460c516b4fSNicolin Chen dev_set_drvdata(dev, cs42xx8); 4470c516b4fSNicolin Chen 4480c516b4fSNicolin Chen if (of_id) 4490c516b4fSNicolin Chen cs42xx8->drvdata = of_id->data; 4500c516b4fSNicolin Chen 4510c516b4fSNicolin Chen if (!cs42xx8->drvdata) { 4520c516b4fSNicolin Chen dev_err(dev, "failed to find driver data\n"); 4530c516b4fSNicolin Chen return -EINVAL; 4540c516b4fSNicolin Chen } 4550c516b4fSNicolin Chen 4560c516b4fSNicolin Chen cs42xx8->clk = devm_clk_get(dev, "mclk"); 4570c516b4fSNicolin Chen if (IS_ERR(cs42xx8->clk)) { 4580c516b4fSNicolin Chen dev_err(dev, "failed to get the clock: %ld\n", 4590c516b4fSNicolin Chen PTR_ERR(cs42xx8->clk)); 4600c516b4fSNicolin Chen return -EINVAL; 4610c516b4fSNicolin Chen } 4620c516b4fSNicolin Chen 4630c516b4fSNicolin Chen cs42xx8->sysclk = clk_get_rate(cs42xx8->clk); 4640c516b4fSNicolin Chen 4650c516b4fSNicolin Chen for (i = 0; i < ARRAY_SIZE(cs42xx8->supplies); i++) 4660c516b4fSNicolin Chen cs42xx8->supplies[i].supply = cs42xx8_supply_names[i]; 4670c516b4fSNicolin Chen 4680c516b4fSNicolin Chen ret = devm_regulator_bulk_get(dev, 4690c516b4fSNicolin Chen ARRAY_SIZE(cs42xx8->supplies), cs42xx8->supplies); 4700c516b4fSNicolin Chen if (ret) { 4710c516b4fSNicolin Chen dev_err(dev, "failed to request supplies: %d\n", ret); 4720c516b4fSNicolin Chen return ret; 4730c516b4fSNicolin Chen } 4740c516b4fSNicolin Chen 4750c516b4fSNicolin Chen ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies), 4760c516b4fSNicolin Chen cs42xx8->supplies); 4770c516b4fSNicolin Chen if (ret) { 4780c516b4fSNicolin Chen dev_err(dev, "failed to enable supplies: %d\n", ret); 4790c516b4fSNicolin Chen return ret; 4800c516b4fSNicolin Chen } 4810c516b4fSNicolin Chen 4820c516b4fSNicolin Chen /* Make sure hardware reset done */ 4830c516b4fSNicolin Chen msleep(5); 4840c516b4fSNicolin Chen 4850c516b4fSNicolin Chen cs42xx8->regmap = regmap; 4860c516b4fSNicolin Chen if (IS_ERR(cs42xx8->regmap)) { 4870c516b4fSNicolin Chen ret = PTR_ERR(cs42xx8->regmap); 4880c516b4fSNicolin Chen dev_err(dev, "failed to allocate regmap: %d\n", ret); 4890c516b4fSNicolin Chen goto err_enable; 4900c516b4fSNicolin Chen } 4910c516b4fSNicolin Chen 4920c516b4fSNicolin Chen /* 4930c516b4fSNicolin Chen * We haven't marked the chip revision as volatile due to 4940c516b4fSNicolin Chen * sharing a register with the right input volume; explicitly 4950c516b4fSNicolin Chen * bypass the cache to read it. 4960c516b4fSNicolin Chen */ 4970c516b4fSNicolin Chen regcache_cache_bypass(cs42xx8->regmap, true); 4980c516b4fSNicolin Chen 4990c516b4fSNicolin Chen /* Validate the chip ID */ 50006b4b813SAxel Lin ret = regmap_read(cs42xx8->regmap, CS42XX8_CHIPID, &val); 50106b4b813SAxel Lin if (ret < 0) { 50206b4b813SAxel Lin dev_err(dev, "failed to get device ID, ret = %d", ret); 5030c516b4fSNicolin Chen goto err_enable; 5040c516b4fSNicolin Chen } 5050c516b4fSNicolin Chen 5060c516b4fSNicolin Chen /* The top four bits of the chip ID should be 0000 */ 50706b4b813SAxel Lin if (((val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4) != 0x00) { 5080c516b4fSNicolin Chen dev_err(dev, "unmatched chip ID: %d\n", 50906b4b813SAxel Lin (val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4); 5100c516b4fSNicolin Chen ret = -EINVAL; 5110c516b4fSNicolin Chen goto err_enable; 5120c516b4fSNicolin Chen } 5130c516b4fSNicolin Chen 5140c516b4fSNicolin Chen dev_info(dev, "found device, revision %X\n", 5150c516b4fSNicolin Chen val & CS42XX8_CHIPID_REV_ID_MASK); 5160c516b4fSNicolin Chen 5170c516b4fSNicolin Chen regcache_cache_bypass(cs42xx8->regmap, false); 5180c516b4fSNicolin Chen 5190c516b4fSNicolin Chen cs42xx8_dai.name = cs42xx8->drvdata->name; 5200c516b4fSNicolin Chen 5210c516b4fSNicolin Chen /* Each adc supports stereo input */ 5220c516b4fSNicolin Chen cs42xx8_dai.capture.channels_max = cs42xx8->drvdata->num_adcs * 2; 5230c516b4fSNicolin Chen 5240c516b4fSNicolin Chen ret = snd_soc_register_codec(dev, &cs42xx8_driver, &cs42xx8_dai, 1); 5250c516b4fSNicolin Chen if (ret) { 5260c516b4fSNicolin Chen dev_err(dev, "failed to register codec:%d\n", ret); 5270c516b4fSNicolin Chen goto err_enable; 5280c516b4fSNicolin Chen } 5290c516b4fSNicolin Chen 5300c516b4fSNicolin Chen regcache_cache_only(cs42xx8->regmap, true); 5310c516b4fSNicolin Chen 5320c516b4fSNicolin Chen err_enable: 5330c516b4fSNicolin Chen regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies), 5340c516b4fSNicolin Chen cs42xx8->supplies); 5350c516b4fSNicolin Chen 5360c516b4fSNicolin Chen return ret; 5370c516b4fSNicolin Chen } 5380c516b4fSNicolin Chen EXPORT_SYMBOL_GPL(cs42xx8_probe); 5390c516b4fSNicolin Chen 540*641d334bSRafael J. Wysocki #ifdef CONFIG_PM 5410c516b4fSNicolin Chen static int cs42xx8_runtime_resume(struct device *dev) 5420c516b4fSNicolin Chen { 5430c516b4fSNicolin Chen struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev); 5440c516b4fSNicolin Chen int ret; 5450c516b4fSNicolin Chen 5460c516b4fSNicolin Chen ret = clk_prepare_enable(cs42xx8->clk); 5470c516b4fSNicolin Chen if (ret) { 5480c516b4fSNicolin Chen dev_err(dev, "failed to enable mclk: %d\n", ret); 5490c516b4fSNicolin Chen return ret; 5500c516b4fSNicolin Chen } 5510c516b4fSNicolin Chen 5520c516b4fSNicolin Chen ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies), 5530c516b4fSNicolin Chen cs42xx8->supplies); 5540c516b4fSNicolin Chen if (ret) { 5550c516b4fSNicolin Chen dev_err(dev, "failed to enable supplies: %d\n", ret); 5560c516b4fSNicolin Chen goto err_clk; 5570c516b4fSNicolin Chen } 5580c516b4fSNicolin Chen 5590c516b4fSNicolin Chen /* Make sure hardware reset done */ 5600c516b4fSNicolin Chen msleep(5); 5610c516b4fSNicolin Chen 5620c516b4fSNicolin Chen regcache_cache_only(cs42xx8->regmap, false); 5630c516b4fSNicolin Chen 5640c516b4fSNicolin Chen ret = regcache_sync(cs42xx8->regmap); 5650c516b4fSNicolin Chen if (ret) { 5660c516b4fSNicolin Chen dev_err(dev, "failed to sync regmap: %d\n", ret); 5670c516b4fSNicolin Chen goto err_bulk; 5680c516b4fSNicolin Chen } 5690c516b4fSNicolin Chen 5700c516b4fSNicolin Chen return 0; 5710c516b4fSNicolin Chen 5720c516b4fSNicolin Chen err_bulk: 5730c516b4fSNicolin Chen regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies), 5740c516b4fSNicolin Chen cs42xx8->supplies); 5750c516b4fSNicolin Chen err_clk: 5760c516b4fSNicolin Chen clk_disable_unprepare(cs42xx8->clk); 5770c516b4fSNicolin Chen 5780c516b4fSNicolin Chen return ret; 5790c516b4fSNicolin Chen } 5800c516b4fSNicolin Chen 5810c516b4fSNicolin Chen static int cs42xx8_runtime_suspend(struct device *dev) 5820c516b4fSNicolin Chen { 5830c516b4fSNicolin Chen struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev); 5840c516b4fSNicolin Chen 5850c516b4fSNicolin Chen regcache_cache_only(cs42xx8->regmap, true); 5860c516b4fSNicolin Chen 5870c516b4fSNicolin Chen regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies), 5880c516b4fSNicolin Chen cs42xx8->supplies); 5890c516b4fSNicolin Chen 5900c516b4fSNicolin Chen clk_disable_unprepare(cs42xx8->clk); 5910c516b4fSNicolin Chen 5920c516b4fSNicolin Chen return 0; 5930c516b4fSNicolin Chen } 5940c516b4fSNicolin Chen #endif 5950c516b4fSNicolin Chen 5960c516b4fSNicolin Chen const struct dev_pm_ops cs42xx8_pm = { 5970c516b4fSNicolin Chen SET_RUNTIME_PM_OPS(cs42xx8_runtime_suspend, cs42xx8_runtime_resume, NULL) 5980c516b4fSNicolin Chen }; 5990c516b4fSNicolin Chen EXPORT_SYMBOL_GPL(cs42xx8_pm); 6000c516b4fSNicolin Chen 6010c516b4fSNicolin Chen MODULE_DESCRIPTION("Cirrus Logic CS42448/CS42888 ALSA SoC Codec Driver"); 6020c516b4fSNicolin Chen MODULE_AUTHOR("Freescale Semiconductor, Inc."); 6030c516b4fSNicolin Chen MODULE_LICENSE("GPL"); 604