1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l42.c -- CS42L42 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/version.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/i2c.h> 19 #include <linux/gpio.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <linux/acpi.h> 23 #include <linux/platform_device.h> 24 #include <linux/property.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/gpio/consumer.h> 27 #include <linux/of_device.h> 28 #include <linux/pm_runtime.h> 29 #include <sound/core.h> 30 #include <sound/pcm.h> 31 #include <sound/pcm_params.h> 32 #include <sound/soc.h> 33 #include <sound/soc-dapm.h> 34 #include <sound/initval.h> 35 #include <sound/tlv.h> 36 #include <dt-bindings/sound/cs42l42.h> 37 38 #include "cs42l42.h" 39 #include "cirrus_legacy.h" 40 41 static const struct reg_default cs42l42_reg_defaults[] = { 42 { CS42L42_FRZ_CTL, 0x00 }, 43 { CS42L42_SRC_CTL, 0x10 }, 44 { CS42L42_MCLK_STATUS, 0x02 }, 45 { CS42L42_MCLK_CTL, 0x02 }, 46 { CS42L42_SFTRAMP_RATE, 0xA4 }, 47 { CS42L42_I2C_DEBOUNCE, 0x88 }, 48 { CS42L42_I2C_STRETCH, 0x03 }, 49 { CS42L42_I2C_TIMEOUT, 0xB7 }, 50 { CS42L42_PWR_CTL1, 0xFF }, 51 { CS42L42_PWR_CTL2, 0x84 }, 52 { CS42L42_PWR_CTL3, 0x20 }, 53 { CS42L42_RSENSE_CTL1, 0x40 }, 54 { CS42L42_RSENSE_CTL2, 0x00 }, 55 { CS42L42_OSC_SWITCH, 0x00 }, 56 { CS42L42_OSC_SWITCH_STATUS, 0x05 }, 57 { CS42L42_RSENSE_CTL3, 0x1B }, 58 { CS42L42_TSENSE_CTL, 0x1B }, 59 { CS42L42_TSRS_INT_DISABLE, 0x00 }, 60 { CS42L42_TRSENSE_STATUS, 0x00 }, 61 { CS42L42_HSDET_CTL1, 0x77 }, 62 { CS42L42_HSDET_CTL2, 0x00 }, 63 { CS42L42_HS_SWITCH_CTL, 0xF3 }, 64 { CS42L42_HS_DET_STATUS, 0x00 }, 65 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 66 { CS42L42_MCLK_SRC_SEL, 0x00 }, 67 { CS42L42_SPDIF_CLK_CFG, 0x00 }, 68 { CS42L42_FSYNC_PW_LOWER, 0x00 }, 69 { CS42L42_FSYNC_PW_UPPER, 0x00 }, 70 { CS42L42_FSYNC_P_LOWER, 0xF9 }, 71 { CS42L42_FSYNC_P_UPPER, 0x00 }, 72 { CS42L42_ASP_CLK_CFG, 0x00 }, 73 { CS42L42_ASP_FRM_CFG, 0x10 }, 74 { CS42L42_FS_RATE_EN, 0x00 }, 75 { CS42L42_IN_ASRC_CLK, 0x00 }, 76 { CS42L42_OUT_ASRC_CLK, 0x00 }, 77 { CS42L42_PLL_DIV_CFG1, 0x00 }, 78 { CS42L42_ADC_OVFL_STATUS, 0x00 }, 79 { CS42L42_MIXER_STATUS, 0x00 }, 80 { CS42L42_SRC_STATUS, 0x00 }, 81 { CS42L42_ASP_RX_STATUS, 0x00 }, 82 { CS42L42_ASP_TX_STATUS, 0x00 }, 83 { CS42L42_CODEC_STATUS, 0x00 }, 84 { CS42L42_DET_INT_STATUS1, 0x00 }, 85 { CS42L42_DET_INT_STATUS2, 0x00 }, 86 { CS42L42_SRCPL_INT_STATUS, 0x00 }, 87 { CS42L42_VPMON_STATUS, 0x00 }, 88 { CS42L42_PLL_LOCK_STATUS, 0x00 }, 89 { CS42L42_TSRS_PLUG_STATUS, 0x00 }, 90 { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, 91 { CS42L42_MIXER_INT_MASK, 0x0F }, 92 { CS42L42_SRC_INT_MASK, 0x0F }, 93 { CS42L42_ASP_RX_INT_MASK, 0x1F }, 94 { CS42L42_ASP_TX_INT_MASK, 0x0F }, 95 { CS42L42_CODEC_INT_MASK, 0x03 }, 96 { CS42L42_SRCPL_INT_MASK, 0xFF }, 97 { CS42L42_VPMON_INT_MASK, 0x01 }, 98 { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, 99 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, 100 { CS42L42_PLL_CTL1, 0x00 }, 101 { CS42L42_PLL_DIV_FRAC0, 0x00 }, 102 { CS42L42_PLL_DIV_FRAC1, 0x00 }, 103 { CS42L42_PLL_DIV_FRAC2, 0x00 }, 104 { CS42L42_PLL_DIV_INT, 0x40 }, 105 { CS42L42_PLL_CTL3, 0x10 }, 106 { CS42L42_PLL_CAL_RATIO, 0x80 }, 107 { CS42L42_PLL_CTL4, 0x03 }, 108 { CS42L42_LOAD_DET_RCSTAT, 0x00 }, 109 { CS42L42_LOAD_DET_DONE, 0x00 }, 110 { CS42L42_LOAD_DET_EN, 0x00 }, 111 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, 112 { CS42L42_WAKE_CTL, 0xC0 }, 113 { CS42L42_ADC_DISABLE_MUTE, 0x00 }, 114 { CS42L42_TIPSENSE_CTL, 0x02 }, 115 { CS42L42_MISC_DET_CTL, 0x03 }, 116 { CS42L42_MIC_DET_CTL1, 0x1F }, 117 { CS42L42_MIC_DET_CTL2, 0x2F }, 118 { CS42L42_DET_STATUS1, 0x00 }, 119 { CS42L42_DET_STATUS2, 0x00 }, 120 { CS42L42_DET_INT1_MASK, 0xE0 }, 121 { CS42L42_DET_INT2_MASK, 0xFF }, 122 { CS42L42_HS_BIAS_CTL, 0xC2 }, 123 { CS42L42_ADC_CTL, 0x00 }, 124 { CS42L42_ADC_VOLUME, 0x00 }, 125 { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, 126 { CS42L42_DAC_CTL1, 0x00 }, 127 { CS42L42_DAC_CTL2, 0x02 }, 128 { CS42L42_HP_CTL, 0x0D }, 129 { CS42L42_CLASSH_CTL, 0x07 }, 130 { CS42L42_MIXER_CHA_VOL, 0x3F }, 131 { CS42L42_MIXER_ADC_VOL, 0x3F }, 132 { CS42L42_MIXER_CHB_VOL, 0x3F }, 133 { CS42L42_EQ_COEF_IN0, 0x22 }, 134 { CS42L42_EQ_COEF_IN1, 0x00 }, 135 { CS42L42_EQ_COEF_IN2, 0x00 }, 136 { CS42L42_EQ_COEF_IN3, 0x00 }, 137 { CS42L42_EQ_COEF_RW, 0x00 }, 138 { CS42L42_EQ_COEF_OUT0, 0x00 }, 139 { CS42L42_EQ_COEF_OUT1, 0x00 }, 140 { CS42L42_EQ_COEF_OUT2, 0x00 }, 141 { CS42L42_EQ_COEF_OUT3, 0x00 }, 142 { CS42L42_EQ_INIT_STAT, 0x00 }, 143 { CS42L42_EQ_START_FILT, 0x00 }, 144 { CS42L42_EQ_MUTE_CTL, 0x00 }, 145 { CS42L42_SP_RX_CH_SEL, 0x04 }, 146 { CS42L42_SP_RX_ISOC_CTL, 0x04 }, 147 { CS42L42_SP_RX_FS, 0x8C }, 148 { CS42l42_SPDIF_CH_SEL, 0x0E }, 149 { CS42L42_SP_TX_ISOC_CTL, 0x04 }, 150 { CS42L42_SP_TX_FS, 0xCC }, 151 { CS42L42_SPDIF_SW_CTL1, 0x3F }, 152 { CS42L42_SRC_SDIN_FS, 0x40 }, 153 { CS42L42_SRC_SDOUT_FS, 0x40 }, 154 { CS42L42_SPDIF_CTL1, 0x01 }, 155 { CS42L42_SPDIF_CTL2, 0x00 }, 156 { CS42L42_SPDIF_CTL3, 0x00 }, 157 { CS42L42_SPDIF_CTL4, 0x42 }, 158 { CS42L42_ASP_TX_SZ_EN, 0x00 }, 159 { CS42L42_ASP_TX_CH_EN, 0x00 }, 160 { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, 161 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, 162 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, 163 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, 164 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, 165 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, 166 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 167 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, 168 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, 169 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, 170 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, 171 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, 172 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, 173 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, 174 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, 175 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, 176 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, 177 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, 178 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, 179 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, 180 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, 181 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, 182 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, 183 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, 184 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, 185 { CS42L42_SUB_REVID, 0x03 }, 186 }; 187 188 static bool cs42l42_readable_register(struct device *dev, unsigned int reg) 189 { 190 switch (reg) { 191 case CS42L42_PAGE_REGISTER: 192 case CS42L42_DEVID_AB: 193 case CS42L42_DEVID_CD: 194 case CS42L42_DEVID_E: 195 case CS42L42_FABID: 196 case CS42L42_REVID: 197 case CS42L42_FRZ_CTL: 198 case CS42L42_SRC_CTL: 199 case CS42L42_MCLK_STATUS: 200 case CS42L42_MCLK_CTL: 201 case CS42L42_SFTRAMP_RATE: 202 case CS42L42_I2C_DEBOUNCE: 203 case CS42L42_I2C_STRETCH: 204 case CS42L42_I2C_TIMEOUT: 205 case CS42L42_PWR_CTL1: 206 case CS42L42_PWR_CTL2: 207 case CS42L42_PWR_CTL3: 208 case CS42L42_RSENSE_CTL1: 209 case CS42L42_RSENSE_CTL2: 210 case CS42L42_OSC_SWITCH: 211 case CS42L42_OSC_SWITCH_STATUS: 212 case CS42L42_RSENSE_CTL3: 213 case CS42L42_TSENSE_CTL: 214 case CS42L42_TSRS_INT_DISABLE: 215 case CS42L42_TRSENSE_STATUS: 216 case CS42L42_HSDET_CTL1: 217 case CS42L42_HSDET_CTL2: 218 case CS42L42_HS_SWITCH_CTL: 219 case CS42L42_HS_DET_STATUS: 220 case CS42L42_HS_CLAMP_DISABLE: 221 case CS42L42_MCLK_SRC_SEL: 222 case CS42L42_SPDIF_CLK_CFG: 223 case CS42L42_FSYNC_PW_LOWER: 224 case CS42L42_FSYNC_PW_UPPER: 225 case CS42L42_FSYNC_P_LOWER: 226 case CS42L42_FSYNC_P_UPPER: 227 case CS42L42_ASP_CLK_CFG: 228 case CS42L42_ASP_FRM_CFG: 229 case CS42L42_FS_RATE_EN: 230 case CS42L42_IN_ASRC_CLK: 231 case CS42L42_OUT_ASRC_CLK: 232 case CS42L42_PLL_DIV_CFG1: 233 case CS42L42_ADC_OVFL_STATUS: 234 case CS42L42_MIXER_STATUS: 235 case CS42L42_SRC_STATUS: 236 case CS42L42_ASP_RX_STATUS: 237 case CS42L42_ASP_TX_STATUS: 238 case CS42L42_CODEC_STATUS: 239 case CS42L42_DET_INT_STATUS1: 240 case CS42L42_DET_INT_STATUS2: 241 case CS42L42_SRCPL_INT_STATUS: 242 case CS42L42_VPMON_STATUS: 243 case CS42L42_PLL_LOCK_STATUS: 244 case CS42L42_TSRS_PLUG_STATUS: 245 case CS42L42_ADC_OVFL_INT_MASK: 246 case CS42L42_MIXER_INT_MASK: 247 case CS42L42_SRC_INT_MASK: 248 case CS42L42_ASP_RX_INT_MASK: 249 case CS42L42_ASP_TX_INT_MASK: 250 case CS42L42_CODEC_INT_MASK: 251 case CS42L42_SRCPL_INT_MASK: 252 case CS42L42_VPMON_INT_MASK: 253 case CS42L42_PLL_LOCK_INT_MASK: 254 case CS42L42_TSRS_PLUG_INT_MASK: 255 case CS42L42_PLL_CTL1: 256 case CS42L42_PLL_DIV_FRAC0: 257 case CS42L42_PLL_DIV_FRAC1: 258 case CS42L42_PLL_DIV_FRAC2: 259 case CS42L42_PLL_DIV_INT: 260 case CS42L42_PLL_CTL3: 261 case CS42L42_PLL_CAL_RATIO: 262 case CS42L42_PLL_CTL4: 263 case CS42L42_LOAD_DET_RCSTAT: 264 case CS42L42_LOAD_DET_DONE: 265 case CS42L42_LOAD_DET_EN: 266 case CS42L42_HSBIAS_SC_AUTOCTL: 267 case CS42L42_WAKE_CTL: 268 case CS42L42_ADC_DISABLE_MUTE: 269 case CS42L42_TIPSENSE_CTL: 270 case CS42L42_MISC_DET_CTL: 271 case CS42L42_MIC_DET_CTL1: 272 case CS42L42_MIC_DET_CTL2: 273 case CS42L42_DET_STATUS1: 274 case CS42L42_DET_STATUS2: 275 case CS42L42_DET_INT1_MASK: 276 case CS42L42_DET_INT2_MASK: 277 case CS42L42_HS_BIAS_CTL: 278 case CS42L42_ADC_CTL: 279 case CS42L42_ADC_VOLUME: 280 case CS42L42_ADC_WNF_HPF_CTL: 281 case CS42L42_DAC_CTL1: 282 case CS42L42_DAC_CTL2: 283 case CS42L42_HP_CTL: 284 case CS42L42_CLASSH_CTL: 285 case CS42L42_MIXER_CHA_VOL: 286 case CS42L42_MIXER_ADC_VOL: 287 case CS42L42_MIXER_CHB_VOL: 288 case CS42L42_EQ_COEF_IN0: 289 case CS42L42_EQ_COEF_IN1: 290 case CS42L42_EQ_COEF_IN2: 291 case CS42L42_EQ_COEF_IN3: 292 case CS42L42_EQ_COEF_RW: 293 case CS42L42_EQ_COEF_OUT0: 294 case CS42L42_EQ_COEF_OUT1: 295 case CS42L42_EQ_COEF_OUT2: 296 case CS42L42_EQ_COEF_OUT3: 297 case CS42L42_EQ_INIT_STAT: 298 case CS42L42_EQ_START_FILT: 299 case CS42L42_EQ_MUTE_CTL: 300 case CS42L42_SP_RX_CH_SEL: 301 case CS42L42_SP_RX_ISOC_CTL: 302 case CS42L42_SP_RX_FS: 303 case CS42l42_SPDIF_CH_SEL: 304 case CS42L42_SP_TX_ISOC_CTL: 305 case CS42L42_SP_TX_FS: 306 case CS42L42_SPDIF_SW_CTL1: 307 case CS42L42_SRC_SDIN_FS: 308 case CS42L42_SRC_SDOUT_FS: 309 case CS42L42_SPDIF_CTL1: 310 case CS42L42_SPDIF_CTL2: 311 case CS42L42_SPDIF_CTL3: 312 case CS42L42_SPDIF_CTL4: 313 case CS42L42_ASP_TX_SZ_EN: 314 case CS42L42_ASP_TX_CH_EN: 315 case CS42L42_ASP_TX_CH_AP_RES: 316 case CS42L42_ASP_TX_CH1_BIT_MSB: 317 case CS42L42_ASP_TX_CH1_BIT_LSB: 318 case CS42L42_ASP_TX_HIZ_DLY_CFG: 319 case CS42L42_ASP_TX_CH2_BIT_MSB: 320 case CS42L42_ASP_TX_CH2_BIT_LSB: 321 case CS42L42_ASP_RX_DAI0_EN: 322 case CS42L42_ASP_RX_DAI0_CH1_AP_RES: 323 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: 324 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: 325 case CS42L42_ASP_RX_DAI0_CH2_AP_RES: 326 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: 327 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: 328 case CS42L42_ASP_RX_DAI0_CH3_AP_RES: 329 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: 330 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: 331 case CS42L42_ASP_RX_DAI0_CH4_AP_RES: 332 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: 333 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: 334 case CS42L42_ASP_RX_DAI1_CH1_AP_RES: 335 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: 336 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: 337 case CS42L42_ASP_RX_DAI1_CH2_AP_RES: 338 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: 339 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: 340 case CS42L42_SUB_REVID: 341 return true; 342 default: 343 return false; 344 } 345 } 346 347 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 348 { 349 switch (reg) { 350 case CS42L42_DEVID_AB: 351 case CS42L42_DEVID_CD: 352 case CS42L42_DEVID_E: 353 case CS42L42_MCLK_STATUS: 354 case CS42L42_TRSENSE_STATUS: 355 case CS42L42_HS_DET_STATUS: 356 case CS42L42_ADC_OVFL_STATUS: 357 case CS42L42_MIXER_STATUS: 358 case CS42L42_SRC_STATUS: 359 case CS42L42_ASP_RX_STATUS: 360 case CS42L42_ASP_TX_STATUS: 361 case CS42L42_CODEC_STATUS: 362 case CS42L42_DET_INT_STATUS1: 363 case CS42L42_DET_INT_STATUS2: 364 case CS42L42_SRCPL_INT_STATUS: 365 case CS42L42_VPMON_STATUS: 366 case CS42L42_PLL_LOCK_STATUS: 367 case CS42L42_TSRS_PLUG_STATUS: 368 case CS42L42_LOAD_DET_RCSTAT: 369 case CS42L42_LOAD_DET_DONE: 370 case CS42L42_DET_STATUS1: 371 case CS42L42_DET_STATUS2: 372 return true; 373 default: 374 return false; 375 } 376 } 377 378 static const struct regmap_range_cfg cs42l42_page_range = { 379 .name = "Pages", 380 .range_min = 0, 381 .range_max = CS42L42_MAX_REGISTER, 382 .selector_reg = CS42L42_PAGE_REGISTER, 383 .selector_mask = 0xff, 384 .selector_shift = 0, 385 .window_start = 0, 386 .window_len = 256, 387 }; 388 389 static const struct regmap_config cs42l42_regmap = { 390 .reg_bits = 8, 391 .val_bits = 8, 392 393 .readable_reg = cs42l42_readable_register, 394 .volatile_reg = cs42l42_volatile_register, 395 396 .ranges = &cs42l42_page_range, 397 .num_ranges = 1, 398 399 .max_register = CS42L42_MAX_REGISTER, 400 .reg_defaults = cs42l42_reg_defaults, 401 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), 402 .cache_type = REGCACHE_RBTREE, 403 }; 404 405 static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, false); 406 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true); 407 408 static const char * const cs42l42_hpf_freq_text[] = { 409 "1.86Hz", "120Hz", "235Hz", "466Hz" 410 }; 411 412 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 413 CS42L42_ADC_HPF_CF_SHIFT, 414 cs42l42_hpf_freq_text); 415 416 static const char * const cs42l42_wnf3_freq_text[] = { 417 "160Hz", "180Hz", "200Hz", "220Hz", 418 "240Hz", "260Hz", "280Hz", "300Hz" 419 }; 420 421 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 422 CS42L42_ADC_WNF_CF_SHIFT, 423 cs42l42_wnf3_freq_text); 424 425 static const char * const cs42l42_wnf05_freq_text[] = { 426 "280Hz", "315Hz", "350Hz", "385Hz", 427 "420Hz", "455Hz", "490Hz", "525Hz" 428 }; 429 430 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf05_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 431 CS42L42_ADC_WNF_CF_SHIFT, 432 cs42l42_wnf05_freq_text); 433 434 static const struct snd_kcontrol_new cs42l42_snd_controls[] = { 435 /* ADC Volume and Filter Controls */ 436 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL, 437 CS42L42_ADC_NOTCH_DIS_SHIFT, true, false), 438 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL, 439 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), 440 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL, 441 CS42L42_ADC_INV_SHIFT, true, false), 442 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL, 443 CS42L42_ADC_DIG_BOOST_SHIFT, true, false), 444 SOC_SINGLE_SX_TLV("ADC Volume", CS42L42_ADC_VOLUME, 445 CS42L42_ADC_VOL_SHIFT, 0xA0, 0x6C, adc_tlv), 446 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL, 447 CS42L42_ADC_WNF_EN_SHIFT, true, false), 448 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL, 449 CS42L42_ADC_HPF_EN_SHIFT, true, false), 450 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum), 451 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum), 452 SOC_ENUM("WNF 05dB Freq", cs42l42_wnf05_freq_enum), 453 454 /* DAC Volume and Filter Controls */ 455 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1, 456 CS42L42_DACA_INV_SHIFT, true, false), 457 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1, 458 CS42L42_DACB_INV_SHIFT, true, false), 459 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2, 460 CS42L42_DAC_HPF_EN_SHIFT, true, false), 461 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL, 462 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, 463 0x3f, 1, mixer_tlv) 464 }; 465 466 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { 467 /* Playback Path */ 468 SND_SOC_DAPM_OUTPUT("HP"), 469 SND_SOC_DAPM_DAC("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1), 470 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0), 471 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, CS42L42_ASP_RX_DAI0_EN, CS42L42_ASP_RX0_CH1_SHIFT, 0), 472 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, CS42L42_ASP_RX_DAI0_EN, CS42L42_ASP_RX0_CH2_SHIFT, 0), 473 474 /* Playback Requirements */ 475 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0), 476 477 /* Capture Path */ 478 SND_SOC_DAPM_INPUT("HS"), 479 SND_SOC_DAPM_ADC("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1), 480 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0), 481 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0), 482 483 /* Capture Requirements */ 484 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0), 485 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0), 486 487 /* Playback/Capture Requirements */ 488 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0), 489 }; 490 491 static const struct snd_soc_dapm_route cs42l42_audio_map[] = { 492 /* Playback Path */ 493 {"HP", NULL, "DAC"}, 494 {"DAC", NULL, "MIXER"}, 495 {"MIXER", NULL, "SDIN1"}, 496 {"MIXER", NULL, "SDIN2"}, 497 {"SDIN1", NULL, "Playback"}, 498 {"SDIN2", NULL, "Playback"}, 499 500 /* Playback Requirements */ 501 {"SDIN1", NULL, "ASP DAI0"}, 502 {"SDIN2", NULL, "ASP DAI0"}, 503 {"SDIN1", NULL, "SCLK"}, 504 {"SDIN2", NULL, "SCLK"}, 505 506 /* Capture Path */ 507 {"ADC", NULL, "HS"}, 508 { "SDOUT1", NULL, "ADC" }, 509 { "SDOUT2", NULL, "ADC" }, 510 { "Capture", NULL, "SDOUT1" }, 511 { "Capture", NULL, "SDOUT2" }, 512 513 /* Capture Requirements */ 514 { "SDOUT1", NULL, "ASP DAO0" }, 515 { "SDOUT2", NULL, "ASP DAO0" }, 516 { "SDOUT1", NULL, "SCLK" }, 517 { "SDOUT2", NULL, "SCLK" }, 518 { "SDOUT1", NULL, "ASP TX EN" }, 519 { "SDOUT2", NULL, "ASP TX EN" }, 520 }; 521 522 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d) 523 { 524 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 525 526 cs42l42->jack = jk; 527 528 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 529 CS42L42_RS_PLUG_MASK | CS42L42_RS_UNPLUG_MASK | 530 CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK, 531 (1 << CS42L42_RS_PLUG_SHIFT) | (1 << CS42L42_RS_UNPLUG_SHIFT) | 532 (0 << CS42L42_TS_PLUG_SHIFT) | (0 << CS42L42_TS_UNPLUG_SHIFT)); 533 534 return 0; 535 } 536 537 static int cs42l42_component_probe(struct snd_soc_component *component) 538 { 539 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 540 541 cs42l42->component = component; 542 543 return 0; 544 } 545 546 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = { 547 .probe = cs42l42_component_probe, 548 .set_jack = cs42l42_set_jack, 549 .dapm_widgets = cs42l42_dapm_widgets, 550 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), 551 .dapm_routes = cs42l42_audio_map, 552 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), 553 .controls = cs42l42_snd_controls, 554 .num_controls = ARRAY_SIZE(cs42l42_snd_controls), 555 .idle_bias_on = 1, 556 .endianness = 1, 557 .non_legacy_dai_naming = 1, 558 }; 559 560 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */ 561 static const struct reg_sequence cs42l42_to_sclk_seq[] = { 562 { 563 .reg = CS42L42_OSC_SWITCH, 564 .def = CS42L42_SCLK_PRESENT_MASK, 565 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 566 }, 567 }; 568 569 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */ 570 static const struct reg_sequence cs42l42_to_osc_seq[] = { 571 { 572 .reg = CS42L42_OSC_SWITCH, 573 .def = 0, 574 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 575 }, 576 }; 577 578 struct cs42l42_pll_params { 579 u32 sclk; 580 u8 mclk_div; 581 u8 mclk_src_sel; 582 u8 sclk_prediv; 583 u8 pll_div_int; 584 u32 pll_div_frac; 585 u8 pll_mode; 586 u8 pll_divout; 587 u32 mclk_int; 588 u8 pll_cal_ratio; 589 }; 590 591 /* 592 * Common PLL Settings for given SCLK 593 * Table 4-5 from the Datasheet 594 */ 595 static const struct cs42l42_pll_params pll_ratio_table[] = { 596 { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 }, 597 { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 }, 598 { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 }, 599 { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 }, 600 { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 }, 601 { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 }, 602 { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 }, 603 { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 }, 604 { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 }, 605 { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 }, 606 { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 }, 607 { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 }, 608 { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 }, 609 { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 }, 610 { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 } 611 }; 612 613 static int cs42l42_pll_config(struct snd_soc_component *component) 614 { 615 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 616 int i; 617 u32 clk; 618 u32 fsync; 619 620 if (!cs42l42->sclk) 621 clk = cs42l42->bclk; 622 else 623 clk = cs42l42->sclk; 624 625 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 626 if (pll_ratio_table[i].sclk == clk) { 627 /* Configure the internal sample rate */ 628 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, 629 CS42L42_INTERNAL_FS_MASK, 630 ((pll_ratio_table[i].mclk_int != 631 12000000) && 632 (pll_ratio_table[i].mclk_int != 633 24000000)) << 634 CS42L42_INTERNAL_FS_SHIFT); 635 /* Set the MCLK src (PLL or SCLK) and the divide 636 * ratio 637 */ 638 snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL, 639 CS42L42_MCLK_SRC_SEL_MASK | 640 CS42L42_MCLKDIV_MASK, 641 (pll_ratio_table[i].mclk_src_sel 642 << CS42L42_MCLK_SRC_SEL_SHIFT) | 643 (pll_ratio_table[i].mclk_div << 644 CS42L42_MCLKDIV_SHIFT)); 645 /* Set up the LRCLK */ 646 fsync = clk / cs42l42->srate; 647 if (((fsync * cs42l42->srate) != clk) 648 || ((fsync % 2) != 0)) { 649 dev_err(component->dev, 650 "Unsupported sclk %d/sample rate %d\n", 651 clk, 652 cs42l42->srate); 653 return -EINVAL; 654 } 655 /* Set the LRCLK period */ 656 snd_soc_component_update_bits(component, 657 CS42L42_FSYNC_P_LOWER, 658 CS42L42_FSYNC_PERIOD_MASK, 659 CS42L42_FRAC0_VAL(fsync - 1) << 660 CS42L42_FSYNC_PERIOD_SHIFT); 661 snd_soc_component_update_bits(component, 662 CS42L42_FSYNC_P_UPPER, 663 CS42L42_FSYNC_PERIOD_MASK, 664 CS42L42_FRAC1_VAL(fsync - 1) << 665 CS42L42_FSYNC_PERIOD_SHIFT); 666 /* Set the LRCLK to 50% duty cycle */ 667 fsync = fsync / 2; 668 snd_soc_component_update_bits(component, 669 CS42L42_FSYNC_PW_LOWER, 670 CS42L42_FSYNC_PULSE_WIDTH_MASK, 671 CS42L42_FRAC0_VAL(fsync - 1) << 672 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 673 snd_soc_component_update_bits(component, 674 CS42L42_FSYNC_PW_UPPER, 675 CS42L42_FSYNC_PULSE_WIDTH_MASK, 676 CS42L42_FRAC1_VAL(fsync - 1) << 677 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 678 snd_soc_component_update_bits(component, 679 CS42L42_ASP_FRM_CFG, 680 CS42L42_ASP_5050_MASK, 681 CS42L42_ASP_5050_MASK); 682 /* Set the frame delay to 1.0 SCLK clocks */ 683 snd_soc_component_update_bits(component, CS42L42_ASP_FRM_CFG, 684 CS42L42_ASP_FSD_MASK, 685 CS42L42_ASP_FSD_1_0 << 686 CS42L42_ASP_FSD_SHIFT); 687 /* Set the sample rates (96k or lower) */ 688 snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN, 689 CS42L42_FS_EN_MASK, 690 (CS42L42_FS_EN_IASRC_96K | 691 CS42L42_FS_EN_OASRC_96K) << 692 CS42L42_FS_EN_SHIFT); 693 /* Set the input/output internal MCLK clock ~12 MHz */ 694 snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK, 695 CS42L42_CLK_IASRC_SEL_MASK, 696 CS42L42_CLK_IASRC_SEL_12 << 697 CS42L42_CLK_IASRC_SEL_SHIFT); 698 snd_soc_component_update_bits(component, 699 CS42L42_OUT_ASRC_CLK, 700 CS42L42_CLK_OASRC_SEL_MASK, 701 CS42L42_CLK_OASRC_SEL_12 << 702 CS42L42_CLK_OASRC_SEL_SHIFT); 703 if (pll_ratio_table[i].mclk_src_sel == 0) { 704 /* Pass the clock straight through */ 705 snd_soc_component_update_bits(component, 706 CS42L42_PLL_CTL1, 707 CS42L42_PLL_START_MASK, 0); 708 } else { 709 /* Configure PLL per table 4-5 */ 710 snd_soc_component_update_bits(component, 711 CS42L42_PLL_DIV_CFG1, 712 CS42L42_SCLK_PREDIV_MASK, 713 pll_ratio_table[i].sclk_prediv 714 << CS42L42_SCLK_PREDIV_SHIFT); 715 snd_soc_component_update_bits(component, 716 CS42L42_PLL_DIV_INT, 717 CS42L42_PLL_DIV_INT_MASK, 718 pll_ratio_table[i].pll_div_int 719 << CS42L42_PLL_DIV_INT_SHIFT); 720 snd_soc_component_update_bits(component, 721 CS42L42_PLL_DIV_FRAC0, 722 CS42L42_PLL_DIV_FRAC_MASK, 723 CS42L42_FRAC0_VAL( 724 pll_ratio_table[i].pll_div_frac) 725 << CS42L42_PLL_DIV_FRAC_SHIFT); 726 snd_soc_component_update_bits(component, 727 CS42L42_PLL_DIV_FRAC1, 728 CS42L42_PLL_DIV_FRAC_MASK, 729 CS42L42_FRAC1_VAL( 730 pll_ratio_table[i].pll_div_frac) 731 << CS42L42_PLL_DIV_FRAC_SHIFT); 732 snd_soc_component_update_bits(component, 733 CS42L42_PLL_DIV_FRAC2, 734 CS42L42_PLL_DIV_FRAC_MASK, 735 CS42L42_FRAC2_VAL( 736 pll_ratio_table[i].pll_div_frac) 737 << CS42L42_PLL_DIV_FRAC_SHIFT); 738 snd_soc_component_update_bits(component, 739 CS42L42_PLL_CTL4, 740 CS42L42_PLL_MODE_MASK, 741 pll_ratio_table[i].pll_mode 742 << CS42L42_PLL_MODE_SHIFT); 743 snd_soc_component_update_bits(component, 744 CS42L42_PLL_CTL3, 745 CS42L42_PLL_DIVOUT_MASK, 746 pll_ratio_table[i].pll_divout 747 << CS42L42_PLL_DIVOUT_SHIFT); 748 snd_soc_component_update_bits(component, 749 CS42L42_PLL_CAL_RATIO, 750 CS42L42_PLL_CAL_RATIO_MASK, 751 pll_ratio_table[i].pll_cal_ratio 752 << CS42L42_PLL_CAL_RATIO_SHIFT); 753 } 754 return 0; 755 } 756 } 757 758 return -EINVAL; 759 } 760 761 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 762 { 763 struct snd_soc_component *component = codec_dai->component; 764 u32 asp_cfg_val = 0; 765 766 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 767 case SND_SOC_DAIFMT_CBS_CFM: 768 asp_cfg_val |= CS42L42_ASP_MASTER_MODE << 769 CS42L42_ASP_MODE_SHIFT; 770 break; 771 case SND_SOC_DAIFMT_CBS_CFS: 772 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << 773 CS42L42_ASP_MODE_SHIFT; 774 break; 775 default: 776 return -EINVAL; 777 } 778 779 /* interface format */ 780 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 781 case SND_SOC_DAIFMT_I2S: 782 case SND_SOC_DAIFMT_LEFT_J: 783 break; 784 default: 785 return -EINVAL; 786 } 787 788 /* Bitclock/frame inversion */ 789 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 790 case SND_SOC_DAIFMT_NB_NF: 791 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 792 break; 793 case SND_SOC_DAIFMT_NB_IF: 794 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 795 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 796 break; 797 case SND_SOC_DAIFMT_IB_NF: 798 break; 799 case SND_SOC_DAIFMT_IB_IF: 800 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 801 break; 802 } 803 804 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK | 805 CS42L42_ASP_SCPOL_MASK | 806 CS42L42_ASP_LCPOL_MASK, 807 asp_cfg_val); 808 809 return 0; 810 } 811 812 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, 813 struct snd_pcm_hw_params *params, 814 struct snd_soc_dai *dai) 815 { 816 struct snd_soc_component *component = dai->component; 817 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 818 unsigned int channels = params_channels(params); 819 unsigned int width = (params_width(params) / 8) - 1; 820 unsigned int val = 0; 821 822 cs42l42->srate = params_rate(params); 823 cs42l42->bclk = snd_soc_params_to_bclk(params); 824 825 switch(substream->stream) { 826 case SNDRV_PCM_STREAM_CAPTURE: 827 if (channels == 2) { 828 val |= CS42L42_ASP_TX_CH2_AP_MASK; 829 val |= width << CS42L42_ASP_TX_CH2_RES_SHIFT; 830 } 831 val |= width << CS42L42_ASP_TX_CH1_RES_SHIFT; 832 833 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES, 834 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK | 835 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val); 836 break; 837 case SNDRV_PCM_STREAM_PLAYBACK: 838 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT; 839 /* channel 1 on low LRCLK */ 840 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES, 841 CS42L42_ASP_RX_CH_AP_MASK | 842 CS42L42_ASP_RX_CH_RES_MASK, val); 843 /* Channel 2 on high LRCLK */ 844 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT; 845 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES, 846 CS42L42_ASP_RX_CH_AP_MASK | 847 CS42L42_ASP_RX_CH_RES_MASK, val); 848 break; 849 default: 850 break; 851 } 852 853 return cs42l42_pll_config(component); 854 } 855 856 static int cs42l42_set_sysclk(struct snd_soc_dai *dai, 857 int clk_id, unsigned int freq, int dir) 858 { 859 struct snd_soc_component *component = dai->component; 860 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 861 862 cs42l42->sclk = freq; 863 864 return 0; 865 } 866 867 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 868 { 869 struct snd_soc_component *component = dai->component; 870 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 871 unsigned int regval; 872 u8 fullScaleVol; 873 int ret; 874 875 if (mute) { 876 /* Mute the headphone */ 877 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 878 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 879 CS42L42_HP_ANA_AMUTE_MASK | 880 CS42L42_HP_ANA_BMUTE_MASK, 881 CS42L42_HP_ANA_AMUTE_MASK | 882 CS42L42_HP_ANA_BMUTE_MASK); 883 884 cs42l42->stream_use &= ~(1 << stream); 885 if(!cs42l42->stream_use) { 886 /* 887 * Switch to the internal oscillator. 888 * SCLK must remain running until after this clock switch. 889 * Without a source of clock the I2C bus doesn't work. 890 */ 891 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq, 892 ARRAY_SIZE(cs42l42_to_osc_seq)); 893 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 894 CS42L42_PLL_START_MASK, 0); 895 } 896 } else { 897 if (!cs42l42->stream_use) { 898 /* SCLK must be running before codec unmute */ 899 if ((cs42l42->bclk < 11289600) && (cs42l42->sclk < 11289600)) { 900 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 901 CS42L42_PLL_START_MASK, 1); 902 ret = regmap_read_poll_timeout(cs42l42->regmap, 903 CS42L42_PLL_LOCK_STATUS, 904 regval, 905 (regval & 1), 906 CS42L42_PLL_LOCK_POLL_US, 907 CS42L42_PLL_LOCK_TIMEOUT_US); 908 if (ret < 0) 909 dev_warn(component->dev, "PLL failed to lock: %d\n", ret); 910 } 911 912 /* Mark SCLK as present, turn off internal oscillator */ 913 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq, 914 ARRAY_SIZE(cs42l42_to_sclk_seq)); 915 } 916 cs42l42->stream_use |= 1 << stream; 917 918 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 919 /* Read the headphone load */ 920 regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT); 921 if (((regval & CS42L42_RLA_STAT_MASK) >> CS42L42_RLA_STAT_SHIFT) == 922 CS42L42_RLA_STAT_15_OHM) { 923 fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK; 924 } else { 925 fullScaleVol = 0; 926 } 927 928 /* Un-mute the headphone, set the full scale volume flag */ 929 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 930 CS42L42_HP_ANA_AMUTE_MASK | 931 CS42L42_HP_ANA_BMUTE_MASK | 932 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol); 933 } 934 } 935 936 return 0; 937 } 938 939 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 940 SNDRV_PCM_FMTBIT_S24_LE |\ 941 SNDRV_PCM_FMTBIT_S32_LE ) 942 943 944 static const struct snd_soc_dai_ops cs42l42_ops = { 945 .hw_params = cs42l42_pcm_hw_params, 946 .set_fmt = cs42l42_set_dai_fmt, 947 .set_sysclk = cs42l42_set_sysclk, 948 .mute_stream = cs42l42_mute_stream, 949 }; 950 951 static struct snd_soc_dai_driver cs42l42_dai = { 952 .name = "cs42l42", 953 .playback = { 954 .stream_name = "Playback", 955 .channels_min = 1, 956 .channels_max = 2, 957 .rates = SNDRV_PCM_RATE_8000_192000, 958 .formats = CS42L42_FORMATS, 959 }, 960 .capture = { 961 .stream_name = "Capture", 962 .channels_min = 1, 963 .channels_max = 2, 964 .rates = SNDRV_PCM_RATE_8000_192000, 965 .formats = CS42L42_FORMATS, 966 }, 967 .symmetric_rate = 1, 968 .symmetric_sample_bits = 1, 969 .ops = &cs42l42_ops, 970 }; 971 972 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) 973 { 974 unsigned int hs_det_status; 975 unsigned int int_status; 976 977 /* Mask the auto detect interrupt */ 978 regmap_update_bits(cs42l42->regmap, 979 CS42L42_CODEC_INT_MASK, 980 CS42L42_PDN_DONE_MASK | 981 CS42L42_HSDET_AUTO_DONE_MASK, 982 (1 << CS42L42_PDN_DONE_SHIFT) | 983 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 984 985 /* Set hs detect to automatic, disabled mode */ 986 regmap_update_bits(cs42l42->regmap, 987 CS42L42_HSDET_CTL2, 988 CS42L42_HSDET_CTRL_MASK | 989 CS42L42_HSDET_SET_MASK | 990 CS42L42_HSBIAS_REF_MASK | 991 CS42L42_HSDET_AUTO_TIME_MASK, 992 (2 << CS42L42_HSDET_CTRL_SHIFT) | 993 (2 << CS42L42_HSDET_SET_SHIFT) | 994 (0 << CS42L42_HSBIAS_REF_SHIFT) | 995 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 996 997 /* Read and save the hs detection result */ 998 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 999 1000 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> 1001 CS42L42_HSDET_TYPE_SHIFT; 1002 1003 /* Set up button detection */ 1004 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || 1005 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { 1006 /* Set auto HS bias settings to default */ 1007 regmap_update_bits(cs42l42->regmap, 1008 CS42L42_HSBIAS_SC_AUTOCTL, 1009 CS42L42_HSBIAS_SENSE_EN_MASK | 1010 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1011 CS42L42_TIP_SENSE_EN_MASK | 1012 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1013 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1014 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1015 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1016 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1017 1018 /* Set up hs detect level sensitivity */ 1019 regmap_update_bits(cs42l42->regmap, 1020 CS42L42_MIC_DET_CTL1, 1021 CS42L42_LATCH_TO_VP_MASK | 1022 CS42L42_EVENT_STAT_SEL_MASK | 1023 CS42L42_HS_DET_LEVEL_MASK, 1024 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1025 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1026 (cs42l42->bias_thresholds[0] << 1027 CS42L42_HS_DET_LEVEL_SHIFT)); 1028 1029 /* Set auto HS bias settings to default */ 1030 regmap_update_bits(cs42l42->regmap, 1031 CS42L42_HSBIAS_SC_AUTOCTL, 1032 CS42L42_HSBIAS_SENSE_EN_MASK | 1033 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1034 CS42L42_TIP_SENSE_EN_MASK | 1035 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1036 (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1037 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1038 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1039 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1040 1041 /* Turn on level detect circuitry */ 1042 regmap_update_bits(cs42l42->regmap, 1043 CS42L42_MISC_DET_CTL, 1044 CS42L42_DETECT_MODE_MASK | 1045 CS42L42_HSBIAS_CTL_MASK | 1046 CS42L42_PDN_MIC_LVL_DET_MASK, 1047 (0 << CS42L42_DETECT_MODE_SHIFT) | 1048 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1049 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1050 1051 msleep(cs42l42->btn_det_init_dbnce); 1052 1053 /* Clear any button interrupts before unmasking them */ 1054 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1055 &int_status); 1056 1057 /* Unmask button detect interrupts */ 1058 regmap_update_bits(cs42l42->regmap, 1059 CS42L42_DET_INT2_MASK, 1060 CS42L42_M_DETECT_TF_MASK | 1061 CS42L42_M_DETECT_FT_MASK | 1062 CS42L42_M_HSBIAS_HIZ_MASK | 1063 CS42L42_M_SHORT_RLS_MASK | 1064 CS42L42_M_SHORT_DET_MASK, 1065 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1066 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1067 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1068 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1069 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1070 } else { 1071 /* Make sure button detect and HS bias circuits are off */ 1072 regmap_update_bits(cs42l42->regmap, 1073 CS42L42_MISC_DET_CTL, 1074 CS42L42_DETECT_MODE_MASK | 1075 CS42L42_HSBIAS_CTL_MASK | 1076 CS42L42_PDN_MIC_LVL_DET_MASK, 1077 (0 << CS42L42_DETECT_MODE_SHIFT) | 1078 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1079 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1080 } 1081 1082 regmap_update_bits(cs42l42->regmap, 1083 CS42L42_DAC_CTL2, 1084 CS42L42_HPOUT_PULLDOWN_MASK | 1085 CS42L42_HPOUT_LOAD_MASK | 1086 CS42L42_HPOUT_CLAMP_MASK | 1087 CS42L42_DAC_HPF_EN_MASK | 1088 CS42L42_DAC_MON_EN_MASK, 1089 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1090 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1091 (0 << CS42L42_HPOUT_CLAMP_SHIFT) | 1092 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1093 (0 << CS42L42_DAC_MON_EN_SHIFT)); 1094 1095 /* Unmask tip sense interrupts */ 1096 regmap_update_bits(cs42l42->regmap, 1097 CS42L42_TSRS_PLUG_INT_MASK, 1098 CS42L42_RS_PLUG_MASK | 1099 CS42L42_RS_UNPLUG_MASK | 1100 CS42L42_TS_PLUG_MASK | 1101 CS42L42_TS_UNPLUG_MASK, 1102 (1 << CS42L42_RS_PLUG_SHIFT) | 1103 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1104 (0 << CS42L42_TS_PLUG_SHIFT) | 1105 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1106 } 1107 1108 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) 1109 { 1110 /* Mask tip sense interrupts */ 1111 regmap_update_bits(cs42l42->regmap, 1112 CS42L42_TSRS_PLUG_INT_MASK, 1113 CS42L42_RS_PLUG_MASK | 1114 CS42L42_RS_UNPLUG_MASK | 1115 CS42L42_TS_PLUG_MASK | 1116 CS42L42_TS_UNPLUG_MASK, 1117 (1 << CS42L42_RS_PLUG_SHIFT) | 1118 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1119 (1 << CS42L42_TS_PLUG_SHIFT) | 1120 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1121 1122 /* Make sure button detect and HS bias circuits are off */ 1123 regmap_update_bits(cs42l42->regmap, 1124 CS42L42_MISC_DET_CTL, 1125 CS42L42_DETECT_MODE_MASK | 1126 CS42L42_HSBIAS_CTL_MASK | 1127 CS42L42_PDN_MIC_LVL_DET_MASK, 1128 (0 << CS42L42_DETECT_MODE_SHIFT) | 1129 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1130 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1131 1132 /* Set auto HS bias settings to default */ 1133 regmap_update_bits(cs42l42->regmap, 1134 CS42L42_HSBIAS_SC_AUTOCTL, 1135 CS42L42_HSBIAS_SENSE_EN_MASK | 1136 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1137 CS42L42_TIP_SENSE_EN_MASK | 1138 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1139 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1140 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1141 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1142 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1143 1144 /* Set hs detect to manual, disabled mode */ 1145 regmap_update_bits(cs42l42->regmap, 1146 CS42L42_HSDET_CTL2, 1147 CS42L42_HSDET_CTRL_MASK | 1148 CS42L42_HSDET_SET_MASK | 1149 CS42L42_HSBIAS_REF_MASK | 1150 CS42L42_HSDET_AUTO_TIME_MASK, 1151 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1152 (2 << CS42L42_HSDET_SET_SHIFT) | 1153 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1154 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1155 1156 regmap_update_bits(cs42l42->regmap, 1157 CS42L42_DAC_CTL2, 1158 CS42L42_HPOUT_PULLDOWN_MASK | 1159 CS42L42_HPOUT_LOAD_MASK | 1160 CS42L42_HPOUT_CLAMP_MASK | 1161 CS42L42_DAC_HPF_EN_MASK | 1162 CS42L42_DAC_MON_EN_MASK, 1163 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1164 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1165 (1 << CS42L42_HPOUT_CLAMP_SHIFT) | 1166 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1167 (1 << CS42L42_DAC_MON_EN_SHIFT)); 1168 1169 /* Power up HS bias to 2.7V */ 1170 regmap_update_bits(cs42l42->regmap, 1171 CS42L42_MISC_DET_CTL, 1172 CS42L42_DETECT_MODE_MASK | 1173 CS42L42_HSBIAS_CTL_MASK | 1174 CS42L42_PDN_MIC_LVL_DET_MASK, 1175 (0 << CS42L42_DETECT_MODE_SHIFT) | 1176 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1177 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1178 1179 /* Wait for HS bias to ramp up */ 1180 msleep(cs42l42->hs_bias_ramp_time); 1181 1182 /* Unmask auto detect interrupt */ 1183 regmap_update_bits(cs42l42->regmap, 1184 CS42L42_CODEC_INT_MASK, 1185 CS42L42_PDN_DONE_MASK | 1186 CS42L42_HSDET_AUTO_DONE_MASK, 1187 (1 << CS42L42_PDN_DONE_SHIFT) | 1188 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1189 1190 /* Set hs detect to automatic, enabled mode */ 1191 regmap_update_bits(cs42l42->regmap, 1192 CS42L42_HSDET_CTL2, 1193 CS42L42_HSDET_CTRL_MASK | 1194 CS42L42_HSDET_SET_MASK | 1195 CS42L42_HSBIAS_REF_MASK | 1196 CS42L42_HSDET_AUTO_TIME_MASK, 1197 (3 << CS42L42_HSDET_CTRL_SHIFT) | 1198 (2 << CS42L42_HSDET_SET_SHIFT) | 1199 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1200 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1201 } 1202 1203 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) 1204 { 1205 /* Mask button detect interrupts */ 1206 regmap_update_bits(cs42l42->regmap, 1207 CS42L42_DET_INT2_MASK, 1208 CS42L42_M_DETECT_TF_MASK | 1209 CS42L42_M_DETECT_FT_MASK | 1210 CS42L42_M_HSBIAS_HIZ_MASK | 1211 CS42L42_M_SHORT_RLS_MASK | 1212 CS42L42_M_SHORT_DET_MASK, 1213 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1214 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1215 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1216 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1217 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1218 1219 /* Ground HS bias */ 1220 regmap_update_bits(cs42l42->regmap, 1221 CS42L42_MISC_DET_CTL, 1222 CS42L42_DETECT_MODE_MASK | 1223 CS42L42_HSBIAS_CTL_MASK | 1224 CS42L42_PDN_MIC_LVL_DET_MASK, 1225 (0 << CS42L42_DETECT_MODE_SHIFT) | 1226 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1227 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1228 1229 /* Set auto HS bias settings to default */ 1230 regmap_update_bits(cs42l42->regmap, 1231 CS42L42_HSBIAS_SC_AUTOCTL, 1232 CS42L42_HSBIAS_SENSE_EN_MASK | 1233 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1234 CS42L42_TIP_SENSE_EN_MASK | 1235 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1236 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1237 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1238 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1239 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1240 1241 /* Set hs detect to manual, disabled mode */ 1242 regmap_update_bits(cs42l42->regmap, 1243 CS42L42_HSDET_CTL2, 1244 CS42L42_HSDET_CTRL_MASK | 1245 CS42L42_HSDET_SET_MASK | 1246 CS42L42_HSBIAS_REF_MASK | 1247 CS42L42_HSDET_AUTO_TIME_MASK, 1248 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1249 (2 << CS42L42_HSDET_SET_SHIFT) | 1250 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1251 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1252 } 1253 1254 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42) 1255 { 1256 int bias_level; 1257 unsigned int detect_status; 1258 1259 /* Mask button detect interrupts */ 1260 regmap_update_bits(cs42l42->regmap, 1261 CS42L42_DET_INT2_MASK, 1262 CS42L42_M_DETECT_TF_MASK | 1263 CS42L42_M_DETECT_FT_MASK | 1264 CS42L42_M_HSBIAS_HIZ_MASK | 1265 CS42L42_M_SHORT_RLS_MASK | 1266 CS42L42_M_SHORT_DET_MASK, 1267 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1268 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1269 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1270 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1271 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1272 1273 usleep_range(cs42l42->btn_det_event_dbnce * 1000, 1274 cs42l42->btn_det_event_dbnce * 2000); 1275 1276 /* Test all 4 level detect biases */ 1277 bias_level = 1; 1278 do { 1279 /* Adjust button detect level sensitivity */ 1280 regmap_update_bits(cs42l42->regmap, 1281 CS42L42_MIC_DET_CTL1, 1282 CS42L42_LATCH_TO_VP_MASK | 1283 CS42L42_EVENT_STAT_SEL_MASK | 1284 CS42L42_HS_DET_LEVEL_MASK, 1285 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1286 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1287 (cs42l42->bias_thresholds[bias_level] << 1288 CS42L42_HS_DET_LEVEL_SHIFT)); 1289 1290 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2, 1291 &detect_status); 1292 } while ((detect_status & CS42L42_HS_TRUE_MASK) && 1293 (++bias_level < CS42L42_NUM_BIASES)); 1294 1295 switch (bias_level) { 1296 case 1: /* Function C button press */ 1297 bias_level = SND_JACK_BTN_2; 1298 dev_dbg(cs42l42->component->dev, "Function C button press\n"); 1299 break; 1300 case 2: /* Function B button press */ 1301 bias_level = SND_JACK_BTN_1; 1302 dev_dbg(cs42l42->component->dev, "Function B button press\n"); 1303 break; 1304 case 3: /* Function D button press */ 1305 bias_level = SND_JACK_BTN_3; 1306 dev_dbg(cs42l42->component->dev, "Function D button press\n"); 1307 break; 1308 case 4: /* Function A button press */ 1309 bias_level = SND_JACK_BTN_0; 1310 dev_dbg(cs42l42->component->dev, "Function A button press\n"); 1311 break; 1312 default: 1313 bias_level = 0; 1314 break; 1315 } 1316 1317 /* Set button detect level sensitivity back to default */ 1318 regmap_update_bits(cs42l42->regmap, 1319 CS42L42_MIC_DET_CTL1, 1320 CS42L42_LATCH_TO_VP_MASK | 1321 CS42L42_EVENT_STAT_SEL_MASK | 1322 CS42L42_HS_DET_LEVEL_MASK, 1323 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1324 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1325 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); 1326 1327 /* Clear any button interrupts before unmasking them */ 1328 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1329 &detect_status); 1330 1331 /* Unmask button detect interrupts */ 1332 regmap_update_bits(cs42l42->regmap, 1333 CS42L42_DET_INT2_MASK, 1334 CS42L42_M_DETECT_TF_MASK | 1335 CS42L42_M_DETECT_FT_MASK | 1336 CS42L42_M_HSBIAS_HIZ_MASK | 1337 CS42L42_M_SHORT_RLS_MASK | 1338 CS42L42_M_SHORT_DET_MASK, 1339 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1340 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1341 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1342 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1343 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1344 1345 return bias_level; 1346 } 1347 1348 struct cs42l42_irq_params { 1349 u16 status_addr; 1350 u16 mask_addr; 1351 u8 mask; 1352 }; 1353 1354 static const struct cs42l42_irq_params irq_params_table[] = { 1355 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, 1356 CS42L42_ADC_OVFL_VAL_MASK}, 1357 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, 1358 CS42L42_MIXER_VAL_MASK}, 1359 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, 1360 CS42L42_SRC_VAL_MASK}, 1361 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, 1362 CS42L42_ASP_RX_VAL_MASK}, 1363 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, 1364 CS42L42_ASP_TX_VAL_MASK}, 1365 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, 1366 CS42L42_CODEC_VAL_MASK}, 1367 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, 1368 CS42L42_DET_INT_VAL1_MASK}, 1369 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, 1370 CS42L42_DET_INT_VAL2_MASK}, 1371 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, 1372 CS42L42_SRCPL_VAL_MASK}, 1373 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, 1374 CS42L42_VPMON_VAL_MASK}, 1375 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, 1376 CS42L42_PLL_LOCK_VAL_MASK}, 1377 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, 1378 CS42L42_TSRS_PLUG_VAL_MASK} 1379 }; 1380 1381 static irqreturn_t cs42l42_irq_thread(int irq, void *data) 1382 { 1383 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; 1384 struct snd_soc_component *component = cs42l42->component; 1385 unsigned int stickies[12]; 1386 unsigned int masks[12]; 1387 unsigned int current_plug_status; 1388 unsigned int current_button_status; 1389 unsigned int i; 1390 int report = 0; 1391 1392 1393 /* Read sticky registers to clear interurpt */ 1394 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 1395 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr, 1396 &(stickies[i])); 1397 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr, 1398 &(masks[i])); 1399 stickies[i] = stickies[i] & (~masks[i]) & 1400 irq_params_table[i].mask; 1401 } 1402 1403 /* Read tip sense status before handling type detect */ 1404 current_plug_status = (stickies[11] & 1405 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1406 CS42L42_TS_PLUG_SHIFT; 1407 1408 /* Read button sense status */ 1409 current_button_status = stickies[7] & 1410 (CS42L42_M_DETECT_TF_MASK | 1411 CS42L42_M_DETECT_FT_MASK | 1412 CS42L42_M_HSBIAS_HIZ_MASK); 1413 1414 /* Check auto-detect status */ 1415 if ((~masks[5]) & irq_params_table[5].mask) { 1416 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { 1417 cs42l42_process_hs_type_detect(cs42l42); 1418 switch(cs42l42->hs_type){ 1419 case CS42L42_PLUG_CTIA: 1420 case CS42L42_PLUG_OMTP: 1421 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET, 1422 SND_JACK_HEADSET); 1423 break; 1424 case CS42L42_PLUG_HEADPHONE: 1425 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE, 1426 SND_JACK_HEADPHONE); 1427 break; 1428 default: 1429 break; 1430 } 1431 dev_dbg(component->dev, "Auto detect done (%d)\n", cs42l42->hs_type); 1432 } 1433 } 1434 1435 /* Check tip sense status */ 1436 if ((~masks[11]) & irq_params_table[11].mask) { 1437 switch (current_plug_status) { 1438 case CS42L42_TS_PLUG: 1439 if (cs42l42->plug_state != CS42L42_TS_PLUG) { 1440 cs42l42->plug_state = CS42L42_TS_PLUG; 1441 cs42l42_init_hs_type_detect(cs42l42); 1442 } 1443 break; 1444 1445 case CS42L42_TS_UNPLUG: 1446 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { 1447 cs42l42->plug_state = CS42L42_TS_UNPLUG; 1448 cs42l42_cancel_hs_type_detect(cs42l42); 1449 1450 switch(cs42l42->hs_type){ 1451 case CS42L42_PLUG_CTIA: 1452 case CS42L42_PLUG_OMTP: 1453 snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADSET); 1454 break; 1455 case CS42L42_PLUG_HEADPHONE: 1456 snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADPHONE); 1457 break; 1458 default: 1459 break; 1460 } 1461 dev_dbg(component->dev, "Unplug event\n"); 1462 } 1463 break; 1464 1465 default: 1466 if (cs42l42->plug_state != CS42L42_TS_TRANS) 1467 cs42l42->plug_state = CS42L42_TS_TRANS; 1468 } 1469 } 1470 1471 /* Check button detect status */ 1472 if ((~masks[7]) & irq_params_table[7].mask) { 1473 if (!(current_button_status & 1474 CS42L42_M_HSBIAS_HIZ_MASK)) { 1475 1476 if (current_button_status & CS42L42_M_DETECT_TF_MASK) { 1477 dev_dbg(component->dev, "Button released\n"); 1478 report = 0; 1479 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) { 1480 report = cs42l42_handle_button_press(cs42l42); 1481 1482 } 1483 snd_soc_jack_report(cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1484 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1485 } 1486 } 1487 1488 return IRQ_HANDLED; 1489 } 1490 1491 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) 1492 { 1493 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, 1494 CS42L42_ADC_OVFL_MASK, 1495 (1 << CS42L42_ADC_OVFL_SHIFT)); 1496 1497 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK, 1498 CS42L42_MIX_CHB_OVFL_MASK | 1499 CS42L42_MIX_CHA_OVFL_MASK | 1500 CS42L42_EQ_OVFL_MASK | 1501 CS42L42_EQ_BIQUAD_OVFL_MASK, 1502 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | 1503 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | 1504 (1 << CS42L42_EQ_OVFL_SHIFT) | 1505 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); 1506 1507 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK, 1508 CS42L42_SRC_ILK_MASK | 1509 CS42L42_SRC_OLK_MASK | 1510 CS42L42_SRC_IUNLK_MASK | 1511 CS42L42_SRC_OUNLK_MASK, 1512 (1 << CS42L42_SRC_ILK_SHIFT) | 1513 (1 << CS42L42_SRC_OLK_SHIFT) | 1514 (1 << CS42L42_SRC_IUNLK_SHIFT) | 1515 (1 << CS42L42_SRC_OUNLK_SHIFT)); 1516 1517 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, 1518 CS42L42_ASPRX_NOLRCK_MASK | 1519 CS42L42_ASPRX_EARLY_MASK | 1520 CS42L42_ASPRX_LATE_MASK | 1521 CS42L42_ASPRX_ERROR_MASK | 1522 CS42L42_ASPRX_OVLD_MASK, 1523 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | 1524 (1 << CS42L42_ASPRX_EARLY_SHIFT) | 1525 (1 << CS42L42_ASPRX_LATE_SHIFT) | 1526 (1 << CS42L42_ASPRX_ERROR_SHIFT) | 1527 (1 << CS42L42_ASPRX_OVLD_SHIFT)); 1528 1529 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, 1530 CS42L42_ASPTX_NOLRCK_MASK | 1531 CS42L42_ASPTX_EARLY_MASK | 1532 CS42L42_ASPTX_LATE_MASK | 1533 CS42L42_ASPTX_SMERROR_MASK, 1534 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | 1535 (1 << CS42L42_ASPTX_EARLY_SHIFT) | 1536 (1 << CS42L42_ASPTX_LATE_SHIFT) | 1537 (1 << CS42L42_ASPTX_SMERROR_SHIFT)); 1538 1539 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 1540 CS42L42_PDN_DONE_MASK | 1541 CS42L42_HSDET_AUTO_DONE_MASK, 1542 (1 << CS42L42_PDN_DONE_SHIFT) | 1543 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1544 1545 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK, 1546 CS42L42_SRCPL_ADC_LK_MASK | 1547 CS42L42_SRCPL_DAC_LK_MASK | 1548 CS42L42_SRCPL_ADC_UNLK_MASK | 1549 CS42L42_SRCPL_DAC_UNLK_MASK, 1550 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | 1551 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | 1552 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | 1553 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); 1554 1555 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK, 1556 CS42L42_TIP_SENSE_UNPLUG_MASK | 1557 CS42L42_TIP_SENSE_PLUG_MASK | 1558 CS42L42_HSBIAS_SENSE_MASK, 1559 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | 1560 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | 1561 (1 << CS42L42_HSBIAS_SENSE_SHIFT)); 1562 1563 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK, 1564 CS42L42_M_DETECT_TF_MASK | 1565 CS42L42_M_DETECT_FT_MASK | 1566 CS42L42_M_HSBIAS_HIZ_MASK | 1567 CS42L42_M_SHORT_RLS_MASK | 1568 CS42L42_M_SHORT_DET_MASK, 1569 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1570 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1571 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1572 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1573 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1574 1575 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK, 1576 CS42L42_VPMON_MASK, 1577 (1 << CS42L42_VPMON_SHIFT)); 1578 1579 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, 1580 CS42L42_PLL_LOCK_MASK, 1581 (1 << CS42L42_PLL_LOCK_SHIFT)); 1582 1583 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 1584 CS42L42_RS_PLUG_MASK | 1585 CS42L42_RS_UNPLUG_MASK | 1586 CS42L42_TS_PLUG_MASK | 1587 CS42L42_TS_UNPLUG_MASK, 1588 (1 << CS42L42_RS_PLUG_SHIFT) | 1589 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1590 (1 << CS42L42_TS_PLUG_SHIFT) | 1591 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1592 } 1593 1594 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) 1595 { 1596 unsigned int reg; 1597 1598 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1599 1600 /* Latch analog controls to VP power domain */ 1601 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1, 1602 CS42L42_LATCH_TO_VP_MASK | 1603 CS42L42_EVENT_STAT_SEL_MASK | 1604 CS42L42_HS_DET_LEVEL_MASK, 1605 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1606 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1607 (cs42l42->bias_thresholds[0] << 1608 CS42L42_HS_DET_LEVEL_SHIFT)); 1609 1610 /* Remove ground noise-suppression clamps */ 1611 regmap_update_bits(cs42l42->regmap, 1612 CS42L42_HS_CLAMP_DISABLE, 1613 CS42L42_HS_CLAMP_DISABLE_MASK, 1614 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); 1615 1616 /* Enable the tip sense circuit */ 1617 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL, 1618 CS42L42_TIP_SENSE_CTRL_MASK | 1619 CS42L42_TIP_SENSE_INV_MASK | 1620 CS42L42_TIP_SENSE_DEBOUNCE_MASK, 1621 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | 1622 (0 << CS42L42_TIP_SENSE_INV_SHIFT) | 1623 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); 1624 1625 /* Save the initial status of the tip sense */ 1626 regmap_read(cs42l42->regmap, 1627 CS42L42_TSRS_PLUG_STATUS, 1628 ®); 1629 cs42l42->plug_state = (((char) reg) & 1630 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1631 CS42L42_TS_PLUG_SHIFT; 1632 } 1633 1634 static const unsigned int threshold_defaults[] = { 1635 CS42L42_HS_DET_LEVEL_15, 1636 CS42L42_HS_DET_LEVEL_8, 1637 CS42L42_HS_DET_LEVEL_4, 1638 CS42L42_HS_DET_LEVEL_1 1639 }; 1640 1641 static int cs42l42_handle_device_data(struct device *dev, 1642 struct cs42l42_private *cs42l42) 1643 { 1644 unsigned int val; 1645 u32 thresholds[CS42L42_NUM_BIASES]; 1646 int ret; 1647 int i; 1648 1649 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val); 1650 if (!ret) { 1651 switch (val) { 1652 case CS42L42_TS_INV_EN: 1653 case CS42L42_TS_INV_DIS: 1654 cs42l42->ts_inv = val; 1655 break; 1656 default: 1657 dev_err(dev, 1658 "Wrong cirrus,ts-inv DT value %d\n", 1659 val); 1660 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1661 } 1662 } else { 1663 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1664 } 1665 1666 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1667 CS42L42_TS_INV_MASK, 1668 (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT)); 1669 1670 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val); 1671 if (!ret) { 1672 switch (val) { 1673 case CS42L42_TS_DBNCE_0: 1674 case CS42L42_TS_DBNCE_125: 1675 case CS42L42_TS_DBNCE_250: 1676 case CS42L42_TS_DBNCE_500: 1677 case CS42L42_TS_DBNCE_750: 1678 case CS42L42_TS_DBNCE_1000: 1679 case CS42L42_TS_DBNCE_1250: 1680 case CS42L42_TS_DBNCE_1500: 1681 cs42l42->ts_dbnc_rise = val; 1682 break; 1683 default: 1684 dev_err(dev, 1685 "Wrong cirrus,ts-dbnc-rise DT value %d\n", 1686 val); 1687 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1688 } 1689 } else { 1690 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1691 } 1692 1693 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1694 CS42L42_TS_RISE_DBNCE_TIME_MASK, 1695 (cs42l42->ts_dbnc_rise << 1696 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); 1697 1698 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val); 1699 if (!ret) { 1700 switch (val) { 1701 case CS42L42_TS_DBNCE_0: 1702 case CS42L42_TS_DBNCE_125: 1703 case CS42L42_TS_DBNCE_250: 1704 case CS42L42_TS_DBNCE_500: 1705 case CS42L42_TS_DBNCE_750: 1706 case CS42L42_TS_DBNCE_1000: 1707 case CS42L42_TS_DBNCE_1250: 1708 case CS42L42_TS_DBNCE_1500: 1709 cs42l42->ts_dbnc_fall = val; 1710 break; 1711 default: 1712 dev_err(dev, 1713 "Wrong cirrus,ts-dbnc-fall DT value %d\n", 1714 val); 1715 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1716 } 1717 } else { 1718 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1719 } 1720 1721 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1722 CS42L42_TS_FALL_DBNCE_TIME_MASK, 1723 (cs42l42->ts_dbnc_fall << 1724 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); 1725 1726 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val); 1727 if (!ret) { 1728 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) 1729 cs42l42->btn_det_init_dbnce = val; 1730 else { 1731 dev_err(dev, 1732 "Wrong cirrus,btn-det-init-dbnce DT value %d\n", 1733 val); 1734 cs42l42->btn_det_init_dbnce = 1735 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1736 } 1737 } else { 1738 cs42l42->btn_det_init_dbnce = 1739 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1740 } 1741 1742 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val); 1743 if (!ret) { 1744 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) 1745 cs42l42->btn_det_event_dbnce = val; 1746 else { 1747 dev_err(dev, 1748 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); 1749 cs42l42->btn_det_event_dbnce = 1750 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1751 } 1752 } else { 1753 cs42l42->btn_det_event_dbnce = 1754 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1755 } 1756 1757 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls", 1758 thresholds, ARRAY_SIZE(thresholds)); 1759 if (!ret) { 1760 for (i = 0; i < CS42L42_NUM_BIASES; i++) { 1761 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) 1762 cs42l42->bias_thresholds[i] = thresholds[i]; 1763 else { 1764 dev_err(dev, 1765 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i, 1766 thresholds[i]); 1767 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 1768 } 1769 } 1770 } else { 1771 for (i = 0; i < CS42L42_NUM_BIASES; i++) 1772 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 1773 } 1774 1775 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val); 1776 if (!ret) { 1777 switch (val) { 1778 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: 1779 cs42l42->hs_bias_ramp_rate = val; 1780 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; 1781 break; 1782 case CS42L42_HSBIAS_RAMP_FAST: 1783 cs42l42->hs_bias_ramp_rate = val; 1784 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; 1785 break; 1786 case CS42L42_HSBIAS_RAMP_SLOW: 1787 cs42l42->hs_bias_ramp_rate = val; 1788 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1789 break; 1790 case CS42L42_HSBIAS_RAMP_SLOWEST: 1791 cs42l42->hs_bias_ramp_rate = val; 1792 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; 1793 break; 1794 default: 1795 dev_err(dev, 1796 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n", 1797 val); 1798 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 1799 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1800 } 1801 } else { 1802 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 1803 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1804 } 1805 1806 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL, 1807 CS42L42_HSBIAS_RAMP_MASK, 1808 (cs42l42->hs_bias_ramp_rate << 1809 CS42L42_HSBIAS_RAMP_SHIFT)); 1810 1811 if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable")) 1812 cs42l42->hs_bias_sense_en = 0; 1813 else 1814 cs42l42->hs_bias_sense_en = 1; 1815 1816 return 0; 1817 } 1818 1819 static int cs42l42_i2c_probe(struct i2c_client *i2c_client, 1820 const struct i2c_device_id *id) 1821 { 1822 struct cs42l42_private *cs42l42; 1823 int ret, i, devid; 1824 unsigned int reg; 1825 1826 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private), 1827 GFP_KERNEL); 1828 if (!cs42l42) 1829 return -ENOMEM; 1830 1831 i2c_set_clientdata(i2c_client, cs42l42); 1832 1833 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap); 1834 if (IS_ERR(cs42l42->regmap)) { 1835 ret = PTR_ERR(cs42l42->regmap); 1836 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 1837 return ret; 1838 } 1839 1840 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) 1841 cs42l42->supplies[i].supply = cs42l42_supply_names[i]; 1842 1843 ret = devm_regulator_bulk_get(&i2c_client->dev, 1844 ARRAY_SIZE(cs42l42->supplies), 1845 cs42l42->supplies); 1846 if (ret != 0) { 1847 dev_err(&i2c_client->dev, 1848 "Failed to request supplies: %d\n", ret); 1849 return ret; 1850 } 1851 1852 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 1853 cs42l42->supplies); 1854 if (ret != 0) { 1855 dev_err(&i2c_client->dev, 1856 "Failed to enable supplies: %d\n", ret); 1857 return ret; 1858 } 1859 1860 /* Reset the Device */ 1861 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, 1862 "reset", GPIOD_OUT_LOW); 1863 if (IS_ERR(cs42l42->reset_gpio)) { 1864 ret = PTR_ERR(cs42l42->reset_gpio); 1865 goto err_disable; 1866 } 1867 1868 if (cs42l42->reset_gpio) { 1869 dev_dbg(&i2c_client->dev, "Found reset GPIO\n"); 1870 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 1871 } 1872 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 1873 1874 /* Request IRQ */ 1875 ret = devm_request_threaded_irq(&i2c_client->dev, 1876 i2c_client->irq, 1877 NULL, cs42l42_irq_thread, 1878 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 1879 "cs42l42", cs42l42); 1880 1881 if (ret != 0) 1882 dev_err(&i2c_client->dev, 1883 "Failed to request IRQ: %d\n", ret); 1884 1885 /* initialize codec */ 1886 devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB); 1887 if (devid < 0) { 1888 ret = devid; 1889 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret); 1890 goto err_disable; 1891 } 1892 1893 if (devid != CS42L42_CHIP_ID) { 1894 ret = -ENODEV; 1895 dev_err(&i2c_client->dev, 1896 "CS42L42 Device ID (%X). Expected %X\n", 1897 devid, CS42L42_CHIP_ID); 1898 goto err_disable; 1899 } 1900 1901 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); 1902 if (ret < 0) { 1903 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 1904 goto err_disable; 1905 } 1906 1907 dev_info(&i2c_client->dev, 1908 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF); 1909 1910 /* Power up the codec */ 1911 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1, 1912 CS42L42_ASP_DAO_PDN_MASK | 1913 CS42L42_ASP_DAI_PDN_MASK | 1914 CS42L42_MIXER_PDN_MASK | 1915 CS42L42_EQ_PDN_MASK | 1916 CS42L42_HP_PDN_MASK | 1917 CS42L42_ADC_PDN_MASK | 1918 CS42L42_PDN_ALL_MASK, 1919 (1 << CS42L42_ASP_DAO_PDN_SHIFT) | 1920 (1 << CS42L42_ASP_DAI_PDN_SHIFT) | 1921 (1 << CS42L42_MIXER_PDN_SHIFT) | 1922 (1 << CS42L42_EQ_PDN_SHIFT) | 1923 (1 << CS42L42_HP_PDN_SHIFT) | 1924 (1 << CS42L42_ADC_PDN_SHIFT) | 1925 (0 << CS42L42_PDN_ALL_SHIFT)); 1926 1927 ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42); 1928 if (ret != 0) 1929 goto err_disable; 1930 1931 /* Setup headset detection */ 1932 cs42l42_setup_hs_type_detect(cs42l42); 1933 1934 /* Mask/Unmask Interrupts */ 1935 cs42l42_set_interrupt_masks(cs42l42); 1936 1937 /* Register codec for machine driver */ 1938 ret = devm_snd_soc_register_component(&i2c_client->dev, 1939 &soc_component_dev_cs42l42, &cs42l42_dai, 1); 1940 if (ret < 0) 1941 goto err_disable; 1942 return 0; 1943 1944 err_disable: 1945 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 1946 cs42l42->supplies); 1947 return ret; 1948 } 1949 1950 static int cs42l42_i2c_remove(struct i2c_client *i2c_client) 1951 { 1952 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client); 1953 1954 devm_free_irq(&i2c_client->dev, i2c_client->irq, cs42l42); 1955 pm_runtime_suspend(&i2c_client->dev); 1956 pm_runtime_disable(&i2c_client->dev); 1957 1958 return 0; 1959 } 1960 1961 #ifdef CONFIG_PM 1962 static int cs42l42_runtime_suspend(struct device *dev) 1963 { 1964 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 1965 1966 regcache_cache_only(cs42l42->regmap, true); 1967 regcache_mark_dirty(cs42l42->regmap); 1968 1969 /* Hold down reset */ 1970 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 1971 1972 /* remove power */ 1973 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 1974 cs42l42->supplies); 1975 1976 return 0; 1977 } 1978 1979 static int cs42l42_runtime_resume(struct device *dev) 1980 { 1981 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 1982 int ret; 1983 1984 /* Enable power */ 1985 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 1986 cs42l42->supplies); 1987 if (ret != 0) { 1988 dev_err(dev, "Failed to enable supplies: %d\n", 1989 ret); 1990 return ret; 1991 } 1992 1993 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 1994 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 1995 1996 regcache_cache_only(cs42l42->regmap, false); 1997 regcache_sync(cs42l42->regmap); 1998 1999 return 0; 2000 } 2001 #endif 2002 2003 static const struct dev_pm_ops cs42l42_runtime_pm = { 2004 SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume, 2005 NULL) 2006 }; 2007 2008 #ifdef CONFIG_OF 2009 static const struct of_device_id cs42l42_of_match[] = { 2010 { .compatible = "cirrus,cs42l42", }, 2011 {} 2012 }; 2013 MODULE_DEVICE_TABLE(of, cs42l42_of_match); 2014 #endif 2015 2016 #ifdef CONFIG_ACPI 2017 static const struct acpi_device_id cs42l42_acpi_match[] = { 2018 {"10134242", 0,}, 2019 {} 2020 }; 2021 MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match); 2022 #endif 2023 2024 static const struct i2c_device_id cs42l42_id[] = { 2025 {"cs42l42", 0}, 2026 {} 2027 }; 2028 2029 MODULE_DEVICE_TABLE(i2c, cs42l42_id); 2030 2031 static struct i2c_driver cs42l42_i2c_driver = { 2032 .driver = { 2033 .name = "cs42l42", 2034 .pm = &cs42l42_runtime_pm, 2035 .of_match_table = of_match_ptr(cs42l42_of_match), 2036 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match), 2037 }, 2038 .id_table = cs42l42_id, 2039 .probe = cs42l42_i2c_probe, 2040 .remove = cs42l42_i2c_remove, 2041 }; 2042 2043 module_i2c_driver(cs42l42_i2c_driver); 2044 2045 MODULE_DESCRIPTION("ASoC CS42L42 driver"); 2046 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 2047 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 2048 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>"); 2049 MODULE_LICENSE("GPL"); 2050