1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l42.c -- CS42L42 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/version.h> 15 #include <linux/types.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/gpio.h> 19 #include <linux/regmap.h> 20 #include <linux/slab.h> 21 #include <linux/acpi.h> 22 #include <linux/platform_device.h> 23 #include <linux/property.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/of_device.h> 27 #include <sound/core.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/soc-dapm.h> 32 #include <sound/initval.h> 33 #include <sound/tlv.h> 34 #include <dt-bindings/sound/cs42l42.h> 35 36 #include "cs42l42.h" 37 #include "cirrus_legacy.h" 38 39 static const char * const cs42l42_supply_names[] = { 40 "VA", 41 "VP", 42 "VCP", 43 "VD_FILT", 44 "VL", 45 }; 46 47 static const struct reg_default cs42l42_reg_defaults[] = { 48 { CS42L42_FRZ_CTL, 0x00 }, 49 { CS42L42_SRC_CTL, 0x10 }, 50 { CS42L42_MCLK_CTL, 0x02 }, 51 { CS42L42_SFTRAMP_RATE, 0xA4 }, 52 { CS42L42_SLOW_START_ENABLE, 0x70 }, 53 { CS42L42_I2C_DEBOUNCE, 0x88 }, 54 { CS42L42_I2C_STRETCH, 0x03 }, 55 { CS42L42_I2C_TIMEOUT, 0xB7 }, 56 { CS42L42_PWR_CTL1, 0xFF }, 57 { CS42L42_PWR_CTL2, 0x84 }, 58 { CS42L42_PWR_CTL3, 0x20 }, 59 { CS42L42_RSENSE_CTL1, 0x40 }, 60 { CS42L42_RSENSE_CTL2, 0x00 }, 61 { CS42L42_OSC_SWITCH, 0x00 }, 62 { CS42L42_RSENSE_CTL3, 0x1B }, 63 { CS42L42_TSENSE_CTL, 0x1B }, 64 { CS42L42_TSRS_INT_DISABLE, 0x00 }, 65 { CS42L42_HSDET_CTL1, 0x77 }, 66 { CS42L42_HSDET_CTL2, 0x00 }, 67 { CS42L42_HS_SWITCH_CTL, 0xF3 }, 68 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 69 { CS42L42_MCLK_SRC_SEL, 0x00 }, 70 { CS42L42_SPDIF_CLK_CFG, 0x00 }, 71 { CS42L42_FSYNC_PW_LOWER, 0x00 }, 72 { CS42L42_FSYNC_PW_UPPER, 0x00 }, 73 { CS42L42_FSYNC_P_LOWER, 0xF9 }, 74 { CS42L42_FSYNC_P_UPPER, 0x00 }, 75 { CS42L42_ASP_CLK_CFG, 0x00 }, 76 { CS42L42_ASP_FRM_CFG, 0x10 }, 77 { CS42L42_FS_RATE_EN, 0x00 }, 78 { CS42L42_IN_ASRC_CLK, 0x00 }, 79 { CS42L42_OUT_ASRC_CLK, 0x00 }, 80 { CS42L42_PLL_DIV_CFG1, 0x00 }, 81 { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, 82 { CS42L42_MIXER_INT_MASK, 0x0F }, 83 { CS42L42_SRC_INT_MASK, 0x0F }, 84 { CS42L42_ASP_RX_INT_MASK, 0x1F }, 85 { CS42L42_ASP_TX_INT_MASK, 0x0F }, 86 { CS42L42_CODEC_INT_MASK, 0x03 }, 87 { CS42L42_SRCPL_INT_MASK, 0x7F }, 88 { CS42L42_VPMON_INT_MASK, 0x01 }, 89 { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, 90 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, 91 { CS42L42_PLL_CTL1, 0x00 }, 92 { CS42L42_PLL_DIV_FRAC0, 0x00 }, 93 { CS42L42_PLL_DIV_FRAC1, 0x00 }, 94 { CS42L42_PLL_DIV_FRAC2, 0x00 }, 95 { CS42L42_PLL_DIV_INT, 0x40 }, 96 { CS42L42_PLL_CTL3, 0x10 }, 97 { CS42L42_PLL_CAL_RATIO, 0x80 }, 98 { CS42L42_PLL_CTL4, 0x03 }, 99 { CS42L42_LOAD_DET_EN, 0x00 }, 100 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, 101 { CS42L42_WAKE_CTL, 0xC0 }, 102 { CS42L42_ADC_DISABLE_MUTE, 0x00 }, 103 { CS42L42_TIPSENSE_CTL, 0x02 }, 104 { CS42L42_MISC_DET_CTL, 0x03 }, 105 { CS42L42_MIC_DET_CTL1, 0x1F }, 106 { CS42L42_MIC_DET_CTL2, 0x2F }, 107 { CS42L42_DET_INT1_MASK, 0xE0 }, 108 { CS42L42_DET_INT2_MASK, 0xFF }, 109 { CS42L42_HS_BIAS_CTL, 0xC2 }, 110 { CS42L42_ADC_CTL, 0x00 }, 111 { CS42L42_ADC_VOLUME, 0x00 }, 112 { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, 113 { CS42L42_DAC_CTL1, 0x00 }, 114 { CS42L42_DAC_CTL2, 0x02 }, 115 { CS42L42_HP_CTL, 0x0D }, 116 { CS42L42_CLASSH_CTL, 0x07 }, 117 { CS42L42_MIXER_CHA_VOL, 0x3F }, 118 { CS42L42_MIXER_ADC_VOL, 0x3F }, 119 { CS42L42_MIXER_CHB_VOL, 0x3F }, 120 { CS42L42_EQ_COEF_IN0, 0x00 }, 121 { CS42L42_EQ_COEF_IN1, 0x00 }, 122 { CS42L42_EQ_COEF_IN2, 0x00 }, 123 { CS42L42_EQ_COEF_IN3, 0x00 }, 124 { CS42L42_EQ_COEF_RW, 0x00 }, 125 { CS42L42_EQ_COEF_OUT0, 0x00 }, 126 { CS42L42_EQ_COEF_OUT1, 0x00 }, 127 { CS42L42_EQ_COEF_OUT2, 0x00 }, 128 { CS42L42_EQ_COEF_OUT3, 0x00 }, 129 { CS42L42_EQ_INIT_STAT, 0x00 }, 130 { CS42L42_EQ_START_FILT, 0x00 }, 131 { CS42L42_EQ_MUTE_CTL, 0x00 }, 132 { CS42L42_SP_RX_CH_SEL, 0x04 }, 133 { CS42L42_SP_RX_ISOC_CTL, 0x04 }, 134 { CS42L42_SP_RX_FS, 0x8C }, 135 { CS42l42_SPDIF_CH_SEL, 0x0E }, 136 { CS42L42_SP_TX_ISOC_CTL, 0x04 }, 137 { CS42L42_SP_TX_FS, 0xCC }, 138 { CS42L42_SPDIF_SW_CTL1, 0x3F }, 139 { CS42L42_SRC_SDIN_FS, 0x40 }, 140 { CS42L42_SRC_SDOUT_FS, 0x40 }, 141 { CS42L42_SPDIF_CTL1, 0x01 }, 142 { CS42L42_SPDIF_CTL2, 0x00 }, 143 { CS42L42_SPDIF_CTL3, 0x00 }, 144 { CS42L42_SPDIF_CTL4, 0x42 }, 145 { CS42L42_ASP_TX_SZ_EN, 0x00 }, 146 { CS42L42_ASP_TX_CH_EN, 0x00 }, 147 { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, 148 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, 149 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, 150 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, 151 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, 152 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, 153 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 154 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, 155 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, 156 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, 157 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, 158 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, 159 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, 160 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, 161 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, 162 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, 163 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, 164 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, 165 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, 166 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, 167 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, 168 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, 169 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, 170 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, 171 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, 172 }; 173 174 bool cs42l42_readable_register(struct device *dev, unsigned int reg) 175 { 176 switch (reg) { 177 case CS42L42_PAGE_REGISTER: 178 case CS42L42_DEVID_AB: 179 case CS42L42_DEVID_CD: 180 case CS42L42_DEVID_E: 181 case CS42L42_FABID: 182 case CS42L42_REVID: 183 case CS42L42_FRZ_CTL: 184 case CS42L42_SRC_CTL: 185 case CS42L42_MCLK_STATUS: 186 case CS42L42_MCLK_CTL: 187 case CS42L42_SFTRAMP_RATE: 188 case CS42L42_SLOW_START_ENABLE: 189 case CS42L42_I2C_DEBOUNCE: 190 case CS42L42_I2C_STRETCH: 191 case CS42L42_I2C_TIMEOUT: 192 case CS42L42_PWR_CTL1: 193 case CS42L42_PWR_CTL2: 194 case CS42L42_PWR_CTL3: 195 case CS42L42_RSENSE_CTL1: 196 case CS42L42_RSENSE_CTL2: 197 case CS42L42_OSC_SWITCH: 198 case CS42L42_OSC_SWITCH_STATUS: 199 case CS42L42_RSENSE_CTL3: 200 case CS42L42_TSENSE_CTL: 201 case CS42L42_TSRS_INT_DISABLE: 202 case CS42L42_TRSENSE_STATUS: 203 case CS42L42_HSDET_CTL1: 204 case CS42L42_HSDET_CTL2: 205 case CS42L42_HS_SWITCH_CTL: 206 case CS42L42_HS_DET_STATUS: 207 case CS42L42_HS_CLAMP_DISABLE: 208 case CS42L42_MCLK_SRC_SEL: 209 case CS42L42_SPDIF_CLK_CFG: 210 case CS42L42_FSYNC_PW_LOWER: 211 case CS42L42_FSYNC_PW_UPPER: 212 case CS42L42_FSYNC_P_LOWER: 213 case CS42L42_FSYNC_P_UPPER: 214 case CS42L42_ASP_CLK_CFG: 215 case CS42L42_ASP_FRM_CFG: 216 case CS42L42_FS_RATE_EN: 217 case CS42L42_IN_ASRC_CLK: 218 case CS42L42_OUT_ASRC_CLK: 219 case CS42L42_PLL_DIV_CFG1: 220 case CS42L42_ADC_OVFL_STATUS: 221 case CS42L42_MIXER_STATUS: 222 case CS42L42_SRC_STATUS: 223 case CS42L42_ASP_RX_STATUS: 224 case CS42L42_ASP_TX_STATUS: 225 case CS42L42_CODEC_STATUS: 226 case CS42L42_DET_INT_STATUS1: 227 case CS42L42_DET_INT_STATUS2: 228 case CS42L42_SRCPL_INT_STATUS: 229 case CS42L42_VPMON_STATUS: 230 case CS42L42_PLL_LOCK_STATUS: 231 case CS42L42_TSRS_PLUG_STATUS: 232 case CS42L42_ADC_OVFL_INT_MASK: 233 case CS42L42_MIXER_INT_MASK: 234 case CS42L42_SRC_INT_MASK: 235 case CS42L42_ASP_RX_INT_MASK: 236 case CS42L42_ASP_TX_INT_MASK: 237 case CS42L42_CODEC_INT_MASK: 238 case CS42L42_SRCPL_INT_MASK: 239 case CS42L42_VPMON_INT_MASK: 240 case CS42L42_PLL_LOCK_INT_MASK: 241 case CS42L42_TSRS_PLUG_INT_MASK: 242 case CS42L42_PLL_CTL1: 243 case CS42L42_PLL_DIV_FRAC0: 244 case CS42L42_PLL_DIV_FRAC1: 245 case CS42L42_PLL_DIV_FRAC2: 246 case CS42L42_PLL_DIV_INT: 247 case CS42L42_PLL_CTL3: 248 case CS42L42_PLL_CAL_RATIO: 249 case CS42L42_PLL_CTL4: 250 case CS42L42_LOAD_DET_RCSTAT: 251 case CS42L42_LOAD_DET_DONE: 252 case CS42L42_LOAD_DET_EN: 253 case CS42L42_HSBIAS_SC_AUTOCTL: 254 case CS42L42_WAKE_CTL: 255 case CS42L42_ADC_DISABLE_MUTE: 256 case CS42L42_TIPSENSE_CTL: 257 case CS42L42_MISC_DET_CTL: 258 case CS42L42_MIC_DET_CTL1: 259 case CS42L42_MIC_DET_CTL2: 260 case CS42L42_DET_STATUS1: 261 case CS42L42_DET_STATUS2: 262 case CS42L42_DET_INT1_MASK: 263 case CS42L42_DET_INT2_MASK: 264 case CS42L42_HS_BIAS_CTL: 265 case CS42L42_ADC_CTL: 266 case CS42L42_ADC_VOLUME: 267 case CS42L42_ADC_WNF_HPF_CTL: 268 case CS42L42_DAC_CTL1: 269 case CS42L42_DAC_CTL2: 270 case CS42L42_HP_CTL: 271 case CS42L42_CLASSH_CTL: 272 case CS42L42_MIXER_CHA_VOL: 273 case CS42L42_MIXER_ADC_VOL: 274 case CS42L42_MIXER_CHB_VOL: 275 case CS42L42_EQ_COEF_IN0: 276 case CS42L42_EQ_COEF_IN1: 277 case CS42L42_EQ_COEF_IN2: 278 case CS42L42_EQ_COEF_IN3: 279 case CS42L42_EQ_COEF_RW: 280 case CS42L42_EQ_COEF_OUT0: 281 case CS42L42_EQ_COEF_OUT1: 282 case CS42L42_EQ_COEF_OUT2: 283 case CS42L42_EQ_COEF_OUT3: 284 case CS42L42_EQ_INIT_STAT: 285 case CS42L42_EQ_START_FILT: 286 case CS42L42_EQ_MUTE_CTL: 287 case CS42L42_SP_RX_CH_SEL: 288 case CS42L42_SP_RX_ISOC_CTL: 289 case CS42L42_SP_RX_FS: 290 case CS42l42_SPDIF_CH_SEL: 291 case CS42L42_SP_TX_ISOC_CTL: 292 case CS42L42_SP_TX_FS: 293 case CS42L42_SPDIF_SW_CTL1: 294 case CS42L42_SRC_SDIN_FS: 295 case CS42L42_SRC_SDOUT_FS: 296 case CS42L42_SPDIF_CTL1: 297 case CS42L42_SPDIF_CTL2: 298 case CS42L42_SPDIF_CTL3: 299 case CS42L42_SPDIF_CTL4: 300 case CS42L42_ASP_TX_SZ_EN: 301 case CS42L42_ASP_TX_CH_EN: 302 case CS42L42_ASP_TX_CH_AP_RES: 303 case CS42L42_ASP_TX_CH1_BIT_MSB: 304 case CS42L42_ASP_TX_CH1_BIT_LSB: 305 case CS42L42_ASP_TX_HIZ_DLY_CFG: 306 case CS42L42_ASP_TX_CH2_BIT_MSB: 307 case CS42L42_ASP_TX_CH2_BIT_LSB: 308 case CS42L42_ASP_RX_DAI0_EN: 309 case CS42L42_ASP_RX_DAI0_CH1_AP_RES: 310 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: 311 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: 312 case CS42L42_ASP_RX_DAI0_CH2_AP_RES: 313 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: 314 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: 315 case CS42L42_ASP_RX_DAI0_CH3_AP_RES: 316 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: 317 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: 318 case CS42L42_ASP_RX_DAI0_CH4_AP_RES: 319 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: 320 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: 321 case CS42L42_ASP_RX_DAI1_CH1_AP_RES: 322 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: 323 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: 324 case CS42L42_ASP_RX_DAI1_CH2_AP_RES: 325 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: 326 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: 327 case CS42L42_SUB_REVID: 328 return true; 329 default: 330 return false; 331 } 332 } 333 EXPORT_SYMBOL_NS_GPL(cs42l42_readable_register, SND_SOC_CS42L42_CORE); 334 335 bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 336 { 337 switch (reg) { 338 case CS42L42_DEVID_AB: 339 case CS42L42_DEVID_CD: 340 case CS42L42_DEVID_E: 341 case CS42L42_MCLK_STATUS: 342 case CS42L42_OSC_SWITCH_STATUS: 343 case CS42L42_TRSENSE_STATUS: 344 case CS42L42_HS_DET_STATUS: 345 case CS42L42_ADC_OVFL_STATUS: 346 case CS42L42_MIXER_STATUS: 347 case CS42L42_SRC_STATUS: 348 case CS42L42_ASP_RX_STATUS: 349 case CS42L42_ASP_TX_STATUS: 350 case CS42L42_CODEC_STATUS: 351 case CS42L42_DET_INT_STATUS1: 352 case CS42L42_DET_INT_STATUS2: 353 case CS42L42_SRCPL_INT_STATUS: 354 case CS42L42_VPMON_STATUS: 355 case CS42L42_PLL_LOCK_STATUS: 356 case CS42L42_TSRS_PLUG_STATUS: 357 case CS42L42_LOAD_DET_RCSTAT: 358 case CS42L42_LOAD_DET_DONE: 359 case CS42L42_DET_STATUS1: 360 case CS42L42_DET_STATUS2: 361 return true; 362 default: 363 return false; 364 } 365 } 366 EXPORT_SYMBOL_NS_GPL(cs42l42_volatile_register, SND_SOC_CS42L42_CORE); 367 368 const struct regmap_range_cfg cs42l42_page_range = { 369 .name = "Pages", 370 .range_min = 0, 371 .range_max = CS42L42_MAX_REGISTER, 372 .selector_reg = CS42L42_PAGE_REGISTER, 373 .selector_mask = 0xff, 374 .selector_shift = 0, 375 .window_start = 0, 376 .window_len = 256, 377 }; 378 EXPORT_SYMBOL_NS_GPL(cs42l42_page_range, SND_SOC_CS42L42_CORE); 379 380 const struct regmap_config cs42l42_regmap = { 381 .reg_bits = 8, 382 .val_bits = 8, 383 384 .readable_reg = cs42l42_readable_register, 385 .volatile_reg = cs42l42_volatile_register, 386 387 .ranges = &cs42l42_page_range, 388 .num_ranges = 1, 389 390 .max_register = CS42L42_MAX_REGISTER, 391 .reg_defaults = cs42l42_reg_defaults, 392 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), 393 .cache_type = REGCACHE_RBTREE, 394 395 .use_single_read = true, 396 .use_single_write = true, 397 }; 398 EXPORT_SYMBOL_NS_GPL(cs42l42_regmap, SND_SOC_CS42L42_CORE); 399 400 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true); 401 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true); 402 403 static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol, 404 struct snd_ctl_elem_value *ucontrol) 405 { 406 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 407 u8 val; 408 409 /* all bits of SLOW_START_EN must change together */ 410 switch (ucontrol->value.integer.value[0]) { 411 case 0: 412 val = 0; 413 break; 414 case 1: 415 val = CS42L42_SLOW_START_EN_MASK; 416 break; 417 default: 418 return -EINVAL; 419 } 420 421 return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE, 422 CS42L42_SLOW_START_EN_MASK, val); 423 } 424 425 static const char * const cs42l42_hpf_freq_text[] = { 426 "1.86Hz", "120Hz", "235Hz", "466Hz" 427 }; 428 429 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 430 CS42L42_ADC_HPF_CF_SHIFT, 431 cs42l42_hpf_freq_text); 432 433 static const char * const cs42l42_wnf3_freq_text[] = { 434 "160Hz", "180Hz", "200Hz", "220Hz", 435 "240Hz", "260Hz", "280Hz", "300Hz" 436 }; 437 438 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 439 CS42L42_ADC_WNF_CF_SHIFT, 440 cs42l42_wnf3_freq_text); 441 442 static const struct snd_kcontrol_new cs42l42_snd_controls[] = { 443 /* ADC Volume and Filter Controls */ 444 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL, 445 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true), 446 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL, 447 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), 448 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL, 449 CS42L42_ADC_INV_SHIFT, true, false), 450 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL, 451 CS42L42_ADC_DIG_BOOST_SHIFT, true, false), 452 SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv), 453 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL, 454 CS42L42_ADC_WNF_EN_SHIFT, true, false), 455 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL, 456 CS42L42_ADC_HPF_EN_SHIFT, true, false), 457 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum), 458 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum), 459 460 /* DAC Volume and Filter Controls */ 461 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1, 462 CS42L42_DACA_INV_SHIFT, true, false), 463 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1, 464 CS42L42_DACB_INV_SHIFT, true, false), 465 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2, 466 CS42L42_DAC_HPF_EN_SHIFT, true, false), 467 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL, 468 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, 469 0x3f, 1, mixer_tlv), 470 471 SOC_SINGLE_EXT("Slow Start Switch", CS42L42_SLOW_START_ENABLE, 472 CS42L42_SLOW_START_EN_SHIFT, true, false, 473 snd_soc_get_volsw, cs42l42_slow_start_put), 474 }; 475 476 static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w, 477 struct snd_kcontrol *kcontrol, int event) 478 { 479 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 480 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 481 482 switch (event) { 483 case SND_SOC_DAPM_PRE_PMU: 484 cs42l42->hp_adc_up_pending = true; 485 break; 486 case SND_SOC_DAPM_POST_PMU: 487 /* Only need one delay if HP and ADC are both powering-up */ 488 if (cs42l42->hp_adc_up_pending) { 489 usleep_range(CS42L42_HP_ADC_EN_TIME_US, 490 CS42L42_HP_ADC_EN_TIME_US + 1000); 491 cs42l42->hp_adc_up_pending = false; 492 } 493 break; 494 default: 495 break; 496 } 497 498 return 0; 499 } 500 501 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { 502 /* Playback Path */ 503 SND_SOC_DAPM_OUTPUT("HP"), 504 SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1, 505 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 506 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0), 507 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0), 508 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0), 509 510 /* Playback Requirements */ 511 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0), 512 513 /* Capture Path */ 514 SND_SOC_DAPM_INPUT("HS"), 515 SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1, 516 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 517 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0), 518 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0), 519 520 /* Capture Requirements */ 521 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0), 522 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0), 523 524 /* Playback/Capture Requirements */ 525 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0), 526 }; 527 528 static const struct snd_soc_dapm_route cs42l42_audio_map[] = { 529 /* Playback Path */ 530 {"HP", NULL, "DAC"}, 531 {"DAC", NULL, "MIXER"}, 532 {"MIXER", NULL, "SDIN1"}, 533 {"MIXER", NULL, "SDIN2"}, 534 {"SDIN1", NULL, "Playback"}, 535 {"SDIN2", NULL, "Playback"}, 536 537 /* Playback Requirements */ 538 {"SDIN1", NULL, "ASP DAI0"}, 539 {"SDIN2", NULL, "ASP DAI0"}, 540 {"SDIN1", NULL, "SCLK"}, 541 {"SDIN2", NULL, "SCLK"}, 542 543 /* Capture Path */ 544 {"ADC", NULL, "HS"}, 545 { "SDOUT1", NULL, "ADC" }, 546 { "SDOUT2", NULL, "ADC" }, 547 { "Capture", NULL, "SDOUT1" }, 548 { "Capture", NULL, "SDOUT2" }, 549 550 /* Capture Requirements */ 551 { "SDOUT1", NULL, "ASP DAO0" }, 552 { "SDOUT2", NULL, "ASP DAO0" }, 553 { "SDOUT1", NULL, "SCLK" }, 554 { "SDOUT2", NULL, "SCLK" }, 555 { "SDOUT1", NULL, "ASP TX EN" }, 556 { "SDOUT2", NULL, "ASP TX EN" }, 557 }; 558 559 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d) 560 { 561 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 562 563 /* Prevent race with interrupt handler */ 564 mutex_lock(&cs42l42->irq_lock); 565 cs42l42->jack = jk; 566 567 if (jk) { 568 switch (cs42l42->hs_type) { 569 case CS42L42_PLUG_CTIA: 570 case CS42L42_PLUG_OMTP: 571 snd_soc_jack_report(jk, SND_JACK_HEADSET, SND_JACK_HEADSET); 572 break; 573 case CS42L42_PLUG_HEADPHONE: 574 snd_soc_jack_report(jk, SND_JACK_HEADPHONE, SND_JACK_HEADPHONE); 575 break; 576 default: 577 break; 578 } 579 } 580 mutex_unlock(&cs42l42->irq_lock); 581 582 return 0; 583 } 584 585 const struct snd_soc_component_driver cs42l42_soc_component = { 586 .set_jack = cs42l42_set_jack, 587 .dapm_widgets = cs42l42_dapm_widgets, 588 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), 589 .dapm_routes = cs42l42_audio_map, 590 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), 591 .controls = cs42l42_snd_controls, 592 .num_controls = ARRAY_SIZE(cs42l42_snd_controls), 593 .idle_bias_on = 1, 594 .endianness = 1, 595 }; 596 EXPORT_SYMBOL_NS_GPL(cs42l42_soc_component, SND_SOC_CS42L42_CORE); 597 598 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */ 599 static const struct reg_sequence cs42l42_to_sclk_seq[] = { 600 { 601 .reg = CS42L42_OSC_SWITCH, 602 .def = CS42L42_SCLK_PRESENT_MASK, 603 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 604 }, 605 }; 606 607 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */ 608 static const struct reg_sequence cs42l42_to_osc_seq[] = { 609 { 610 .reg = CS42L42_OSC_SWITCH, 611 .def = 0, 612 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 613 }, 614 }; 615 616 struct cs42l42_pll_params { 617 u32 sclk; 618 u8 mclk_src_sel; 619 u8 sclk_prediv; 620 u8 pll_div_int; 621 u32 pll_div_frac; 622 u8 pll_mode; 623 u8 pll_divout; 624 u32 mclk_int; 625 u8 pll_cal_ratio; 626 u8 n; 627 }; 628 629 /* 630 * Common PLL Settings for given SCLK 631 * Table 4-5 from the Datasheet 632 */ 633 static const struct cs42l42_pll_params pll_ratio_table[] = { 634 { 1411200, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2}, 635 { 1536000, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2}, 636 { 2304000, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2}, 637 { 2400000, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 638 { 2822400, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 639 { 3000000, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 640 { 3072000, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 641 { 4000000, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1}, 642 { 4096000, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1}, 643 { 5644800, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 644 { 6000000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 645 { 6144000, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 646 { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1}, 647 { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1}, 648 { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1}, 649 { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 650 { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 651 { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1} 652 }; 653 654 static int cs42l42_pll_config(struct snd_soc_component *component, unsigned int clk) 655 { 656 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 657 int i; 658 u32 fsync; 659 660 /* Don't reconfigure if there is an audio stream running */ 661 if (cs42l42->stream_use) { 662 if (pll_ratio_table[cs42l42->pll_config].sclk == clk) 663 return 0; 664 else 665 return -EBUSY; 666 } 667 668 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 669 if (pll_ratio_table[i].sclk == clk) { 670 cs42l42->pll_config = i; 671 672 /* Configure the internal sample rate */ 673 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, 674 CS42L42_INTERNAL_FS_MASK, 675 ((pll_ratio_table[i].mclk_int != 676 12000000) && 677 (pll_ratio_table[i].mclk_int != 678 24000000)) << 679 CS42L42_INTERNAL_FS_SHIFT); 680 681 /* Set up the LRCLK */ 682 fsync = clk / cs42l42->srate; 683 if (((fsync * cs42l42->srate) != clk) 684 || ((fsync % 2) != 0)) { 685 dev_err(component->dev, 686 "Unsupported sclk %d/sample rate %d\n", 687 clk, 688 cs42l42->srate); 689 return -EINVAL; 690 } 691 /* Set the LRCLK period */ 692 snd_soc_component_update_bits(component, 693 CS42L42_FSYNC_P_LOWER, 694 CS42L42_FSYNC_PERIOD_MASK, 695 CS42L42_FRAC0_VAL(fsync - 1) << 696 CS42L42_FSYNC_PERIOD_SHIFT); 697 snd_soc_component_update_bits(component, 698 CS42L42_FSYNC_P_UPPER, 699 CS42L42_FSYNC_PERIOD_MASK, 700 CS42L42_FRAC1_VAL(fsync - 1) << 701 CS42L42_FSYNC_PERIOD_SHIFT); 702 /* Set the LRCLK to 50% duty cycle */ 703 fsync = fsync / 2; 704 snd_soc_component_update_bits(component, 705 CS42L42_FSYNC_PW_LOWER, 706 CS42L42_FSYNC_PULSE_WIDTH_MASK, 707 CS42L42_FRAC0_VAL(fsync - 1) << 708 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 709 snd_soc_component_update_bits(component, 710 CS42L42_FSYNC_PW_UPPER, 711 CS42L42_FSYNC_PULSE_WIDTH_MASK, 712 CS42L42_FRAC1_VAL(fsync - 1) << 713 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 714 if (pll_ratio_table[i].mclk_src_sel == 0) { 715 /* Pass the clock straight through */ 716 snd_soc_component_update_bits(component, 717 CS42L42_PLL_CTL1, 718 CS42L42_PLL_START_MASK, 0); 719 } else { 720 /* Configure PLL per table 4-5 */ 721 snd_soc_component_update_bits(component, 722 CS42L42_PLL_DIV_CFG1, 723 CS42L42_SCLK_PREDIV_MASK, 724 pll_ratio_table[i].sclk_prediv 725 << CS42L42_SCLK_PREDIV_SHIFT); 726 snd_soc_component_update_bits(component, 727 CS42L42_PLL_DIV_INT, 728 CS42L42_PLL_DIV_INT_MASK, 729 pll_ratio_table[i].pll_div_int 730 << CS42L42_PLL_DIV_INT_SHIFT); 731 snd_soc_component_update_bits(component, 732 CS42L42_PLL_DIV_FRAC0, 733 CS42L42_PLL_DIV_FRAC_MASK, 734 CS42L42_FRAC0_VAL( 735 pll_ratio_table[i].pll_div_frac) 736 << CS42L42_PLL_DIV_FRAC_SHIFT); 737 snd_soc_component_update_bits(component, 738 CS42L42_PLL_DIV_FRAC1, 739 CS42L42_PLL_DIV_FRAC_MASK, 740 CS42L42_FRAC1_VAL( 741 pll_ratio_table[i].pll_div_frac) 742 << CS42L42_PLL_DIV_FRAC_SHIFT); 743 snd_soc_component_update_bits(component, 744 CS42L42_PLL_DIV_FRAC2, 745 CS42L42_PLL_DIV_FRAC_MASK, 746 CS42L42_FRAC2_VAL( 747 pll_ratio_table[i].pll_div_frac) 748 << CS42L42_PLL_DIV_FRAC_SHIFT); 749 snd_soc_component_update_bits(component, 750 CS42L42_PLL_CTL4, 751 CS42L42_PLL_MODE_MASK, 752 pll_ratio_table[i].pll_mode 753 << CS42L42_PLL_MODE_SHIFT); 754 snd_soc_component_update_bits(component, 755 CS42L42_PLL_CTL3, 756 CS42L42_PLL_DIVOUT_MASK, 757 (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n) 758 << CS42L42_PLL_DIVOUT_SHIFT); 759 snd_soc_component_update_bits(component, 760 CS42L42_PLL_CAL_RATIO, 761 CS42L42_PLL_CAL_RATIO_MASK, 762 pll_ratio_table[i].pll_cal_ratio 763 << CS42L42_PLL_CAL_RATIO_SHIFT); 764 } 765 return 0; 766 } 767 } 768 769 return -EINVAL; 770 } 771 772 static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate) 773 { 774 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 775 unsigned int fs; 776 777 /* Don't reconfigure if there is an audio stream running */ 778 if (cs42l42->stream_use) 779 return; 780 781 /* SRC MCLK must be as close as possible to 125 * sample rate */ 782 if (sample_rate <= 48000) 783 fs = CS42L42_CLK_IASRC_SEL_6; 784 else 785 fs = CS42L42_CLK_IASRC_SEL_12; 786 787 /* Set the sample rates (96k or lower) */ 788 snd_soc_component_update_bits(component, 789 CS42L42_FS_RATE_EN, 790 CS42L42_FS_EN_MASK, 791 (CS42L42_FS_EN_IASRC_96K | 792 CS42L42_FS_EN_OASRC_96K) << 793 CS42L42_FS_EN_SHIFT); 794 795 snd_soc_component_update_bits(component, 796 CS42L42_IN_ASRC_CLK, 797 CS42L42_CLK_IASRC_SEL_MASK, 798 fs << CS42L42_CLK_IASRC_SEL_SHIFT); 799 snd_soc_component_update_bits(component, 800 CS42L42_OUT_ASRC_CLK, 801 CS42L42_CLK_OASRC_SEL_MASK, 802 fs << CS42L42_CLK_OASRC_SEL_SHIFT); 803 } 804 805 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 806 { 807 struct snd_soc_component *component = codec_dai->component; 808 u32 asp_cfg_val = 0; 809 810 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 811 case SND_SOC_DAIFMT_CBS_CFM: 812 asp_cfg_val |= CS42L42_ASP_MASTER_MODE << 813 CS42L42_ASP_MODE_SHIFT; 814 break; 815 case SND_SOC_DAIFMT_CBS_CFS: 816 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << 817 CS42L42_ASP_MODE_SHIFT; 818 break; 819 default: 820 return -EINVAL; 821 } 822 823 /* interface format */ 824 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 825 case SND_SOC_DAIFMT_I2S: 826 /* 827 * 5050 mode, frame starts on falling edge of LRCLK, 828 * frame delayed by 1.0 SCLKs 829 */ 830 snd_soc_component_update_bits(component, 831 CS42L42_ASP_FRM_CFG, 832 CS42L42_ASP_STP_MASK | 833 CS42L42_ASP_5050_MASK | 834 CS42L42_ASP_FSD_MASK, 835 CS42L42_ASP_5050_MASK | 836 (CS42L42_ASP_FSD_1_0 << 837 CS42L42_ASP_FSD_SHIFT)); 838 break; 839 default: 840 return -EINVAL; 841 } 842 843 /* Bitclock/frame inversion */ 844 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 845 case SND_SOC_DAIFMT_NB_NF: 846 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 847 break; 848 case SND_SOC_DAIFMT_NB_IF: 849 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 850 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 851 break; 852 case SND_SOC_DAIFMT_IB_NF: 853 break; 854 case SND_SOC_DAIFMT_IB_IF: 855 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 856 break; 857 } 858 859 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK | 860 CS42L42_ASP_SCPOL_MASK | 861 CS42L42_ASP_LCPOL_MASK, 862 asp_cfg_val); 863 864 return 0; 865 } 866 867 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 868 { 869 struct snd_soc_component *component = dai->component; 870 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 871 872 /* 873 * Sample rates < 44.1 kHz would produce an out-of-range SCLK with 874 * a standard I2S frame. If the machine driver sets SCLK it must be 875 * legal. 876 */ 877 if (cs42l42->sclk) 878 return 0; 879 880 /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */ 881 return snd_pcm_hw_constraint_minmax(substream->runtime, 882 SNDRV_PCM_HW_PARAM_RATE, 883 44100, 96000); 884 } 885 886 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, 887 struct snd_pcm_hw_params *params, 888 struct snd_soc_dai *dai) 889 { 890 struct snd_soc_component *component = dai->component; 891 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 892 unsigned int channels = params_channels(params); 893 unsigned int width = (params_width(params) / 8) - 1; 894 unsigned int slot_width = 0; 895 unsigned int val = 0; 896 unsigned int bclk; 897 int ret; 898 899 cs42l42->srate = params_rate(params); 900 901 if (cs42l42->sclk) { 902 /* machine driver has set the SCLK */ 903 bclk = cs42l42->sclk; 904 } else { 905 /* 906 * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being 907 * more than assumed (which would result in overclocking). 908 */ 909 if (params_width(params) == 24) 910 slot_width = 32; 911 912 /* I2S frame always has multiple of 2 channels */ 913 bclk = snd_soc_tdm_params_to_bclk(params, slot_width, 0, 2); 914 } 915 916 switch (substream->stream) { 917 case SNDRV_PCM_STREAM_CAPTURE: 918 /* channel 2 on high LRCLK */ 919 val = CS42L42_ASP_TX_CH2_AP_MASK | 920 (width << CS42L42_ASP_TX_CH2_RES_SHIFT) | 921 (width << CS42L42_ASP_TX_CH1_RES_SHIFT); 922 923 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES, 924 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK | 925 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val); 926 break; 927 case SNDRV_PCM_STREAM_PLAYBACK: 928 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT; 929 /* channel 1 on low LRCLK */ 930 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES, 931 CS42L42_ASP_RX_CH_AP_MASK | 932 CS42L42_ASP_RX_CH_RES_MASK, val); 933 /* Channel 2 on high LRCLK */ 934 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT; 935 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES, 936 CS42L42_ASP_RX_CH_AP_MASK | 937 CS42L42_ASP_RX_CH_RES_MASK, val); 938 939 /* Channel B comes from the last active channel */ 940 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL, 941 CS42L42_SP_RX_CHB_SEL_MASK, 942 (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT); 943 944 /* Both LRCLK slots must be enabled */ 945 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN, 946 CS42L42_ASP_RX0_CH_EN_MASK, 947 BIT(CS42L42_ASP_RX0_CH1_SHIFT) | 948 BIT(CS42L42_ASP_RX0_CH2_SHIFT)); 949 break; 950 default: 951 break; 952 } 953 954 ret = cs42l42_pll_config(component, bclk); 955 if (ret) 956 return ret; 957 958 cs42l42_src_config(component, params_rate(params)); 959 960 return 0; 961 } 962 963 static int cs42l42_set_sysclk(struct snd_soc_dai *dai, 964 int clk_id, unsigned int freq, int dir) 965 { 966 struct snd_soc_component *component = dai->component; 967 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 968 int i; 969 970 if (freq == 0) { 971 cs42l42->sclk = 0; 972 return 0; 973 } 974 975 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 976 if (pll_ratio_table[i].sclk == freq) { 977 cs42l42->sclk = freq; 978 return 0; 979 } 980 } 981 982 dev_err(component->dev, "SCLK %u not supported\n", freq); 983 984 return -EINVAL; 985 } 986 987 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 988 { 989 struct snd_soc_component *component = dai->component; 990 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 991 unsigned int regval; 992 int ret; 993 994 if (mute) { 995 /* Mute the headphone */ 996 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 997 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 998 CS42L42_HP_ANA_AMUTE_MASK | 999 CS42L42_HP_ANA_BMUTE_MASK, 1000 CS42L42_HP_ANA_AMUTE_MASK | 1001 CS42L42_HP_ANA_BMUTE_MASK); 1002 1003 cs42l42->stream_use &= ~(1 << stream); 1004 if (!cs42l42->stream_use) { 1005 /* 1006 * Switch to the internal oscillator. 1007 * SCLK must remain running until after this clock switch. 1008 * Without a source of clock the I2C bus doesn't work. 1009 */ 1010 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq, 1011 ARRAY_SIZE(cs42l42_to_osc_seq)); 1012 1013 /* Must disconnect PLL before stopping it */ 1014 snd_soc_component_update_bits(component, 1015 CS42L42_MCLK_SRC_SEL, 1016 CS42L42_MCLK_SRC_SEL_MASK, 1017 0); 1018 usleep_range(100, 200); 1019 1020 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 1021 CS42L42_PLL_START_MASK, 0); 1022 } 1023 } else { 1024 if (!cs42l42->stream_use) { 1025 /* SCLK must be running before codec unmute. 1026 * 1027 * PLL must not be started with ADC and HP both off 1028 * otherwise the FILT+ supply will not charge properly. 1029 * DAPM widgets power-up before stream unmute so at least 1030 * one of the "DAC" or "ADC" widgets will already have 1031 * powered-up. 1032 */ 1033 if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) { 1034 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 1035 CS42L42_PLL_START_MASK, 1); 1036 1037 if (pll_ratio_table[cs42l42->pll_config].n > 1) { 1038 usleep_range(CS42L42_PLL_DIVOUT_TIME_US, 1039 CS42L42_PLL_DIVOUT_TIME_US * 2); 1040 regval = pll_ratio_table[cs42l42->pll_config].pll_divout; 1041 snd_soc_component_update_bits(component, CS42L42_PLL_CTL3, 1042 CS42L42_PLL_DIVOUT_MASK, 1043 regval << 1044 CS42L42_PLL_DIVOUT_SHIFT); 1045 } 1046 1047 ret = regmap_read_poll_timeout(cs42l42->regmap, 1048 CS42L42_PLL_LOCK_STATUS, 1049 regval, 1050 (regval & 1), 1051 CS42L42_PLL_LOCK_POLL_US, 1052 CS42L42_PLL_LOCK_TIMEOUT_US); 1053 if (ret < 0) 1054 dev_warn(component->dev, "PLL failed to lock: %d\n", ret); 1055 1056 /* PLL must be running to drive glitchless switch logic */ 1057 snd_soc_component_update_bits(component, 1058 CS42L42_MCLK_SRC_SEL, 1059 CS42L42_MCLK_SRC_SEL_MASK, 1060 CS42L42_MCLK_SRC_SEL_MASK); 1061 } 1062 1063 /* Mark SCLK as present, turn off internal oscillator */ 1064 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq, 1065 ARRAY_SIZE(cs42l42_to_sclk_seq)); 1066 } 1067 cs42l42->stream_use |= 1 << stream; 1068 1069 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1070 /* Un-mute the headphone */ 1071 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 1072 CS42L42_HP_ANA_AMUTE_MASK | 1073 CS42L42_HP_ANA_BMUTE_MASK, 1074 0); 1075 } 1076 } 1077 1078 return 0; 1079 } 1080 1081 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1082 SNDRV_PCM_FMTBIT_S24_LE |\ 1083 SNDRV_PCM_FMTBIT_S32_LE) 1084 1085 static const struct snd_soc_dai_ops cs42l42_ops = { 1086 .startup = cs42l42_dai_startup, 1087 .hw_params = cs42l42_pcm_hw_params, 1088 .set_fmt = cs42l42_set_dai_fmt, 1089 .set_sysclk = cs42l42_set_sysclk, 1090 .mute_stream = cs42l42_mute_stream, 1091 }; 1092 1093 struct snd_soc_dai_driver cs42l42_dai = { 1094 .name = "cs42l42", 1095 .playback = { 1096 .stream_name = "Playback", 1097 .channels_min = 1, 1098 .channels_max = 2, 1099 .rates = SNDRV_PCM_RATE_8000_96000, 1100 .formats = CS42L42_FORMATS, 1101 }, 1102 .capture = { 1103 .stream_name = "Capture", 1104 .channels_min = 1, 1105 .channels_max = 2, 1106 .rates = SNDRV_PCM_RATE_8000_96000, 1107 .formats = CS42L42_FORMATS, 1108 }, 1109 .symmetric_rate = 1, 1110 .symmetric_sample_bits = 1, 1111 .ops = &cs42l42_ops, 1112 }; 1113 EXPORT_SYMBOL_NS_GPL(cs42l42_dai, SND_SOC_CS42L42_CORE); 1114 1115 static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42) 1116 { 1117 unsigned int hs_det_status; 1118 unsigned int hs_det_comp1; 1119 unsigned int hs_det_comp2; 1120 unsigned int hs_det_sw; 1121 1122 /* Set hs detect to manual, active mode */ 1123 regmap_update_bits(cs42l42->regmap, 1124 CS42L42_HSDET_CTL2, 1125 CS42L42_HSDET_CTRL_MASK | 1126 CS42L42_HSDET_SET_MASK | 1127 CS42L42_HSBIAS_REF_MASK | 1128 CS42L42_HSDET_AUTO_TIME_MASK, 1129 (1 << CS42L42_HSDET_CTRL_SHIFT) | 1130 (0 << CS42L42_HSDET_SET_SHIFT) | 1131 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1132 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1133 1134 /* Configure HS DET comparator reference levels. */ 1135 regmap_update_bits(cs42l42->regmap, 1136 CS42L42_HSDET_CTL1, 1137 CS42L42_HSDET_COMP1_LVL_MASK | 1138 CS42L42_HSDET_COMP2_LVL_MASK, 1139 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) | 1140 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT)); 1141 1142 /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */ 1143 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1); 1144 1145 msleep(100); 1146 1147 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1148 1149 hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 1150 CS42L42_HSDET_COMP1_OUT_SHIFT; 1151 hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 1152 CS42L42_HSDET_COMP2_OUT_SHIFT; 1153 1154 /* Close the SW_HSB_HS3 switch for a Type 2 headset. */ 1155 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2); 1156 1157 msleep(100); 1158 1159 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1160 1161 hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 1162 CS42L42_HSDET_COMP1_OUT_SHIFT) << 1; 1163 hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 1164 CS42L42_HSDET_COMP2_OUT_SHIFT) << 1; 1165 1166 /* Use Comparator 1 with 1.25V Threshold. */ 1167 switch (hs_det_comp1) { 1168 case CS42L42_HSDET_COMP_TYPE1: 1169 cs42l42->hs_type = CS42L42_PLUG_CTIA; 1170 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 1171 break; 1172 case CS42L42_HSDET_COMP_TYPE2: 1173 cs42l42->hs_type = CS42L42_PLUG_OMTP; 1174 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 1175 break; 1176 default: 1177 /* Fallback to Comparator 2 with 1.75V Threshold. */ 1178 switch (hs_det_comp2) { 1179 case CS42L42_HSDET_COMP_TYPE1: 1180 cs42l42->hs_type = CS42L42_PLUG_CTIA; 1181 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 1182 break; 1183 case CS42L42_HSDET_COMP_TYPE2: 1184 cs42l42->hs_type = CS42L42_PLUG_OMTP; 1185 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 1186 break; 1187 case CS42L42_HSDET_COMP_TYPE3: 1188 cs42l42->hs_type = CS42L42_PLUG_HEADPHONE; 1189 hs_det_sw = CS42L42_HSDET_SW_TYPE3; 1190 break; 1191 default: 1192 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1193 hs_det_sw = CS42L42_HSDET_SW_TYPE4; 1194 break; 1195 } 1196 } 1197 1198 /* Set Switches */ 1199 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw); 1200 1201 /* Set HSDET mode to Manual—Disabled */ 1202 regmap_update_bits(cs42l42->regmap, 1203 CS42L42_HSDET_CTL2, 1204 CS42L42_HSDET_CTRL_MASK | 1205 CS42L42_HSDET_SET_MASK | 1206 CS42L42_HSBIAS_REF_MASK | 1207 CS42L42_HSDET_AUTO_TIME_MASK, 1208 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1209 (0 << CS42L42_HSDET_SET_SHIFT) | 1210 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1211 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1212 1213 /* Configure HS DET comparator reference levels. */ 1214 regmap_update_bits(cs42l42->regmap, 1215 CS42L42_HSDET_CTL1, 1216 CS42L42_HSDET_COMP1_LVL_MASK | 1217 CS42L42_HSDET_COMP2_LVL_MASK, 1218 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) | 1219 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT)); 1220 } 1221 1222 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) 1223 { 1224 unsigned int hs_det_status; 1225 unsigned int int_status; 1226 1227 /* Read and save the hs detection result */ 1228 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1229 1230 /* Mask the auto detect interrupt */ 1231 regmap_update_bits(cs42l42->regmap, 1232 CS42L42_CODEC_INT_MASK, 1233 CS42L42_PDN_DONE_MASK | 1234 CS42L42_HSDET_AUTO_DONE_MASK, 1235 (1 << CS42L42_PDN_DONE_SHIFT) | 1236 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1237 1238 1239 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> 1240 CS42L42_HSDET_TYPE_SHIFT; 1241 1242 /* Set hs detect to automatic, disabled mode */ 1243 regmap_update_bits(cs42l42->regmap, 1244 CS42L42_HSDET_CTL2, 1245 CS42L42_HSDET_CTRL_MASK | 1246 CS42L42_HSDET_SET_MASK | 1247 CS42L42_HSBIAS_REF_MASK | 1248 CS42L42_HSDET_AUTO_TIME_MASK, 1249 (2 << CS42L42_HSDET_CTRL_SHIFT) | 1250 (2 << CS42L42_HSDET_SET_SHIFT) | 1251 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1252 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1253 1254 /* Run Manual detection if auto detect has not found a headset. 1255 * We Re-Run with Manual Detection if the original detection was invalid or headphones, 1256 * to ensure that a headset mic is detected in all cases. 1257 */ 1258 if (cs42l42->hs_type == CS42L42_PLUG_INVALID || 1259 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) { 1260 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n"); 1261 cs42l42_manual_hs_type_detect(cs42l42); 1262 } 1263 1264 /* Set up button detection */ 1265 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || 1266 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { 1267 /* Set auto HS bias settings to default */ 1268 regmap_update_bits(cs42l42->regmap, 1269 CS42L42_HSBIAS_SC_AUTOCTL, 1270 CS42L42_HSBIAS_SENSE_EN_MASK | 1271 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1272 CS42L42_TIP_SENSE_EN_MASK | 1273 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1274 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1275 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1276 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1277 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1278 1279 /* Set up hs detect level sensitivity */ 1280 regmap_update_bits(cs42l42->regmap, 1281 CS42L42_MIC_DET_CTL1, 1282 CS42L42_LATCH_TO_VP_MASK | 1283 CS42L42_EVENT_STAT_SEL_MASK | 1284 CS42L42_HS_DET_LEVEL_MASK, 1285 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1286 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1287 (cs42l42->bias_thresholds[0] << 1288 CS42L42_HS_DET_LEVEL_SHIFT)); 1289 1290 /* Set auto HS bias settings to default */ 1291 regmap_update_bits(cs42l42->regmap, 1292 CS42L42_HSBIAS_SC_AUTOCTL, 1293 CS42L42_HSBIAS_SENSE_EN_MASK | 1294 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1295 CS42L42_TIP_SENSE_EN_MASK | 1296 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1297 (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1298 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1299 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1300 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1301 1302 /* Turn on level detect circuitry */ 1303 regmap_update_bits(cs42l42->regmap, 1304 CS42L42_MISC_DET_CTL, 1305 CS42L42_HSBIAS_CTL_MASK | 1306 CS42L42_PDN_MIC_LVL_DET_MASK, 1307 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1308 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1309 1310 msleep(cs42l42->btn_det_init_dbnce); 1311 1312 /* Clear any button interrupts before unmasking them */ 1313 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1314 &int_status); 1315 1316 /* Unmask button detect interrupts */ 1317 regmap_update_bits(cs42l42->regmap, 1318 CS42L42_DET_INT2_MASK, 1319 CS42L42_M_DETECT_TF_MASK | 1320 CS42L42_M_DETECT_FT_MASK | 1321 CS42L42_M_HSBIAS_HIZ_MASK | 1322 CS42L42_M_SHORT_RLS_MASK | 1323 CS42L42_M_SHORT_DET_MASK, 1324 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1325 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1326 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1327 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1328 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1329 } else { 1330 /* Make sure button detect and HS bias circuits are off */ 1331 regmap_update_bits(cs42l42->regmap, 1332 CS42L42_MISC_DET_CTL, 1333 CS42L42_HSBIAS_CTL_MASK | 1334 CS42L42_PDN_MIC_LVL_DET_MASK, 1335 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1336 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1337 } 1338 1339 regmap_update_bits(cs42l42->regmap, 1340 CS42L42_DAC_CTL2, 1341 CS42L42_HPOUT_PULLDOWN_MASK | 1342 CS42L42_HPOUT_LOAD_MASK | 1343 CS42L42_HPOUT_CLAMP_MASK | 1344 CS42L42_DAC_HPF_EN_MASK | 1345 CS42L42_DAC_MON_EN_MASK, 1346 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1347 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1348 (0 << CS42L42_HPOUT_CLAMP_SHIFT) | 1349 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1350 (0 << CS42L42_DAC_MON_EN_SHIFT)); 1351 1352 /* Unmask tip sense interrupts */ 1353 regmap_update_bits(cs42l42->regmap, 1354 CS42L42_TSRS_PLUG_INT_MASK, 1355 CS42L42_TS_PLUG_MASK | 1356 CS42L42_TS_UNPLUG_MASK, 1357 (0 << CS42L42_TS_PLUG_SHIFT) | 1358 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1359 } 1360 1361 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) 1362 { 1363 /* Mask tip sense interrupts */ 1364 regmap_update_bits(cs42l42->regmap, 1365 CS42L42_TSRS_PLUG_INT_MASK, 1366 CS42L42_TS_PLUG_MASK | 1367 CS42L42_TS_UNPLUG_MASK, 1368 (1 << CS42L42_TS_PLUG_SHIFT) | 1369 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1370 1371 /* Make sure button detect and HS bias circuits are off */ 1372 regmap_update_bits(cs42l42->regmap, 1373 CS42L42_MISC_DET_CTL, 1374 CS42L42_HSBIAS_CTL_MASK | 1375 CS42L42_PDN_MIC_LVL_DET_MASK, 1376 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1377 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1378 1379 /* Set auto HS bias settings to default */ 1380 regmap_update_bits(cs42l42->regmap, 1381 CS42L42_HSBIAS_SC_AUTOCTL, 1382 CS42L42_HSBIAS_SENSE_EN_MASK | 1383 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1384 CS42L42_TIP_SENSE_EN_MASK | 1385 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1386 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1387 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1388 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1389 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1390 1391 /* Set hs detect to manual, disabled mode */ 1392 regmap_update_bits(cs42l42->regmap, 1393 CS42L42_HSDET_CTL2, 1394 CS42L42_HSDET_CTRL_MASK | 1395 CS42L42_HSDET_SET_MASK | 1396 CS42L42_HSBIAS_REF_MASK | 1397 CS42L42_HSDET_AUTO_TIME_MASK, 1398 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1399 (2 << CS42L42_HSDET_SET_SHIFT) | 1400 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1401 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1402 1403 regmap_update_bits(cs42l42->regmap, 1404 CS42L42_DAC_CTL2, 1405 CS42L42_HPOUT_PULLDOWN_MASK | 1406 CS42L42_HPOUT_LOAD_MASK | 1407 CS42L42_HPOUT_CLAMP_MASK | 1408 CS42L42_DAC_HPF_EN_MASK | 1409 CS42L42_DAC_MON_EN_MASK, 1410 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1411 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1412 (1 << CS42L42_HPOUT_CLAMP_SHIFT) | 1413 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1414 (1 << CS42L42_DAC_MON_EN_SHIFT)); 1415 1416 /* Power up HS bias to 2.7V */ 1417 regmap_update_bits(cs42l42->regmap, 1418 CS42L42_MISC_DET_CTL, 1419 CS42L42_HSBIAS_CTL_MASK | 1420 CS42L42_PDN_MIC_LVL_DET_MASK, 1421 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1422 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1423 1424 /* Wait for HS bias to ramp up */ 1425 msleep(cs42l42->hs_bias_ramp_time); 1426 1427 /* Unmask auto detect interrupt */ 1428 regmap_update_bits(cs42l42->regmap, 1429 CS42L42_CODEC_INT_MASK, 1430 CS42L42_PDN_DONE_MASK | 1431 CS42L42_HSDET_AUTO_DONE_MASK, 1432 (1 << CS42L42_PDN_DONE_SHIFT) | 1433 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1434 1435 /* Set hs detect to automatic, enabled mode */ 1436 regmap_update_bits(cs42l42->regmap, 1437 CS42L42_HSDET_CTL2, 1438 CS42L42_HSDET_CTRL_MASK | 1439 CS42L42_HSDET_SET_MASK | 1440 CS42L42_HSBIAS_REF_MASK | 1441 CS42L42_HSDET_AUTO_TIME_MASK, 1442 (3 << CS42L42_HSDET_CTRL_SHIFT) | 1443 (2 << CS42L42_HSDET_SET_SHIFT) | 1444 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1445 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1446 } 1447 1448 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) 1449 { 1450 /* Mask button detect interrupts */ 1451 regmap_update_bits(cs42l42->regmap, 1452 CS42L42_DET_INT2_MASK, 1453 CS42L42_M_DETECT_TF_MASK | 1454 CS42L42_M_DETECT_FT_MASK | 1455 CS42L42_M_HSBIAS_HIZ_MASK | 1456 CS42L42_M_SHORT_RLS_MASK | 1457 CS42L42_M_SHORT_DET_MASK, 1458 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1459 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1460 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1461 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1462 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1463 1464 /* Ground HS bias */ 1465 regmap_update_bits(cs42l42->regmap, 1466 CS42L42_MISC_DET_CTL, 1467 CS42L42_HSBIAS_CTL_MASK | 1468 CS42L42_PDN_MIC_LVL_DET_MASK, 1469 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1470 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1471 1472 /* Set auto HS bias settings to default */ 1473 regmap_update_bits(cs42l42->regmap, 1474 CS42L42_HSBIAS_SC_AUTOCTL, 1475 CS42L42_HSBIAS_SENSE_EN_MASK | 1476 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1477 CS42L42_TIP_SENSE_EN_MASK | 1478 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1479 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1480 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1481 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1482 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1483 1484 /* Set hs detect to manual, disabled mode */ 1485 regmap_update_bits(cs42l42->regmap, 1486 CS42L42_HSDET_CTL2, 1487 CS42L42_HSDET_CTRL_MASK | 1488 CS42L42_HSDET_SET_MASK | 1489 CS42L42_HSBIAS_REF_MASK | 1490 CS42L42_HSDET_AUTO_TIME_MASK, 1491 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1492 (2 << CS42L42_HSDET_SET_SHIFT) | 1493 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1494 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1495 } 1496 1497 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42) 1498 { 1499 int bias_level; 1500 unsigned int detect_status; 1501 1502 /* Mask button detect interrupts */ 1503 regmap_update_bits(cs42l42->regmap, 1504 CS42L42_DET_INT2_MASK, 1505 CS42L42_M_DETECT_TF_MASK | 1506 CS42L42_M_DETECT_FT_MASK | 1507 CS42L42_M_HSBIAS_HIZ_MASK | 1508 CS42L42_M_SHORT_RLS_MASK | 1509 CS42L42_M_SHORT_DET_MASK, 1510 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1511 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1512 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1513 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1514 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1515 1516 usleep_range(cs42l42->btn_det_event_dbnce * 1000, 1517 cs42l42->btn_det_event_dbnce * 2000); 1518 1519 /* Test all 4 level detect biases */ 1520 bias_level = 1; 1521 do { 1522 /* Adjust button detect level sensitivity */ 1523 regmap_update_bits(cs42l42->regmap, 1524 CS42L42_MIC_DET_CTL1, 1525 CS42L42_LATCH_TO_VP_MASK | 1526 CS42L42_EVENT_STAT_SEL_MASK | 1527 CS42L42_HS_DET_LEVEL_MASK, 1528 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1529 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1530 (cs42l42->bias_thresholds[bias_level] << 1531 CS42L42_HS_DET_LEVEL_SHIFT)); 1532 1533 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2, 1534 &detect_status); 1535 } while ((detect_status & CS42L42_HS_TRUE_MASK) && 1536 (++bias_level < CS42L42_NUM_BIASES)); 1537 1538 switch (bias_level) { 1539 case 1: /* Function C button press */ 1540 bias_level = SND_JACK_BTN_2; 1541 dev_dbg(cs42l42->dev, "Function C button press\n"); 1542 break; 1543 case 2: /* Function B button press */ 1544 bias_level = SND_JACK_BTN_1; 1545 dev_dbg(cs42l42->dev, "Function B button press\n"); 1546 break; 1547 case 3: /* Function D button press */ 1548 bias_level = SND_JACK_BTN_3; 1549 dev_dbg(cs42l42->dev, "Function D button press\n"); 1550 break; 1551 case 4: /* Function A button press */ 1552 bias_level = SND_JACK_BTN_0; 1553 dev_dbg(cs42l42->dev, "Function A button press\n"); 1554 break; 1555 default: 1556 bias_level = 0; 1557 break; 1558 } 1559 1560 /* Set button detect level sensitivity back to default */ 1561 regmap_update_bits(cs42l42->regmap, 1562 CS42L42_MIC_DET_CTL1, 1563 CS42L42_LATCH_TO_VP_MASK | 1564 CS42L42_EVENT_STAT_SEL_MASK | 1565 CS42L42_HS_DET_LEVEL_MASK, 1566 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1567 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1568 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); 1569 1570 /* Clear any button interrupts before unmasking them */ 1571 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1572 &detect_status); 1573 1574 /* Unmask button detect interrupts */ 1575 regmap_update_bits(cs42l42->regmap, 1576 CS42L42_DET_INT2_MASK, 1577 CS42L42_M_DETECT_TF_MASK | 1578 CS42L42_M_DETECT_FT_MASK | 1579 CS42L42_M_HSBIAS_HIZ_MASK | 1580 CS42L42_M_SHORT_RLS_MASK | 1581 CS42L42_M_SHORT_DET_MASK, 1582 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1583 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1584 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1585 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1586 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1587 1588 return bias_level; 1589 } 1590 1591 struct cs42l42_irq_params { 1592 u16 status_addr; 1593 u16 mask_addr; 1594 u8 mask; 1595 }; 1596 1597 static const struct cs42l42_irq_params irq_params_table[] = { 1598 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, 1599 CS42L42_ADC_OVFL_VAL_MASK}, 1600 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, 1601 CS42L42_MIXER_VAL_MASK}, 1602 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, 1603 CS42L42_SRC_VAL_MASK}, 1604 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, 1605 CS42L42_ASP_RX_VAL_MASK}, 1606 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, 1607 CS42L42_ASP_TX_VAL_MASK}, 1608 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, 1609 CS42L42_CODEC_VAL_MASK}, 1610 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, 1611 CS42L42_DET_INT_VAL1_MASK}, 1612 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, 1613 CS42L42_DET_INT_VAL2_MASK}, 1614 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, 1615 CS42L42_SRCPL_VAL_MASK}, 1616 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, 1617 CS42L42_VPMON_VAL_MASK}, 1618 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, 1619 CS42L42_PLL_LOCK_VAL_MASK}, 1620 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, 1621 CS42L42_TSRS_PLUG_VAL_MASK} 1622 }; 1623 1624 static irqreturn_t cs42l42_irq_thread(int irq, void *data) 1625 { 1626 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; 1627 unsigned int stickies[12]; 1628 unsigned int masks[12]; 1629 unsigned int current_plug_status; 1630 unsigned int current_button_status; 1631 unsigned int i; 1632 1633 mutex_lock(&cs42l42->irq_lock); 1634 if (cs42l42->suspended || !cs42l42->init_done) { 1635 mutex_unlock(&cs42l42->irq_lock); 1636 return IRQ_NONE; 1637 } 1638 1639 /* Read sticky registers to clear interurpt */ 1640 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 1641 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr, 1642 &(stickies[i])); 1643 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr, 1644 &(masks[i])); 1645 stickies[i] = stickies[i] & (~masks[i]) & 1646 irq_params_table[i].mask; 1647 } 1648 1649 /* Read tip sense status before handling type detect */ 1650 current_plug_status = (stickies[11] & 1651 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1652 CS42L42_TS_PLUG_SHIFT; 1653 1654 /* Read button sense status */ 1655 current_button_status = stickies[7] & 1656 (CS42L42_M_DETECT_TF_MASK | 1657 CS42L42_M_DETECT_FT_MASK | 1658 CS42L42_M_HSBIAS_HIZ_MASK); 1659 1660 /* 1661 * Check auto-detect status. Don't assume a previous unplug event has 1662 * cleared the flags. If the jack is unplugged and plugged during 1663 * system suspend there won't have been an unplug event. 1664 */ 1665 if ((~masks[5]) & irq_params_table[5].mask) { 1666 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { 1667 cs42l42_process_hs_type_detect(cs42l42); 1668 switch (cs42l42->hs_type) { 1669 case CS42L42_PLUG_CTIA: 1670 case CS42L42_PLUG_OMTP: 1671 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET, 1672 SND_JACK_HEADSET | 1673 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1674 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1675 break; 1676 case CS42L42_PLUG_HEADPHONE: 1677 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE, 1678 SND_JACK_HEADSET | 1679 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1680 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1681 break; 1682 default: 1683 break; 1684 } 1685 dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type); 1686 } 1687 } 1688 1689 /* Check tip sense status */ 1690 if ((~masks[11]) & irq_params_table[11].mask) { 1691 switch (current_plug_status) { 1692 case CS42L42_TS_PLUG: 1693 if (cs42l42->plug_state != CS42L42_TS_PLUG) { 1694 cs42l42->plug_state = CS42L42_TS_PLUG; 1695 cs42l42_init_hs_type_detect(cs42l42); 1696 } 1697 break; 1698 1699 case CS42L42_TS_UNPLUG: 1700 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { 1701 cs42l42->plug_state = CS42L42_TS_UNPLUG; 1702 cs42l42_cancel_hs_type_detect(cs42l42); 1703 1704 snd_soc_jack_report(cs42l42->jack, 0, 1705 SND_JACK_HEADSET | 1706 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1707 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1708 1709 dev_dbg(cs42l42->dev, "Unplug event\n"); 1710 } 1711 break; 1712 1713 default: 1714 cs42l42->plug_state = CS42L42_TS_TRANS; 1715 } 1716 } 1717 1718 /* Check button detect status */ 1719 if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) { 1720 if (!(current_button_status & 1721 CS42L42_M_HSBIAS_HIZ_MASK)) { 1722 1723 if (current_button_status & CS42L42_M_DETECT_TF_MASK) { 1724 dev_dbg(cs42l42->dev, "Button released\n"); 1725 snd_soc_jack_report(cs42l42->jack, 0, 1726 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1727 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1728 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) { 1729 snd_soc_jack_report(cs42l42->jack, 1730 cs42l42_handle_button_press(cs42l42), 1731 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1732 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1733 } 1734 } 1735 } 1736 1737 mutex_unlock(&cs42l42->irq_lock); 1738 1739 return IRQ_HANDLED; 1740 } 1741 1742 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) 1743 { 1744 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, 1745 CS42L42_ADC_OVFL_MASK, 1746 (1 << CS42L42_ADC_OVFL_SHIFT)); 1747 1748 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK, 1749 CS42L42_MIX_CHB_OVFL_MASK | 1750 CS42L42_MIX_CHA_OVFL_MASK | 1751 CS42L42_EQ_OVFL_MASK | 1752 CS42L42_EQ_BIQUAD_OVFL_MASK, 1753 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | 1754 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | 1755 (1 << CS42L42_EQ_OVFL_SHIFT) | 1756 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); 1757 1758 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK, 1759 CS42L42_SRC_ILK_MASK | 1760 CS42L42_SRC_OLK_MASK | 1761 CS42L42_SRC_IUNLK_MASK | 1762 CS42L42_SRC_OUNLK_MASK, 1763 (1 << CS42L42_SRC_ILK_SHIFT) | 1764 (1 << CS42L42_SRC_OLK_SHIFT) | 1765 (1 << CS42L42_SRC_IUNLK_SHIFT) | 1766 (1 << CS42L42_SRC_OUNLK_SHIFT)); 1767 1768 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, 1769 CS42L42_ASPRX_NOLRCK_MASK | 1770 CS42L42_ASPRX_EARLY_MASK | 1771 CS42L42_ASPRX_LATE_MASK | 1772 CS42L42_ASPRX_ERROR_MASK | 1773 CS42L42_ASPRX_OVLD_MASK, 1774 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | 1775 (1 << CS42L42_ASPRX_EARLY_SHIFT) | 1776 (1 << CS42L42_ASPRX_LATE_SHIFT) | 1777 (1 << CS42L42_ASPRX_ERROR_SHIFT) | 1778 (1 << CS42L42_ASPRX_OVLD_SHIFT)); 1779 1780 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, 1781 CS42L42_ASPTX_NOLRCK_MASK | 1782 CS42L42_ASPTX_EARLY_MASK | 1783 CS42L42_ASPTX_LATE_MASK | 1784 CS42L42_ASPTX_SMERROR_MASK, 1785 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | 1786 (1 << CS42L42_ASPTX_EARLY_SHIFT) | 1787 (1 << CS42L42_ASPTX_LATE_SHIFT) | 1788 (1 << CS42L42_ASPTX_SMERROR_SHIFT)); 1789 1790 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 1791 CS42L42_PDN_DONE_MASK | 1792 CS42L42_HSDET_AUTO_DONE_MASK, 1793 (1 << CS42L42_PDN_DONE_SHIFT) | 1794 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1795 1796 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK, 1797 CS42L42_SRCPL_ADC_LK_MASK | 1798 CS42L42_SRCPL_DAC_LK_MASK | 1799 CS42L42_SRCPL_ADC_UNLK_MASK | 1800 CS42L42_SRCPL_DAC_UNLK_MASK, 1801 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | 1802 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | 1803 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | 1804 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); 1805 1806 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK, 1807 CS42L42_TIP_SENSE_UNPLUG_MASK | 1808 CS42L42_TIP_SENSE_PLUG_MASK | 1809 CS42L42_HSBIAS_SENSE_MASK, 1810 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | 1811 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | 1812 (1 << CS42L42_HSBIAS_SENSE_SHIFT)); 1813 1814 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK, 1815 CS42L42_M_DETECT_TF_MASK | 1816 CS42L42_M_DETECT_FT_MASK | 1817 CS42L42_M_HSBIAS_HIZ_MASK | 1818 CS42L42_M_SHORT_RLS_MASK | 1819 CS42L42_M_SHORT_DET_MASK, 1820 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1821 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1822 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1823 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1824 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1825 1826 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK, 1827 CS42L42_VPMON_MASK, 1828 (1 << CS42L42_VPMON_SHIFT)); 1829 1830 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, 1831 CS42L42_PLL_LOCK_MASK, 1832 (1 << CS42L42_PLL_LOCK_SHIFT)); 1833 1834 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 1835 CS42L42_RS_PLUG_MASK | 1836 CS42L42_RS_UNPLUG_MASK | 1837 CS42L42_TS_PLUG_MASK | 1838 CS42L42_TS_UNPLUG_MASK, 1839 (1 << CS42L42_RS_PLUG_SHIFT) | 1840 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1841 (0 << CS42L42_TS_PLUG_SHIFT) | 1842 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1843 } 1844 1845 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) 1846 { 1847 unsigned int reg; 1848 1849 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1850 1851 /* 1852 * DETECT_MODE must always be 0 with ADC and HP both off otherwise the 1853 * FILT+ supply will not charge properly. 1854 */ 1855 regmap_update_bits(cs42l42->regmap, CS42L42_MISC_DET_CTL, 1856 CS42L42_DETECT_MODE_MASK, 0); 1857 1858 /* Latch analog controls to VP power domain */ 1859 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1, 1860 CS42L42_LATCH_TO_VP_MASK | 1861 CS42L42_EVENT_STAT_SEL_MASK | 1862 CS42L42_HS_DET_LEVEL_MASK, 1863 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1864 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1865 (cs42l42->bias_thresholds[0] << 1866 CS42L42_HS_DET_LEVEL_SHIFT)); 1867 1868 /* Remove ground noise-suppression clamps */ 1869 regmap_update_bits(cs42l42->regmap, 1870 CS42L42_HS_CLAMP_DISABLE, 1871 CS42L42_HS_CLAMP_DISABLE_MASK, 1872 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); 1873 1874 /* Enable the tip sense circuit */ 1875 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1876 CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK); 1877 1878 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL, 1879 CS42L42_TIP_SENSE_CTRL_MASK | 1880 CS42L42_TIP_SENSE_INV_MASK | 1881 CS42L42_TIP_SENSE_DEBOUNCE_MASK, 1882 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | 1883 (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) | 1884 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); 1885 1886 /* Save the initial status of the tip sense */ 1887 regmap_read(cs42l42->regmap, 1888 CS42L42_TSRS_PLUG_STATUS, 1889 ®); 1890 cs42l42->plug_state = (((char) reg) & 1891 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1892 CS42L42_TS_PLUG_SHIFT; 1893 } 1894 1895 static const unsigned int threshold_defaults[] = { 1896 CS42L42_HS_DET_LEVEL_15, 1897 CS42L42_HS_DET_LEVEL_8, 1898 CS42L42_HS_DET_LEVEL_4, 1899 CS42L42_HS_DET_LEVEL_1 1900 }; 1901 1902 static int cs42l42_handle_device_data(struct device *dev, 1903 struct cs42l42_private *cs42l42) 1904 { 1905 unsigned int val; 1906 u32 thresholds[CS42L42_NUM_BIASES]; 1907 int ret; 1908 int i; 1909 1910 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val); 1911 if (!ret) { 1912 switch (val) { 1913 case CS42L42_TS_INV_EN: 1914 case CS42L42_TS_INV_DIS: 1915 cs42l42->ts_inv = val; 1916 break; 1917 default: 1918 dev_err(dev, 1919 "Wrong cirrus,ts-inv DT value %d\n", 1920 val); 1921 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1922 } 1923 } else { 1924 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1925 } 1926 1927 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val); 1928 if (!ret) { 1929 switch (val) { 1930 case CS42L42_TS_DBNCE_0: 1931 case CS42L42_TS_DBNCE_125: 1932 case CS42L42_TS_DBNCE_250: 1933 case CS42L42_TS_DBNCE_500: 1934 case CS42L42_TS_DBNCE_750: 1935 case CS42L42_TS_DBNCE_1000: 1936 case CS42L42_TS_DBNCE_1250: 1937 case CS42L42_TS_DBNCE_1500: 1938 cs42l42->ts_dbnc_rise = val; 1939 break; 1940 default: 1941 dev_err(dev, 1942 "Wrong cirrus,ts-dbnc-rise DT value %d\n", 1943 val); 1944 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1945 } 1946 } else { 1947 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1948 } 1949 1950 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1951 CS42L42_TS_RISE_DBNCE_TIME_MASK, 1952 (cs42l42->ts_dbnc_rise << 1953 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); 1954 1955 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val); 1956 if (!ret) { 1957 switch (val) { 1958 case CS42L42_TS_DBNCE_0: 1959 case CS42L42_TS_DBNCE_125: 1960 case CS42L42_TS_DBNCE_250: 1961 case CS42L42_TS_DBNCE_500: 1962 case CS42L42_TS_DBNCE_750: 1963 case CS42L42_TS_DBNCE_1000: 1964 case CS42L42_TS_DBNCE_1250: 1965 case CS42L42_TS_DBNCE_1500: 1966 cs42l42->ts_dbnc_fall = val; 1967 break; 1968 default: 1969 dev_err(dev, 1970 "Wrong cirrus,ts-dbnc-fall DT value %d\n", 1971 val); 1972 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1973 } 1974 } else { 1975 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1976 } 1977 1978 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1979 CS42L42_TS_FALL_DBNCE_TIME_MASK, 1980 (cs42l42->ts_dbnc_fall << 1981 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); 1982 1983 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val); 1984 if (!ret) { 1985 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) 1986 cs42l42->btn_det_init_dbnce = val; 1987 else { 1988 dev_err(dev, 1989 "Wrong cirrus,btn-det-init-dbnce DT value %d\n", 1990 val); 1991 cs42l42->btn_det_init_dbnce = 1992 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1993 } 1994 } else { 1995 cs42l42->btn_det_init_dbnce = 1996 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1997 } 1998 1999 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val); 2000 if (!ret) { 2001 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) 2002 cs42l42->btn_det_event_dbnce = val; 2003 else { 2004 dev_err(dev, 2005 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); 2006 cs42l42->btn_det_event_dbnce = 2007 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 2008 } 2009 } else { 2010 cs42l42->btn_det_event_dbnce = 2011 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 2012 } 2013 2014 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls", 2015 thresholds, ARRAY_SIZE(thresholds)); 2016 if (!ret) { 2017 for (i = 0; i < CS42L42_NUM_BIASES; i++) { 2018 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) 2019 cs42l42->bias_thresholds[i] = thresholds[i]; 2020 else { 2021 dev_err(dev, 2022 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i, 2023 thresholds[i]); 2024 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 2025 } 2026 } 2027 } else { 2028 for (i = 0; i < CS42L42_NUM_BIASES; i++) 2029 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 2030 } 2031 2032 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val); 2033 if (!ret) { 2034 switch (val) { 2035 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: 2036 cs42l42->hs_bias_ramp_rate = val; 2037 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; 2038 break; 2039 case CS42L42_HSBIAS_RAMP_FAST: 2040 cs42l42->hs_bias_ramp_rate = val; 2041 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; 2042 break; 2043 case CS42L42_HSBIAS_RAMP_SLOW: 2044 cs42l42->hs_bias_ramp_rate = val; 2045 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2046 break; 2047 case CS42L42_HSBIAS_RAMP_SLOWEST: 2048 cs42l42->hs_bias_ramp_rate = val; 2049 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; 2050 break; 2051 default: 2052 dev_err(dev, 2053 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n", 2054 val); 2055 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 2056 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2057 } 2058 } else { 2059 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 2060 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2061 } 2062 2063 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL, 2064 CS42L42_HSBIAS_RAMP_MASK, 2065 (cs42l42->hs_bias_ramp_rate << 2066 CS42L42_HSBIAS_RAMP_SHIFT)); 2067 2068 if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable")) 2069 cs42l42->hs_bias_sense_en = 0; 2070 else 2071 cs42l42->hs_bias_sense_en = 1; 2072 2073 return 0; 2074 } 2075 2076 /* Datasheet suspend sequence */ 2077 static const struct reg_sequence __maybe_unused cs42l42_shutdown_seq[] = { 2078 REG_SEQ0(CS42L42_MIC_DET_CTL1, 0x9F), 2079 REG_SEQ0(CS42L42_ADC_OVFL_INT_MASK, 0x01), 2080 REG_SEQ0(CS42L42_MIXER_INT_MASK, 0x0F), 2081 REG_SEQ0(CS42L42_SRC_INT_MASK, 0x0F), 2082 REG_SEQ0(CS42L42_ASP_RX_INT_MASK, 0x1F), 2083 REG_SEQ0(CS42L42_ASP_TX_INT_MASK, 0x0F), 2084 REG_SEQ0(CS42L42_CODEC_INT_MASK, 0x03), 2085 REG_SEQ0(CS42L42_SRCPL_INT_MASK, 0x7F), 2086 REG_SEQ0(CS42L42_VPMON_INT_MASK, 0x01), 2087 REG_SEQ0(CS42L42_PLL_LOCK_INT_MASK, 0x01), 2088 REG_SEQ0(CS42L42_TSRS_PLUG_INT_MASK, 0x0F), 2089 REG_SEQ0(CS42L42_WAKE_CTL, 0xE1), 2090 REG_SEQ0(CS42L42_DET_INT1_MASK, 0xE0), 2091 REG_SEQ0(CS42L42_DET_INT2_MASK, 0xFF), 2092 REG_SEQ0(CS42L42_MIXER_CHA_VOL, 0x3F), 2093 REG_SEQ0(CS42L42_MIXER_ADC_VOL, 0x3F), 2094 REG_SEQ0(CS42L42_MIXER_CHB_VOL, 0x3F), 2095 REG_SEQ0(CS42L42_HP_CTL, 0x0F), 2096 REG_SEQ0(CS42L42_ASP_RX_DAI0_EN, 0x00), 2097 REG_SEQ0(CS42L42_ASP_CLK_CFG, 0x00), 2098 REG_SEQ0(CS42L42_HSDET_CTL2, 0x00), 2099 REG_SEQ0(CS42L42_PWR_CTL1, 0xFE), 2100 REG_SEQ0(CS42L42_PWR_CTL2, 0x8C), 2101 REG_SEQ0(CS42L42_DAC_CTL2, 0x02), 2102 REG_SEQ0(CS42L42_HS_CLAMP_DISABLE, 0x00), 2103 REG_SEQ0(CS42L42_MISC_DET_CTL, 0x03), 2104 REG_SEQ0(CS42L42_TIPSENSE_CTL, 0x02), 2105 REG_SEQ0(CS42L42_HSBIAS_SC_AUTOCTL, 0x03), 2106 REG_SEQ0(CS42L42_PWR_CTL1, 0xFF) 2107 }; 2108 2109 int cs42l42_suspend(struct device *dev) 2110 { 2111 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2112 unsigned int reg; 2113 u8 save_regs[ARRAY_SIZE(cs42l42_shutdown_seq)]; 2114 int i, ret; 2115 2116 /* 2117 * Wait for threaded irq handler to be idle and stop it processing 2118 * future interrupts. This ensures a safe disable if the interrupt 2119 * is shared. 2120 */ 2121 mutex_lock(&cs42l42->irq_lock); 2122 cs42l42->suspended = true; 2123 2124 /* Save register values that will be overwritten by shutdown sequence */ 2125 for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) { 2126 regmap_read(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, ®); 2127 save_regs[i] = (u8)reg; 2128 } 2129 2130 /* Shutdown codec */ 2131 regmap_multi_reg_write(cs42l42->regmap, 2132 cs42l42_shutdown_seq, 2133 ARRAY_SIZE(cs42l42_shutdown_seq)); 2134 2135 /* All interrupt sources are now disabled */ 2136 mutex_unlock(&cs42l42->irq_lock); 2137 2138 /* Wait for power-down complete */ 2139 msleep(CS42L42_PDN_DONE_TIME_MS); 2140 ret = regmap_read_poll_timeout(cs42l42->regmap, 2141 CS42L42_CODEC_STATUS, reg, 2142 (reg & CS42L42_PDN_DONE_MASK), 2143 CS42L42_PDN_DONE_POLL_US, 2144 CS42L42_PDN_DONE_TIMEOUT_US); 2145 if (ret) 2146 dev_warn(dev, "Failed to get PDN_DONE: %d\n", ret); 2147 2148 /* Discharge FILT+ */ 2149 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2, 2150 CS42L42_DISCHARGE_FILT_MASK, CS42L42_DISCHARGE_FILT_MASK); 2151 msleep(CS42L42_FILT_DISCHARGE_TIME_MS); 2152 2153 regcache_cache_only(cs42l42->regmap, true); 2154 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2155 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2156 2157 /* Restore register values to the regmap cache */ 2158 for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) 2159 regmap_write(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, save_regs[i]); 2160 2161 /* The cached address page register value is now stale */ 2162 regcache_drop_region(cs42l42->regmap, CS42L42_PAGE_REGISTER, CS42L42_PAGE_REGISTER); 2163 2164 dev_dbg(dev, "System suspended\n"); 2165 2166 return 0; 2167 2168 } 2169 EXPORT_SYMBOL_NS_GPL(cs42l42_suspend, SND_SOC_CS42L42_CORE); 2170 2171 int cs42l42_resume(struct device *dev) 2172 { 2173 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2174 int ret; 2175 2176 /* 2177 * If jack was unplugged and re-plugged during suspend it could 2178 * have changed type but the tip-sense state hasn't changed. 2179 * Force a plugged state to be re-evaluated. 2180 */ 2181 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) 2182 cs42l42->plug_state = CS42L42_TS_TRANS; 2183 2184 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2185 if (ret != 0) { 2186 dev_err(dev, "Failed to enable supplies: %d\n", ret); 2187 return ret; 2188 } 2189 2190 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 2191 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 2192 2193 dev_dbg(dev, "System resume powered up\n"); 2194 2195 return 0; 2196 } 2197 EXPORT_SYMBOL_NS_GPL(cs42l42_resume, SND_SOC_CS42L42_CORE); 2198 2199 void cs42l42_resume_restore(struct device *dev) 2200 { 2201 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2202 2203 regcache_cache_only(cs42l42->regmap, false); 2204 regcache_mark_dirty(cs42l42->regmap); 2205 2206 mutex_lock(&cs42l42->irq_lock); 2207 /* Sync LATCH_TO_VP first so the VP domain registers sync correctly */ 2208 regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1); 2209 regcache_sync(cs42l42->regmap); 2210 2211 cs42l42->suspended = false; 2212 mutex_unlock(&cs42l42->irq_lock); 2213 2214 dev_dbg(dev, "System resumed\n"); 2215 } 2216 EXPORT_SYMBOL_NS_GPL(cs42l42_resume_restore, SND_SOC_CS42L42_CORE); 2217 2218 static int __maybe_unused cs42l42_i2c_resume(struct device *dev) 2219 { 2220 int ret; 2221 2222 ret = cs42l42_resume(dev); 2223 if (ret) 2224 return ret; 2225 2226 cs42l42_resume_restore(dev); 2227 2228 return 0; 2229 } 2230 2231 int cs42l42_common_probe(struct cs42l42_private *cs42l42, 2232 const struct snd_soc_component_driver *component_drv, 2233 struct snd_soc_dai_driver *dai) 2234 { 2235 int ret, i; 2236 2237 dev_set_drvdata(cs42l42->dev, cs42l42); 2238 mutex_init(&cs42l42->irq_lock); 2239 2240 BUILD_BUG_ON(ARRAY_SIZE(cs42l42_supply_names) != ARRAY_SIZE(cs42l42->supplies)); 2241 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) 2242 cs42l42->supplies[i].supply = cs42l42_supply_names[i]; 2243 2244 ret = devm_regulator_bulk_get(cs42l42->dev, 2245 ARRAY_SIZE(cs42l42->supplies), 2246 cs42l42->supplies); 2247 if (ret != 0) { 2248 dev_err(cs42l42->dev, 2249 "Failed to request supplies: %d\n", ret); 2250 return ret; 2251 } 2252 2253 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 2254 cs42l42->supplies); 2255 if (ret != 0) { 2256 dev_err(cs42l42->dev, 2257 "Failed to enable supplies: %d\n", ret); 2258 return ret; 2259 } 2260 2261 /* Reset the Device */ 2262 cs42l42->reset_gpio = devm_gpiod_get_optional(cs42l42->dev, 2263 "reset", GPIOD_OUT_LOW); 2264 if (IS_ERR(cs42l42->reset_gpio)) { 2265 ret = PTR_ERR(cs42l42->reset_gpio); 2266 goto err_disable_noreset; 2267 } 2268 2269 if (cs42l42->reset_gpio) { 2270 dev_dbg(cs42l42->dev, "Found reset GPIO\n"); 2271 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 2272 } 2273 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 2274 2275 /* Request IRQ if one was specified */ 2276 if (cs42l42->irq) { 2277 ret = request_threaded_irq(cs42l42->irq, 2278 NULL, cs42l42_irq_thread, 2279 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 2280 "cs42l42", cs42l42); 2281 if (ret) { 2282 dev_err_probe(cs42l42->dev, ret, 2283 "Failed to request IRQ\n"); 2284 goto err_disable_noirq; 2285 } 2286 } 2287 2288 /* Register codec now so it can EPROBE_DEFER */ 2289 ret = devm_snd_soc_register_component(cs42l42->dev, component_drv, dai, 1); 2290 if (ret < 0) 2291 goto err; 2292 2293 return 0; 2294 2295 err: 2296 if (cs42l42->irq) 2297 free_irq(cs42l42->irq, cs42l42); 2298 2299 err_disable_noirq: 2300 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2301 err_disable_noreset: 2302 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2303 2304 return ret; 2305 } 2306 EXPORT_SYMBOL_NS_GPL(cs42l42_common_probe, SND_SOC_CS42L42_CORE); 2307 2308 int cs42l42_init(struct cs42l42_private *cs42l42) 2309 { 2310 unsigned int reg; 2311 int devid, ret; 2312 2313 /* initialize codec */ 2314 devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB); 2315 if (devid < 0) { 2316 ret = devid; 2317 dev_err(cs42l42->dev, "Failed to read device ID: %d\n", ret); 2318 goto err_disable; 2319 } 2320 2321 if (devid != cs42l42->devid) { 2322 ret = -ENODEV; 2323 dev_err(cs42l42->dev, 2324 "CS42L%x Device ID (%X). Expected %X\n", 2325 cs42l42->devid & 0xff, devid, cs42l42->devid); 2326 goto err_disable; 2327 } 2328 2329 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); 2330 if (ret < 0) { 2331 dev_err(cs42l42->dev, "Get Revision ID failed\n"); 2332 goto err_shutdown; 2333 } 2334 2335 dev_info(cs42l42->dev, 2336 "Cirrus Logic CS42L%x, Revision: %02X\n", 2337 cs42l42->devid & 0xff, reg & 0xFF); 2338 2339 /* Power up the codec */ 2340 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1, 2341 CS42L42_ASP_DAO_PDN_MASK | 2342 CS42L42_ASP_DAI_PDN_MASK | 2343 CS42L42_MIXER_PDN_MASK | 2344 CS42L42_EQ_PDN_MASK | 2345 CS42L42_HP_PDN_MASK | 2346 CS42L42_ADC_PDN_MASK | 2347 CS42L42_PDN_ALL_MASK, 2348 (1 << CS42L42_ASP_DAO_PDN_SHIFT) | 2349 (1 << CS42L42_ASP_DAI_PDN_SHIFT) | 2350 (1 << CS42L42_MIXER_PDN_SHIFT) | 2351 (1 << CS42L42_EQ_PDN_SHIFT) | 2352 (1 << CS42L42_HP_PDN_SHIFT) | 2353 (1 << CS42L42_ADC_PDN_SHIFT) | 2354 (0 << CS42L42_PDN_ALL_SHIFT)); 2355 2356 ret = cs42l42_handle_device_data(cs42l42->dev, cs42l42); 2357 if (ret != 0) 2358 goto err_shutdown; 2359 2360 /* Setup headset detection */ 2361 cs42l42_setup_hs_type_detect(cs42l42); 2362 2363 /* 2364 * Set init_done before unmasking interrupts so any triggered 2365 * immediately will be handled. 2366 */ 2367 cs42l42->init_done = true; 2368 2369 /* Mask/Unmask Interrupts */ 2370 cs42l42_set_interrupt_masks(cs42l42); 2371 2372 return 0; 2373 2374 err_shutdown: 2375 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff); 2376 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff); 2377 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff); 2378 2379 err_disable: 2380 if (cs42l42->irq) 2381 free_irq(cs42l42->irq, cs42l42); 2382 2383 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2384 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 2385 cs42l42->supplies); 2386 return ret; 2387 } 2388 EXPORT_SYMBOL_NS_GPL(cs42l42_init, SND_SOC_CS42L42_CORE); 2389 2390 void cs42l42_common_remove(struct cs42l42_private *cs42l42) 2391 { 2392 if (cs42l42->irq) 2393 free_irq(cs42l42->irq, cs42l42); 2394 2395 /* 2396 * The driver might not have control of reset and power supplies, 2397 * so ensure that the chip internals are powered down. 2398 */ 2399 if (cs42l42->init_done) { 2400 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff); 2401 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff); 2402 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff); 2403 } 2404 2405 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2406 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2407 } 2408 EXPORT_SYMBOL_NS_GPL(cs42l42_common_remove, SND_SOC_CS42L42_CORE); 2409 2410 MODULE_DESCRIPTION("ASoC CS42L42 driver"); 2411 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 2412 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 2413 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>"); 2414 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>"); 2415 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 2416 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>"); 2417 MODULE_LICENSE("GPL"); 2418