1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l42.c -- CS42L42 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/version.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/i2c.h> 19 #include <linux/gpio.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <linux/acpi.h> 23 #include <linux/platform_device.h> 24 #include <linux/property.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/gpio/consumer.h> 27 #include <linux/of_device.h> 28 #include <linux/pm_runtime.h> 29 #include <sound/core.h> 30 #include <sound/pcm.h> 31 #include <sound/pcm_params.h> 32 #include <sound/soc.h> 33 #include <sound/soc-dapm.h> 34 #include <sound/initval.h> 35 #include <sound/tlv.h> 36 #include <dt-bindings/sound/cs42l42.h> 37 38 #include "cs42l42.h" 39 #include "cirrus_legacy.h" 40 41 static const struct reg_default cs42l42_reg_defaults[] = { 42 { CS42L42_FRZ_CTL, 0x00 }, 43 { CS42L42_SRC_CTL, 0x10 }, 44 { CS42L42_MCLK_STATUS, 0x02 }, 45 { CS42L42_MCLK_CTL, 0x02 }, 46 { CS42L42_SFTRAMP_RATE, 0xA4 }, 47 { CS42L42_I2C_DEBOUNCE, 0x88 }, 48 { CS42L42_I2C_STRETCH, 0x03 }, 49 { CS42L42_I2C_TIMEOUT, 0xB7 }, 50 { CS42L42_PWR_CTL1, 0xFF }, 51 { CS42L42_PWR_CTL2, 0x84 }, 52 { CS42L42_PWR_CTL3, 0x20 }, 53 { CS42L42_RSENSE_CTL1, 0x40 }, 54 { CS42L42_RSENSE_CTL2, 0x00 }, 55 { CS42L42_OSC_SWITCH, 0x00 }, 56 { CS42L42_OSC_SWITCH_STATUS, 0x05 }, 57 { CS42L42_RSENSE_CTL3, 0x1B }, 58 { CS42L42_TSENSE_CTL, 0x1B }, 59 { CS42L42_TSRS_INT_DISABLE, 0x00 }, 60 { CS42L42_TRSENSE_STATUS, 0x00 }, 61 { CS42L42_HSDET_CTL1, 0x77 }, 62 { CS42L42_HSDET_CTL2, 0x00 }, 63 { CS42L42_HS_SWITCH_CTL, 0xF3 }, 64 { CS42L42_HS_DET_STATUS, 0x00 }, 65 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 66 { CS42L42_MCLK_SRC_SEL, 0x00 }, 67 { CS42L42_SPDIF_CLK_CFG, 0x00 }, 68 { CS42L42_FSYNC_PW_LOWER, 0x00 }, 69 { CS42L42_FSYNC_PW_UPPER, 0x00 }, 70 { CS42L42_FSYNC_P_LOWER, 0xF9 }, 71 { CS42L42_FSYNC_P_UPPER, 0x00 }, 72 { CS42L42_ASP_CLK_CFG, 0x00 }, 73 { CS42L42_ASP_FRM_CFG, 0x10 }, 74 { CS42L42_FS_RATE_EN, 0x00 }, 75 { CS42L42_IN_ASRC_CLK, 0x00 }, 76 { CS42L42_OUT_ASRC_CLK, 0x00 }, 77 { CS42L42_PLL_DIV_CFG1, 0x00 }, 78 { CS42L42_ADC_OVFL_STATUS, 0x00 }, 79 { CS42L42_MIXER_STATUS, 0x00 }, 80 { CS42L42_SRC_STATUS, 0x00 }, 81 { CS42L42_ASP_RX_STATUS, 0x00 }, 82 { CS42L42_ASP_TX_STATUS, 0x00 }, 83 { CS42L42_CODEC_STATUS, 0x00 }, 84 { CS42L42_DET_INT_STATUS1, 0x00 }, 85 { CS42L42_DET_INT_STATUS2, 0x00 }, 86 { CS42L42_SRCPL_INT_STATUS, 0x00 }, 87 { CS42L42_VPMON_STATUS, 0x00 }, 88 { CS42L42_PLL_LOCK_STATUS, 0x00 }, 89 { CS42L42_TSRS_PLUG_STATUS, 0x00 }, 90 { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, 91 { CS42L42_MIXER_INT_MASK, 0x0F }, 92 { CS42L42_SRC_INT_MASK, 0x0F }, 93 { CS42L42_ASP_RX_INT_MASK, 0x1F }, 94 { CS42L42_ASP_TX_INT_MASK, 0x0F }, 95 { CS42L42_CODEC_INT_MASK, 0x03 }, 96 { CS42L42_SRCPL_INT_MASK, 0xFF }, 97 { CS42L42_VPMON_INT_MASK, 0x01 }, 98 { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, 99 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, 100 { CS42L42_PLL_CTL1, 0x00 }, 101 { CS42L42_PLL_DIV_FRAC0, 0x00 }, 102 { CS42L42_PLL_DIV_FRAC1, 0x00 }, 103 { CS42L42_PLL_DIV_FRAC2, 0x00 }, 104 { CS42L42_PLL_DIV_INT, 0x40 }, 105 { CS42L42_PLL_CTL3, 0x10 }, 106 { CS42L42_PLL_CAL_RATIO, 0x80 }, 107 { CS42L42_PLL_CTL4, 0x03 }, 108 { CS42L42_LOAD_DET_RCSTAT, 0x00 }, 109 { CS42L42_LOAD_DET_DONE, 0x00 }, 110 { CS42L42_LOAD_DET_EN, 0x00 }, 111 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, 112 { CS42L42_WAKE_CTL, 0xC0 }, 113 { CS42L42_ADC_DISABLE_MUTE, 0x00 }, 114 { CS42L42_TIPSENSE_CTL, 0x02 }, 115 { CS42L42_MISC_DET_CTL, 0x03 }, 116 { CS42L42_MIC_DET_CTL1, 0x1F }, 117 { CS42L42_MIC_DET_CTL2, 0x2F }, 118 { CS42L42_DET_STATUS1, 0x00 }, 119 { CS42L42_DET_STATUS2, 0x00 }, 120 { CS42L42_DET_INT1_MASK, 0xE0 }, 121 { CS42L42_DET_INT2_MASK, 0xFF }, 122 { CS42L42_HS_BIAS_CTL, 0xC2 }, 123 { CS42L42_ADC_CTL, 0x00 }, 124 { CS42L42_ADC_VOLUME, 0x00 }, 125 { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, 126 { CS42L42_DAC_CTL1, 0x00 }, 127 { CS42L42_DAC_CTL2, 0x02 }, 128 { CS42L42_HP_CTL, 0x0D }, 129 { CS42L42_CLASSH_CTL, 0x07 }, 130 { CS42L42_MIXER_CHA_VOL, 0x3F }, 131 { CS42L42_MIXER_ADC_VOL, 0x3F }, 132 { CS42L42_MIXER_CHB_VOL, 0x3F }, 133 { CS42L42_EQ_COEF_IN0, 0x22 }, 134 { CS42L42_EQ_COEF_IN1, 0x00 }, 135 { CS42L42_EQ_COEF_IN2, 0x00 }, 136 { CS42L42_EQ_COEF_IN3, 0x00 }, 137 { CS42L42_EQ_COEF_RW, 0x00 }, 138 { CS42L42_EQ_COEF_OUT0, 0x00 }, 139 { CS42L42_EQ_COEF_OUT1, 0x00 }, 140 { CS42L42_EQ_COEF_OUT2, 0x00 }, 141 { CS42L42_EQ_COEF_OUT3, 0x00 }, 142 { CS42L42_EQ_INIT_STAT, 0x00 }, 143 { CS42L42_EQ_START_FILT, 0x00 }, 144 { CS42L42_EQ_MUTE_CTL, 0x00 }, 145 { CS42L42_SP_RX_CH_SEL, 0x04 }, 146 { CS42L42_SP_RX_ISOC_CTL, 0x04 }, 147 { CS42L42_SP_RX_FS, 0x8C }, 148 { CS42l42_SPDIF_CH_SEL, 0x0E }, 149 { CS42L42_SP_TX_ISOC_CTL, 0x04 }, 150 { CS42L42_SP_TX_FS, 0xCC }, 151 { CS42L42_SPDIF_SW_CTL1, 0x3F }, 152 { CS42L42_SRC_SDIN_FS, 0x40 }, 153 { CS42L42_SRC_SDOUT_FS, 0x40 }, 154 { CS42L42_SPDIF_CTL1, 0x01 }, 155 { CS42L42_SPDIF_CTL2, 0x00 }, 156 { CS42L42_SPDIF_CTL3, 0x00 }, 157 { CS42L42_SPDIF_CTL4, 0x42 }, 158 { CS42L42_ASP_TX_SZ_EN, 0x00 }, 159 { CS42L42_ASP_TX_CH_EN, 0x00 }, 160 { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, 161 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, 162 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, 163 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, 164 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, 165 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, 166 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 167 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, 168 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, 169 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, 170 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, 171 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, 172 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, 173 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, 174 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, 175 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, 176 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, 177 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, 178 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, 179 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, 180 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, 181 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, 182 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, 183 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, 184 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, 185 { CS42L42_SUB_REVID, 0x03 }, 186 }; 187 188 static bool cs42l42_readable_register(struct device *dev, unsigned int reg) 189 { 190 switch (reg) { 191 case CS42L42_PAGE_REGISTER: 192 case CS42L42_DEVID_AB: 193 case CS42L42_DEVID_CD: 194 case CS42L42_DEVID_E: 195 case CS42L42_FABID: 196 case CS42L42_REVID: 197 case CS42L42_FRZ_CTL: 198 case CS42L42_SRC_CTL: 199 case CS42L42_MCLK_STATUS: 200 case CS42L42_MCLK_CTL: 201 case CS42L42_SFTRAMP_RATE: 202 case CS42L42_I2C_DEBOUNCE: 203 case CS42L42_I2C_STRETCH: 204 case CS42L42_I2C_TIMEOUT: 205 case CS42L42_PWR_CTL1: 206 case CS42L42_PWR_CTL2: 207 case CS42L42_PWR_CTL3: 208 case CS42L42_RSENSE_CTL1: 209 case CS42L42_RSENSE_CTL2: 210 case CS42L42_OSC_SWITCH: 211 case CS42L42_OSC_SWITCH_STATUS: 212 case CS42L42_RSENSE_CTL3: 213 case CS42L42_TSENSE_CTL: 214 case CS42L42_TSRS_INT_DISABLE: 215 case CS42L42_TRSENSE_STATUS: 216 case CS42L42_HSDET_CTL1: 217 case CS42L42_HSDET_CTL2: 218 case CS42L42_HS_SWITCH_CTL: 219 case CS42L42_HS_DET_STATUS: 220 case CS42L42_HS_CLAMP_DISABLE: 221 case CS42L42_MCLK_SRC_SEL: 222 case CS42L42_SPDIF_CLK_CFG: 223 case CS42L42_FSYNC_PW_LOWER: 224 case CS42L42_FSYNC_PW_UPPER: 225 case CS42L42_FSYNC_P_LOWER: 226 case CS42L42_FSYNC_P_UPPER: 227 case CS42L42_ASP_CLK_CFG: 228 case CS42L42_ASP_FRM_CFG: 229 case CS42L42_FS_RATE_EN: 230 case CS42L42_IN_ASRC_CLK: 231 case CS42L42_OUT_ASRC_CLK: 232 case CS42L42_PLL_DIV_CFG1: 233 case CS42L42_ADC_OVFL_STATUS: 234 case CS42L42_MIXER_STATUS: 235 case CS42L42_SRC_STATUS: 236 case CS42L42_ASP_RX_STATUS: 237 case CS42L42_ASP_TX_STATUS: 238 case CS42L42_CODEC_STATUS: 239 case CS42L42_DET_INT_STATUS1: 240 case CS42L42_DET_INT_STATUS2: 241 case CS42L42_SRCPL_INT_STATUS: 242 case CS42L42_VPMON_STATUS: 243 case CS42L42_PLL_LOCK_STATUS: 244 case CS42L42_TSRS_PLUG_STATUS: 245 case CS42L42_ADC_OVFL_INT_MASK: 246 case CS42L42_MIXER_INT_MASK: 247 case CS42L42_SRC_INT_MASK: 248 case CS42L42_ASP_RX_INT_MASK: 249 case CS42L42_ASP_TX_INT_MASK: 250 case CS42L42_CODEC_INT_MASK: 251 case CS42L42_SRCPL_INT_MASK: 252 case CS42L42_VPMON_INT_MASK: 253 case CS42L42_PLL_LOCK_INT_MASK: 254 case CS42L42_TSRS_PLUG_INT_MASK: 255 case CS42L42_PLL_CTL1: 256 case CS42L42_PLL_DIV_FRAC0: 257 case CS42L42_PLL_DIV_FRAC1: 258 case CS42L42_PLL_DIV_FRAC2: 259 case CS42L42_PLL_DIV_INT: 260 case CS42L42_PLL_CTL3: 261 case CS42L42_PLL_CAL_RATIO: 262 case CS42L42_PLL_CTL4: 263 case CS42L42_LOAD_DET_RCSTAT: 264 case CS42L42_LOAD_DET_DONE: 265 case CS42L42_LOAD_DET_EN: 266 case CS42L42_HSBIAS_SC_AUTOCTL: 267 case CS42L42_WAKE_CTL: 268 case CS42L42_ADC_DISABLE_MUTE: 269 case CS42L42_TIPSENSE_CTL: 270 case CS42L42_MISC_DET_CTL: 271 case CS42L42_MIC_DET_CTL1: 272 case CS42L42_MIC_DET_CTL2: 273 case CS42L42_DET_STATUS1: 274 case CS42L42_DET_STATUS2: 275 case CS42L42_DET_INT1_MASK: 276 case CS42L42_DET_INT2_MASK: 277 case CS42L42_HS_BIAS_CTL: 278 case CS42L42_ADC_CTL: 279 case CS42L42_ADC_VOLUME: 280 case CS42L42_ADC_WNF_HPF_CTL: 281 case CS42L42_DAC_CTL1: 282 case CS42L42_DAC_CTL2: 283 case CS42L42_HP_CTL: 284 case CS42L42_CLASSH_CTL: 285 case CS42L42_MIXER_CHA_VOL: 286 case CS42L42_MIXER_ADC_VOL: 287 case CS42L42_MIXER_CHB_VOL: 288 case CS42L42_EQ_COEF_IN0: 289 case CS42L42_EQ_COEF_IN1: 290 case CS42L42_EQ_COEF_IN2: 291 case CS42L42_EQ_COEF_IN3: 292 case CS42L42_EQ_COEF_RW: 293 case CS42L42_EQ_COEF_OUT0: 294 case CS42L42_EQ_COEF_OUT1: 295 case CS42L42_EQ_COEF_OUT2: 296 case CS42L42_EQ_COEF_OUT3: 297 case CS42L42_EQ_INIT_STAT: 298 case CS42L42_EQ_START_FILT: 299 case CS42L42_EQ_MUTE_CTL: 300 case CS42L42_SP_RX_CH_SEL: 301 case CS42L42_SP_RX_ISOC_CTL: 302 case CS42L42_SP_RX_FS: 303 case CS42l42_SPDIF_CH_SEL: 304 case CS42L42_SP_TX_ISOC_CTL: 305 case CS42L42_SP_TX_FS: 306 case CS42L42_SPDIF_SW_CTL1: 307 case CS42L42_SRC_SDIN_FS: 308 case CS42L42_SRC_SDOUT_FS: 309 case CS42L42_SPDIF_CTL1: 310 case CS42L42_SPDIF_CTL2: 311 case CS42L42_SPDIF_CTL3: 312 case CS42L42_SPDIF_CTL4: 313 case CS42L42_ASP_TX_SZ_EN: 314 case CS42L42_ASP_TX_CH_EN: 315 case CS42L42_ASP_TX_CH_AP_RES: 316 case CS42L42_ASP_TX_CH1_BIT_MSB: 317 case CS42L42_ASP_TX_CH1_BIT_LSB: 318 case CS42L42_ASP_TX_HIZ_DLY_CFG: 319 case CS42L42_ASP_TX_CH2_BIT_MSB: 320 case CS42L42_ASP_TX_CH2_BIT_LSB: 321 case CS42L42_ASP_RX_DAI0_EN: 322 case CS42L42_ASP_RX_DAI0_CH1_AP_RES: 323 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: 324 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: 325 case CS42L42_ASP_RX_DAI0_CH2_AP_RES: 326 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: 327 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: 328 case CS42L42_ASP_RX_DAI0_CH3_AP_RES: 329 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: 330 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: 331 case CS42L42_ASP_RX_DAI0_CH4_AP_RES: 332 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: 333 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: 334 case CS42L42_ASP_RX_DAI1_CH1_AP_RES: 335 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: 336 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: 337 case CS42L42_ASP_RX_DAI1_CH2_AP_RES: 338 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: 339 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: 340 case CS42L42_SUB_REVID: 341 return true; 342 default: 343 return false; 344 } 345 } 346 347 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 348 { 349 switch (reg) { 350 case CS42L42_DEVID_AB: 351 case CS42L42_DEVID_CD: 352 case CS42L42_DEVID_E: 353 case CS42L42_MCLK_STATUS: 354 case CS42L42_TRSENSE_STATUS: 355 case CS42L42_HS_DET_STATUS: 356 case CS42L42_ADC_OVFL_STATUS: 357 case CS42L42_MIXER_STATUS: 358 case CS42L42_SRC_STATUS: 359 case CS42L42_ASP_RX_STATUS: 360 case CS42L42_ASP_TX_STATUS: 361 case CS42L42_CODEC_STATUS: 362 case CS42L42_DET_INT_STATUS1: 363 case CS42L42_DET_INT_STATUS2: 364 case CS42L42_SRCPL_INT_STATUS: 365 case CS42L42_VPMON_STATUS: 366 case CS42L42_PLL_LOCK_STATUS: 367 case CS42L42_TSRS_PLUG_STATUS: 368 case CS42L42_LOAD_DET_RCSTAT: 369 case CS42L42_LOAD_DET_DONE: 370 case CS42L42_DET_STATUS1: 371 case CS42L42_DET_STATUS2: 372 return true; 373 default: 374 return false; 375 } 376 } 377 378 static const struct regmap_range_cfg cs42l42_page_range = { 379 .name = "Pages", 380 .range_min = 0, 381 .range_max = CS42L42_MAX_REGISTER, 382 .selector_reg = CS42L42_PAGE_REGISTER, 383 .selector_mask = 0xff, 384 .selector_shift = 0, 385 .window_start = 0, 386 .window_len = 256, 387 }; 388 389 static const struct regmap_config cs42l42_regmap = { 390 .reg_bits = 8, 391 .val_bits = 8, 392 393 .readable_reg = cs42l42_readable_register, 394 .volatile_reg = cs42l42_volatile_register, 395 396 .ranges = &cs42l42_page_range, 397 .num_ranges = 1, 398 399 .max_register = CS42L42_MAX_REGISTER, 400 .reg_defaults = cs42l42_reg_defaults, 401 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), 402 .cache_type = REGCACHE_RBTREE, 403 404 .use_single_read = true, 405 .use_single_write = true, 406 }; 407 408 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true); 409 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true); 410 411 static const char * const cs42l42_hpf_freq_text[] = { 412 "1.86Hz", "120Hz", "235Hz", "466Hz" 413 }; 414 415 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 416 CS42L42_ADC_HPF_CF_SHIFT, 417 cs42l42_hpf_freq_text); 418 419 static const char * const cs42l42_wnf3_freq_text[] = { 420 "160Hz", "180Hz", "200Hz", "220Hz", 421 "240Hz", "260Hz", "280Hz", "300Hz" 422 }; 423 424 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 425 CS42L42_ADC_WNF_CF_SHIFT, 426 cs42l42_wnf3_freq_text); 427 428 static const struct snd_kcontrol_new cs42l42_snd_controls[] = { 429 /* ADC Volume and Filter Controls */ 430 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL, 431 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true), 432 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL, 433 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), 434 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL, 435 CS42L42_ADC_INV_SHIFT, true, false), 436 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL, 437 CS42L42_ADC_DIG_BOOST_SHIFT, true, false), 438 SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv), 439 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL, 440 CS42L42_ADC_WNF_EN_SHIFT, true, false), 441 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL, 442 CS42L42_ADC_HPF_EN_SHIFT, true, false), 443 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum), 444 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum), 445 446 /* DAC Volume and Filter Controls */ 447 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1, 448 CS42L42_DACA_INV_SHIFT, true, false), 449 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1, 450 CS42L42_DACB_INV_SHIFT, true, false), 451 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2, 452 CS42L42_DAC_HPF_EN_SHIFT, true, false), 453 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL, 454 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, 455 0x3f, 1, mixer_tlv) 456 }; 457 458 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { 459 /* Playback Path */ 460 SND_SOC_DAPM_OUTPUT("HP"), 461 SND_SOC_DAPM_DAC("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1), 462 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0), 463 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0), 464 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0), 465 466 /* Playback Requirements */ 467 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0), 468 469 /* Capture Path */ 470 SND_SOC_DAPM_INPUT("HS"), 471 SND_SOC_DAPM_ADC("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1), 472 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0), 473 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0), 474 475 /* Capture Requirements */ 476 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0), 477 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0), 478 479 /* Playback/Capture Requirements */ 480 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0), 481 }; 482 483 static const struct snd_soc_dapm_route cs42l42_audio_map[] = { 484 /* Playback Path */ 485 {"HP", NULL, "DAC"}, 486 {"DAC", NULL, "MIXER"}, 487 {"MIXER", NULL, "SDIN1"}, 488 {"MIXER", NULL, "SDIN2"}, 489 {"SDIN1", NULL, "Playback"}, 490 {"SDIN2", NULL, "Playback"}, 491 492 /* Playback Requirements */ 493 {"SDIN1", NULL, "ASP DAI0"}, 494 {"SDIN2", NULL, "ASP DAI0"}, 495 {"SDIN1", NULL, "SCLK"}, 496 {"SDIN2", NULL, "SCLK"}, 497 498 /* Capture Path */ 499 {"ADC", NULL, "HS"}, 500 { "SDOUT1", NULL, "ADC" }, 501 { "SDOUT2", NULL, "ADC" }, 502 { "Capture", NULL, "SDOUT1" }, 503 { "Capture", NULL, "SDOUT2" }, 504 505 /* Capture Requirements */ 506 { "SDOUT1", NULL, "ASP DAO0" }, 507 { "SDOUT2", NULL, "ASP DAO0" }, 508 { "SDOUT1", NULL, "SCLK" }, 509 { "SDOUT2", NULL, "SCLK" }, 510 { "SDOUT1", NULL, "ASP TX EN" }, 511 { "SDOUT2", NULL, "ASP TX EN" }, 512 }; 513 514 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d) 515 { 516 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 517 518 cs42l42->jack = jk; 519 520 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 521 CS42L42_RS_PLUG_MASK | CS42L42_RS_UNPLUG_MASK | 522 CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK, 523 (1 << CS42L42_RS_PLUG_SHIFT) | (1 << CS42L42_RS_UNPLUG_SHIFT) | 524 (0 << CS42L42_TS_PLUG_SHIFT) | (0 << CS42L42_TS_UNPLUG_SHIFT)); 525 526 return 0; 527 } 528 529 static int cs42l42_component_probe(struct snd_soc_component *component) 530 { 531 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 532 533 cs42l42->component = component; 534 535 return 0; 536 } 537 538 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = { 539 .probe = cs42l42_component_probe, 540 .set_jack = cs42l42_set_jack, 541 .dapm_widgets = cs42l42_dapm_widgets, 542 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), 543 .dapm_routes = cs42l42_audio_map, 544 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), 545 .controls = cs42l42_snd_controls, 546 .num_controls = ARRAY_SIZE(cs42l42_snd_controls), 547 .idle_bias_on = 1, 548 .endianness = 1, 549 .non_legacy_dai_naming = 1, 550 }; 551 552 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */ 553 static const struct reg_sequence cs42l42_to_sclk_seq[] = { 554 { 555 .reg = CS42L42_OSC_SWITCH, 556 .def = CS42L42_SCLK_PRESENT_MASK, 557 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 558 }, 559 }; 560 561 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */ 562 static const struct reg_sequence cs42l42_to_osc_seq[] = { 563 { 564 .reg = CS42L42_OSC_SWITCH, 565 .def = 0, 566 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 567 }, 568 }; 569 570 struct cs42l42_pll_params { 571 u32 sclk; 572 u8 mclk_div; 573 u8 mclk_src_sel; 574 u8 sclk_prediv; 575 u8 pll_div_int; 576 u32 pll_div_frac; 577 u8 pll_mode; 578 u8 pll_divout; 579 u32 mclk_int; 580 u8 pll_cal_ratio; 581 u8 n; 582 }; 583 584 /* 585 * Common PLL Settings for given SCLK 586 * Table 4-5 from the Datasheet 587 */ 588 static const struct cs42l42_pll_params pll_ratio_table[] = { 589 { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2}, 590 { 2304000, 0, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2}, 591 { 2400000, 0, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 592 { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 593 { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 594 { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 595 { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1}, 596 { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1}, 597 { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 598 { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 599 { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 600 { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0, 1}, 601 { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0, 1}, 602 { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0, 1}, 603 { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0, 1}, 604 { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0, 1}, 605 { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0, 1} 606 }; 607 608 static int cs42l42_pll_config(struct snd_soc_component *component) 609 { 610 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 611 int i; 612 u32 clk; 613 u32 fsync; 614 615 if (!cs42l42->sclk) 616 clk = cs42l42->bclk; 617 else 618 clk = cs42l42->sclk; 619 620 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 621 if (pll_ratio_table[i].sclk == clk) { 622 cs42l42->pll_config = i; 623 624 /* Configure the internal sample rate */ 625 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, 626 CS42L42_INTERNAL_FS_MASK, 627 ((pll_ratio_table[i].mclk_int != 628 12000000) && 629 (pll_ratio_table[i].mclk_int != 630 24000000)) << 631 CS42L42_INTERNAL_FS_SHIFT); 632 633 snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL, 634 CS42L42_MCLKDIV_MASK, 635 (pll_ratio_table[i].mclk_div << 636 CS42L42_MCLKDIV_SHIFT)); 637 /* Set up the LRCLK */ 638 fsync = clk / cs42l42->srate; 639 if (((fsync * cs42l42->srate) != clk) 640 || ((fsync % 2) != 0)) { 641 dev_err(component->dev, 642 "Unsupported sclk %d/sample rate %d\n", 643 clk, 644 cs42l42->srate); 645 return -EINVAL; 646 } 647 /* Set the LRCLK period */ 648 snd_soc_component_update_bits(component, 649 CS42L42_FSYNC_P_LOWER, 650 CS42L42_FSYNC_PERIOD_MASK, 651 CS42L42_FRAC0_VAL(fsync - 1) << 652 CS42L42_FSYNC_PERIOD_SHIFT); 653 snd_soc_component_update_bits(component, 654 CS42L42_FSYNC_P_UPPER, 655 CS42L42_FSYNC_PERIOD_MASK, 656 CS42L42_FRAC1_VAL(fsync - 1) << 657 CS42L42_FSYNC_PERIOD_SHIFT); 658 /* Set the LRCLK to 50% duty cycle */ 659 fsync = fsync / 2; 660 snd_soc_component_update_bits(component, 661 CS42L42_FSYNC_PW_LOWER, 662 CS42L42_FSYNC_PULSE_WIDTH_MASK, 663 CS42L42_FRAC0_VAL(fsync - 1) << 664 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 665 snd_soc_component_update_bits(component, 666 CS42L42_FSYNC_PW_UPPER, 667 CS42L42_FSYNC_PULSE_WIDTH_MASK, 668 CS42L42_FRAC1_VAL(fsync - 1) << 669 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 670 /* Set the sample rates (96k or lower) */ 671 snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN, 672 CS42L42_FS_EN_MASK, 673 (CS42L42_FS_EN_IASRC_96K | 674 CS42L42_FS_EN_OASRC_96K) << 675 CS42L42_FS_EN_SHIFT); 676 /* Set the input/output internal MCLK clock ~12 MHz */ 677 snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK, 678 CS42L42_CLK_IASRC_SEL_MASK, 679 CS42L42_CLK_IASRC_SEL_12 << 680 CS42L42_CLK_IASRC_SEL_SHIFT); 681 snd_soc_component_update_bits(component, 682 CS42L42_OUT_ASRC_CLK, 683 CS42L42_CLK_OASRC_SEL_MASK, 684 CS42L42_CLK_OASRC_SEL_12 << 685 CS42L42_CLK_OASRC_SEL_SHIFT); 686 if (pll_ratio_table[i].mclk_src_sel == 0) { 687 /* Pass the clock straight through */ 688 snd_soc_component_update_bits(component, 689 CS42L42_PLL_CTL1, 690 CS42L42_PLL_START_MASK, 0); 691 } else { 692 /* Configure PLL per table 4-5 */ 693 snd_soc_component_update_bits(component, 694 CS42L42_PLL_DIV_CFG1, 695 CS42L42_SCLK_PREDIV_MASK, 696 pll_ratio_table[i].sclk_prediv 697 << CS42L42_SCLK_PREDIV_SHIFT); 698 snd_soc_component_update_bits(component, 699 CS42L42_PLL_DIV_INT, 700 CS42L42_PLL_DIV_INT_MASK, 701 pll_ratio_table[i].pll_div_int 702 << CS42L42_PLL_DIV_INT_SHIFT); 703 snd_soc_component_update_bits(component, 704 CS42L42_PLL_DIV_FRAC0, 705 CS42L42_PLL_DIV_FRAC_MASK, 706 CS42L42_FRAC0_VAL( 707 pll_ratio_table[i].pll_div_frac) 708 << CS42L42_PLL_DIV_FRAC_SHIFT); 709 snd_soc_component_update_bits(component, 710 CS42L42_PLL_DIV_FRAC1, 711 CS42L42_PLL_DIV_FRAC_MASK, 712 CS42L42_FRAC1_VAL( 713 pll_ratio_table[i].pll_div_frac) 714 << CS42L42_PLL_DIV_FRAC_SHIFT); 715 snd_soc_component_update_bits(component, 716 CS42L42_PLL_DIV_FRAC2, 717 CS42L42_PLL_DIV_FRAC_MASK, 718 CS42L42_FRAC2_VAL( 719 pll_ratio_table[i].pll_div_frac) 720 << CS42L42_PLL_DIV_FRAC_SHIFT); 721 snd_soc_component_update_bits(component, 722 CS42L42_PLL_CTL4, 723 CS42L42_PLL_MODE_MASK, 724 pll_ratio_table[i].pll_mode 725 << CS42L42_PLL_MODE_SHIFT); 726 snd_soc_component_update_bits(component, 727 CS42L42_PLL_CTL3, 728 CS42L42_PLL_DIVOUT_MASK, 729 (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n) 730 << CS42L42_PLL_DIVOUT_SHIFT); 731 if (pll_ratio_table[i].n != 1) 732 cs42l42->pll_divout = pll_ratio_table[i].pll_divout; 733 else 734 cs42l42->pll_divout = 0; 735 snd_soc_component_update_bits(component, 736 CS42L42_PLL_CAL_RATIO, 737 CS42L42_PLL_CAL_RATIO_MASK, 738 pll_ratio_table[i].pll_cal_ratio 739 << CS42L42_PLL_CAL_RATIO_SHIFT); 740 } 741 return 0; 742 } 743 } 744 745 return -EINVAL; 746 } 747 748 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 749 { 750 struct snd_soc_component *component = codec_dai->component; 751 u32 asp_cfg_val = 0; 752 753 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 754 case SND_SOC_DAIFMT_CBS_CFM: 755 asp_cfg_val |= CS42L42_ASP_MASTER_MODE << 756 CS42L42_ASP_MODE_SHIFT; 757 break; 758 case SND_SOC_DAIFMT_CBS_CFS: 759 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << 760 CS42L42_ASP_MODE_SHIFT; 761 break; 762 default: 763 return -EINVAL; 764 } 765 766 /* interface format */ 767 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 768 case SND_SOC_DAIFMT_I2S: 769 /* 770 * 5050 mode, frame starts on falling edge of LRCLK, 771 * frame delayed by 1.0 SCLKs 772 */ 773 snd_soc_component_update_bits(component, 774 CS42L42_ASP_FRM_CFG, 775 CS42L42_ASP_STP_MASK | 776 CS42L42_ASP_5050_MASK | 777 CS42L42_ASP_FSD_MASK, 778 CS42L42_ASP_5050_MASK | 779 (CS42L42_ASP_FSD_1_0 << 780 CS42L42_ASP_FSD_SHIFT)); 781 break; 782 default: 783 return -EINVAL; 784 } 785 786 /* Bitclock/frame inversion */ 787 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 788 case SND_SOC_DAIFMT_NB_NF: 789 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 790 break; 791 case SND_SOC_DAIFMT_NB_IF: 792 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 793 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 794 break; 795 case SND_SOC_DAIFMT_IB_NF: 796 break; 797 case SND_SOC_DAIFMT_IB_IF: 798 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 799 break; 800 } 801 802 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK | 803 CS42L42_ASP_SCPOL_MASK | 804 CS42L42_ASP_LCPOL_MASK, 805 asp_cfg_val); 806 807 return 0; 808 } 809 810 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 811 { 812 struct snd_soc_component *component = dai->component; 813 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 814 815 /* 816 * Sample rates < 44.1 kHz would produce an out-of-range SCLK with 817 * a standard I2S frame. If the machine driver sets SCLK it must be 818 * legal. 819 */ 820 if (cs42l42->sclk) 821 return 0; 822 823 /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */ 824 return snd_pcm_hw_constraint_minmax(substream->runtime, 825 SNDRV_PCM_HW_PARAM_RATE, 826 44100, 192000); 827 } 828 829 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, 830 struct snd_pcm_hw_params *params, 831 struct snd_soc_dai *dai) 832 { 833 struct snd_soc_component *component = dai->component; 834 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 835 unsigned int channels = params_channels(params); 836 unsigned int width = (params_width(params) / 8) - 1; 837 unsigned int val = 0; 838 839 cs42l42->srate = params_rate(params); 840 cs42l42->bclk = snd_soc_params_to_bclk(params); 841 842 /* I2S frame always has 2 channels even for mono audio */ 843 if (channels == 1) 844 cs42l42->bclk *= 2; 845 846 switch(substream->stream) { 847 case SNDRV_PCM_STREAM_CAPTURE: 848 if (channels == 2) { 849 val |= CS42L42_ASP_TX_CH2_AP_MASK; 850 val |= width << CS42L42_ASP_TX_CH2_RES_SHIFT; 851 } 852 val |= width << CS42L42_ASP_TX_CH1_RES_SHIFT; 853 854 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES, 855 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK | 856 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val); 857 break; 858 case SNDRV_PCM_STREAM_PLAYBACK: 859 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT; 860 /* channel 1 on low LRCLK */ 861 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES, 862 CS42L42_ASP_RX_CH_AP_MASK | 863 CS42L42_ASP_RX_CH_RES_MASK, val); 864 /* Channel 2 on high LRCLK */ 865 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT; 866 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES, 867 CS42L42_ASP_RX_CH_AP_MASK | 868 CS42L42_ASP_RX_CH_RES_MASK, val); 869 870 /* Channel B comes from the last active channel */ 871 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL, 872 CS42L42_SP_RX_CHB_SEL_MASK, 873 (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT); 874 875 /* Both LRCLK slots must be enabled */ 876 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN, 877 CS42L42_ASP_RX0_CH_EN_MASK, 878 BIT(CS42L42_ASP_RX0_CH1_SHIFT) | 879 BIT(CS42L42_ASP_RX0_CH2_SHIFT)); 880 break; 881 default: 882 break; 883 } 884 885 return cs42l42_pll_config(component); 886 } 887 888 static int cs42l42_set_sysclk(struct snd_soc_dai *dai, 889 int clk_id, unsigned int freq, int dir) 890 { 891 struct snd_soc_component *component = dai->component; 892 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 893 894 cs42l42->sclk = freq; 895 896 return 0; 897 } 898 899 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 900 { 901 struct snd_soc_component *component = dai->component; 902 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 903 unsigned int regval; 904 u8 fullScaleVol; 905 int ret; 906 907 if (mute) { 908 /* Mute the headphone */ 909 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 910 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 911 CS42L42_HP_ANA_AMUTE_MASK | 912 CS42L42_HP_ANA_BMUTE_MASK, 913 CS42L42_HP_ANA_AMUTE_MASK | 914 CS42L42_HP_ANA_BMUTE_MASK); 915 916 cs42l42->stream_use &= ~(1 << stream); 917 if(!cs42l42->stream_use) { 918 /* 919 * Switch to the internal oscillator. 920 * SCLK must remain running until after this clock switch. 921 * Without a source of clock the I2C bus doesn't work. 922 */ 923 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq, 924 ARRAY_SIZE(cs42l42_to_osc_seq)); 925 926 /* Must disconnect PLL before stopping it */ 927 snd_soc_component_update_bits(component, 928 CS42L42_MCLK_SRC_SEL, 929 CS42L42_MCLK_SRC_SEL_MASK, 930 0); 931 usleep_range(100, 200); 932 933 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 934 CS42L42_PLL_START_MASK, 0); 935 } 936 } else { 937 if (!cs42l42->stream_use) { 938 /* SCLK must be running before codec unmute */ 939 if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) { 940 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 941 CS42L42_PLL_START_MASK, 1); 942 943 if (cs42l42->pll_divout) { 944 usleep_range(CS42L42_PLL_DIVOUT_TIME_US, 945 CS42L42_PLL_DIVOUT_TIME_US * 2); 946 snd_soc_component_update_bits(component, CS42L42_PLL_CTL3, 947 CS42L42_PLL_DIVOUT_MASK, 948 cs42l42->pll_divout << 949 CS42L42_PLL_DIVOUT_SHIFT); 950 } 951 952 ret = regmap_read_poll_timeout(cs42l42->regmap, 953 CS42L42_PLL_LOCK_STATUS, 954 regval, 955 (regval & 1), 956 CS42L42_PLL_LOCK_POLL_US, 957 CS42L42_PLL_LOCK_TIMEOUT_US); 958 if (ret < 0) 959 dev_warn(component->dev, "PLL failed to lock: %d\n", ret); 960 961 /* PLL must be running to drive glitchless switch logic */ 962 snd_soc_component_update_bits(component, 963 CS42L42_MCLK_SRC_SEL, 964 CS42L42_MCLK_SRC_SEL_MASK, 965 CS42L42_MCLK_SRC_SEL_MASK); 966 } 967 968 /* Mark SCLK as present, turn off internal oscillator */ 969 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq, 970 ARRAY_SIZE(cs42l42_to_sclk_seq)); 971 } 972 cs42l42->stream_use |= 1 << stream; 973 974 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 975 /* Read the headphone load */ 976 regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT); 977 if (((regval & CS42L42_RLA_STAT_MASK) >> CS42L42_RLA_STAT_SHIFT) == 978 CS42L42_RLA_STAT_15_OHM) { 979 fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK; 980 } else { 981 fullScaleVol = 0; 982 } 983 984 /* Un-mute the headphone, set the full scale volume flag */ 985 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 986 CS42L42_HP_ANA_AMUTE_MASK | 987 CS42L42_HP_ANA_BMUTE_MASK | 988 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol); 989 } 990 } 991 992 return 0; 993 } 994 995 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 996 SNDRV_PCM_FMTBIT_S24_LE |\ 997 SNDRV_PCM_FMTBIT_S32_LE ) 998 999 static const struct snd_soc_dai_ops cs42l42_ops = { 1000 .startup = cs42l42_dai_startup, 1001 .hw_params = cs42l42_pcm_hw_params, 1002 .set_fmt = cs42l42_set_dai_fmt, 1003 .set_sysclk = cs42l42_set_sysclk, 1004 .mute_stream = cs42l42_mute_stream, 1005 }; 1006 1007 static struct snd_soc_dai_driver cs42l42_dai = { 1008 .name = "cs42l42", 1009 .playback = { 1010 .stream_name = "Playback", 1011 .channels_min = 1, 1012 .channels_max = 2, 1013 .rates = SNDRV_PCM_RATE_8000_192000, 1014 .formats = CS42L42_FORMATS, 1015 }, 1016 .capture = { 1017 .stream_name = "Capture", 1018 .channels_min = 1, 1019 .channels_max = 2, 1020 .rates = SNDRV_PCM_RATE_8000_192000, 1021 .formats = CS42L42_FORMATS, 1022 }, 1023 .symmetric_rate = 1, 1024 .symmetric_sample_bits = 1, 1025 .ops = &cs42l42_ops, 1026 }; 1027 1028 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) 1029 { 1030 unsigned int hs_det_status; 1031 unsigned int int_status; 1032 1033 /* Mask the auto detect interrupt */ 1034 regmap_update_bits(cs42l42->regmap, 1035 CS42L42_CODEC_INT_MASK, 1036 CS42L42_PDN_DONE_MASK | 1037 CS42L42_HSDET_AUTO_DONE_MASK, 1038 (1 << CS42L42_PDN_DONE_SHIFT) | 1039 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1040 1041 /* Set hs detect to automatic, disabled mode */ 1042 regmap_update_bits(cs42l42->regmap, 1043 CS42L42_HSDET_CTL2, 1044 CS42L42_HSDET_CTRL_MASK | 1045 CS42L42_HSDET_SET_MASK | 1046 CS42L42_HSBIAS_REF_MASK | 1047 CS42L42_HSDET_AUTO_TIME_MASK, 1048 (2 << CS42L42_HSDET_CTRL_SHIFT) | 1049 (2 << CS42L42_HSDET_SET_SHIFT) | 1050 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1051 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1052 1053 /* Read and save the hs detection result */ 1054 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1055 1056 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> 1057 CS42L42_HSDET_TYPE_SHIFT; 1058 1059 /* Set up button detection */ 1060 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || 1061 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { 1062 /* Set auto HS bias settings to default */ 1063 regmap_update_bits(cs42l42->regmap, 1064 CS42L42_HSBIAS_SC_AUTOCTL, 1065 CS42L42_HSBIAS_SENSE_EN_MASK | 1066 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1067 CS42L42_TIP_SENSE_EN_MASK | 1068 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1069 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1070 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1071 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1072 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1073 1074 /* Set up hs detect level sensitivity */ 1075 regmap_update_bits(cs42l42->regmap, 1076 CS42L42_MIC_DET_CTL1, 1077 CS42L42_LATCH_TO_VP_MASK | 1078 CS42L42_EVENT_STAT_SEL_MASK | 1079 CS42L42_HS_DET_LEVEL_MASK, 1080 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1081 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1082 (cs42l42->bias_thresholds[0] << 1083 CS42L42_HS_DET_LEVEL_SHIFT)); 1084 1085 /* Set auto HS bias settings to default */ 1086 regmap_update_bits(cs42l42->regmap, 1087 CS42L42_HSBIAS_SC_AUTOCTL, 1088 CS42L42_HSBIAS_SENSE_EN_MASK | 1089 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1090 CS42L42_TIP_SENSE_EN_MASK | 1091 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1092 (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1093 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1094 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1095 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1096 1097 /* Turn on level detect circuitry */ 1098 regmap_update_bits(cs42l42->regmap, 1099 CS42L42_MISC_DET_CTL, 1100 CS42L42_DETECT_MODE_MASK | 1101 CS42L42_HSBIAS_CTL_MASK | 1102 CS42L42_PDN_MIC_LVL_DET_MASK, 1103 (0 << CS42L42_DETECT_MODE_SHIFT) | 1104 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1105 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1106 1107 msleep(cs42l42->btn_det_init_dbnce); 1108 1109 /* Clear any button interrupts before unmasking them */ 1110 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1111 &int_status); 1112 1113 /* Unmask button detect interrupts */ 1114 regmap_update_bits(cs42l42->regmap, 1115 CS42L42_DET_INT2_MASK, 1116 CS42L42_M_DETECT_TF_MASK | 1117 CS42L42_M_DETECT_FT_MASK | 1118 CS42L42_M_HSBIAS_HIZ_MASK | 1119 CS42L42_M_SHORT_RLS_MASK | 1120 CS42L42_M_SHORT_DET_MASK, 1121 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1122 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1123 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1124 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1125 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1126 } else { 1127 /* Make sure button detect and HS bias circuits are off */ 1128 regmap_update_bits(cs42l42->regmap, 1129 CS42L42_MISC_DET_CTL, 1130 CS42L42_DETECT_MODE_MASK | 1131 CS42L42_HSBIAS_CTL_MASK | 1132 CS42L42_PDN_MIC_LVL_DET_MASK, 1133 (0 << CS42L42_DETECT_MODE_SHIFT) | 1134 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1135 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1136 } 1137 1138 regmap_update_bits(cs42l42->regmap, 1139 CS42L42_DAC_CTL2, 1140 CS42L42_HPOUT_PULLDOWN_MASK | 1141 CS42L42_HPOUT_LOAD_MASK | 1142 CS42L42_HPOUT_CLAMP_MASK | 1143 CS42L42_DAC_HPF_EN_MASK | 1144 CS42L42_DAC_MON_EN_MASK, 1145 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1146 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1147 (0 << CS42L42_HPOUT_CLAMP_SHIFT) | 1148 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1149 (0 << CS42L42_DAC_MON_EN_SHIFT)); 1150 1151 /* Unmask tip sense interrupts */ 1152 regmap_update_bits(cs42l42->regmap, 1153 CS42L42_TSRS_PLUG_INT_MASK, 1154 CS42L42_RS_PLUG_MASK | 1155 CS42L42_RS_UNPLUG_MASK | 1156 CS42L42_TS_PLUG_MASK | 1157 CS42L42_TS_UNPLUG_MASK, 1158 (1 << CS42L42_RS_PLUG_SHIFT) | 1159 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1160 (0 << CS42L42_TS_PLUG_SHIFT) | 1161 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1162 } 1163 1164 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) 1165 { 1166 /* Mask tip sense interrupts */ 1167 regmap_update_bits(cs42l42->regmap, 1168 CS42L42_TSRS_PLUG_INT_MASK, 1169 CS42L42_RS_PLUG_MASK | 1170 CS42L42_RS_UNPLUG_MASK | 1171 CS42L42_TS_PLUG_MASK | 1172 CS42L42_TS_UNPLUG_MASK, 1173 (1 << CS42L42_RS_PLUG_SHIFT) | 1174 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1175 (1 << CS42L42_TS_PLUG_SHIFT) | 1176 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1177 1178 /* Make sure button detect and HS bias circuits are off */ 1179 regmap_update_bits(cs42l42->regmap, 1180 CS42L42_MISC_DET_CTL, 1181 CS42L42_DETECT_MODE_MASK | 1182 CS42L42_HSBIAS_CTL_MASK | 1183 CS42L42_PDN_MIC_LVL_DET_MASK, 1184 (0 << CS42L42_DETECT_MODE_SHIFT) | 1185 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1186 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1187 1188 /* Set auto HS bias settings to default */ 1189 regmap_update_bits(cs42l42->regmap, 1190 CS42L42_HSBIAS_SC_AUTOCTL, 1191 CS42L42_HSBIAS_SENSE_EN_MASK | 1192 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1193 CS42L42_TIP_SENSE_EN_MASK | 1194 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1195 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1196 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1197 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1198 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1199 1200 /* Set hs detect to manual, disabled mode */ 1201 regmap_update_bits(cs42l42->regmap, 1202 CS42L42_HSDET_CTL2, 1203 CS42L42_HSDET_CTRL_MASK | 1204 CS42L42_HSDET_SET_MASK | 1205 CS42L42_HSBIAS_REF_MASK | 1206 CS42L42_HSDET_AUTO_TIME_MASK, 1207 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1208 (2 << CS42L42_HSDET_SET_SHIFT) | 1209 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1210 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1211 1212 regmap_update_bits(cs42l42->regmap, 1213 CS42L42_DAC_CTL2, 1214 CS42L42_HPOUT_PULLDOWN_MASK | 1215 CS42L42_HPOUT_LOAD_MASK | 1216 CS42L42_HPOUT_CLAMP_MASK | 1217 CS42L42_DAC_HPF_EN_MASK | 1218 CS42L42_DAC_MON_EN_MASK, 1219 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1220 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1221 (1 << CS42L42_HPOUT_CLAMP_SHIFT) | 1222 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1223 (1 << CS42L42_DAC_MON_EN_SHIFT)); 1224 1225 /* Power up HS bias to 2.7V */ 1226 regmap_update_bits(cs42l42->regmap, 1227 CS42L42_MISC_DET_CTL, 1228 CS42L42_DETECT_MODE_MASK | 1229 CS42L42_HSBIAS_CTL_MASK | 1230 CS42L42_PDN_MIC_LVL_DET_MASK, 1231 (0 << CS42L42_DETECT_MODE_SHIFT) | 1232 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1233 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1234 1235 /* Wait for HS bias to ramp up */ 1236 msleep(cs42l42->hs_bias_ramp_time); 1237 1238 /* Unmask auto detect interrupt */ 1239 regmap_update_bits(cs42l42->regmap, 1240 CS42L42_CODEC_INT_MASK, 1241 CS42L42_PDN_DONE_MASK | 1242 CS42L42_HSDET_AUTO_DONE_MASK, 1243 (1 << CS42L42_PDN_DONE_SHIFT) | 1244 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1245 1246 /* Set hs detect to automatic, enabled mode */ 1247 regmap_update_bits(cs42l42->regmap, 1248 CS42L42_HSDET_CTL2, 1249 CS42L42_HSDET_CTRL_MASK | 1250 CS42L42_HSDET_SET_MASK | 1251 CS42L42_HSBIAS_REF_MASK | 1252 CS42L42_HSDET_AUTO_TIME_MASK, 1253 (3 << CS42L42_HSDET_CTRL_SHIFT) | 1254 (2 << CS42L42_HSDET_SET_SHIFT) | 1255 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1256 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1257 } 1258 1259 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) 1260 { 1261 /* Mask button detect interrupts */ 1262 regmap_update_bits(cs42l42->regmap, 1263 CS42L42_DET_INT2_MASK, 1264 CS42L42_M_DETECT_TF_MASK | 1265 CS42L42_M_DETECT_FT_MASK | 1266 CS42L42_M_HSBIAS_HIZ_MASK | 1267 CS42L42_M_SHORT_RLS_MASK | 1268 CS42L42_M_SHORT_DET_MASK, 1269 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1270 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1271 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1272 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1273 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1274 1275 /* Ground HS bias */ 1276 regmap_update_bits(cs42l42->regmap, 1277 CS42L42_MISC_DET_CTL, 1278 CS42L42_DETECT_MODE_MASK | 1279 CS42L42_HSBIAS_CTL_MASK | 1280 CS42L42_PDN_MIC_LVL_DET_MASK, 1281 (0 << CS42L42_DETECT_MODE_SHIFT) | 1282 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1283 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1284 1285 /* Set auto HS bias settings to default */ 1286 regmap_update_bits(cs42l42->regmap, 1287 CS42L42_HSBIAS_SC_AUTOCTL, 1288 CS42L42_HSBIAS_SENSE_EN_MASK | 1289 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1290 CS42L42_TIP_SENSE_EN_MASK | 1291 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1292 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1293 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1294 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1295 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1296 1297 /* Set hs detect to manual, disabled mode */ 1298 regmap_update_bits(cs42l42->regmap, 1299 CS42L42_HSDET_CTL2, 1300 CS42L42_HSDET_CTRL_MASK | 1301 CS42L42_HSDET_SET_MASK | 1302 CS42L42_HSBIAS_REF_MASK | 1303 CS42L42_HSDET_AUTO_TIME_MASK, 1304 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1305 (2 << CS42L42_HSDET_SET_SHIFT) | 1306 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1307 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1308 } 1309 1310 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42) 1311 { 1312 int bias_level; 1313 unsigned int detect_status; 1314 1315 /* Mask button detect interrupts */ 1316 regmap_update_bits(cs42l42->regmap, 1317 CS42L42_DET_INT2_MASK, 1318 CS42L42_M_DETECT_TF_MASK | 1319 CS42L42_M_DETECT_FT_MASK | 1320 CS42L42_M_HSBIAS_HIZ_MASK | 1321 CS42L42_M_SHORT_RLS_MASK | 1322 CS42L42_M_SHORT_DET_MASK, 1323 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1324 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1325 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1326 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1327 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1328 1329 usleep_range(cs42l42->btn_det_event_dbnce * 1000, 1330 cs42l42->btn_det_event_dbnce * 2000); 1331 1332 /* Test all 4 level detect biases */ 1333 bias_level = 1; 1334 do { 1335 /* Adjust button detect level sensitivity */ 1336 regmap_update_bits(cs42l42->regmap, 1337 CS42L42_MIC_DET_CTL1, 1338 CS42L42_LATCH_TO_VP_MASK | 1339 CS42L42_EVENT_STAT_SEL_MASK | 1340 CS42L42_HS_DET_LEVEL_MASK, 1341 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1342 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1343 (cs42l42->bias_thresholds[bias_level] << 1344 CS42L42_HS_DET_LEVEL_SHIFT)); 1345 1346 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2, 1347 &detect_status); 1348 } while ((detect_status & CS42L42_HS_TRUE_MASK) && 1349 (++bias_level < CS42L42_NUM_BIASES)); 1350 1351 switch (bias_level) { 1352 case 1: /* Function C button press */ 1353 bias_level = SND_JACK_BTN_2; 1354 dev_dbg(cs42l42->component->dev, "Function C button press\n"); 1355 break; 1356 case 2: /* Function B button press */ 1357 bias_level = SND_JACK_BTN_1; 1358 dev_dbg(cs42l42->component->dev, "Function B button press\n"); 1359 break; 1360 case 3: /* Function D button press */ 1361 bias_level = SND_JACK_BTN_3; 1362 dev_dbg(cs42l42->component->dev, "Function D button press\n"); 1363 break; 1364 case 4: /* Function A button press */ 1365 bias_level = SND_JACK_BTN_0; 1366 dev_dbg(cs42l42->component->dev, "Function A button press\n"); 1367 break; 1368 default: 1369 bias_level = 0; 1370 break; 1371 } 1372 1373 /* Set button detect level sensitivity back to default */ 1374 regmap_update_bits(cs42l42->regmap, 1375 CS42L42_MIC_DET_CTL1, 1376 CS42L42_LATCH_TO_VP_MASK | 1377 CS42L42_EVENT_STAT_SEL_MASK | 1378 CS42L42_HS_DET_LEVEL_MASK, 1379 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1380 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1381 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); 1382 1383 /* Clear any button interrupts before unmasking them */ 1384 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1385 &detect_status); 1386 1387 /* Unmask button detect interrupts */ 1388 regmap_update_bits(cs42l42->regmap, 1389 CS42L42_DET_INT2_MASK, 1390 CS42L42_M_DETECT_TF_MASK | 1391 CS42L42_M_DETECT_FT_MASK | 1392 CS42L42_M_HSBIAS_HIZ_MASK | 1393 CS42L42_M_SHORT_RLS_MASK | 1394 CS42L42_M_SHORT_DET_MASK, 1395 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1396 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1397 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1398 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1399 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1400 1401 return bias_level; 1402 } 1403 1404 struct cs42l42_irq_params { 1405 u16 status_addr; 1406 u16 mask_addr; 1407 u8 mask; 1408 }; 1409 1410 static const struct cs42l42_irq_params irq_params_table[] = { 1411 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, 1412 CS42L42_ADC_OVFL_VAL_MASK}, 1413 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, 1414 CS42L42_MIXER_VAL_MASK}, 1415 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, 1416 CS42L42_SRC_VAL_MASK}, 1417 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, 1418 CS42L42_ASP_RX_VAL_MASK}, 1419 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, 1420 CS42L42_ASP_TX_VAL_MASK}, 1421 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, 1422 CS42L42_CODEC_VAL_MASK}, 1423 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, 1424 CS42L42_DET_INT_VAL1_MASK}, 1425 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, 1426 CS42L42_DET_INT_VAL2_MASK}, 1427 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, 1428 CS42L42_SRCPL_VAL_MASK}, 1429 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, 1430 CS42L42_VPMON_VAL_MASK}, 1431 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, 1432 CS42L42_PLL_LOCK_VAL_MASK}, 1433 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, 1434 CS42L42_TSRS_PLUG_VAL_MASK} 1435 }; 1436 1437 static irqreturn_t cs42l42_irq_thread(int irq, void *data) 1438 { 1439 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; 1440 struct snd_soc_component *component = cs42l42->component; 1441 unsigned int stickies[12]; 1442 unsigned int masks[12]; 1443 unsigned int current_plug_status; 1444 unsigned int current_button_status; 1445 unsigned int i; 1446 int report = 0; 1447 1448 1449 /* Read sticky registers to clear interurpt */ 1450 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 1451 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr, 1452 &(stickies[i])); 1453 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr, 1454 &(masks[i])); 1455 stickies[i] = stickies[i] & (~masks[i]) & 1456 irq_params_table[i].mask; 1457 } 1458 1459 /* Read tip sense status before handling type detect */ 1460 current_plug_status = (stickies[11] & 1461 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1462 CS42L42_TS_PLUG_SHIFT; 1463 1464 /* Read button sense status */ 1465 current_button_status = stickies[7] & 1466 (CS42L42_M_DETECT_TF_MASK | 1467 CS42L42_M_DETECT_FT_MASK | 1468 CS42L42_M_HSBIAS_HIZ_MASK); 1469 1470 /* Check auto-detect status */ 1471 if ((~masks[5]) & irq_params_table[5].mask) { 1472 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { 1473 cs42l42_process_hs_type_detect(cs42l42); 1474 switch(cs42l42->hs_type){ 1475 case CS42L42_PLUG_CTIA: 1476 case CS42L42_PLUG_OMTP: 1477 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET, 1478 SND_JACK_HEADSET); 1479 break; 1480 case CS42L42_PLUG_HEADPHONE: 1481 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE, 1482 SND_JACK_HEADPHONE); 1483 break; 1484 default: 1485 break; 1486 } 1487 dev_dbg(component->dev, "Auto detect done (%d)\n", cs42l42->hs_type); 1488 } 1489 } 1490 1491 /* Check tip sense status */ 1492 if ((~masks[11]) & irq_params_table[11].mask) { 1493 switch (current_plug_status) { 1494 case CS42L42_TS_PLUG: 1495 if (cs42l42->plug_state != CS42L42_TS_PLUG) { 1496 cs42l42->plug_state = CS42L42_TS_PLUG; 1497 cs42l42_init_hs_type_detect(cs42l42); 1498 } 1499 break; 1500 1501 case CS42L42_TS_UNPLUG: 1502 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { 1503 cs42l42->plug_state = CS42L42_TS_UNPLUG; 1504 cs42l42_cancel_hs_type_detect(cs42l42); 1505 1506 switch(cs42l42->hs_type){ 1507 case CS42L42_PLUG_CTIA: 1508 case CS42L42_PLUG_OMTP: 1509 snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADSET); 1510 break; 1511 case CS42L42_PLUG_HEADPHONE: 1512 snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADPHONE); 1513 break; 1514 default: 1515 break; 1516 } 1517 snd_soc_jack_report(cs42l42->jack, 0, 1518 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1519 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1520 1521 dev_dbg(component->dev, "Unplug event\n"); 1522 } 1523 break; 1524 1525 default: 1526 if (cs42l42->plug_state != CS42L42_TS_TRANS) 1527 cs42l42->plug_state = CS42L42_TS_TRANS; 1528 } 1529 } 1530 1531 /* Check button detect status */ 1532 if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) { 1533 if (!(current_button_status & 1534 CS42L42_M_HSBIAS_HIZ_MASK)) { 1535 1536 if (current_button_status & CS42L42_M_DETECT_TF_MASK) { 1537 dev_dbg(component->dev, "Button released\n"); 1538 report = 0; 1539 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) { 1540 report = cs42l42_handle_button_press(cs42l42); 1541 1542 } 1543 snd_soc_jack_report(cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1544 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1545 } 1546 } 1547 1548 return IRQ_HANDLED; 1549 } 1550 1551 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) 1552 { 1553 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, 1554 CS42L42_ADC_OVFL_MASK, 1555 (1 << CS42L42_ADC_OVFL_SHIFT)); 1556 1557 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK, 1558 CS42L42_MIX_CHB_OVFL_MASK | 1559 CS42L42_MIX_CHA_OVFL_MASK | 1560 CS42L42_EQ_OVFL_MASK | 1561 CS42L42_EQ_BIQUAD_OVFL_MASK, 1562 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | 1563 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | 1564 (1 << CS42L42_EQ_OVFL_SHIFT) | 1565 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); 1566 1567 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK, 1568 CS42L42_SRC_ILK_MASK | 1569 CS42L42_SRC_OLK_MASK | 1570 CS42L42_SRC_IUNLK_MASK | 1571 CS42L42_SRC_OUNLK_MASK, 1572 (1 << CS42L42_SRC_ILK_SHIFT) | 1573 (1 << CS42L42_SRC_OLK_SHIFT) | 1574 (1 << CS42L42_SRC_IUNLK_SHIFT) | 1575 (1 << CS42L42_SRC_OUNLK_SHIFT)); 1576 1577 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, 1578 CS42L42_ASPRX_NOLRCK_MASK | 1579 CS42L42_ASPRX_EARLY_MASK | 1580 CS42L42_ASPRX_LATE_MASK | 1581 CS42L42_ASPRX_ERROR_MASK | 1582 CS42L42_ASPRX_OVLD_MASK, 1583 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | 1584 (1 << CS42L42_ASPRX_EARLY_SHIFT) | 1585 (1 << CS42L42_ASPRX_LATE_SHIFT) | 1586 (1 << CS42L42_ASPRX_ERROR_SHIFT) | 1587 (1 << CS42L42_ASPRX_OVLD_SHIFT)); 1588 1589 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, 1590 CS42L42_ASPTX_NOLRCK_MASK | 1591 CS42L42_ASPTX_EARLY_MASK | 1592 CS42L42_ASPTX_LATE_MASK | 1593 CS42L42_ASPTX_SMERROR_MASK, 1594 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | 1595 (1 << CS42L42_ASPTX_EARLY_SHIFT) | 1596 (1 << CS42L42_ASPTX_LATE_SHIFT) | 1597 (1 << CS42L42_ASPTX_SMERROR_SHIFT)); 1598 1599 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 1600 CS42L42_PDN_DONE_MASK | 1601 CS42L42_HSDET_AUTO_DONE_MASK, 1602 (1 << CS42L42_PDN_DONE_SHIFT) | 1603 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1604 1605 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK, 1606 CS42L42_SRCPL_ADC_LK_MASK | 1607 CS42L42_SRCPL_DAC_LK_MASK | 1608 CS42L42_SRCPL_ADC_UNLK_MASK | 1609 CS42L42_SRCPL_DAC_UNLK_MASK, 1610 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | 1611 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | 1612 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | 1613 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); 1614 1615 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK, 1616 CS42L42_TIP_SENSE_UNPLUG_MASK | 1617 CS42L42_TIP_SENSE_PLUG_MASK | 1618 CS42L42_HSBIAS_SENSE_MASK, 1619 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | 1620 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | 1621 (1 << CS42L42_HSBIAS_SENSE_SHIFT)); 1622 1623 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK, 1624 CS42L42_M_DETECT_TF_MASK | 1625 CS42L42_M_DETECT_FT_MASK | 1626 CS42L42_M_HSBIAS_HIZ_MASK | 1627 CS42L42_M_SHORT_RLS_MASK | 1628 CS42L42_M_SHORT_DET_MASK, 1629 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1630 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1631 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1632 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1633 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1634 1635 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK, 1636 CS42L42_VPMON_MASK, 1637 (1 << CS42L42_VPMON_SHIFT)); 1638 1639 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, 1640 CS42L42_PLL_LOCK_MASK, 1641 (1 << CS42L42_PLL_LOCK_SHIFT)); 1642 1643 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 1644 CS42L42_RS_PLUG_MASK | 1645 CS42L42_RS_UNPLUG_MASK | 1646 CS42L42_TS_PLUG_MASK | 1647 CS42L42_TS_UNPLUG_MASK, 1648 (1 << CS42L42_RS_PLUG_SHIFT) | 1649 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1650 (1 << CS42L42_TS_PLUG_SHIFT) | 1651 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1652 } 1653 1654 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) 1655 { 1656 unsigned int reg; 1657 1658 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1659 1660 /* Latch analog controls to VP power domain */ 1661 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1, 1662 CS42L42_LATCH_TO_VP_MASK | 1663 CS42L42_EVENT_STAT_SEL_MASK | 1664 CS42L42_HS_DET_LEVEL_MASK, 1665 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1666 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1667 (cs42l42->bias_thresholds[0] << 1668 CS42L42_HS_DET_LEVEL_SHIFT)); 1669 1670 /* Remove ground noise-suppression clamps */ 1671 regmap_update_bits(cs42l42->regmap, 1672 CS42L42_HS_CLAMP_DISABLE, 1673 CS42L42_HS_CLAMP_DISABLE_MASK, 1674 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); 1675 1676 /* Enable the tip sense circuit */ 1677 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL, 1678 CS42L42_TIP_SENSE_CTRL_MASK | 1679 CS42L42_TIP_SENSE_INV_MASK | 1680 CS42L42_TIP_SENSE_DEBOUNCE_MASK, 1681 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | 1682 (0 << CS42L42_TIP_SENSE_INV_SHIFT) | 1683 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); 1684 1685 /* Save the initial status of the tip sense */ 1686 regmap_read(cs42l42->regmap, 1687 CS42L42_TSRS_PLUG_STATUS, 1688 ®); 1689 cs42l42->plug_state = (((char) reg) & 1690 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1691 CS42L42_TS_PLUG_SHIFT; 1692 } 1693 1694 static const unsigned int threshold_defaults[] = { 1695 CS42L42_HS_DET_LEVEL_15, 1696 CS42L42_HS_DET_LEVEL_8, 1697 CS42L42_HS_DET_LEVEL_4, 1698 CS42L42_HS_DET_LEVEL_1 1699 }; 1700 1701 static int cs42l42_handle_device_data(struct device *dev, 1702 struct cs42l42_private *cs42l42) 1703 { 1704 unsigned int val; 1705 u32 thresholds[CS42L42_NUM_BIASES]; 1706 int ret; 1707 int i; 1708 1709 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val); 1710 if (!ret) { 1711 switch (val) { 1712 case CS42L42_TS_INV_EN: 1713 case CS42L42_TS_INV_DIS: 1714 cs42l42->ts_inv = val; 1715 break; 1716 default: 1717 dev_err(dev, 1718 "Wrong cirrus,ts-inv DT value %d\n", 1719 val); 1720 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1721 } 1722 } else { 1723 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1724 } 1725 1726 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1727 CS42L42_TS_INV_MASK, 1728 (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT)); 1729 1730 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val); 1731 if (!ret) { 1732 switch (val) { 1733 case CS42L42_TS_DBNCE_0: 1734 case CS42L42_TS_DBNCE_125: 1735 case CS42L42_TS_DBNCE_250: 1736 case CS42L42_TS_DBNCE_500: 1737 case CS42L42_TS_DBNCE_750: 1738 case CS42L42_TS_DBNCE_1000: 1739 case CS42L42_TS_DBNCE_1250: 1740 case CS42L42_TS_DBNCE_1500: 1741 cs42l42->ts_dbnc_rise = val; 1742 break; 1743 default: 1744 dev_err(dev, 1745 "Wrong cirrus,ts-dbnc-rise DT value %d\n", 1746 val); 1747 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1748 } 1749 } else { 1750 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1751 } 1752 1753 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1754 CS42L42_TS_RISE_DBNCE_TIME_MASK, 1755 (cs42l42->ts_dbnc_rise << 1756 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); 1757 1758 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val); 1759 if (!ret) { 1760 switch (val) { 1761 case CS42L42_TS_DBNCE_0: 1762 case CS42L42_TS_DBNCE_125: 1763 case CS42L42_TS_DBNCE_250: 1764 case CS42L42_TS_DBNCE_500: 1765 case CS42L42_TS_DBNCE_750: 1766 case CS42L42_TS_DBNCE_1000: 1767 case CS42L42_TS_DBNCE_1250: 1768 case CS42L42_TS_DBNCE_1500: 1769 cs42l42->ts_dbnc_fall = val; 1770 break; 1771 default: 1772 dev_err(dev, 1773 "Wrong cirrus,ts-dbnc-fall DT value %d\n", 1774 val); 1775 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1776 } 1777 } else { 1778 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1779 } 1780 1781 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1782 CS42L42_TS_FALL_DBNCE_TIME_MASK, 1783 (cs42l42->ts_dbnc_fall << 1784 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); 1785 1786 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val); 1787 if (!ret) { 1788 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) 1789 cs42l42->btn_det_init_dbnce = val; 1790 else { 1791 dev_err(dev, 1792 "Wrong cirrus,btn-det-init-dbnce DT value %d\n", 1793 val); 1794 cs42l42->btn_det_init_dbnce = 1795 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1796 } 1797 } else { 1798 cs42l42->btn_det_init_dbnce = 1799 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1800 } 1801 1802 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val); 1803 if (!ret) { 1804 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) 1805 cs42l42->btn_det_event_dbnce = val; 1806 else { 1807 dev_err(dev, 1808 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); 1809 cs42l42->btn_det_event_dbnce = 1810 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1811 } 1812 } else { 1813 cs42l42->btn_det_event_dbnce = 1814 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1815 } 1816 1817 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls", 1818 thresholds, ARRAY_SIZE(thresholds)); 1819 if (!ret) { 1820 for (i = 0; i < CS42L42_NUM_BIASES; i++) { 1821 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) 1822 cs42l42->bias_thresholds[i] = thresholds[i]; 1823 else { 1824 dev_err(dev, 1825 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i, 1826 thresholds[i]); 1827 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 1828 } 1829 } 1830 } else { 1831 for (i = 0; i < CS42L42_NUM_BIASES; i++) 1832 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 1833 } 1834 1835 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val); 1836 if (!ret) { 1837 switch (val) { 1838 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: 1839 cs42l42->hs_bias_ramp_rate = val; 1840 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; 1841 break; 1842 case CS42L42_HSBIAS_RAMP_FAST: 1843 cs42l42->hs_bias_ramp_rate = val; 1844 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; 1845 break; 1846 case CS42L42_HSBIAS_RAMP_SLOW: 1847 cs42l42->hs_bias_ramp_rate = val; 1848 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1849 break; 1850 case CS42L42_HSBIAS_RAMP_SLOWEST: 1851 cs42l42->hs_bias_ramp_rate = val; 1852 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; 1853 break; 1854 default: 1855 dev_err(dev, 1856 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n", 1857 val); 1858 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 1859 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1860 } 1861 } else { 1862 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 1863 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1864 } 1865 1866 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL, 1867 CS42L42_HSBIAS_RAMP_MASK, 1868 (cs42l42->hs_bias_ramp_rate << 1869 CS42L42_HSBIAS_RAMP_SHIFT)); 1870 1871 if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable")) 1872 cs42l42->hs_bias_sense_en = 0; 1873 else 1874 cs42l42->hs_bias_sense_en = 1; 1875 1876 return 0; 1877 } 1878 1879 static int cs42l42_i2c_probe(struct i2c_client *i2c_client, 1880 const struct i2c_device_id *id) 1881 { 1882 struct cs42l42_private *cs42l42; 1883 int ret, i, devid; 1884 unsigned int reg; 1885 1886 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private), 1887 GFP_KERNEL); 1888 if (!cs42l42) 1889 return -ENOMEM; 1890 1891 i2c_set_clientdata(i2c_client, cs42l42); 1892 1893 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap); 1894 if (IS_ERR(cs42l42->regmap)) { 1895 ret = PTR_ERR(cs42l42->regmap); 1896 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 1897 return ret; 1898 } 1899 1900 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) 1901 cs42l42->supplies[i].supply = cs42l42_supply_names[i]; 1902 1903 ret = devm_regulator_bulk_get(&i2c_client->dev, 1904 ARRAY_SIZE(cs42l42->supplies), 1905 cs42l42->supplies); 1906 if (ret != 0) { 1907 dev_err(&i2c_client->dev, 1908 "Failed to request supplies: %d\n", ret); 1909 return ret; 1910 } 1911 1912 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 1913 cs42l42->supplies); 1914 if (ret != 0) { 1915 dev_err(&i2c_client->dev, 1916 "Failed to enable supplies: %d\n", ret); 1917 return ret; 1918 } 1919 1920 /* Reset the Device */ 1921 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, 1922 "reset", GPIOD_OUT_LOW); 1923 if (IS_ERR(cs42l42->reset_gpio)) { 1924 ret = PTR_ERR(cs42l42->reset_gpio); 1925 goto err_disable; 1926 } 1927 1928 if (cs42l42->reset_gpio) { 1929 dev_dbg(&i2c_client->dev, "Found reset GPIO\n"); 1930 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 1931 } 1932 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 1933 1934 /* Request IRQ */ 1935 ret = devm_request_threaded_irq(&i2c_client->dev, 1936 i2c_client->irq, 1937 NULL, cs42l42_irq_thread, 1938 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 1939 "cs42l42", cs42l42); 1940 1941 if (ret != 0) 1942 dev_err(&i2c_client->dev, 1943 "Failed to request IRQ: %d\n", ret); 1944 1945 /* initialize codec */ 1946 devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB); 1947 if (devid < 0) { 1948 ret = devid; 1949 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret); 1950 goto err_disable; 1951 } 1952 1953 if (devid != CS42L42_CHIP_ID) { 1954 ret = -ENODEV; 1955 dev_err(&i2c_client->dev, 1956 "CS42L42 Device ID (%X). Expected %X\n", 1957 devid, CS42L42_CHIP_ID); 1958 goto err_disable; 1959 } 1960 1961 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); 1962 if (ret < 0) { 1963 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 1964 goto err_disable; 1965 } 1966 1967 dev_info(&i2c_client->dev, 1968 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF); 1969 1970 /* Power up the codec */ 1971 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1, 1972 CS42L42_ASP_DAO_PDN_MASK | 1973 CS42L42_ASP_DAI_PDN_MASK | 1974 CS42L42_MIXER_PDN_MASK | 1975 CS42L42_EQ_PDN_MASK | 1976 CS42L42_HP_PDN_MASK | 1977 CS42L42_ADC_PDN_MASK | 1978 CS42L42_PDN_ALL_MASK, 1979 (1 << CS42L42_ASP_DAO_PDN_SHIFT) | 1980 (1 << CS42L42_ASP_DAI_PDN_SHIFT) | 1981 (1 << CS42L42_MIXER_PDN_SHIFT) | 1982 (1 << CS42L42_EQ_PDN_SHIFT) | 1983 (1 << CS42L42_HP_PDN_SHIFT) | 1984 (1 << CS42L42_ADC_PDN_SHIFT) | 1985 (0 << CS42L42_PDN_ALL_SHIFT)); 1986 1987 ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42); 1988 if (ret != 0) 1989 goto err_disable; 1990 1991 /* Setup headset detection */ 1992 cs42l42_setup_hs_type_detect(cs42l42); 1993 1994 /* Mask/Unmask Interrupts */ 1995 cs42l42_set_interrupt_masks(cs42l42); 1996 1997 /* Register codec for machine driver */ 1998 ret = devm_snd_soc_register_component(&i2c_client->dev, 1999 &soc_component_dev_cs42l42, &cs42l42_dai, 1); 2000 if (ret < 0) 2001 goto err_disable; 2002 return 0; 2003 2004 err_disable: 2005 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 2006 cs42l42->supplies); 2007 return ret; 2008 } 2009 2010 static int cs42l42_i2c_remove(struct i2c_client *i2c_client) 2011 { 2012 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client); 2013 2014 devm_free_irq(&i2c_client->dev, i2c_client->irq, cs42l42); 2015 pm_runtime_suspend(&i2c_client->dev); 2016 pm_runtime_disable(&i2c_client->dev); 2017 2018 return 0; 2019 } 2020 2021 #ifdef CONFIG_PM 2022 static int cs42l42_runtime_suspend(struct device *dev) 2023 { 2024 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2025 2026 regcache_cache_only(cs42l42->regmap, true); 2027 regcache_mark_dirty(cs42l42->regmap); 2028 2029 /* Hold down reset */ 2030 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2031 2032 /* remove power */ 2033 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 2034 cs42l42->supplies); 2035 2036 return 0; 2037 } 2038 2039 static int cs42l42_runtime_resume(struct device *dev) 2040 { 2041 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2042 int ret; 2043 2044 /* Enable power */ 2045 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 2046 cs42l42->supplies); 2047 if (ret != 0) { 2048 dev_err(dev, "Failed to enable supplies: %d\n", 2049 ret); 2050 return ret; 2051 } 2052 2053 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 2054 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 2055 2056 regcache_cache_only(cs42l42->regmap, false); 2057 regcache_sync(cs42l42->regmap); 2058 2059 return 0; 2060 } 2061 #endif 2062 2063 static const struct dev_pm_ops cs42l42_runtime_pm = { 2064 SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume, 2065 NULL) 2066 }; 2067 2068 #ifdef CONFIG_OF 2069 static const struct of_device_id cs42l42_of_match[] = { 2070 { .compatible = "cirrus,cs42l42", }, 2071 {} 2072 }; 2073 MODULE_DEVICE_TABLE(of, cs42l42_of_match); 2074 #endif 2075 2076 #ifdef CONFIG_ACPI 2077 static const struct acpi_device_id cs42l42_acpi_match[] = { 2078 {"10134242", 0,}, 2079 {} 2080 }; 2081 MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match); 2082 #endif 2083 2084 static const struct i2c_device_id cs42l42_id[] = { 2085 {"cs42l42", 0}, 2086 {} 2087 }; 2088 2089 MODULE_DEVICE_TABLE(i2c, cs42l42_id); 2090 2091 static struct i2c_driver cs42l42_i2c_driver = { 2092 .driver = { 2093 .name = "cs42l42", 2094 .pm = &cs42l42_runtime_pm, 2095 .of_match_table = of_match_ptr(cs42l42_of_match), 2096 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match), 2097 }, 2098 .id_table = cs42l42_id, 2099 .probe = cs42l42_i2c_probe, 2100 .remove = cs42l42_i2c_remove, 2101 }; 2102 2103 module_i2c_driver(cs42l42_i2c_driver); 2104 2105 MODULE_DESCRIPTION("ASoC CS42L42 driver"); 2106 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 2107 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 2108 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>"); 2109 MODULE_LICENSE("GPL"); 2110